FDB060AN08A0 / FDP060AN08A0 N-Channel PowerTrench(R) MOSFET 75V, 80A, 6.0m Features Applications * r DS(ON) = 4.8m (Typ.), V GS = 10V, ID = 80A * 42V Automotive Load Control * Qg(tot) = 73nC (Typ.), VGS = 10V * Starter / Alternator Systems * Low Miller Charge * Electronic Power Steering Systems * Low QRR Body Diode * Electronic Valve Train Systems * UIS Capability (Single Pulse and Repetitive Pulse) * DC-DC converters and Off-line UPS * Qualified to AEC Q101 * Distributed Power Architectures and VRMs Formerly developmental type 82680 * Primary Switch for 24V and 48V systems D DRAIN (FLANGE) SOURCE GATE DRAIN G GATE SOURCE TO-220AB FDP SERIES TO-263AB FDB SERIES DRAIN (FLANGE) S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 75 Units V VGS Gate to Source Voltage 20 V Continuous (TC < 127oC, VGS = 10V) 80 A Continuous (Tamb = 25oC, VGS = 10V, with RJA = 43oC/W) 16 A Drain Current ID Pulsed EAS PD TJ, TSTG Figure 4 A Single Pulse Avalanche Energy (Note 1) 350 mJ Power dissipation 255 W Derate above 25oC 1.7 W/oC Operating and Storage Temperature o -55 to 175 C Thermal Characteristics oC/W RJC Thermal Resistance Junction to Case TO-220,TO-263 RJA Thermal Resistance Junction to Ambient TO-220,TO-263 (Note 2) 62 o C/W RJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 o C/W 0.58 This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 November 2002 Device Marking FDB060AN08A0 Device FDB060AN08A0 Package TO-263AB Reel Size 330mm Tape Width 24mm Quantity 800 units FDP060AN08A0 FDP060AN08A0 TO-220AB Tube N/A 50 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 75 - - V - - 1 - - 250 A VGS = 20V - - 100 nA V V DS = 60V VGS = 0V TC = 150oC On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A 2 - 4 ID = 80A, VGS = 10V - 0.0048 0.006 ID = 40A, VGS = 6V - 0.0066 0.010 ID = 80A, VGS = 10V, TJ = 175oC - 0.010 0.013 - 5150 - - 800 - pF - 230 - pF nC Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge VGS = 0V to 2V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge V DS = 25V, VGS = 0V, f = 1MHz VDD = 40V ID = 80A Ig = 1.0mA pF 73 95 - 10 13 nC - 29 - nC - 19 - nC - 16 - nC ns Switching Characteristics (VGS = 10V) tON Turn-On Time - - 147 td(ON) Turn-On Delay Time - 19 - ns tr Rise Time - 79 - ns td(OFF) Turn-Off Delay Time - 37 - ns tf Fall Time - 38 - ns tOFF Turn-Off Time - - 113 ns V V DD = 40V, ID = 80A VGS = 10V, RGS = 3.9 Drain-Source Diode Characteristics ISD = 80A - - 1.25 ISD = 40A - - 1.0 V Reverse Recovery Time ISD = 75A, dISD/dt = 100A/s - - 37 ns Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/s - - 38 nC VSD Source to Drain Diode Voltage trr QRR Notes: 1: Starting TJ = 25C, L = 109H, IAS = 80A. 2: Pulse width = 100s (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Package Marking and Ordering Information 150 1.0 125 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 100 75 50 25 0 0 0 25 50 75 100 150 125 25 175 50 TC , CASE TEMPERATURE (o C) 75 100 125 TC, CASE TEMPERATURE Figure 1. Normalized Power Dissipation vs Ambient Temperature 150 175 (oC) Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x R JC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t , RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TC = 25oC FOR TEMPERATURES TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) 1000 ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 100 70 10-5 10-4 10-3 10-2 10 -1 100 101 t , PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Typical Characteristics TC = 25C unless otherwise noted 1000 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) 10s ID, DRAIN CURRENT (A) 100s 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 TJ = 175o C 75 TJ = 25oC TJ = -55oC VGS = 6V 125 100 75 VGS = 5V 50 TC = 25o C 25 25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 0 6.0 0.5 1.0 1.5 2.0 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 2.5 7.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 7.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE(m) VGS = 7V VGS = 10V 150 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 175 125 50 100 Figure 6. Unclamped Inductive Switching Capability PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 150 0.1 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area 175 1 0.01 100 6.5 VGS = 6V 6.0 5.5 VGS = 10V 5.0 4.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID = 80A 4.0 0 20 40 ID, DRAIN CURRENT (A) 60 80 Figure 9. Drain to Source On Resistance vs Drain Current (c)2002 Fairchild Semiconductor Corporation 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Typical Characteristics TC = 25C unless otherwise noted 1.2 1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 0.9 -80 200 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 7000 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 40V C, CAPACITANCE (pF) CISS = CGS + CGD COSS CDS + C GD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage (c)2002 Fairchild Semiconductor Corporation 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 16A 2 0 75 0 20 40 60 80 Qg, GATE CHARGE (nC) Figure 14. Gate Charge Waveforms for Constant Gate Current FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Typical Characteristics TC = 25C unless otherwise noted VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 19. Switching Time Test Circuit (c)2002 Fairchild Semiconductor Corporation 10% Figure 20. Switching Time Waveforms FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Test Circuits and Waveforms (T -T ) JM A P D M = ----------------------------R JA (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 80 RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 40 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm2 ) (64.5) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA 19.84 ( 0.262 + Area ) = 26.51 + ------------------------------------- (EQ. 2) Area in Inches Squared R JA 128 ( 1.69 + Area ) = 26.51 + ---------------------------------- (EQ. 3) Area in Centimeters Squared (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 Thermal Resistance vs. Mounting Pad Area .SUBCKT FDP060AN08A0 2 1 3 ; rev October 2002 Ca 12 8 2.5e-9 Cb 15 14 2.1e-9 Cin 6 8 4.7e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 82.1 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 5e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 53 RLdrain 2 5 10 RLsource 3 7 50 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 17 18 RVTEMP S2B 13 CB 6 8 5 8 EDS - 19 VBAT + IT 14 + + EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 9e-4 Rgate 9 20 1.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 15 14 13 S1B CA RBREAK - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),5))} .MODEL DbodyMOD D (IS=2E-11 N=1.04 RS=1.76e-3 TRS1=2.7e-3 TRS2=1e-6 + CJO=3.2e-9 M=5.6e-1 TT=3e-10 XTI=3.9) .MODEL DbreakMOD D (RS=3e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.56e-9 IS=1e-30 N=10 M=0.53) .MODEL MmedMOD NMOS (VTO=3.6 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4) .MODEL MstroMOD NMOS (VTO=4.22 KP=220 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1) .MODEL RbreakMOD RES (TC1=9.4e-4 TC2=-9e-7) .MODEL RdrainMOD RES (TC1=2.2e-2 TC2=6e-5) .MODEL RSLCMOD RES (TC1=2e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-6e-3 TC2=-1.6e-5) .MODEL RvtempMOD RES (TC1=-2.4e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 PSPICE Electrical Model rev October 2002 template FDP060AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=1e-6,cjo=3.2e-9,m=5.6e-1,tt=3e-10,xti=3.9) dp..model dbreakmod = (rs=3e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.56e-9,isl=10e-30,nl=10,m=0.53) m..model mmedmod = (type=_n,vto=3.6,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.22,kp=220,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5) DPLCAP 5 DRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8) 2 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) RSLC1 51 c.ca n12 n8 = 2.5e-9 RSLC2 c.cb n15 n14 = 2.1e-9 ISCL c.cin n6 n8 = 4.7e-9 spe.ebreak n11 n7 n17 n18 = 82.1 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE i.it n8 n17 = 1 S1A 12 l.lgate n1 n9 = 5.3e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 5e-9 S2A 13 8 res.rlgate n1 n9 = 53 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 50 15 14 13 S1B CA RBREAK 17 18 RVTEMP S2B 13 CB + 6 8 EGS - 19 IT 14 + VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=9.4e-4,tc2=-9e-7 res.rdrain n50 n16 = 9e-4, tc1=2.2e-2,tc2=6e-5 res.rgate n9 n20 = 1.4 res.rslc1 n5 n51 = 1e-6, tc1=2e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-6e-3,tc2=-1.6e-5 res.rvtemp n18 n19 = 1, tc1=-2.4e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 5)) } } (c)2002 Fairchild Semiconductor Corporation FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 SABER Electrical Model th JUNCTION REV 23 October 2002 FDP060AN08A0T CTHERM1 TH 6 9.6e-3 CTHERM2 6 5 9.7e-3 CTHERM3 5 4 9.8e-3 CTHERM4 4 3 1e-2 CTHERM5 3 2 3e-2 CTHERM6 2 TL 9e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 3.2e-3 RTHERM2 6 5 8.1e-3 RTHERM3 5 4 2.3e-2 RTHERM4 4 3 1.2e-1 RTHERM5 3 2 1.5e-1 RTHERM6 2 TL 1.6e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP060AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9.6e-3 ctherm.ctherm2 6 5 =9.7e-3 ctherm.ctherm3 5 4 =9.8e-3 ctherm.ctherm4 4 3 =1e-2 ctherm.ctherm5 3 2 =3e-2 ctherm.ctherm6 2 tl =9e-2 rtherm.rtherm1 th 6 =3.2e-3 rtherm.rtherm2 6 5 =8.1e-3 rtherm.rtherm3 5 4 =2.3e-2 rtherm.rtherm4 4 3 =1.2e-1 rtherm.rtherm5 3 2 =1.5e-1 rtherm.rtherm6 2 tl =1.6e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2002 Fairchild Semiconductor Corporation CASE FDB060AN08A0 / FDP060AN08A0 Rev. A FDB060AN08A0 / FDP060AN08A0 PSPICE Thermal Model TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FACTTM ActiveArrayTM FACT Quiet SeriesTM BottomlessTM FAST(R) CoolFETTM FASTrTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM I2CTM EnSignaTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM ImpliedDisconnectTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET(R) VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I1