TAS5630
PurePathTM HD
TAS5631
TAS5518
Digital PWM
Processor
DIGITAL
AUDIO
INPUT
♫♪
♫♪
TAS5631
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SLES221C –JULY 2009–REVISED APRIL 2010
300-W STEREO / 600-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
Check for Samples: TAS5631
1FEATURES APPLICATIONS
• Mini Combo System
23• PurePath™ HD Enabled Integrated Feedback
Provides: • AV Receivers
• DVD Receivers
– Signal Bandwidth up to 80 kHz for
High-Frequency Content From HD Sources • Active Speakers
– Ultralow 0.03% THD at 1 W Into 4 ΩDESCRIPTION
– Flat THD at All Frequencies for Natural
Sound The TAS5631 is a high-performance PWM input
class-D amplifier with integrated closed-loop
– 80-dB PSRR (BTL, No Input Signal) feedback technology (known as PurePath HD
– >100-dB (A-weighted) SNR technology) with the ability to drive up to 300 W (1)
– Click- and Pop-Free Start-Up stereo into 4-Ωto 8-Ωspeakers from a single 50-V
supply.
• Multiple Configurations Possible on the Same
PCB With Stuffing Options: PurePath HD technology enables traditional
– Mono Parallel Bridge-Tied Load (PBTL) AB-amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class-D
– Stereo Bridge-Tied Load (BTL) amplifiers.
– 2.1 Single-Ended Stereo Pair and Unlike traditional class-D amplifiers, the distortion
Bridge-Tied Load Subwoofer curve only increases once the output levels move into
– Quad Single-Ended Outputs clipping. PurePath HD™
• Total Output Power at 10% THD+N PurePath HD technology enables lower idle losses,
– 600 W in Mono PBTL Configuration making the device even more efficient.
– 300 W per Channel in Stereo BTL
Configuration Note 1. Achievable output power levels are
– 145 W per Channel in Quad Single-Ended dependent on the thermal configuration of the target
Configuration application. A high-performance thermal interface
material between the package exposed heat slug
• High-Efficiency Power Stage (>88%) With and the heat sink should be used to achieve high
60-mΩOutput MOSFETs output-power levels.
• Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
• Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
• EMI Compliant When Used With
Recommended System Design
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PurePath HD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Not Recommended For New Designs
PIN ONE LOCATION PHD PACKAGE
26
16
15
OC_ADJ
14
RESET
13
C_STARTUP
12
INPUT_A
11
INPUT_B
10
VI_CM
9
GND
8
AGND 7
VREG
6
INPUT_C
5
INPUT_D
4
TEST
3
2
1
SD 64-pins QFP package
32
GND_D
31
PVDD_D
30
PVDD_D
29
OUT_D
28
OUT_D
27
BST_D
GVDD_D
25
GVDD_C
24
GND
23
GND
22 NC
21 NC
20 NC
19 NC
18 PSU_REF
17 VDD
33 GND_D
34 GND_C_
35 GND_C
36 OUT_C
37 OUT_C
38 PVDD_C
39 PVDD_C
40 BST_C
41 BST_B
42 PVDD_B
43 OUT_B
44
GND_B
45
GND_A
46
47
48
55
49
50
51
READY
52
M1
53
M2
54
M3
GND
56
GND
57
GVDD_B
58
GVDD_A
59
BST_A
60
OUT_A
61
OUT_A
62
PVDD_A
63
PVDD_A
64
GND_A
OTW1
CLIP
PVDD_B
OUT_B
GND_B
DKD PACKAGE
(TOP VIEW)
44 pins PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23M3
OC_ADJ
VDD
PSU_REF
M2
M1
READY
OTW
SD
NC
NC TEST
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
RESET
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
OUT_D
PVDD_D
BST_D
GND_D
GVDD_AB
GVDD_CD
PVDD_A
PVDD_D
OUT_D
OUT_A
OTW2
PHD PACKAGE
(TOP VIEW)
Electrical Pin 1
NC
NC
Pin 1 Marker
White Dot
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
Both package types contains a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
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SLES221C –JULY 2009–REVISED APRIL 2010
MODE SELECTION PINS
MODE PINS OUTPUT
PWM INPUT(1) DESCRIPTION
CONFIGURATION
M3 M2 M1
0 0 0 2N 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 2N 2 × BTL BD mode
0 1 1 1N 1 × BTL +2 × SE AD mode
1 0 0 1N 4 × SE AD mode
INPUT_C(2) INPUT_D(2)
2N
1 0 1 1 × PBTL 0 0 AD mode
1N 1 0 BD mode
1 1 0 Reserved
1 1 1
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER TAS5631PHD TAS5631DKD
RqJC (°C/W) – 2 BTL or 4 SE channels 2.63 14
RqJC (°C/W) – 1 BTL or 2 SE channel(s) 4.13 2.04
RqJC (°C/W) – 1 SE channel 6.45 3.45
Pad area (2) 64 mm280 mm2
(1) RqJC is junction-to-case; RqCH is case-to-heatsink.
(2) RqCH is an important consideration. Assume a 2-mil (0.051-mm) thickness of thermal grease with a thermal conductivity of 2.5 W/mK
between the pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and
0.44°C/W for the DKD package.
Table 1. ORDERING INFORMATION(1)
TAPACKAGE DESCRIPTION
0°C–70°C TAS5631PHD 64-pin HTQFP
0°C–70°C TAS5631DKD 44-pin PSOP3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TAS5631 UNIT
VDD to AGND –0.3 to 13.2 V
GVDD to AGND –0.3 to 13.2 V
PVDD_X to GND_X(2) –0.3 to 69 V
OUT_X to GND_X(2) –0.3 to 69 V
BST_X to GND_X(2) –0.3 to 82.2 V
BST_X to GVDD_X(2) –0.3 to 69 V
VREG to AGND –0.3 to 4.2 V
GND_X to GND –0.3 to 0.3 V
GND_X to AGND –0.3 to 0.3 V
GND to AGND –0.3 to 0.3 V
INPUT_X, OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, –0.3 to 4.2 V
PSU_REF to AGND
RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 to 7 V
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA
Maximum operating junction temperature range, TJ0 to 150 °C
Storage temperature, Tstg –40 to 150 °C
Human-body model(3) (all pins) ±2 kV
Electrostatic discharge Charged-device model(3) (all pins) ±500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework contributes to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V
Supply for logic regulators and gate-drive
GVDD_x DC supply voltage 10.8 12 13.2 V
circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 3.5 4
Output filter according to schematics in
RL(SE) Load impedance 1.8 2 Ω
the application information section.
RL(PBTL) 1.6 2
LOUTPUT(BTL) 7 10
LOUTPUT(SE) Output filter inductance Minimum output inductance at IOC 7 15 mH
LOUTPUT(PBTL) 7 10
fPWM PWM frame rate 352 384 500 kHz
TJJunction temperature 0 150 °C
TERMINAL FUNCTIONS
TERMINAL Function(1) DESCRIPTION
NAME PHD NO. DKD NO.
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_A required
BST_B 41 34 P HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_B required
(1) I = Input, O = Output, P = Power
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SLES221C –JULY 2009–REVISED APRIL 2010
TERMINAL FUNCTIONS (continued)
TERMINAL Function(1) DESCRIPTION
NAME PHD NO. DKD NO.
BST_C 40 33 P HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_C required
BST_D 27 24 P HS bootstrap supply (BST); external 0.033-mF capacitor to OUT_D required
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND.
TEST 12 14 I Connect to VREG node
GND 7, 23, 24, 57, 58 9 P Ground
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_B 56 — P Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_C 25 — P Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_D 26 — P Gate drive voltage supply requires 0.1-mF capacitor to AGND.
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-mF capacitor to AGND.
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-mF capacitor to AGND.
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.
NC 13, 14 15, 16 — No connect; pins may be grounded.
OC_ADJ 1 3 O Analog overcurrent programming pin requires resistor to ground.
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 4.7 mF to AGND.
Power-supply input for half-bridge A requires close decoupling of 0.01-mF capacitor in
PVDD_A 50, 51 41, 42 P parallel with 1-mF capacitor to GND_A.
Power-supply input for half-bridge B requires close decoupling of 0.01-mF capacitor in
PVDD_B 42, 43 35 P parallel with 1-mF capacitor to GND_B.
Power-supply input for half-bridge C requires close decoupling of 0.01-mF capacitor in
PVDD_C 38, 39 32 P parallel with 1-mF capacitor to GND_C.
Power-supply input for half-bridge D requires close decoupling of 0.01-mF capacitor in
PVDD_D 30, 31 25, 26 P parallel with 1-mF capacitor to GND_D.
READY 19 19 O Normal operation; open-drain; active-high
RESET 2 4 I Device reset input; active-low
SD 15 17 O Shutdown signal; open-drain, active-low
Power supply for digital voltage regulator requires a 47-mF capacitor in parallel with a
VDD 64 2 P 0.1-mF capacitor to GND for decoupling.
VI_CM 6 8 O Analog comparator reference node requires close decoupling of 4.7 mF to AGND.
VREG 9 11 P Digital regulator supply filter pin requires 0.1-mF capacitor to AGND.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
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Not Recommended For New Designs
2-CHANNEL
H-BRIDGE
BTL MODE
Output
H-Bridge 2
PVDD_A, B, C, D
GND_A, B, C, D
Hardwire
Over-
Current
Limit
8
GND
VDD
VREG
AGND
OC_ADJ
PVDD
Power Supply
Decoupling
GVDD, VDD,
and VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
PVDD
GVDD (12V)/VDD (12V)
GND
50V
12V
GND
VAC
Bootstrap
Caps
BST_C
BST_D
2nd Order
L-C Output
Filter for
each
H-Bridge
OUT_C
OUT_D
GVDD_A, B, C, D
Bootstrap
Caps
BST_A
BST_B
INPUT_A 2nd Order
L-C Output
Filter for
each
H-Bridge
OUT_A
OUT_B
8 4
Output
H-Bridge 1
Input
H-Bridge 1
INPUT_B
M2
M1
M3
Hardwire
Mode
Control
Input
H-Bridge 2
INPUT_C
INPUT_D
VI_CM
C_STARTUP
PSU_REF
Caps for
External
Filtering
and
Startup/Stop
/OTW1, /OTW2, /OTW
/CLIP
System
microcontroller
READY
/SD
PWM_A
PWM_B
PWM_C
PWM_D
2
2
2
2
(2)
TAS5518/
TAS5508/
TAS5086
I2C
Left-
Channel
Output
Right-
Channel
Output
VALID
RESET
TEST
AMP RESET
*NOTE1
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
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TYPICAL SYSTEM BLOCK DIAGRAM
(1) Logic AND is inside or outside the microcontroller.
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M1
M2
RESET
SD
OTW2
AGND
OC_ADJ
VREG
VDD
GVDD_A
M3
GND
INPUT_D
OUT_A
GND_A
PVDD_A
BST_A
GVDD_A
PWM
ACTIVITY
DETECTOR
GVDD_C
GVDD_B
INPUT_C
OUT_B
GND_B
PVDD_B
BST_B
GVDD_B GVDD_D
GVDD_C
OUT_C
GND_C
PVDD_C
BST_C
GVDD_D
OUT_D
GND_D
PVDD_D
BST_D
INPUT_B
INPUT_A
PVDD_X
OUT_X
GND_X
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
TIMING
CONTROL
CONTROL GATE-DRIVE
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
PWM
RECEIVER
+
-
ANALOG COMPARATOR MUX
+
-
+
-
+
-
PROTECTION & I/O LOGIC
VI_CM
STARTUP
CONTROL
POWER-UP
RESET
TEMP
SENSE
OVER-LOAD
PROTECTION
PPSC
CB3C
UVP
CURRENT
SENSE
VREG
C_STARTUP
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG
LOOP FILTER
ANALOG INPUT MUX
AGC
PSU_REF
4
4
4
PVDD_X
4
GND
OTW1
READY
CLIP
TAS5631
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SLES221C –JULY 2009–REVISED APRIL 2010
FUNCTIONAL BLOCK DIAGRAM
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AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL= 4 Ω, fS= 384 kHz, ROC = 22 kΩ, TC= 75°C;
output filter: LDEM = 7 mH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 4 Ω, 10% THD+N, clipped input signal 300
RL= 6 Ω, 10% THD+N, clipped input signal 210
RL= 8 Ω, 10% THD+N, clipped input signal 160
POPower output per channel W
RL= 4 Ω, 1% THD+N, unclipped input signal 240
RL= 6 Ω, 1% THD+N, unclipped input signal 160
RL= 8 Ω, 1% THD+N, unclipped input signal 125
THD+N Total harmonic distortion + noise 1 W 0.03%
VnOutput integrated noise A-weighted, TAS5518 modulator 180 mV
|VOS| Output offset voltage No signal 40 150 mV
SNR Signal-to-noise ratio(1) A-weighted, TAS5518 modulator 103 dB
A-weighted, input level –60 dBFS using TAS5518
DNR Dynamic range 103 dB
modulator
Power dissipation due to idle losses
Pidle PO= 0, four channels switching(2) 3.9 W
(IPVDD_X)
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%)
and a TAS5631 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL= 2 Ω, fS= 384 kHz, ROC = 22 kΩ, TC= 75°C;
output filter: LDEM = 7 mH, CDEM = 470 nF, MODE = 100, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 2 Ω, 10%, THD+N, clipped input signal 145
RL= 3 Ω, 10%, THD+N, clipped input signal 100
RL= 4 Ω, 10%, THD+N, clipped input signal 75
POPower output per channel W
RL= 2 Ω, 1% THD+N, unclipped input signal 110
RL= 3 Ω, 1% THD+N, unclipped input signal 75
RL= 4 Ω, 1% THD+N, unclipped input signal 55
THD+N Total harmonic distortion + noise 1 W 0.04%
VnOutput integrated noise A-weighted, TAS5086 modulator 140 mV
SNR Signal-to-noise ratio(1) A-weighted, TAS5086 modulator 100 dB
A-weighted, input level –60 dBFS using TAS5086
DNR Dynamic range 100 dB
modulator
Pidle Power dissipation due to idle losses (IPVDD_X) PO= 0, 4 channels switching(2) 3 W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
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AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)
and a TAS5631 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio
frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL= 2 Ω, fS= 384 kHz, ROC = 22 kΩ, TC= 75°C;
output filter: LDEM = 7 mH, CDEM = 1 mF, MODE = 101-00, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL= 2 Ω, 10%, THD+N, clipped input signal 600
RL= 3 Ω, 10%, THD+N, clipped input signal 400
RL= 4 Ω, 10%, THD+N, unclipped input signal 300
POPower output per channel W
RL= 2 Ω, 1% THD+N, unclipped input signal 480
RL= 3 Ω, 1% THD+N, unclipped input signal 310
RL= 4 Ω, 1% THD+N, unclipped input signal 230
THD+N Total harmonic distortion + noise 1 W 0.03%
VnOutput integrated noise A-weighted, TAS5518 modulator 170 mV
SNR Signal-to-noise ratio(1) A-weighted, TAS5518 modulator 103 dB
A-weighted, input level –60 dBFS using
DNR Dynamic range 103 dB
TAS5518 modulator
Pidle Power dissipation due to idle losses (IPVDD_X) PO= 0, 4 channels switching(2) 3.7 W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC(case temperature) = 75°C, fS= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 22.5
IVDD VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
IGVDD_x Gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle without output filter or 19.5 mA
load
IPVDD_x Half-bridge idle current Reset mode, no switching 750 mA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ= 25°C, excludes metallization 60 100 mΩ
resistance,
RDS(on) Drain-to-source resistance, high side (HS) 60 100 mΩ
GVDD = 12 V
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC(case temperature) = 75°C, fS= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I/O PROTECTION
Vuvp,G Undervoltage protection limit, GVDD_X 10 V
Vuvp,hyst (1) 0.6 V
OTW1(1) Overtemperature warning 1 95 100 105 °C
OTW2(1) Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW
OTWhyst (1) temperature for OTW to be inactive after 25 °C
OTW event
Overtemperature error 145 155 165 °C
OTE(1) OTE-OTW differential 30 °C
A reset must occur for SD to be released
OTEHYST (1) 25 °C
following an OTE event
OLPC Overload protection counter fPWM = 384 kHz 2.6 ms
Resistor – programmable, nominal peak
current in 1-Ωload, 19 A
64-pin QFP package (PHD)
ROCP = 22 kΩ
Overcurrent limit response Resistor – programmable, nominal peak
current in 1-Ωload,
IOC 19 A
44-pin PSOP3 package (DKD)
ROCP = 24 kΩ
Resistor – programmable, nominal peak
current in 1-Ωload,
Overcurrent response time, latched 19 A
ROCP = 47 kΩ
Time from application of short condition to
IOCT Overcurrent response time 150 ns
Hi-Z of affected half-bridge
Connected when RESET is active to
Internal pulldown resistor at output of each
IPD provide bootstrap charge. Not used in SE 3 mA
half-bridge mode.
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
VIL Low-level input voltage 1.45 V
Ilkg Input leakage current 100 mA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW1 to VREG,
RINT_PU 20 26 33 kΩ
OTW2 to VREG, SD to VREG Internal pullup resistor 3 3.3 3.6
VOH High-level output voltage V
External pullup of 4.7 kΩto 5 V 4.5 5
VOL Low-level output voltage IO= 4 mA 200 500 mV
Device fanout OTW1, OTW2, SD, CLIP,
FANOUT No external pullup 30 devices
READY
(1) Specified by design
10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
320
25 5030 35 40 45
PVDD-SupplyVoltage-V
P -OutputPower-W
O
T =75°C
THD+Nat10%
C
4W
6W
8W
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 400100m200m 1 2 5 10 20 50 100
THD+N-TotalHarmonicDistortion+Noise-%
P -OutputPower-W
O
4W
6W
8W
T =75°C
C
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
25 5030 35 40 45
P -OutputPower-W
O
T =75°C
C
4W
6W
8W
0
100
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
0600
100 200 300 400 500
2ChannelOutputPower-W
Efficiency-%
650
T =25°C
THD+Nat10%
C
4W
6W
8W
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
Figure 1. Figure 2.
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY
vs vs
SUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TAS5631
Not Recommended For New Designs
0
100
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0 650100 200 300 400 500
2ChannelOutputPower-W
PowerLoss-W
T =25°C
THD+Nat10%
C
4W
8W
6W
600
80
85
90
95
-160
+0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0k 4k 6k 8k 10k 12k 14k 16k 18k 22k
f-Frequency-Hz
Noise Amplitude-dB
2k 20k
T =75°C,
V =31.7V,
SampleRate=48kHz,
FFTSize=16384
C
REF
4W
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEMS POWER LOSS OUTPUT POWER
vs vs
OUTPUT POWER CASE TEMPERATURE
Figure 5. Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
Figure 7.
12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 1 2 10 20 100
P -OutputPower-W
O
THD+N-TotalHarmonicDistortion+Noise-%
4W
3W
T =75°C
C
2W
200200m
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
25 5030 35 40 45
PVDD-SupplyVoltage-V
P -OutputPower-W
O
T =75°C
THD+Nat10%
C
4W
3W
2W
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
10 12020 30 40 50 60 70 80 90 100 110
P -OutputPower-W
O
T -CaseTemperature-°C
C
THD+Nat10%
4W
3W2W
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC dISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
Figure 8. Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
Figure 10.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TAS5631
Not Recommended For New Designs
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 700100m 200m 1 2 5 10 20 50 100 200
THD+N-TotalHarmonicDistortion+Noise-%
P -OutputPower-W
O
TTTTTTTT
T =75°C
C
4W
3W
2 (T =50 C)WC
o
6W
8W
0
650
50
100
150
200
250
300
350
400
450
500
550
600
25 5030 35 40 45
PVDD-SupplyVoltage-V
P -OutputPower-W
O
T =75°C
THD+Nat10%
C
6W
8W
4W
3W
2 (T =50 C)WC
o
0
700
50
100
150
200
250
300
350
400
450
500
550
600
650
10 12020 30 40 50 60 70 80 90 100 110
P -OutputPower-W
O
T -CaseTemperature-°C
C
THD+Nat10%
6W
8W
4W
3W
2W
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
Figure 11. Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
Figure 13.
14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 2-oz. (70 mm) glass epoxy material is recommended for use with the TAS5631. The use of this material can
provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace
inductance).
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well-designed system power supply, 1000 mF, 63 V support more applications.
The PVDD capacitors should be the low-ESR type because they are used in a circuit associated with high-speed
switching.
DECOUPLING CAPACITOR RECOMMENDATION
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good-quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1-mF capacitor that is placed on the power supply to each half-bridge. It must withstand the
voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the
ripple current created by high power output. A minimum voltage rating of 63 V is required for use with a 50-V
power supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5631.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TAS5631
Not Recommended For New Designs
IN_LEFT_N
IN_LEFT_P
R_RIGHT_N
IN_RIGHT_P
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
GVDD/VDD(+12V)
PVDD
GVDD/VDD(+12V)
PVDD
PVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
GND
GND
GND
GND
GND
GND
VREG
VREG
GND
GND
GND
GND
GND
VREG
GND
OUT_LEFT_M
OUT_LEFT_P
+
-
OUT_RIGHT_R
OUT_RIGHT_P
+
-
C53
680nF
C53
680nF
C78
10nF
C78
10nF
C18
100pF
C18
100pF
C42
33nF
C42
33nF
L10
7uH
L10
7uH
C52
680nF
C52
680nF
L11
7uH
L11
7uH
R74
3.3R
R74
3.3R
C69
2.2uF
C69
2.2uF
L13
7uH
L13
7uH
C40
33nF
C40
33nF
L12
7uH
L12
7uH
C60
2.2uF
C60
2.2uF
R10
100R
R10
100R
C32
100nF
C32
100nF
R19
47k
R19
47k
R33
3.3R
R33
3.3R
C62
2.2uF
C62
2.2uF
C76
10nF
C76
10nF
C77
10nF
C77
10nF
R73
3.3R
R73
3.3R
C50
680nF
C50
680nF
C25
10uF
C25
10uF
C33
100nF
C33
100nF
C20
4.7nF
C20
4.7nF
R72
3.3R
R72
3.3R
C61
2.2uF
C61
2.2uF
R20
22.0k
R20
22.0k
C67
1000uF
C67
1000uF
C30
100nF
C30
100nF
C63
2.2uF
C63
2.2uF
U10
TAS5631PHD
U10
TAS5631PHD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
C21
4.7uF
C21
4.7uF
C72
1nF
C72
1nF
C22
100nF
C22
100nF
R31
3.3R
R31
3.3R
C31
100nF
C31
100nF
R18
100R
R18
100R
R70
3.3R
R70
3.3R
R11
100R
R11
100R
C71
1nF
C71
1nF
C66
1000uF
C66
1000uF
C65
1000uF
C65
1000uF
R30
3.3R
R30
3.3R
R71
3.3R
R71
3.3R
C73
1nF
C73
1nF
C23
4.7uF
C23
4.7uF
R32
3.3R
R32
3.3R
C70
1nF
C70
1nF
C41
33nF
C41
33nF
C26
100nF
C26
100nF
R13
100R
R13
100R
C68
47uF
63V
C68
47uF
63V
R12
100R
R12
100R
C51
680nF
C51
680nF
C75
10nF
C75
10nF
C74
10nF
C74
10nF
C43
33nF
C43
33nF
C64
1000uF
C64
1000uF
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
Figure 14. Typical Differential (2N) BTL Application With BD Modulation Filters
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
IN_N
IN_P
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
GVDD(+12V)
PVDD
GVDD(+12V)
VDD(+12V)
PVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
GND GND
VREG
GND GND GND
GND
GND
GND
VREG
VREG
GND
GND
GND
GND
GND
VREG
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OUT_LEFT_M
OUT_LEFT_P
+
-
3.3R3.3R
100nF100nF
4.7nF4.7nF
100nF100nF
1000uF1000uF
100nF100nF
4.7uF4.7uF
1000uF1000uF
TAS5631PHDTAS5631PHD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
7uH7uH
3.3R3.3R
2.2uF2.2uF
47k47k
100nF100nF
1nF1nF
3.3R3.3R
33nF33nF
3.3R3.3R
7uH7uH
1000uF1000uF
10nF10nF
3.3R3.3R
100R100R
4.7uF4.7uF
100R100R
1uF1uF
1uF1uF
47uF47uF
1nF1nF
10uF10uF
10nF10nF
100nF100nF 33nF33nF 7uH7uH
2.2uF2.2uF
100R100R
3.3R3.3R
33nF33nF
3.3R3.3R
2.2uF2.2uF
10nF10nF
22.0k22.0k
2.2uF2.2uF
33nF33nF
100nF100nF
100pF100pF
1000uF1000uF
2.2uF2.2uF
7uH7uH
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
Figure 15. Typical (2N) PBTL Application With AD Modulation Filters
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TAS5631
Not Recommended For New Designs
IN_B
IN_A
IN_D
IN_C
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
PVDD
A
PVDD
B
PVDD
C
PVDD
D
A
B
C
D
GVDD(+12V)
PVDD
GVDD(+12V)
VDD(+12V)
PVDD
PVDD
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
VREG
GND GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
VREG
VREG
GND
62
17
6318
64
19
20
21
24
23
22
25
27
26
29
28
30
31
32
33
34
1
35
37
2
36
3
38
4
39
5
6
40
41
742
8
9
10
43
44
45
11
46
12
47
13
48
14
15
49
16
50
51
52
54
53
56
55
57
58
59
60
61
OUT_B_M
OUT_B_P
OUT_D_M
OUT_D_P
OUT_C_M
OUT_C_P
OUT_A_M
OUT_A_P
PVDD R_COMP
50V
49V
48V
<47V
169kOhm
150kOhm
191kOhm
191kOhm
+
-
+
-
+
-
+
-
47V
196kOhm
7uH7uH
2.2uF2.2uF
2.2uF2.2uF
100nF100nF
3.3R3.3R
470uF470uF
470uF470uF
10nF10nF
470uF470uF
470uF470uF
33nF33nF
7uH7uH
3.3R3.3R
100R100R
47uF47uF
10k10k
3.3R3.3R
10nF10nF
470uF470uF
3.3R3.3R
100nF100nF
470nF470nF
TAS5631PHDTAS5631PHD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
100nF100nF
100R100R
7uH7uH
22.0k22.0k
100nF100nF
4.7uF4.7uF
10uF10uF
100nF100nF
10k10k
R_COMPR_COMP
R_COMPR_COMP
10k10k
3.3R3.3R
470nF470nF
3.3R3.3R
470uF470uF
100nF100nF
3.3R3.3R
10nF10nF
3.3R3.3R
10nF10nF
10k10k
100nF100nF
R_COMPR_COMP
10k10k
R_COMPR_COMP
47k47k
4.7uF4.7uF
100nF100nF
10k10k
10k10k
100R100R
2.2uF2.2uF
100nF100nF
100R100R
100nF100nF
10nF10nF
470nF470nF
10nF10nF
7uH7uH
3.3R3.3R
10k10k
10k10k
10nF10nF
100pF100pF
100nF100nF
2.2uF2.2uF
470uF470uF
10k10k
10k10k 470nF470nF
3.3R3.3R
33nF33nF
470uF470uF
3.3R3.3R
100nF100nF 33nF33nF
10nF10nF
10k10k
100nF100nF
2.2uF2.2uF
10nF10nF
100nF100nF
100R100R
10nF10nF
3.3R3.3R
33nF33nF
3.3R3.3R
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
Figure 16. Typical SE Application
18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
IN_CENTER
IN_RIGHT
IN_LEFT
/RESET
/SD
/OTW1
/OTW2
/CLIP
READY
GVDD(+12V)
PVDD
GVDD(+12V)
VDD(+12V)
PVDD
PVDD
PVDD
PVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
VREG
GND
GND GND
VREG
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
VREG
62
17
6318
64
19
20
21
24
23
22
25
27
26
29
28
30
31
32
33
34
1
35
37
2
36
3
38
4
39
5
6
40
41
742
8
9
10
43
44
45
11
46
12
47
13
48
14
15
49
16
50
51
52
54
53
56
55
57
58
59
60
61
OUT_CENTER_M
OUT_CENTER_P
OUT_LEFT_P
OUT_RIGHT_P
OUT_LEFT_M
OUT_RIGHT_M
-
+
-
+
-
+
47V
196kOhm
PVDD R_COMP
50V
49V
48V
<47V
169kOhm
150kOhm
191kOhm
191kOhm
100nF100nF
100nF100nF
10uF10uF
10k10k
100nF100nF
3.3R3.3R
10k10k
100pF100pF
R_COMPR_COMP
470nF470nF
100nF100nF
10nF10nF
470uF470uF
100nF100nF
1000uF1000uF
100nF100nF
100nF100nF
4.7uF4.7uF
10nF10nF
470uF470uF
10k10k
10k10k
3.3R3.3R
47uF47uF
3.3R3.3R
10k10k
2.2uF2.2uF
470nF470nF
10nF10nF
7uH7uH
TAS5631PHD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
/SD
/OTW1
/OTW2
/CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
3.3R3.3R
680nF680nF
R_COMPR_COMP
33nF33nF
470uF470uF
3.3R3.3R
10nF10nF
10nF10nF
1nF1nF
3.3R3.3R
100R100R 3.3R3.3R
47k47k
2.2uF2.2uF
7uH7uH
33nF33nF
100nF100nF
100nF100nF
100R100R
3.3R3.3R
100nF100nF
3.3R3.3R
100R100R
2.2uF2.2uF
2.2uF2.2uF
10nF10nF
10nF10nF
2.2uF2.2uF
1nF1nF
680nF680nF
33nF33nF
7uH7uH
33nF33nF
10nF10nF
22.0k22.0k
100R100R
7uH7uH
1000uF1000uF
470uF470uF
3.3R3.3R
4.7uF4.7uF
3.3R3.3R
10k10k
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TAS5631
Not Recommended For New Designs
IN_LEFT_N
IN_LEFT_P
IN_RIGHT_N
IN_RIGHT_P
/SD
/OTW
READY
GVDD(+12V)
PVDD
GVDD(+12V)
VDD(+12V)
PVDD
PVDD
/RESET
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREG
GND
GND
GND
GND
GND
GND
VREG
GND
GND
VREG
GND
GND
VREG
OUT_LEFT_M
OUT_LEFT_P
OUT_RIGHT_M
OUT_RIGHT_P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
34
35
36
37
38
39
40
41
42
43
44
23
24
25
26
27
28
29
30
31
32
+
-
+
-
24k24k
1.5R1.5R
100nF100nF
7uH7uH
33nF33nF
10nF10nF
7uH7uH
33nF33nF
1.5R1.5R
4.7nF4.7nF
10nF10nF
4.7uF4.7uF
100nF100nF
680nF680nF
1nF1nF
100nF100nF
47uF47uF
100nF100nF
680nF680nF
1000uF1000uF
3.3R3.3R
2.2uF2.2uF
TAS5631DKDTAS5631DKD
PSU_REF
VDD
OC_ADJ
/RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
NC
NC
/OTW OUT_D
OUT_D
GND_D
GND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
OUT_A
/SD
GVDD_AB
BST_A
PVDD_A
PVDD_A
M1
M2
M3 GVDD_CD
BST_D
PVDD_D
READY PVDD_D
100R100R
1nF1nF
10nF10nF
47k47k
33nF33nF
100R100R
2.2uF2.2uF
2.2uF2.2uF 1000uF1000uF
100pF100pF
3.3R3.3R
2.2uF2.2uF
10uF10uF
3.3R3.3R
3.3R3.3R
1nF1nF
100nF100nF
100R100R
1000uF1000uF
10nF10nF
680nF680nF
100R100R
4.7uF4.7uF
7uH7uH
680nF680nF
2.2uF2.2uF
10nF10nF
3.3R3.3R
100nF100nF
100R100R
33nF33nF
7uH7uH
1nF1nF
1000uF1000uF
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
Figure 18. Typical Differential Input BTL Application With BD Modulation Filters, DKD Package
20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5631 needs only a 12-V supply in addition to the (typical) 50-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path, including gate drive and
output stage, is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate-drive supply pins (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as a supply for all common circuits. Although supplied from the
same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 4000 kHz, it is recommended to use 33-nF ceramic
capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage,
even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during
the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2-mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5631 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5631 is fully protected against
erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5631 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5631 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TAS5631
Not Recommended For New Designs
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
ERROR REPORTING
The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
OTW2,
SD OTW1 DESCRIPTION
OTW
0 0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
0 0 1 warning)
0 1 1 Overload (OLP) or undervoltage (UVP)
1 0 0 Junction temperature higher than 125°C (overtemperature warning)
1 0 1 Junction temperature higher than 100°C (overtemperature warning)
1 1 1 Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the SD signal high, independent of faults being present. TI recommends
monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning
signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown
(OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5631 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5631 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device functions on errors, as shown in the following table.
BTL Mode PBTL Mode SE Mode
Local Error In Turns Off Local Error In Turns Off Local Error In Turns Off
A A A
A+B A+B
B B B
A+B+C+D
C C C
C+D C+D
D D D
Bootstrap UVP does not shut down according to the table; it shuts down the respective half-bridge.
PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup, i.e., when VDD is supplied; consequently, a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the
start-up sequence and starts switching. The detection is controlled globally by a two-step sequence. The first
step ensures that there are no shorts from OUT_X to GND_X; the second step tests that there are no shorts
from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the
22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
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Not Recommended For New Designs
TAS5631
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SLES221C –JULY 2009–REVISED APRIL 2010
output LC filter. The typical duration is <15 ms/mF. While the PPSC detection is in progress, SD is kept low, and
the device does not react to changes applied to the RESET pin. If no shorts are present, the PPSC detection
passes, and SD is released. A device reset does not start a new PPSC detection. PPSC detection is enabled in
BTL and PBTL output configurations; the detection is not performed in SE mode. To make sure not to trip the
PPSC detection system, it is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual overtemperature protection schemes.
PHD Package
The TAS5631 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5631 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5631 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical Characteristics
table. Although GVDD_X and VDD are independently monitored, a supply-voltage drop below the UVP threshold
on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high-impedance state when
asserting the reset input low. Asserting the reset input low removes any fault information to be signaled on the
SD output, i.e., SD is forced high. A rising-edge transition on the reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than
4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATIONS
A rising-edge transition on the reset input allows the device to execute the startup sequence and start switching.
Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible
artifacts that are heard in the output transducers. If an overcurrent protection event is introduced, the READY
signal goes low; hence, filtering is needed if the signal is intended for audio muting in non-microcontroller
systems.
The CLIP signal indicates that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device inverts the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TAS5631
Not Recommended For New Designs
TAS5631
SLES221C –JULY 2009–REVISED APRIL 2010
www.ti.com
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low-impedance and -inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high, fast-switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
for the audio input should be kept short and together with the accompanying audio source ground. It is important
to keep a solid local ground area underneath the device to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 14.
Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins;
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink must have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range, and preferably metal film types.
Figure 19. Printed Circuit Board – Top Layer
24 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5631
Not Recommended For New Designs
TAS5631
www.ti.com
SLES221C –JULY 2009–REVISED APRIL 2010
Note B1: It is important to have a direct, low-impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short low-inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors
Figure 20. Printed Circuit Board – Bottom Layer
REVISION HISTORY
Changes from Original (July 2009) to Revision A Page
• Deleted Product Preview from the PHD package ................................................................................................................. 3
Changes from Revision A (September 2009) to Revision B Page
• Changed OLPC - Overload protection counter TYP value From: 1.3 To: 2.6 ms .............................................................. 10
Changes from Revision B (January 2010) to Revision C Page
• Deleted text form the last paragraph of the DESCRIPTION: Coupled with TI’s class-G power-supply reference
design for TAS563x, industry-leading levels of efficiency can be achieved. ........................................................................ 1
• Changed the front page illustration ....................................................................................................................................... 1
• Changed Pin 41 From BST_C To BST_B in the PHD PACKAGE ....................................................................................... 2
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TAS5631
Not Recommended For New Designs
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TAS5631DKD NRND HSSOP DKD 44 29 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5631DKDR NRND HSSOP DKD 44 500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TAS5631PHD NRND HTQFP PHD 64 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-5A-260C-24 HR
TAS5631PHDR NRND HTQFP PHD 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-5A-260C-24 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5631DKDR HSSOP DKD 44 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1
TAS5631PHDR HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5631DKDR HSSOP DKD 44 500 367.0 367.0 45.0
TAS5631PHDR HTQFP PHD 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
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