CY62147EV30 MoBL®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05440 Rev. *J Revised January 31, 2011
Features
■Very high speed: 45 ns
■Temperature ranges
❐Industrial: –40 °C to +85 °C
■Wide voltage range: 2.20 V to 3.60 V
■Pin compatible with CY62147DV30
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 7 A (Industrial)
■Ultra low active power
❐Typical active current: 2 mA at f = 1 MHz
■Easy memory expansion with CE [1] and OE features
■Automatic power-down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 48-ball very fine ball grid array (VFBGA)
(single/dual CE option) and 44-pin thin small outline package
(TSOP) II packages
■Byte power-down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH or both BLE and BHE are HIGH). The input and output pins
(I/O0 through I/O15) are placed in a high impedance state when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
256K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
[1]
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
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CY62147EV30 MoBL®
Document Number: 38-05440 Rev. *J Page 2 of 16
Contents
Product Portfolio ..............................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 4
Thermal Resistance...........................................................5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................6
Switching Waveforms ......................................................7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
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Pin Configuration
Figure 1. 48-Ball VFBGA (Single Chip Enable) [3, 4] Figure 2. 48-Ball VFBGA (Dual Chip Enable)[3, 4]
Figure 3. 44-Pin TSOP II [3]
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (A)
f = 1 MHz f = fmax
Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max
CY62147EV30LL Industrial 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
NC
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
NC NC
326
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
A
17
WE
A11
A10
A6
A0
A3CE1
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
A7
I/O0
BHE
CE2
A2
A1
BLE
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
A17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
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CY62147EV30 MoBL®
Document Number: 38-05440 Rev. *J Page 4 of 16
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential ..........................–0.3 V to + 3.9 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High Z state [5, 6] ..............–0.3 V to 3.9 V (VCCmax + 0.3 V)
DC input voltage [5, 6] ........... –0.3 V to 3.9 V (VCCmax + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage .......................................... >2001 V
(MIL-STD-883, method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Device Range Ambient
Temperature VCC [7]
CY62147EV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Industrial) Unit
Min Typ [8] Max
VOH Output HIGH
voltage
IOH = –0.1 mA 2.0 – – V
IOH = –1.0 mA, VCC > 2.70 V 2.4 – – V
VOL Output LOW
voltage
IOL = 0.1 mA – – 0.4 V
IOL = 2.1 mA, VCC = 2.70 V – – 0.4 V
VIH Input HIGH
voltage
VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V
VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 V
VIL Input LOW
voltage
VCC = 2.2 V to 2.7 V –0.3 – 0.6 V
VCC= 2.7 V to 3.6 V –0.3 – 0.8 V
IIX Input leakage
current
GND < VI < VCC –1 – +1 A
IOZ Output leakage
current
GND < VO < VCC, output disabled –1 – +1 A
ICC VCC operating
supply current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
CMOS levels
–15 20mA
f = 1 MHz – 2 2.5
ISB1 Automatic CE
power-down
current — CMOS
inputs
CE > VCC – 0.2 V
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–1 7 A
ISB2 [9] Automatic CE
power-down
current — CMOS
inputs
CE > VCC – 0.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–1 7 A
Capacitance
For all packages.[10]
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output capacitance 10 pF
Notes
5. VIL(min) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
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CY62147EV30 MoBL®
Document Number: 38-05440 Rev. *J Page 5 of 16
Thermal Resistance[11]
Parameter Description Test Conditions VFBGA
Package
TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
75 77 C / W
JC Thermal resistance
(junction to case)
10 13 C / W
Figure 4. AC Test Load and Waveforms
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [12] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR[13] Data retention current VCC= 1.5 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–0.87A
tCDR [11] Chip deselect to data retention time 0 – – ns
tR [14] Operation recovery time 45 – – ns
Figure 5. Data Retention Waveform[15, 16]
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
ALL INPUT PULSES
RTH
R1
Equivalent to: THEVENIN EQUIVALENT
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE
Notes
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating..
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
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CY62147EV30 MoBL®
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Switching Characteristics
Over the Operating Range [17, 18]
Parameter Description 45 ns (Industrial) Unit
Min Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid – 45 ns
tDOE OE LOW to data valid – 22 ns
tLZOE OE LOW to LOW Z[19] 5–ns
tHZOE OE HIGH to High Z[19, 20] –18ns
tLZCE CE LOW to Low Z[19] 10 – ns
tHZCE CE HIGH to High Z[19, 20] –18ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down – 45 ns
tDBE BLE/BHE LOW to data valid – 45 ns
tLZBE BLE/BHE LOW to Low Z[19] 10 – ns
tHZBE BLE/BHE HIGH to HIGH Z[19, 20] –18ns
Write Cycle[21]
tWC Write cycle time 45 – ns
tSCE CE LOW to write end 35 – ns
tAW Address setup to write end 35 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 – ns
tBW BLE/BHE LOW to write end 35 – ns
tSD Data setup to write end 25 – ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High Z[19, 20] –18ns
tLZWE WE HIGH to Low Z[19] 10 – ns
Notes
17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 5.
18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 6. Read Cycle No. 1: Address Transition Controlled[22, 23]
Figure 7. Read Cycle No. 2: OE Controlled[23, 24, 25]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
22. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
23. WE is HIGH for read cycle.
24. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1
and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
25. Address valid before or similar to CE and BHE, BLE transition LOW.
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Figure 8. Write Cycle No. 1: WE Controlled[26, 27, 28, 29]
Figure 9. Write Cycle No. 2: CE Controlled[26, 27, 28, 29]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 30
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 30
Notes
26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1
and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
27. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
28. Data I/O is high impedance if OE = VIH.
29. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
30. During this period, the I/Os are in output state. Do not apply input signals.
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CY62147EV30 MoBL®
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Figure 10. Write Cycle No. 3: WE Controlled, OE LOW[31, 32]
Figure 11. Write Cycle No. 4: BHE/BLE Controlled, OE LOW[31, 32]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 33
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 33
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
31. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
32. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
33. During this period, the I/Os are in output state. Do not apply input signals.
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CY62147EV30 MoBL®
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Truth Table
CE[34, 35] WE OE BHE BLE I/Os Mode Power
H X X X X High Z Deselect/Power-down Standby (ISB)
L X X H H High Z Deselect/Power -down Standby (ISB)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write Active (ICC)
Notes
34. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and
CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
35. For the Dual Chip Enable device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all
other cases CE is HIGH. Intermediate voltage levels is not permitted on any of the Chip Enable pins (CE for the Single Chip Enable device; CE1 and CE2 for the Dual
Chip Enable device).
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CY62147EV30 MoBL®
Document Number: 38-05440 Rev. *J Page 11 of 16
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62147EV30LL-45BVI 51-85150 48-Ball Very Fine Pitch Ball Grid Array [36] Industrial
CY62147EV30LL-45BVXI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [36]
CY62147EV30LL-45B2XI 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [37]
CY62147EV30LL-45ZSXI 51-85087 44-Pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Notes
36. This BGA package is offered with single chip enable.
37. This BGA package is offered with dual chip enable.
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Package Diagrams
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
51-85150 *F
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Acronyms Document Conventions
Units of Measure
Figure 13. 44-Pin TSOP II, 51-85087
Package Diagrams (continued)
51-85087 *C
Acronym Description
CMOS complementary metal oxide semiconductor
I/O input/output
SRAM static random access memory
VFBGA very fine ball grid array
TSOP thin small outline package
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliampere
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
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Document History Page
Document Title: CY62147EV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05440
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 201861 AJU 01/13/04 New Data Sheet
*A 247009 SYT See ECN Changed from Advanced Information to Preliminary
Moved Product Portfolio to Page 2
Changed Vcc stabilization time in footnote #8 from 100 s to 200 s
Removed Footnote #15(tLZBE) from Previous Revision
Changed ICCDR from 2.0 A to 2.5 A
Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to
18 ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
for 45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B 414807 ZSD See ECN Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin, “L” version of CY62147EV30
Changed ball E3 from DNU to NC.
Removed redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from
2.5 A to 7 A.
Changed ICCDR from 2.5 A to 7 A.
Added ICCDR typical value.
Changed AC test load capacitance from 50 pF to 30 pF on Page #4, changed
tLZOE from 3 ns to 5 ns, changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns,
changed tHZCE from 22 ns to 18 ns, changed tPWE from 30 ns to 35 ns and
changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name column
with Package Diagram.
*C 464503 NXR See ECN Included Automotive Range in product offering
Updated the Ordering Information
*D 925501 VKN See ECN Added Preliminary Automotive-A information
Added footnote #9 related to ISB2 and ICCDR
Added footnote #14 related AC timing parameters
*E 1045701 VKN See ECN Converted Automotive-A and Automotive -E specs from preliminary to final
*F 2577505 VKN/PYRS 10/03/08 Added -45B2XI part (Dual CE option)
*G 2681901 VKN/PYRS 04/01/09 Added CY62147EV30LL-45ZSXA in the ordering information table
*H 2886488 AJU 03/02/2010 Updated package diagrams.
Added Contents.
Updated links in Sales, Solutions, and Legal Information.
Added Note 23.
*I 3109050 12/13/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
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CY62147EV30 MoBL®
Document Number: 38-05440 Rev. *J Page 15 of 16
*J 3123973 RAME 01/31/2011 Separated Industrial and Auto parts from this datasheet
Removed Automotive info
Added Acronyms and Units of Measure table
Document Title: CY62147EV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05440
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
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Document Number: 38-05440 Rev. *J Revised January 31, 2011 Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY62147EV30 MoBL®
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