(INTERSIL AD7523 8 Bit Monolithic Multiplying D/A Converters FEATURES 8, 9 and 10 bit linearity Low gain and linearity Tempcos Full temperature range operation Full input static. protection e DTL/TTL/CMOS compatible e +5 to +15 volts supply range Fast settling time: 100 nS Four quadrant multiplication 883B Processed versions available GENERAL DESCRIPTION The Intersil AD7523 is a monolithic, low cost, high performance, 10 bit accurate, multiplying digital-to-analog converter (DAC), in a 16-pin DIP. Intersils thin-film resistors on CMOS circuitry provide 8-bit resolution (8, 9 and 10-bit accuracy), with DTL/TTL/CMOS compatible operation. Intersil AD7523s accurate four quadrant multiplication, full military temperature range operation, full input protection from damage due to static discharge by clamps to V+ and GND and very low power dissipation make it a very versatile converter. Low noise audio gain control, motor speed control, digitally controlled gain and attenuators are a few of the wide number of applications of the 7523. FUNCTIONAL DIAGRAM. 10K1) 10KQ) 40Ki) 10K) VeeriN | PIN CONFIGURATION out (1) ouTz2 [2] 16] RreeDBack lout (2) 1 ' NM ! tt SWITCHES tours (1) ' 4 4 4 tee en RFEepBack MSB BIT2 BITS (16) (4) (5) (6) (Switches shown for Digital-Inputs High) ano [3] [14] V+ Biti(mse)(4| AD7523_ [13] Nc BiT 2 (5] NC BiT 3 [6 | BIT4 BIT5 [3] TOP VIEW OUTLINE DRAWINGS DE,PE ORDERING INFORMATION Temperature Range Nonlinearity | 0C to +70C|- 20C to + 85C} -55C to +125C 0.2% (8 Bit) AD7523JN AD7523AD AD7523SD 0.1% (9 Bit) AD7523KN AD7523BD AD7523TD 0.05% : (10 Bit) AD7523LN AD7523CD AD7523UD AD7523 T o L Package D 18-Pin Ceramic DIP N 18-Pin Plastic DIP Nonlinearity and Range 4,K,L - Commerctal 0C to + 70C A,B,C Indu S$,7,U Milttery 58C to +125C Basic Part Number 4-74AD7523 INTERSIL ABSOLUTE MAXIMUM RATINGS (Ta = 25C unless otherwise noted) Ceramic VT cee cee cece en tbe been bee eet en eee +17V TV) 0 Co Ao ie 450mW A +25V derates above 75C DY: ... cece eee eee ee eens 6mw/?C Digital Input Voltage Range ............-..66- ~0.3to VDD Operating Temperatures : Output Voltage Compliance ...........06ee -0:3 to VOD JN, KN, LN Versions .......-00- cece eee 0C to+70C Power Dissipation (package) AD, BD, CD Versions ..........6+..eee ~25C to+86C Plastic SD, TD, UD Versions .......-...-4055 -55C to +125C UPTOF7OS 2. ccc cece cece eee e eet e eee 670mWw Storage Temperature .......---0.000- 65C to +150C derates above +70C by ......---. cece eee 8.3mW/C Lead Temperature (soldering, 10 seconds) ...... +300 C CAUTION: 1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. 2. Do not apply voltages higher than VDD and lower than GND to any terminal except Vaer + Res. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica- tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS (v+ = +15V, Vref= + 10V unless otherwise specified) _TA TA PARAMETER . +25C | MIN-MAX UNITS LIMIT TEST CONDITIONS DC ACCURACY (Note 1) Resolution 8 8 Bits : Min Nonlinearity (Note 2) (+1/2 LSB) +0.2 +0.2 % of FSR Max (+1/4 LSB) +0.1 +0.1 % of FSR Max 10V <Vrer = +10V (+1/8LSB) +0.05 +0.05 % of FSR Max | Vout1 = Vout2 =0V Monotonicity Guaranteed Gain Error (Note 2) +15 +1.8 % of FSR Max Digital inputs high. Nonlinearity Tempco (Note 2 and 3) 2 PPM of FSA/C Max -10V Vrer + 10V " Gain Error Tempco (Note 2 and 3) 10 PPM of FSR/C Max : Output Leakage Current (either output) +50 +200 nA Max Voutt = Vout2 = 0 AC ACCURACY (Note 3) Power Supply Rejection (Note 2) 0.02 0.03 % ot FSR/% Max vt = 14.0 to 15.0V Output Current Settling Time 150 - 200 ns Max To 0.2% of FSR, Ri = 1000 Feedthrough Error +1/2 + LSB Max Vrer = 20V pp, 200KHz sine wave. All . digital inputs low. REFERENCE INPUT 5K Min Input Resistance (Pin 15) 20K a Max | All digital inputs high. lout: at ground. Temperature Coefficient (Note 3) -500 ppm/?C Max ANALOG OUTPUT (Note 3) Both outputs. Voltage Compliance (Note 4) 100mvV to Vt See maximum ratings. Output Capacitance CouT1 100 pF Max || All digital inputs high (VINH) Cout2 30 pF Max CouT1 30 pF Max All digital inputs low (VINL) Coutz 100 pF Max . DIGITAL INPUTS Low State Threshold (Vini) 0.8 Vv Max | Guarantees DTL/TTL and CMOS (0.5 High State Threshold (Vi) 2.4 Vv Min max, 14.5 min) levels Input Current (per input) +1 uA Max Vin = OV. or +15V Input Coding Binary/OffSet Binary See Tables 1 & 2 Input Capacitance (Note 3) 4 pF Max POWER REQUIREMENTS Accuracy is tested and guaranteed at Power Supply Voltage Range +5 to +16 Vv vt = +15V, only. (+ 100 BA Max /] All digital inputs low or high. NOTES: 1. Full scale range (FSR) is 10V for unipolar and +10V for bipolar modes. Specifications subject to 2. Using internal feedback resistor, RFEEDBACK. change without notice. 3. Guaranteed by design; not subject to test. 4. Accuracy not guaranteed unless outputs at ground potential. 4-75AD7523 APPLICATIONS INTERSIL DIGITAL INPUT ANALOG OUTPUT UNIPOLAR OPERATION MSB_ LSB 110 +15V NOTES: 11111111 -VREF ( 258) VREF 1, R1 AND R2 USED ONLY IF GAIN 256. ADJUSTMENT IS REQUIRED. 129 2. C81 PROTECTS AD7523 AGAINST 10000001 -~VREF (358) a NEGATIVE TRANSIENTS. 108 V REF 10000000 -Vper ) _ VRer 15 14 Tree R2 1k 2 easel * 01141114 Vv xt INeUTS | ap7523. 1f9UT! REF 256 LSB ouT2 1 ate? crt Your 0000001 -VREF x) 256 GND . ( 0. t : 90000000 ~Vrer (55g) = 0 . = (9-8 = Figure 1. Unipolar Binary Operation (2-Quadrant Multiptication) Note: 1 LSB = (2) (VreF!= (5e5) VREF) Table 1, Unipolar Binary Code Table BIPOLAR OPERATION 40V -15 VREF DIGITAL INPUT ANALOG OUTPUT MSB LSB yada -VReEF (333) A DATA rasa 1 INPUTS is Ra 5k RS 5k 10000001 VReF (a8) oo 1 o RS 100k Vout 10000000 0 1 a7 amo o1tttttt +Vaer (=) RE 10k : 00000001 +VREF (355) = = 00000000 +VREF (28 od) NOTES: 3, RS-A7 USED TO ADJUST Vout = OV AT 1. R3/R4 MATCH 0.1% OR BETTER. INPUT CODE 10000000. 2. 1, R2 USED ONLY IF GAIN 4. CR1 & CR2 PROTECT AD7523 AGAINST . ADJUSTMENT IS REQUIRED. NEGATIVE TRANSIENTS. Note: 1LSB = (277) (Vref) = (35) (VREF) Figure 2. Bipolar (4-Quadrant) Operation Table 2. Bipolar (Offset Binary) Code Table POWER DAC DESIGN USING AD7523 1 #6 AA- 2 154 Vrer (10V) +g5y 30KH 3 14 +15 + ja INTERSIL io} nc 10K02 2 0.680) = J, AD7S23 ol ine NA +o Vour BIT switcHEes } 1& WE) pit INTERSIL mk 10F- switches tH8510 a 9 wT ~16V 35V 0.681: 7.5KO Figure 3. The Basic Power DAC A typical power DAC designed for 10 bit accuracy and 8 bit resolution is shown in Figure 3. INTERSIL IH8510 power amplifier 1 Amp continuous output with up to +25V) is driven by the AD7523. A summing amplifier between the AD7523 and the 1H8510 is used to separate the gain block containing the AD7520 on- chip resistors from the power amplifier gain stage whose gain is set only by the external resistors. This approach minimizes drift since the resistor pairs will track properly. Otherwise AD7523 can be directly connected to the 1H8510, by using a 25 volts reference for the DAC. 4-76AD7523 APPLICATIONS (continued) DIVIDER (DIGITALLY CONTROLLED GAIN) VIN +15V Rre { out2 |, 16 14 BIT1 tase DIGITAL AD7523 | (INPUT OuT1 LSB: Db 11}-o Vout = - Vin/> 3 is} brs WHERE: | Veer _ BIT? BIT2, BITE D 2) + 22 + 28 255 ( OsDs 358 ) -2 VouT INVERSIL MODIFIED SCALE FACTOR AND OFFSET VRer 15V mi + f co Vout BIT1 15 14 16 Re picitat Twsel * INPUT | AD7523 pe lise VrerD tt 2 BITS 3 R2 RiD BIT? BIT2 BITS = Vaee || _ } - WHERE: 0 = += = Vout vr 85) (@2,) ERE: O 2 + rm) + 2 < 355) (0 3D S356 DEFINITION OF TERMS NONLINEARITY: Error contributed by deviation of the DAC transfer function from a best straight line function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire Vaer range. RESOLUTION: Value of the LSB. For example, a unipolar converter with n bits has a resolution of (27) (Vrer). A bipolay converter of n bits has a resolution of [2-(-"][Vree). Resolution in no way implies linearity. SETTLING TIME: Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, i.e., 0 to Full Scale. . GAIN: Ratio of the DACs operational amplifier output voltage to the nominal input voltage value. FEEDTHROUGH ERROR: Error caused by capacitive coupling from Vrer to output with all switches OFF. OUTPUT CAPACITANCE: Capacity from lout: and lout2 terminals to ground. OUTPUT LEAKAGE CURRENT: Current which appears on lout1 terminal with all digital inputs LOW or on lout2 terminal when ail inputs are HIGH. For further information on the use of this device, see the following Application Bulletins: A016 A018 A020 A021 ROOS Selecting A/D Converters, by David Fullagar A Cookbook Approach to High-Speed Data Acquisition 4-77 Dos and Don'ts of Applying A/D Converters, by Peter Bradshaw and Skip Osgood and Microprocessor Interfacing by Ed Sliger Power D/A Converters Using the IH8510, by Dick Wilenken Interfacing Data Converters & Microprocessors, by Peter Bradshaw et al., Electronics, Dec. 9, 1976