P0116-01
1
2
3VSW
VSW
VSW
4BG
5
TGR
6
TG
PGND
(Pin9)
7
VIN
8
VIN
0 5 10 15 20 25 30 35 40
75
77
79
81
83
85
87
89
91
93
95
0
1.2
2.4
3.6
4.8
6
7.2
8.4
9.6
10.8
12
Output Current (A)
Efficiency (%)
Power Loss (W)
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
Synchronous Buck NexFET™Power Block
1FEATURES DESCRIPTION
The CSD87350Q5D NexFET™power block is an
2•Half-Bridge Power Block optimized design for synchronous buck applications
•90% system Efficiency at 25A offering high current, high efficiency, and high
•Up To 40A Operation frequency capability in a small 5-mm ×6-mm outline.
Optimized for 5V gate drive applications, this product
•High Frequency Operation (Up To 1.5MHz) offers a flexible solution capable of offering a high
•High Density –SON 5-mm ×6-mm Footprint density power supply when paired with any 5V gate
•Optimized for 5V Gate Drive drive from an external controller/driver.
•Low Switching Losses TEXT ADDED FOR SPACING
•Ultra Low Inductance Package Top View
•RoHS Compliant
•Halogen Free
•Pb-Free Terminal Plating
APPLICATIONS
•Synchronous Buck Converters
–High Frequency Applications TEXT ADDED FOR SPACING
–High Current, Low Duty Cycle Applications ORDERING INFORMATION
•Multiphase Synchronous Buck Converters Device Package Media Qty Ship
•POL DC-DC Converters SON 5-mm ×6-mm 13-Inch Tape and
CSD87350Q5D 2500
Plastic Package Reel Reel
•IMVP, VRM, and VRD Applications
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING TYPICAL POWER BLOCK EFFICIENCY
TYPICAL CIRCUIT and POWER LOSS
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
TA= 25°C (unless otherwise noted) (1)
Parameter Conditions VALUE UNIT
VIN to PGND -0.8 to 30 V
Voltage range TGto TGR -8 to 10 V
BGto PGND -8 to 10 V
Pulsed Current Rating, IDM 120 A
Power Dissipation, PD12 W
Sync FET, ID= 105A, L = 0.1mH 551
Avalanche Energy EAS mJ
Control FET, ID= 60A, L = 0.1mH 180
Operating Junction and Storage Temperature Range, TJ, TSTG -55 to 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA= 25°(unless otherwise noted)
Parameter Conditions MIN MAX UNIT
Gate Drive Voltage, VGS 4.5 8 V
Input Supply Voltage, VIN 27 V
Switching Frequency, fSW CBST = 0.1μF (min) 200 1500 kHz
Operating Current 40 A
Operating Temperature, TJ125 °C
POWER BLOCK PERFORMANCE
TA= 25°(unless otherwise noted)
Parameter Conditions MIN TYP MAX UNIT
VIN = 12V, VGS = 5V, VOUT = 1.3V,
Power Loss, PLOSS (1) IOUT = 25A, fSW = 500kHz, 3.0 W
LOUT = 0.3µH, TJ= 25ºC
VIN Quiescent Current, IQVIN TGto TGR = 0V ,BGto PGND = 0V 10 µA
(1) Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
THERMAL INFORMATION
TA= 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT
Junction to ambient thermal resistance (Min Cu) (1)(2) 102
RθJA Junction to ambient thermal resistance (Max Cu) (1)(2) 50 °C/W
Junction to case thermal resistance (Top of package) (2) 20
RθJC Junction to case thermal resistance (PGND Pin) (2) 2
(1) Device mounted on FR4 material with 1-inch2(6.45-cm2) Cu.
(2) RθJC is determined with the device mounted on a 1-inch2(6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch ×1.5-inch
(3.81-cm ×3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
2Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
HD
HG
LG
LD
M0189-01
5x6 QFN TTA MIN Rev1
LS
HS
HD
HG
LG
LD
M0190-01
5x6 QFN TTA MIN Rev1
LS
HS
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS
TA= 25°C (unless otherwise stated) Q1 Control FET Q2 Sync FET
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
Static Characteristics
BVDSS Drain to Source Voltage VGS = 0V, IDS = 250μA 30 30 V
Drain to Source Leakage
IDSS VGS = 0V, VDS = 20V 1 1 μA
Current
Gate to Source Leakage
IGSS VDS = 0V, VGS = +10 / -8 100 100 nA
Current
Gate to Source Threshold
VGS(th) VDS = VGS, IDS = 250μA 1 2.1 0.75 1.4 V
Voltage VIN = 12V, VGS = 5V,
Effective AC VOUT = 1.3V, IOUT = 20A,
ZDS(on)(1) 5 1.2 mΩ
On-Impedance fSW = 500kHz,
LOUT = 0.3µH
gfs Transconductance VDS = 15V, IDS = 20A 97 157 S
Dynamic Characteristics
CISS Input Capacitance 1360 1770 2950 3835 pF
COSS Output Capacitance VGS = 0V, VDS = 15V, 565 735 1300 1690 pF
f = 1MHz
Reverse Transfer
CRSS 19 25 50 65 pF
Capacitance
RGSeries Gate Resistance 1.3 3.0 0.8 2.0 Ω
QgGate Charge Total (4.5V) 8.4 10.9 20 26 nC
Gate Charge - Gate to
Qgd 1.6 3.6 nC
Drain VDS = 15V,
IDS = 20A
Gate Charge - Gate to
Qgs 2.6 4.3 nC
Source
Qg(th) Gate Charge at Vth 1.6 2.3 nC
QOSS Output Charge VDS = 17V, VGS = 0V 9.7 28 nC
td(on) Turn On Delay Time 7 8 ns
trRise Time 17 10 ns
VDS = 15V, VGS = 4.5V,
IDS = 20A, RG= 2Ω
td(off) Turn Off Delay Time 13 33 ns
tfFall Time 2.3 4.7 ns
Diode Characteristics
VSD Diode Forward Voltage IDS = 20A, VGS = 0V 0.85 1 0.77 1 V
Qrr Reverse Recovery Charge 12.5 32 nC
Vdd = 17V, IF= 20A,
di/dt = 300A/μs
trr Reverse Recovery Time 22 28 ns
(1) Equivalent System Performance based on application testing. See page 9 for details.
Max RθJA = 50°C/W Max RθJA = 102°C/W
when mounted on when mounted on
1 inch2(6.45 cm2) of minimum pad area of
2-oz. (0.071-mm thick) 2-oz. (0.071-mm thick)
Cu. Cu.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 3
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40
Output Current (A)
Power Loss (W)
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
−50 −25 0 25 50 75 100 125 150
TC − Junction Temperature − ºC
Power Loss, Normalized
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
0
5
10
15
20
25
30
35
40
45
50
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (ºC)
Output Current (A)
400LFM
200LFM
100LFM
Nat Conv
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
0
5
10
15
20
25
30
35
40
45
50
0 10 20 30 40 50 60 70 80 90
Ambient Temperature (ºC)
Output Current (A)
400LFM
200LFM
100LFM
Nat Conv
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
0
5
10
15
20
25
30
35
40
45
50
0 20 40 60 80 100 120 140
Board Temperature (ºC)
Output Current (A)
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3µH
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
TJ= 125°C, unless stated otherwise.
Figure 1. Power Loss vs Output Current Figure 2. Normalized Power Loss vs Temperature
Figure 3. Safe Operating Area –PCB Vertical Mount(1) Figure 4. Safe Operating Area –PCB Horizontal Mount(1)
Figure 5. Typical Safe Operating Area(1)
(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0”(W) ×3.5”(L) x 0.062”(H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
4Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
200 350 500 650 800 950 1100 1250 1400 1550
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
−11.7
−8.8
−5.9
−2.9
0.0
3.0
5.9
8.8
11.8
14.7
17.6
Switching Frequency (kHz)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
IOUT = 40A
3 5 7 9 11 13 15 17 19 21 23
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
−11.7
−8.8
−5.9
−2.9
0.0
2.9
5.9
8.8
11.7
14.6
17.6
Input Voltage (V)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VGS = 5V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
IOUT = 40A
0.5 1 1.5 2 2.5 3 3.5 4
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
−11.7
−8.8
−5.9
−2.9
0
2.9
5.9
8.8
11.7
14.7
17.6
Output Voltage (V)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 0.3µH
IOUT = 40A
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
−11.7
−8.8
−5.9
−2.9
0
3
5.9
8.8
11.8
14.7
17.6
Output Inductance (µH)
Power Loss, Normalized
SOA Temperature Adj (ºC)
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
IOUT = 40A
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
TJ= 125°C, unless stated otherwise.
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 6. Normalized Power Loss vs Switching Frequency Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 8. Normalized Power Loss vs. Output Voltage Figure 9. Normalized Power Loss vs. Output Inductance
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 5
0
10
20
30
40
50
60
70
80
0 0.1 0.2 0.3 0.4 0.5 0.6
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0
10
20
30
40
50
60
70
80
0 0.05 0.1 0.15 0.2 0.25 0.3
VDS - Drain-to-Source Voltage - V
IDS - Drain-to-Source Current - A
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
0.001
0.01
0.1
1
10
100
0 0.5 1 1.5 2 2.5 3 3.5 4
VGS - Gate-to-Source Voltage - V
IDS - Drain-to-Source Current - A
TC = 125°C
TC = 25°C
TC = −55°C
VDS = 5V
0.001
0.01
0.1
1
10
100
0 0.5 1 1.5 2 2.5 3
VGS - Gate-to-Source Voltage - V
IDS - Drain-to-Source Current - A
TC = 125°C
TC = 25°C
TC = −55°C
VDS = 5V
0
1
2
3
4
5
6
7
8
9
10
0 2 4 6 8 10 12 14 16
Qg - Gate Charge - nC (nC)
VGS - Gate-to-Source Voltage (V)
ID = 20A
VDD = 15V
0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30 35
Qg - Gate Charge - nC (nC)
VGS - Gate-to-Source Voltage (V)
ID = 20A
VDD = 15V
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
TA= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 10. Control MOSFET Saturation Figure 11. Sync MOSFET Saturation
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 12. Control MOSFET Transfer Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 14. Control MOSFET Gate Charge Figure 15. Sync MOSFET Gate Charge
6Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
0.001
0.01
0.1
1
10
0 5 10 15 20 25 30
VDS - Drain-to-Source Voltage - V
C − Capacitance − nF
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
0.001
0.01
0.1
1
10
0 5 10 15 20 25 30
VDS - Drain-to-Source Voltage - V
C − Capacitance − nF
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd f = 1MHz
VGS = 0V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
−75 −25 25 75 125 175
TC - Case Temperature - ºC
VGS(th) - Threshold Voltage - V
ID = 250µA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
−75 −25 25 75 125 175
TC - Case Temperature - ºC
VGS(th) - Threshold Voltage - V
ID = 250µA
0
2
4
6
8
10
12
14
16
0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to- Source Voltage - V
RDS(on) - On-State Resistance - mΩ
TC = 25°C
TC = 125ºC
ID = 20A
0
1
2
3
4
5
6
7
8
0 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to- Source Voltage - V
RDS(on) - On-State Resistance - mΩ
TC = 25°C
TC = 125ºC
ID = 20A
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 16. Control MOSFET Capacitance Figure 17. Sync MOSFET Capacitance
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 18. Control MOSFET VGS(th) Figure 19. Sync MOSFET VGS(th)
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 20. Control MOSFET RDS(on) vs VGS Figure 21. Sync MOSFET RDS(on) vs VGS
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 7
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−75 −25 25 75 125 175
TC - Case Temperature - ºC
Normalized On-State Resistance
ID = 20A
VGS = 8V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
−75 −25 25 75 125 175
TC - Case Temperature - ºC
Normalized On-State Resistance
ID = 20A
VGS = 8V
0.0001
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1
VSD − Source-to-Drain Voltage - V
ISD − Source-to-Drain Current - A
TC = 25°C
TC = 125°C
0.0001
0.001
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1
VSD − Source-to-Drain Voltage - V
ISD − Source-to-Drain Current - A
TC = 25°C
TC = 125°C
1
10
100
0.01 0.1 1 10
t(AV) - Time in Avalanche - ms
I(AV) - Peak Avalanche Current - A
TC = 25°C
TC = 125°C
1
10
100
1000
0.01 0.1 1 10
t(AV) - Time in Avalanche - ms
I(AV) - Peak Avalanche Current - A
TC = 25°C
TC = 125°C
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA= 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 22. Control MOSFET Normalized RDS(on) Figure 23. Sync MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 24. Control MOSFET Body Diode Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING
Figure 26. Control MOSFET Unclamped Inductive Figure 27. Sync MOSFET Unclamped Inductive Switching
Switching
8Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
APPLICATION INFORMATION
Equivalent System Performance
Many of today’s high performance computing systems require low power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an
emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this
Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to
go beyond simply reducing RDS(ON).
Figure 28.
The CSD87350Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in TI’s Application Note SLPA009.
Figure 29.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 9
72
75
78
81
84
87
90
93
96
0 5 10 15 20 25 30 35 40 45
Output Current (A)
Efficiency (%)
PowerBlock HS/LS RDS(ON) = 5mΩ/2.1mΩ
Discrete HS/LS RDS(ON) = 5mΩ/2.1mΩ
Discrete HS/LS RDS(ON) = 5mΩ/1.2mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40 45
Output Current (A)
Power Loss (W)
PowerBlock HS/LS RDS(ON) = 5mΩ/2.1mΩ
Discrete HS/LS RDS(ON) = 5mΩ/1.2mΩ
Discrete HS/LS RDS(ON) = 5mΩ/2.1mΩ
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
fSW = 500kHz
TA = 25ºC
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON).Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87350Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87350Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
Figure 30. Figure 31.
The chart below compares the traditional DC measured RDS(ON) of CSD87350Q5D versus its ZDS(ON). This
comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As
such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs
in a standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87350Q5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete
MOSFETs or dual MOSFETs in a standard package.
Comparison of RDS(ON) vs. ZDS(ON)
HS LS
Parameter Typ Max Typ Max
Effective AC On-Impedance ZDS(ON) (VGS = 5V) 5 - 1.2 -
DC Measured RDS(ON) (VGS = 4.5V) 5 6.8 2.1 2.8
10 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
The CSD87350Q5D NexFET™power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87350Q5D as a function of load current. This curve
is measured by configuring and running the CSD87350Q5D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87350Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN x IIN) + (VDD x IDD)–(VSW_AVG x IOUT) = Power Loss (1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD87350Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4”(W) x
3.5”(L) x 0.062”(T) and 6 copper layers of 1 oz. copper thickness
Normalized Curves
The normalized curves in the CSD87350Q5D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Figure 32. Typical Application
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Board Temperature (°C)
0 20 40 60 80 100 120 140
0
5
10
15
20
25
30
35
40
45
50
G028
V = 12V
IN
V = 5V
GS
V = 1.3V
OUT
f = 500kHz
SW
L = 0.3 µH
OUT
Output Current (A)
1
2
3
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
•Output Current = 25A
•Input Voltage = 7V
•Output Voltage = 1V
•Switching Frequency = 800kHz
•Inductor = 0.2µH
Calculating Power Loss
•Power Loss at 25A = 3.5W (Figure 1)
•Normalized Power Loss for input voltage ≈1.07 (Figure 7)
•Normalized Power Loss for output voltage ≈0.95 (Figure 8)
•Normalized Power Loss for switching frequency ≈1.11 (Figure 6)
•Normalized Power Loss for output inductor ≈1.07 (Figure 9)
•Final calculated Power Loss = 3.5W x 1.07 x 0.95 x 1.11 x 1.07 ≈4.23W
Calculating SOA Adjustments
•SOA adjustment for input voltage ≈2ºC (Figure 7)
•SOA adjustment for output voltage ≈-1.3ºC (Figure 8)
•SOA adjustment for switching frequency ≈2.8ºC (Figure 6)
•SOA adjustment for output inductor ≈1.6ºC (Figure 9)
•Final calculated SOA adjustment = 2 + (-1.3) + 2.8 + 1.6 ≈5.1ºC
In the design example above, the estimated power loss of the CSD87350Q5D would increase to 4.23W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1ºC. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.1ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 33. Power Block SOA
12 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
•The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6x10µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
•The Driver IC should be placed relatively close to the Power Block Gate pins. TGand BGshould connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
•The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.
•In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost
Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost
Resistor value will range between 1 Ωto 4.7 Ωdepending on the output characteristics of Driver IC used in
conjunction with the Power Block. The RC snubber values can range from 0.5 Ωto 2.2 Ωfor the R and 330pF
to 2200pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC snubber
values. The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure 34(1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri –Rolla
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 13
VIN
VSW
PGND
BG
TG
TGR
VSW VSW
Output Inductor
Input Capacitors
Power Block
Input Capacitors
Output Capacitors
Driver IC
Bottom Layer
Top Layer
RC Snubber
Power Block
Location on Top
Layer
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
•Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 34. Recommended PCB Layout (Top Down View)
14 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
M0187-01
E1
E
q
c
5 6 78
1 2 34
L
d1
f
K
b
d3
L
E1
e
a
E2
D2
TopView BottomView
FrontView
SideView
5
9
6
7
8
12
3
4
qc1
D1
d2
d
Position
Designation
Pin1
VIN
Pin2
VIN
Pin3
TG
Pin4
TGR
Pin5
BG
Pin6
VSW
Pin7
VSW
Pin8
VSW
Pin9
PGND
Exposed TieBarMayVary
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
MECHANICAL DATA
Q5D Package Dimensions
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
a 1.40 1.5 0.055 0.059
b 0.360 0.460 0.014 0.018
c 0.150 0.250 0.006 0.010
c1 0.150 0.250 0.006 0.010
d 1.630 1.730 0.064 0.068
d1 0.280 0.380 0.011 0.015
d2 0.200 0.300 0.008 0.012
d3 0.291 0.391 0.012 0.015
D1 4.900 5.100 0.193 0.201
D2 4.269 4.369 0.168 0.172
E 4.900 5.100 0.193 0.201
E1 5.900 6.100 0.232 0.240
E2 3.106 3.206 0.122 0.126
e 1.27 TYP 0.050
f 0.396 0.496 0.016 0.020
L 0.510 0.710 0.020 0.028
θ0.00 –––
K 0.812 0.032
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 15
M0188-01
0.650(0.026)0.650(0.026)
0.620(0.024)
0.620
(0.024)
0.415(0.016)
14
58
0.345(0.014)
3.480(0.137)
0.850(0.033) 0.850(0.033)
0.530(0.021)
0.400(0.016)
6.240(0.246)
1.920
(0.076)
4.460
(0.176)
4.460
(0.176)
1.270
(0.050)
M0208-01
0.341(0.013)
0.410(0.016)
14
58
0.250(0.010)
0.300(0.012)
0.300(0.012)
StencilOpening
0.300(0.012)
0.950(0.037)
PCBPattern
1.290(0.051)
0.610(0.024)
1.680
(0.066)
1.710
(0.067)
CSD87350Q5D
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
www.ti.com
Land Pattern Recommendation
NOTE: Dimensions are in mm (inches).
Text For Spacing
Stencil Recommendation
NOTE: Dimensions are in mm (inches).
Text For Spacing
For recommended circuit layout for PCB designs, see application note SLPA005 –Reducing Ringing Through
PCB Layout Techniques.
16 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Ø1.50 +0.10
–0.00
4.00±0.10(SeeNote1)
1.75±0.10
R0.30 TYP
Ø1.50MIN
A0
K0
0.30±0.05
R0.20MAX
A0=5.30±0.10
B0=6.50±0.10
K0=1.90±0.10
M0191-01
2.00±0.05
8.00±0.10
B0
5.50±0.05
12.00±0.30
CSD87350Q5D
www.ti.com
SLPS288C –MARCH 2011–REVISED OCTOBER 2011
Q5D Tape and Reel Information
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
Spacer
REVISION HISTORY
Changes from Original (March 2011) to Revision A Page
•Changed Power Dissipation, PDin the ABSOLUTE MAXIMUM RATINGS table From; 13 W to 12 W ............................... 2
Changes from Revision A (August 2011) to Revision B Page
•Replaced RDS(on) with ZDS(on) ................................................................................................................................................. 3
•Added Equivalent System Performance section ................................................................................................................... 9
•Added the Comparison of RDS(on) vs ZDS(on) table ............................................................................................................... 10
•Added Electrical Performance bullet ................................................................................................................................... 13
Changes from Revision B (September 2011) to Revision C Page
•Changed "DIM a"Millimeter Max value From: 1.55 To: 1.5 and Inches Max value From: 0.061 To: 0.059 ...................... 15
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 17
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD87350Q5D SON DQY 8 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD87350Q5D SON DQY 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2013
Pack Materials-Page 2
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