74HCT595PW,118 - NEXPERIA - Datasheet.Cloud

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output

latches; 3-state

Rev. 9 — 28 February 2017 Product data sheet

1 General description

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a

storage register and 3-state outputs. Both the shift and storage register have separate

clocks. The device features a serial input (DS) and a serial output (Q7S) to enable

cascading and an asynchronous reset MR input. A LOW on MR will reset the shift

the shift register is transferred to the storage register on a LOW-to-HIGH transition of

the STCP input. If both clocks are connected together, the shift register will always be

one clock pulse ahead of the storage register. Data in the storage register appears at

the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the

outputs to assume a high-impedance OFF-state. Operation of the OE input does not

affect the state of the registers. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess of VCC.

2 Features and benefits

•8-bit serial input

•8-bit serial or parallel output

•Storage register with 3-state outputs

•Shift register with direct clear

•100 MHz (typical) shift out frequency

•Complies with JEDEC standard no. 7A

•Input levels:

–For 74HC595: CMOS level

–For 74HCT595: TTL level

•ESD protection:

–HBM JESD22-A114F exceeds 2000 V

–MM JESD22-A115-A exceeds 200 V

•Multiple package options

•Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3 Applications

•Serial-to-parallel data conversion

•Remote control holding register

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

2 / 22

4 Ordering information

Table 1. Ordering information

PackageType number

Temperature

range

Name Description Version

74HC595D

74HCT595D

-40 °C to +125 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HC595DB

74HCT595DB

-40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm

SOT338-1

74HC595PW

74HCT595PW

-40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

74HC595BQ

74HCT595BQ

-40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 16 terminals;

body 2.5 × 3.5 × 0.85 mm

SOT763-1

5 Functional diagram

mna554

3-STATE OUTPUTS

8-BIT STORAGE REGISTER

8-STAGE SHIFT REGISTER

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q7S

15 1 2 3 4 5 6 7

SHCP

STCP

Figure 1. Functional diagram

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

3 / 22

OEMR

1310

11 12

mna552

Q7S

STCP

SHCP

Figure 2. Logic symbol

mna553

1D 2D

C1/

13 EN3

SRG8

Figure 3. IEC logic symbol

STAGE 0 STAGES 1 TO 6 STAGE 7

FF0

LATCH

FF7

LATCH

mna555

D Q

Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q7S

STCP

SHCP

Figure 4. Logic diagram

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

4 / 22

6 Pinning information

6.1 Pinning

74HC595

74HCT595

Q1 VCC

Q2 Q0

Q3 DS

Q4 OE

Q5 STCP

Q6 SHCP

Q7 MR

GND Q7S

001aao242

Figure 5. Pin configuration for SO16, SSOP16 and

TSSOP16

001aao243

74HC595

74HCT595

Q7 MR

Q6 SHCP

Q5 STCP

Q4 OE

Q3 DS

Q2 Q0

GND

Q7S

Transparent top view

7 10

6 11

5 12

4 13

3 14

2 15

terminal 1

index area

GND(1)

(1) This is not a supply pin. The substrate is attached to

this pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Figure 6. Pin configuration for DHVQFN16

6.2 Pin description

Table 2. Pin description

Symbol Pin Description

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output

GND 8 ground (0 V)

Q7S 9 serial data output

MR 10 master reset (active LOW)

SHCP 11 shift register clock input

STCP 12 storage register clock input

OE 13 output enable input (active LOW)

DS 14 serial data input

Q0 15 parallel data output 0

VCC 16 supply voltage

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

5 / 22

7 Functional description

Table 3. Function table [1]

Control Input Output

SHCP STCP OE MR DS Q7S Qn

Function

X X L L X L NC a LOW-level on MR only affects the shift registers

X ↑ L L X L L empty shift register loaded into storage register

X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state

↑ X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

[1] H = HIGH voltage state;

L = LOW voltage state;

↑ = LOW-to-HIGH transition;

X = don’t care;

NC = no change;

Z = high-impedance OFF-state.

SHCP

STCP

Q7S

Z-state

mna556

Figure 7. Timing diagram

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

6 / 22

8 Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +7 V

IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA

IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA

VO = -0.5 V to (VCC + 0.5 V)

pin Q7S - ±25 mA

IOoutput current

pins Qn - ±35 mA

ICC supply current - 70 mA

IGND ground current -70 - mA

Tstg storage temperature -65 +150 °C

SO16 package [1] - 500 mW

SSOP16 package [2] - 500 mW

TSSOP16 package [2] - 500 mW

Ptot total power dissipation

DHVQFN16 package [3] - 500 mW

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

[2] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.

[3] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 °C.

9 Recommended operating conditions

Table 5. Recommended operating conditions

74HC595 74HCT595Symbol Parameter Conditions

Min Typ Max Min Typ Max

Unit

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VIinput voltage 0 - VCC 0 - VCC V

VOoutput voltage 0 - VCC 0 - VCC V

VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V

Δt/ΔV input transition rise and

fall rate

VCC = 6.0 V - - 83 - - - ns/V

Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

7 / 22

10 Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max

Unit

74HC595

VCC = 2.0 V 1.5 1.2 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - V

VIH HIGH-level

input voltage

VCC = 6.0 V 4.2 3.2 - 4.2 - V

VCC = 2.0 V - 0.8 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 V

VIL LOW-level

input voltage

VCC = 6.0 V - 2.8 1.8 - 1.8 V

VI = VIH or VIL

all outputs

IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - V

IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - V

IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - V

Q7S output

IO = -4 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V

IO = -5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V

Qn bus driver outputs

IO = -6 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V

VOH HIGH-level

output voltage

IO = -7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V

VI = VIH or VIL

all outputs

IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 V

IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 V

IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 V

Q7S output

IO = 4 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V

Qn bus driver outputs

IO = 6 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V

VOL LOW-level

output voltage

IO = 7.8 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V

IIinput leakage

current

VI = VCC or GND; VCC = 6.0 V - - ±1.0 - ±1.0 μA

IOZ OFF-state

output current

VI = VIH or VIL; VCC = 6.0 V;

VO = VCC or GND

- - ±5.0 - ±10 μA

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

8 / 22

-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions

Min Typ Max Min Max

Unit

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 6.0 V

- - 80 - 160 μA

CIinput

capacitance

- 3.5 - - - pF

74HCT595

VIH HIGH-level

input voltage

VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V

VIL LOW-level

input voltage

VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V

VI = VIH or VIL; VCC = 4.5 V

all outputs

IO = -20 μA 4.4 4.5 - 4.4 - V

Q7S output

IO = -4 mA 3.84 4.32 - 3.7 - V

Qn bus driver outputs

VOH HIGH-level

output voltage

IO = -6 mA 3.7 4.32 - 3.7 - V

VI = VIH or VIL; VCC = 4.5 V

all outputs

IO = 20 μA - 0 0.1 - 0.1 V

Q7S output

IO = 4.0 mA - 0.15 0.33 - 0.4 V

Qn bus driver outputs

VOL LOW-level

output voltage

IO = 6.0 mA - 0.16 0.33 - 0.4 V

IIinput leakage

current

VI = VCC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 μA

IOZ OFF-state

output current

VI = VIH or VIL; VCC = 5.5 V;

VO = VCC or GND

- - ±5.0 - ±10 μA

ICC supply current VI = VCC or GND; IO = 0 A;

VCC = 5.5 V

- - 80 - 160 μA

per input pin;

other inputs at VCC or GND;

IO = 0 A; VI = VCC - 2.1 V;

VCC = 4.5 V to 5.5 V

pins MR, SHCP, STCP, OE - 150 675 - 735 μA

ΔICC additional

supply current

pin DS - 25 113 - 123 μA

CIinput

capacitance

- 3.5 - - - pF

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

9 / 22

11 Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ [1] Max Min Max Min Max

Unit

74HC595

SHCP to Q7S; see Figure 8 [2]

VCC = 2 V - 52 160 - 200 - 240 ns

VCC = 4.5 V - 19 32 - 40 - 48 ns

VCC = 6 V - 15 27 - 34 - 41 ns

STCP to Qn; see Figure 9 [2]

VCC = 2 V - 55 175 - 220 - 265 ns

VCC = 4.5 V - 20 35 - 44 - 53 ns

tpd propagation

delay

VCC = 6 V - 16 30 - 37 - 45 ns

MR to Q7S; see Figure 11

VCC = 2 V - 47 175 - 220 - 265 ns

VCC = 4.5 V - 17 35 - 44 - 53 ns

tPHL HIGH

to LOW

propagation

delay

VCC = 6 V - 14 30 - 37 - 45 ns

OE to Qn; see Figure 12 [3]

VCC = 2 V - 47 150 - 190 - 225 ns

VCC = 4.5 V - 17 30 - 38 - 45 ns

ten enable time

VCC = 6 V - 14 26 - 33 - 38 ns

OE to Qn; see Figure 12 [4]

VCC = 2 V - 41 150 - 190 - 225 ns

VCC = 4.5 V - 15 30 - 38 - 45 ns

tdis disable time

VCC = 6 V - 12 27 - 33 - 38 ns

SHCP HIGH or LOW;

see Figure 8

VCC = 2 V 75 17 - 95 - 110 - ns

VCC = 4.5 V 15 6 - 19 - 22 - ns

VCC = 6 V 13 5 - 16 - 19 - ns

STCP HIGH or LOW;

see Figure 9

VCC = 2 V 75 11 - 95 - 110 - ns

VCC = 4.5 V 15 4 - 19 - 22 - ns

VCC = 6 V 13 3 - 16 - 19 - ns

tWpulse width

MR LOW; see Figure 11

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

10 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ [1] Max Min Max Min Max

Unit

VCC = 2 V 75 17 - 95 - 110 - ns

VCC = 4.5 V 15 6 - 19 - 22 - ns

VCC = 6 V 13 5 - 16 - 19 - ns

DS to SHCP; see Figure 10

VCC = 2 V 50 11 - 65 - 75 - ns

VCC = 4.5 V 10 4 - 13 - 15 - ns

VCC = 6 V 9 3 - 11 - 13 - ns

SHCP to STCP;

see Figure 10

VCC = 2 V 75 22 - 95 - 110 - ns

VCC = 4.5 V 15 8 - 19 - 22 - ns

tsu set-up time

VCC = 6 V 13 7 - 16 - 19 - ns

DS to SHCP; see Figure 10

VCC = 2 V 3 -6 - 3 - 3 - ns

VCC = 4.5 V 3 -2 - 3 - 3 - ns

thhold time

VCC = 6 V 3 -2 - 3 - 3 - ns

MR to SHCP; see Figure 11

VCC = 2 V 50 -19 - 65 - 75 - ns

VCC = 4.5 V 10 -7 - 13 - 15 - ns

trec recovery

time

VCC = 6 V 9 -6 - 11 - 13 - ns

SHCP or STCP; see Figure 8

and Figure 9

VCC = 2 V 9 30 - 4.8 - 4 - MHz

VCC = 4.5 V 30 91 - 24 - 20 - MHz

fmax maximum

frequency

VCC = 6 V 35 108 - 28 - 24 - MHz

CPD power

dissipation

capacitance

fi = 1 MHz; VI = GND to VCC

[5] [6] - 115 - - - - - pF

74HCT595; VCC = 4.5 V to 5.5 V

SHCP to Q7S; see Figure 8 [2] - 25 42 - 53 - 63 nstpd propagation

delay STCP to Qn; see Figure 9 [2] - 24 40 - 50 - 60 ns

tPHL HIGH

to LOW

propagation

delay

MR to Q7S; see Figure 11 - 23 40 - 50 - 60 ns

ten enable time OE to Qn; see Figure 12 [3] - 21 35 - 44 - 53 ns

tdis disable time OE to Qn; see Figure 12 [4] - 18 30 - 38 - 45 ns

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

11 / 22

25 °C -40 °C to

+85 °C

-40 °C to

+125 °C

Symbol Parameter Conditions

Min Typ [1] Max Min Max Min Max

Unit

SHCP HIGH or LOW;

see Figure 8

16 6 - 20 - 24 - ns

STCP HIGH or LOW;

see Figure 9

16 5 - 20 - 24 - ns

tWpulse width

MR LOW; see Figure 11 20 8 - 25 - 30 - ns

DS to SHCP; see Figure 9 16 5 - 20 - 24 - nstsu set-up time

SHCP to STCP;

see Figure 9

16 8 - 20 - 24 - ns

thhold time DS to SHCP; see Figure 10 3 -2 - 3 - 3 - ns

trec recovery

time

MR to SHCP; see Figure 11 10 -7 - 13 - 15 - ns

fmax maximum

frequency

SHCP and STCP;

see Figure 8 and Figure 9

30 52 - 24 - 20 - MHz

CPD power

dissipation

capacitance

fi = 1 MHz;

VI = GND to VCC - 1.5 V

[5] [6] - 130 - - - - - pF

[1] Typical values are measured at nominal supply voltage.

[2] tpd is the same as tPHL and tPLH.

[3] ten is the same as tPZL and tPZH.

[4] tdis is the same as tPLZ and tPHZ.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC

2 × fi + Σ(CL × VCC

2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

Σ(CL × VCC

2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

[6] All 9 outputs switching.

11.1 Waveforms and test circuit

mna557

SHCP input

Q7S output

tPLH tPHL

1/fmax

VOH

GND

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 8. Shift clock pulse, maximum frequency and input to output propagation delays

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

12 / 22

mna558

STCP input

Qn output

tPLH tPHL

tsu 1/fmax

VOH

GND

VOL

SHCP input

GND

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 9. Storage clock to output propagation delays

mna560

GND

tsu

VOH

VOL

Q7S output

SHCP input

DS input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 10. Data set-up and hold times

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

13 / 22

mna561

MR input

SHCP input

Q7S output

tPHL

tWtrec

VOH

VOL

GND

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 11. Master reset to output propagation delays

msa697

tPLZ

tPHZ

outputs

disabled

outputs

enabled

90 %

10 %

outputs

enabled

OE input VM

tPZL

tPZH

Qn output

LOW-to-OFF

OFF-to-LOW

Qn output

HIGH-to-OFF

OFF-to-HIGH

trtf

90 %

10 %

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Figure 12. Enable and disable times

Table 8. Measurement points

Input OutputType

VMVM

74HC595 0.5VCC 0.5VCC

74HCT595 1.3 V 1.3 V

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

14 / 22

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

Test data is given in Table 9.

Definitions for test circuit:

CL = load capacitance including jig and probe capacitance.

RL = load resistance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

S1 = test selection switch.

Figure 13. Test circuit for measuring switching times

Table 9. Test data

Input Load S1 positionType

VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

74HC595 VCC 6 ns 50 pF 1 kΩ open GND VCC

74HCT595 3 V 6 ns 50 pF 1 kΩ open GND VCC

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

15 / 22

12 Package outline

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpc D(1) E(1) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Figure 14. Package outline SOT109-1 (SO16)

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

16 / 22

UNIT A1A2A3bpc D (1) E(1) e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05

1.80

1.65 0.25 0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2 0.65 1.25

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Figure 15. Package outline SOT338-1 (SSOP16)

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

17 / 22

UNIT A1A2A3bpc D (1) E(2) (1)

e HEL LpQ Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3 0.65 6.6

6.2

0.4

0.3

0.40

0.06

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

1 8

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Figure 16. Package outline SOT403-1 (TSSOP16)

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

18 / 22

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

detail X

y1C

2 7

15 10

B A

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Figure 17. Package outline SOT763-1 (DHVQFN16)

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

19 / 22

13 Abbreviations

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

14 Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT595 v.9 20170228 Product data sheet - 74HC_HCT595 v.8

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

74HC_HCT595 v.8 20160225 Product data sheet - 74HC_HCT595 v.7

Modifications: •Type numbers 74HC595N and 74HCT595N (SOT38-4) removed.

74HC_HCT595 v.7 20150126 Product data sheet - 74HC_HCT595 v.6

Modifications: •Table 7: Power dissipation capacitance condition for 74HCT595 is corrected.

74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5

Modifications: •Legal pages updated.

74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4

74HC_HCT595 v.4 20030604 Product specification - 74HC_HCT595_CNV v.3

74HC_HCT595_CNV v.3 19980604 Product specification - -

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

20 / 22

15 Legal information

15.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local Nexperia

sales office. In case of any inconsistency or conflict with the short data sheet,

the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory. Notwithstanding any damages that

customer might incur for any reason whatsoever, Nexperia's aggregate and

cumulative liability towards customer for the products described herein shall

be limited in accordance with the Terms and conditions of commercial sale of

Nexperia.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification. Customers are responsible for the

design and operation of their applications and products using Nexperia

products, and Nexperia accepts no liability for any assistance with

applications or customer product design. It is customer’s sole responsibility

to determine whether the Nexperia product is suitable and fit for the

customer’s applications and products planned, as well as for the planned

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products. Nexperia does not accept

any liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using Nexperia products in order to avoid a default of the

applications and the products or of the application or use by customer’s third

party customer(s). Nexperia does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Product data sheet Rev. 9 — 28 February 2017

21 / 22

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications. In the event that customer

uses the product for design-in and use in automotive applications to

automotive specifications and standards, customer (a) shall use the product

without Nexperia's warranty of the product for such automotive applications,

use and specifications, and (b) whenever customer uses the product for

automotive applications beyond Nexperia's specifications such use shall be

solely at customer’s own risk, and (c) customer fully indemnifies Nexperia

for any liability, damages or failed product claims resulting from customer

design and use of the product for automotive applications beyond Nexperia's

standard warranty and Nexperia's product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

15.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Nexperia 74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 28 February 2017

Document identifier: 74HC_HCT595

Contents

1 General description ............................................ 1

2 Features and benefits .........................................1

3 Applications .........................................................1

4 Ordering information .......................................... 2

5 Functional diagram ............................................. 2

6 Pinning information ............................................ 4

6.1 Pinning ............................................................... 4

6.2 Pin description ................................................... 4

7 Functional description ........................................5

8 Limiting values ....................................................6

9 Recommended operating conditions ................ 6

10 Static characteristics .......................................... 7

11 Dynamic characteristics .....................................9

11.1 Waveforms and test circuit .............................. 11

12 Package outline .................................................15

13 Abbreviations .................................................... 19

14 Revision history ................................................ 19

15 Legal information .............................................. 20