AD1981BJSTZ-REEL - Analog Devices

REV. A

AD1981B

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AC ’97 SoundMAX

Codec

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AC ’97 2.3 COMPATIBLE FEATURES

S/PDIF Output, 20 Bits Data Format, Supporting

48 kHz and 44.1 kHz Sample Rates

Integrated Stereo Headphone Amplifier

Variable Sample Rate Audio

External Audio Power-Down Control

Greater than 90 dB Dynamic Range

Stereo Full-Duplex Codec

20-Bit PCM DAC

3 Analog Line-Level Stereo Inputs for

Line-In, AUX, and CD

Mono Line-Level Phone Input

Dual MIC Input with Built-In Programmable Preamp

High Quality CD Input with Ground Sense

Mono Output for Speakerphone or Internal Speaker Power

Management Support

48-Lead LQFP Package

ENHANCED FEATURES

Stereo MIC Preamps Support

Built-In Digital Equalizer Function for Optimized Speaker

Sound

Full-Duplex Variable Sample Rates from 7040 Hz to 48 kHz

with 1 Hz Resolution

Jack Sense Pins Provide Automatic Output Switching

Software Programmed VREFOUT Output for Biasing

Microphone and External Power Amp

Split Power Supplies: 3.3 V Digital and 5 V Analog

Multiple Codec Configuration Options

MIC1

MIC2

PHONE_IN

CD_L

CD_GND

CD_R

AUX_L

AUX_R

LINE_IN_L

MIC PREAMP

DIFF AMP

MONO_OUT

HP_OUT_L HP

LINE_OUT_L

LINE_OUT_R

HP_OUT_R HP

OUTPUT SELECTOR

G = GAIN

A = ATTENUATION

M = MUTE

Z = HIGH Z

16-BIT

⌺-⌬ ADC

16-BIT

⌺-⌬ ADC

PCM FRONT

DAC RATE

M16-BIT

⌺-⌬ ADC

M16-BIT

⌺-⌬ ADC

PCM L/R

ADC RATE

RECORD

SELECTOR

REF

REFOUT

LINE_IN_R

CODEC CORE

ADC

AND

DAC

SLOT

LOGIC

EQ CORE STORAGE

AC '97

CONTROL

REGISTERS

EAPD

PLL

XTL_OUT XTL_IN SPDIF

SPDIF

ID0

ID1

RESET

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

JS0 JS1 EAPD

AD1981B

2CMIC

MIX

BYPASS

VOLTAG E

REFERENCE

ANALOG MIXING

CONTROL LOGIC

20-BIT

⌺-⌬ DAC

20-BIT

⌺-⌬ DAC

AC '97 INTERFACE

REV. A

–2–

AD1981B

STANDARD TEST CONDITIONS, UNLESS

OTHERWISE NOTED

Temperature 25°C

Digital Supply (VDD) 3.3 V

Analog Supply (VCC) 5.0 V

Sample Rate (FS) 48 kHz

Input Signal 1008 Hz

Analog Output Pass Band 20 Hz to 20 kHz

DAC Test Conditions

Calibrated

–3 dB Attenuation Relative to Full Scale

0 dB Input

10 kΩ Output Load (LINE_OUT)

32 Ω Output Load (HP_OUT)

ADC Test Conditions

Calibrated

0 dB Gain

Input –3.0 dB Relative to Full Scale

Parameter Min Typ Max Unit

ANALOG INPUT

Input Voltage (rms Values Assume Sine Wave Input)

LINE_IN, AUX, CD, PHONE_IN 1 V rms

2.83 V p-p

MIC_IN with +20 dB Gain 0.1 V rms

0.283 V p-p

MIC_IN with 0 dB Gain 1 V rms

2.83 V p-p

Input Impedance

20 kΩ

Input Capacitance

57.5 pF

MASTER VOLUME

Step Size (0 dB to –46.5 dB): LINE_OUT_L, LINE_OUT_R 1.5 dB

Output Attenuation Range

46.5 dB

Step Size (0 dB to –46.5 dB): MONO_OUT 1.5 dB

Output Attenuation Range

46.5 dB

Step Size (0 dB to –46.5 dB): HP_OUT_R, HP_OUT_L 1.5 dB

Output Attenuation Range Span

46.5 dB

Mute Attenuation of 0 dB Fundamental

80 dB

PROGRAMMABLE GAIN AMPLIFIER—ADC

Step Size (0 dB to 22.5 dB) 1.5 dB

PGA Gain Range 22.5 dB

ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS

Signal-to-Noise Ratio (SNR)

CD to LINE_OUT 90 dB

Other to LINE_OUT

90 dB

Step Size (+12 dB to –34.5 dB) (All Steps Tested):

MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 1.5 dB

Input Gain/Attenuation Range:

MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC 46.5 dB

DIGITAL DECIMATION AND INTERPOLATION FILTERS

Pass Band 0 0.4  f

Pass-Band Ripple ±0.09 dB

Transition Band 0.4  f

0.6  f

Stop Band 0.6  f

Hz

Stop-Band Rejection –74 dB

Group Delay 16/f

sec

Group Delay Variation over Pass Band 0 µs

–SPECIFICATIONS

REV. A –3–

AD1981B

Parameter Min Typ Max Unit

ANALOG-TO-DIGITAL CONVERTERS

Resolution 16 Bits

Total Harmonic Distortion (THD) –84 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, 80 85 dB

A-Weighted)

Signal-to-Intermodulation Distortion

(CCIF Method) 85 dB

ADC Crosstalk

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –80 dB

Line_In to Other –100 –80 dB

Gain Error

(Full-Scale Span Relative to Nominal Input Voltage) ±10 %

Interchannel Gain Mismatch (Difference of Gain Errors) ±0.5 dB

ADC Offset Error

±5mV

DIGITAL-TO-ANALOG CONVERTERS

Resolution 20 Bits

Total Harmonic Distortion (THD) LINE_OUT –85 dB

Total Harmonic Distortion (THD) HP_OUT –75 dB

Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, 85 90 dB

A-Weighted)

Signal-to-Intermodulation Distortion

(CCIF Method) –100 dB

Gain Error

(Output FS Voltage Relative to Nominal Output FS Voltage) ±10 %

Interchannel Gain Mismatch (Difference of Gain Errors) ±0.7 dB

DAC Crosstalk

(Input L, Zero R, Measure R_OUT; Input R, –80 dB

Zero L, Measure L_OUT)

Total Audible Out-of-Band Energy

(Measured from 0.6  f

to 20 kHz) –40 dB

ANALOG OUTPUT

Full-Scale Output Voltage; LINE_OUT and MONO_OUT 1 V rms

2.83 V p-p

Output Impedance

800 Ω

External Load Impedance

10 kΩ

Output Capacitance

15 pF

External Load Capacitance

100 pF

Full-Scale Output Voltage; HP_OUT (0 dB Gain) 1 V rms

External Load Impedance

32 Ω

REF

2.05 2.25 2.45 V

REF_OUT

(Programmable to 3.70 V Nominal) 2.25 V

REF_OUT

Current Drive 5mA

Mute Click (Muted Output Minus Unmuted Midscale DAC Output) ±5mV

STATIC DIGITAL SPECIFICATIONS

High Level Input Voltage (V

): Digital Inputs 0.65  DVDD V

Low Level Input Voltage (V

)0.35  DVDD V

High Level Output Voltage (V

), I

= 2 mA 0.9  DVDD V

Low Level Output Voltage (V

), I

= 2 mA 0.1  DVDD V

Input Leakage Current –10 +10 µA

Output Leakage Current –10 +10 µA

POWER SUPPLY

Power Supply Range—Analog (AV

)4.5 5.5 V

Power Supply Range—Digital (DV

)3.0 3.47 V

Power Dissipation—5 V/3.3 V 400 mW

Analog Supply Current—5 V (AV

)50mA

Digital Supply Current—3.3 V (DV

)46mA

Power Supply Rejection (100 mV p-p Signal @ 1 kHz)

(At Both Analog and Digital Supply Pins, Both ADCs and DACs) 40 dB

REV. A

–4–

AD1981B

Parameter Set Bits DV

Typ AV

Typ Unit

POWER-DOWN STATES*

(Fully Active) (No Bits Value) 42 51 mA

ADC PR0 36 45 mA

DAC PR1 29 35 mA

ADC + DAC PR1, PR0 12 28 mA

Mixer PR2 42 24 mA

ADC + Mixer PR2, PR0 36 18 mA

DAC + Mixer PR2, PR1 29 9 mA

ADC + DAC + Mixer PR2, PR1, PR0 12 1.5 mA

Standby PR5, PR4, PR3, PR2, PR1, PR0 0 0 mA

Headphone Standby PR6 42 44 mA

*Values presented with V

REFOUT

not loaded.

Specifications subject to change without notice.

Parameter Symbol Min Typ Max Unit

RESET Active Low Pulsewidth t

RST_LOW

1.0 ms

RESET Inactive to BIT_CLK Start-Up Delay t

RST2CLK

162.8 ns

SYNC Active High Pulsewidth t

SYNC_HIGH

1.3 ms

SYNC Low Pulsewidth t

SYNC_LOW

19.5

SYNC Inactive to BIT_CLK Start-Up Delay t

SYNC2CLK

162.8 ns

BIT_CLK Frequency 12.288 MHz

BIT_CLK Frequency Accuracy ±1ppm

BIT_CLK Period t

CLK_PERIOD

81.4 ns

BIT_CLK Output Jitter

1, 2, 3

750 2000 ps

BIT_CLK High Pulsewidth t

CLK_HIGH

32.56 42 48.84 ns

BIT_CLK Low Pulsewidth t

CLK_LOW

32.56 38 ns

SYNC Frequency 48.0 kHz

SYNC Period t

SYNC_PERIOD

20.8 ms

Setup to Falling Edge of BIT_CLK t

SETUP

52.5 ns

Hold from Falling Edge of BIT_CLK t

HOLD

5ns

BIT_CLK Rise Time t

RISECLK

246ns

BIT_CLK Fall Time t

FALLCLK

246ns

SYNC Rise Time t

RISESYNC

246ns

SYNC Fall Time t

FALLSYNC

246ns

SDATA_IN Rise Time t

RISEDIN

246ns

SDATA_IN Fall Time t

FALLDIN

246ns

SDATA_OUT Rise Time t

RISEDOUT

246ns

SDATA_OUT Fall Time t

FALLDOUT

246ns

End of Slot 2 to BIT_CLK, SDATA_IN Low t

S2_PDOWN

01.0 ms

Setup to Trailing Edge of RESET

(Applies to SYNC, SDATA_OUT) t

SETUP2RST

15 ns

Rising Edge of RESET to HI-Z Delay t

OFF

25 ns

Propagation Delay 15 ns

RESET Rise Time 50 ns

Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns

NOTES

Guaranteed but not tested.

Output jitter is directly dependent on crystal input jitter.

Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.

Specifications subject to change without notice.

Parameter Min Typ Max Unit

CLOCK SPECIFICATIONS

Input Clock Frequency 24.576 MHz

Recommended Clock Duty Cycle 40 50 60 %

NOTES

Guaranteed but not tested.

Measurements reflect main ADC.

Specifications subject to change without notice.

TIMING PARAMETERS

(Guaranteed over Operating Temperature Range)

REV. A –5–

AD1981B

RESET

BIT_CLK

SDATA_IN

tRST_LOW

tRST2CLK

tTRI2ACTV

Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal)

SYNC

BIT_CLK

tSYNC_HIGH tSYNC2CLK

Figure 2. Warm Reset Timing

BIT_CLK

SYNC

tCLK_LOW

tCLK_HIGH

tCLK_PERIOD

tSYNC_LOW

tSYNC_PERIOD

tSYNC_HIGH

Figure 3. Clock Timing

BIT_CLK

SYNC

SDATA_IN

SDATA_OUT

tRISECLK tFALLCLK

tRISESYNC tFALLSYNC

tRISEDIN tFALLDIN

tRISEDOUT tFALLDOUT

Figure 4. Signal Rise and Fall Times

REV. A

–6–

AD1981B

BIT_CLK

SYNC

SDATA_IN

SDATA_OUT

BIT_CLK NOT TO SCALE

SLOT 1 SLOT 2

WRITE TO

0ⴛ20

DATA

PR4

S2_PDOWN

Figure 5. AC-Link Low Power Mode Timing

BIT_CLK

SDATA_O

SDATA_I

SYN

tCO

tSETUP

tHOLD

Figure 6. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped

RESET

SDATA_OUT

SDATA_IN, BIT_CLK,

EAPD, SPDIF_OUT

AND DIGITAL I/O

Hi-Z

SETUP2RST

OFF

Figure 7. ATE Test Mode

REV. A

AD1981B

–7–

PIN CONFIGURATION

48-Lead LQFP

XTL_IN

XTL_OUT

SDATA_OUT

BIT_CLK

SDATA_IN

SYNC

RESET

LINE_OUT_R

LINE_OUT_L

AFILT4

AFILT3

AFILT2

AFILT1

REFOUT

REF

PHONE_IN

AUX_L

AUX_R

JS1

JS0

CD_L

CD_GND_REF

CD_R

MIC1

MIC2

LINE_IN_L

LINE_IN_R

SPDIF

EAPD

ID1

ID0

HP_OUT_R

HP_OUT_L

MONO_OUT

AD1981B

TOP VIEW

(Not to Scale)

NC = NO CONNECT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD1981B features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD1981BJST 0°C to 70°C48-Lead LQFP ST-48

*ST = Low Profile Quad Flatpack

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.)

Power Supplies

Digital (DV

) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

Analog (AV

) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.0 V

Input Current (Except Supply Pins) . . . . . . . . . . . . . . ±10 mA

Signals Pins

Digital Input Voltage . . . . . . . . . . . . . –0.3 V to DV

+ 0.3 V

Analog Input Voltage . . . . . . . . . . . . –0.3 V to AV

+ 0.3 V

Ambient Temperature Range (Operating) . . . . . . . 0°C to 70°C

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating (TQFP Package)

TCASE = Case Temperature in °C

PD = Power Dissipation in W



Thermal Resistance (Junction-to-Ambient)



Thermal Resistance (Junction-to-Case)

Package ␪

␪

LQFP 50.1°C/W 17.8°C/W

*All measurements per EIA-JESD51 with 2S2P test board per

EIA-JESD51-7

REV. A

AD1981B

–8–

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic I/O Function

DIGITAL I/O

2XTL_IN I Crystal Input (24.576 MHz) or External Clock Input

3XTL_OUT O Crystal Output

5SDATA_OUT I AC-Link Serial Data Output, AD1981B Data Input Stream

6BIT_CLK O/I AC-Link Bit Clock Output (12.288 MHz) or Bit Clock Input if Secondary Mode

Selected

8SDATA_IN O AC-Link Serial Data Input, AD1981B Data Output Stream

10 SYNC I AC-Link Frame Sync

11 RESET IAC-Link Reset, AD1981B Master Hardware Reset

48 SPDIF O S/PDIF Output

CHIP SELECTS (These pins can also be used to select an external clock. See Table IX.)

45 ID0 IChip Select Input 0 (Active Low). This pin can also be used as the chain input from

a secondary codec.

46 ID1 IChip Select Input 1 (Active Low)

JACK SENSE AND EAPD

17 JS0 I Jack Sense 0 Input

16 JS1 I Jack Sense 1 Input

47 EAPD O External Amp Power-Down Control

ANALOG I/O

13 PHONE_IN I Phone Input. Mono input from telephony subsystem speaker phone or handset.

14 AUX_L I Auxiliary Input Left Channel

15 AUX_R I Auxiliary Input Right Channel

18 CD_L I CD Audio Left Channel

19 CD_GND_REF I CD Audio Analog Ground Reference for Differential CD Input

20 CD_ R I CD Audio Right Channel

21 MIC1 I Microphone 1 Input (Mono) or Left Channel when 2-Channel Mode

Selected (Stereo MIC)

22 MIC2 I Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode

Selected (Stereo MIC)

23 LINE_IN_L I Line In Left Channel

24 LINE_IN_R I Line In Right Channel

35 LINE_OUT_L O Line Out (Front) Left Channel

36 LINE_OUT_R O Line Out (Front) Right Channel

37 MONO_OUT O Monaural Output to Telephony Subsystem Speakerphone

39 HP_OUT_L O Headphone Left Channel Output

41 HP_OUT_R O Headphone Right Channel Output

FILTER/REFERENCE (These signals are connected to resistors, capacitors, or specific voltages.)

27 V

REF

OVoltage Reference Filter

28 V

REFOUT

OVoltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias)

29 AFILT1 O Antialiasing Filter Capacitor—ADC Right Channel

30 AFILT2 O Antialiasing Filter Capacitor—ADC Left Channel

31 AFILT3 O Antialiasing Filter Capacitor—Mixer ADC Right Channel

32 AFILT4 O Antialiasing Filter Capacitor—Mixer ADC Left Channel

POWER AND GROUND SIGNALS

1DV

1IDigital V

3.3 V

4DV

1IDigital GND

7DV

2IDigital GND

9DV

2IDigital V

3.3 V

25 AV

1IAnalog V

5.0 V

26 AV

1IAnalog GND

38 AV

2IAnalog V

5.0 V

40 AV

2IAnalog GND

43 AV

3IAnalog V

5.0 V

44 AV

3IAnalog GND

34 AV

4IAnalog V

5.0 V

33 AV

4IAnalog GND

NO CONNECTS

12 NC No Connect

42 NC No Connect

REV. A

AD1981B

–9–

Indexed Control Registers

Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h

02h Master Volume MM X X LMV4 LMV3 LMV2 LMV1 LMV0 RM*XXRMV4 RMV3 RMV2 RMV1 RMV0 8000h

04h Headphones HPM X X LHV4 LHV3 LHV2 LHV1 LHV0 RM*XXRHV4 RHV3 RHV2 RHV1 RHV0 8000h

Volume

06h Mono Volume MVM X X XXXXXXX XMV4MV2MV2MV1MV08000h

0Ch Phone Volume PHM X X XXXXXXX XPHV4 PHV3 PHV2 PHV1 PHV0 8008h

0Eh MIC Volume MCM X X XXXXXXM20XMCV4 MCV3 MCV2 MCV1 MCV0 8008h

10h Line In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 RM*XXRLV4 RLV3 RLV2 RLV1 RLV0 8808h

12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 RM*XXRCV4 RCV3 RCV2 RCV1 RCV0 8808h

16h AUX Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 RM*XXRAV4 RAV3 RAV2 RAV1 RAV0 8808h

18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOV1 LOV0 RM*XXROV4 ROV3 ROV2 ROV1 ROV0 8808h

1Ah Record Select X X X X X LS2 LS1 LS0 X X XXXRS2 RS1 RS0 0000h

1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 RM*XXXRIM3 RIM2 RIM1 RIM0 8000h

20h General-Purpose X X X XXXMIX MS LPBK X XXXXXX 0000h

26h Power-Down EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh

Ctrl/Stat

28h Ext’d Audio ID IDC1 IDC0 X X REVC1 REVC0 AMAP X X X DSA1 DSA0 X SPDF X VRAS X605h

2Ah Ext’d Audio Stat/ VFORCE X X X X SPCV XXXX SPSA1 SPSA0 X SPDIF X VRA 0000h

Ctrl

2Ch PCM Front SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h

DAC Rate

32h PCM L/R SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h

ADC Rate

3Ah SPDIF Control V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h

60h EQ CTRL EQM MAD X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 8080h

LBEN

62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h

64h Mixer ADC, MXM X X X LMG3 LMG2 LMG1 LMG0 RM*XXXRMG3 RMG2 RMG1 RMG0 8000h

Volume

72h Jack Sense X X X JS JS JS JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 0000h

MT2 MT1 MT0 EQB EQB TMR TMR MD MD ST ST INT INT

74h Serial SLOT REGM REGM REGM X X X CHEN X X X INTS X SPAL SPDZ SPLNK 7001h

Configuration 16 2 1 0

76h Misc Control DACZ X M LODIS DAM X FMXE X MAD 2CMIC X MAD VREF VREF MBG1 MBG0 0000h

Bits SPLT PD ST H D

7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h

7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h

NOTES

All registers not shown. Bits containing an X are assumed to be reserved.

Odd register addresses are aliased to the next lower even address.

Reserved registers should not be written.

Zeros should be written to reserved bits.

*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect.

REV. A

AD1981B

–10–

Reset Register (Index 00h)

NOTES

X in the above table is a wild card and has no effect on the value.

Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 74h, which forces the serial configuration).

Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.

ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the following:

SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are zeros).

Master Volume Register (Index 02h)

*For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.

Refer to Table I for examples. This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each

volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume

registers, to maintain compatibility whenever the D5 or D13 bits are set to “1,” their respective lower five volume bits are automati-

cally set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever these bits are set to “1.”

RMV[4:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of 46.5 dB.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the MM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”

LMV[4:0] Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from

0 dB to a maximum attenuation of 46.5 dB.

MM Master Volume Mute. When this bit is set to “1,” both the left and right channels are muted, unless the MSPLT

bit in Register 76h is set to “1,” in which case this mute bit will affect only the left channel.

Bit Function AD1981B

ID0 Dedicated Mic PCM In Channel 0

ID1 Modem Line Codec Support 0

ID2 Bass and Treble Control 0

ID3 Simulated Stereo (Mono to Stereo) 0

ID4 Headphone Out Support 1

ID5 Loudness (Bass Boost) Support 0

ID6 18-Bit DAC Resolution 0

ID7 20-Bit DAC Resolution 1

ID8 18-Bit ADC Resolution 0

ID9 20-Bit ADC Resolution 0

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

02h Master MM X X LMV4 LMV3 LMV2 LMV1 LMV0 RM*XXRMV4 RMV3 RMV2 RMV1 RMV0 8000h

Volume

REV. A

AD1981B

–11–

Headphones Volume Register (Index 04h)

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved.

Refer to Table I for examples. This register controls the headphone volume controls for both stereo channels and mute bit. Each

volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume

registers, to maintain compatibility, whenever the D5 or D13 bits are set to “1,” their respective lower five volume bits are automati-

cally set to “1” by the codec logic. On readback, all lower five bits will read “1s” whenever these bits are set to “1.”

RHV [4:0] Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output

from 0 dB to a maximum attenuation of 46.5 dB.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the HPM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”

LHV [4:0] Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output

from 0 dB to a maximum attenuation of 46.5 dB.

HPM Headphones Volume Mute. When this bit is set to “1,” both the left and right channels are muted, unless the

MSPLT bit in Register 76h is set to “1,” in which case this mute bit will affect only the left channel.

Table I. Volume Settings for Master and Headphone

Control Bits

Reg. 76h Master Volume (02h) and Headphone Volume (04h)

MSPLT*Left Channel Volume D[13:8] Right Channel Volume D[5:0]

D15 WRITE READBACK Function D7*WRITE READBACK Function

0000 0000 00 0000 0 dB Gain x 00 0000 00 0000 0 dB Gain

0000 1111 00 1111 –22.5 dB Gain x 00 1111 00 1111 –22.5 dB Gain

0001 1111 01 1111 –46.5 dB Gain x 01 1111 01 1111 –46.5 dB Gain

001x xxxx 01 1111 –46.5 dB Gain x 1x xxxx 01 1111 –46.5 dB Gain

01xx xxxx xx xxxx – dB Gain, Muted x xx xxxx xx xxxx – dB Gain, Muted

101x xxxx 01 1111 –46.5 dB Gain 1 xx xxxx xx xxxx – dB Gain, Right

Only Muted

11xx xxxx xx xxxx – dB Gain, Left Only Muted 0 xx xxxx xx xxxx –46.5 dB Gain

11xx xxxx xx xxxx – dB Gain, Left Muted 1 xx xxxx xx xxxx – dB Gain, Right

Muted

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect.

X in the above table is a wild card and has no effect on the value.

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

04h Headphone HPM X X LHV LHV LHV LHV LHV RM*XXRHVRHV RHV RHV RHV 8000h

Volume 4 3 2 1 0 4 3 2 1 0

REV. A

AD1981B

–12–

Mono Volume Register (Index 06h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

06h Mono Volume MVM X X X X X X X X X X MV4 MV3 MV2 MV1 MV0 8000h

All registers not shown and bits containing an X are assumed to be reserved.

Refer to Table II for examples. This register controls the mono output volume and mute bit. The volume register contains five bits,

generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility,

whenever the D5 bit is set to “1,” their respective lower five volume bits are automatically set to “1” by the codec logic. On

readback, all lower five bits will read “1s” whenever this bit is set to “1.”

MV[4:0] Mono Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a

maximum attenuation of 46.5 dB.

MVM Mono Volume Mute. When this bit is set to “1,” the channel is muted.

Table II. Volume Settings for Mono

Control Bits D[4:0] for Mono (06h)

D15 WRITE READBACK Function

00000 0 0000 0 dB Gain

00 1111 0 1111 –22.5 dB Gain

01 1111 1 1111 –46.5 dB Gain

1x xxxx x xxxx – dB Gain, Muted

x in the above table is a wild card and has no effect on the value.

PHV[4:0] Phone Volume. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB each. The

LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute bit enabled.

PHM Phone Mute. When this bit is set to “1,” the phone channel is muted.

All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.

Phone Volume Register (Index 0Ch)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0Ch Phone Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 8008h

All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.

MIC Volume Register (Index 0Eh)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0Eh MIC Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h

All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples.

REV. A

AD1981B

–13–

MCV[4:0] MIC Volume Gain. Allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 dB

each. The LSB represents 1.5 dB, and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, with the mute

bit enabled.

M20 MIC Gain Boost. This bit allows setting additional MIC gain to increase the microphone sensitivity. The nominal

gain boost by default is 20 dB; however, bits D0 and D1 (MBG[1:0]) on the miscellaneous control bits register

(76h) allow changing the gain boost to 10 dB or 30 dB if necessary.

0 = Disabled; Gain = 0 dB

1 = Enabled; Default Gain = 20 dB (see Register 76h, bits D0, D1)

MCM MIC Mute. When this bit is set to “1,” the MIC channel is muted.

Table III. Volume Settings for Phone and MIC

Control Bits D[4:0]

Phone (0Ch) and Mic (0Eh)

D15 WRITE READBACK Function

00 0000 0 0000 12 dB Gain

00 1000 0 1000 0 dB Gain

01 1111 1 1111 –34.5 dB Gain

1x xxxx x xxxx – dB Gain, Muted

x in the above table is a wild card, and has no effect on the value.

RLV[4:0] Line In Volume Right. Allows setting the line in right channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the LM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”

LLV[4:0] Line In Volume Left. Allows setting the line in left channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

LM Line In Mute. When this bit is set to “1,” both the left and right channels are muted unless the MSPLT bit in

Line-In Volume Register (Index 10h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

10h Line In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 RM*XXRLV4 RLV3 RLV2 RLV1 RLV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

CD Volume Register (Index 12h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 RM*XXRCV4 RCV3 RCV2 RCV1 RCV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit, Register 76h. The MSPLT Bit enables separate mute bits for the left and right

channels. If MSPLT is not set, the RM Bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

REV. A

AD1981B

–14–

RCV[4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the CVM bit. Otherwise, this bit will always read “0” and will have no affect when set to “1.”

LCV[4:0] Left CD Volume. Allows setting the CD left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

CVM CD Volume Mute. When this bit is set to “1,” both the left and right channels are muted, unless the MSPLT bit in

RAV[4:0] Right AUX Volume. Allows setting the AUX right channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the AM bit. Otherwise, this bit will always read “0” and will have no affect when set to “1.”

LAV[4:0] Left AUX Volume. Allows setting the AUX left channel attenuator in 32 volume levels. The LSB represents 1.5 dB,

and the gain range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

AM AUX Mute. When this bit is set to “1,” both the left and right channels are muted, unless the MSPLT bit in

ROV[4:0] Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the OM bit. Otherwise, this bit will always read “0” and will have no effect when set to “1.”

LOV[4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 volume levels. The LSB represents

1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.

OM PCM Out Volume Mute. When this bit is set to “1,” both the left and right channels are muted unless the MSPLT

bit in Register 76h is set to “1,” in which case this mute bit will affect only the left channel.

AUX Volume Register (Index 16h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

16h AUX Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 RM*XXRAV4 RAV3 RAV2 RAV1 RAV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

PCM-Out Volume Register (Index 18h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

18h PCM Out Volume OM X X LOV4 LOV3 LOV2 LOV1 LOV0 RM*XXROV4 ROV3 ROV2 ROV1 ROV0 8808h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table IV for examples.

REV. A

AD1981B

–15–

Table IV. Volume Settings for Line-In, CD Volume, AUX, and PCM-Out

Control Bits

Reg. 76h Line-In (10h), CD (12h), AUX (16h), and PCM-Out (18h)

Left Channel Volume D[12:8] Right Channel Volume D[4:0]

MSPLT*D15 WRITE READBACK Function D7*WRITE READBACK Function

000 0000 0 0000 12 dB Gain x 0 0000 0 0000 +12 dB Gain

000 1000 0 1000 0 dB Gain x 0 1000 0 1000 0 dB Gain

001 1111 1 1111 34.5 dB Gain x 1 1111 1 1111 –34.5 dB Gain

01x xxxx x xxxx – dB Gain, Muted x x xxxx x xxxx – dB Gain, Muted

101 1111 1 1111 –34.5 dB Gain 1 x xxxx x xxxx – dB Gain,

Right Only Muted

11x xxxx x xxxx – dB Gain, 0 1 1111 1 1111 –34.5 dB Gain

Left Only Muted

11x xxxx x xxxx – dB Gain, Left Muted 1 x xxxx x xxxx – dB Gain, Right Muted

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect.

x in the above table is a wild card and has no effect on the value.

Table V. Settings for Record Select Control

LS [10:8] Left Record Source RS [2:0] Right Record Source

000 MIC 000 MIC

001 CD_L 001 CD_R

010 Muted 010 Muted

011 AUX_L 011 AUX_R

100 LINE_IN_L 100 LINE_IN_R

101 Stereo Mix (L) 101 Stereo Mix (R)

110 Mono Mix 110 Mono Mix

111 PHONE_IN 111 PHONE_IN

RS[2:0] Right Record Select

LS[2:0] Left Record Select

Record Select Control Register (Index 1Ah)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

1Ah Record Select X X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h

All registers not shown and bits containing an X are assumed to be reserved. Used to select the record source independently for right and left. The default value is

0000h, which corresponds to MIC In. Refer to Table V for examples.

Record Gain Register (Index 1Ch)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

1Ch Record Gain IM X X X LIM3 LIM2 LIM1 LIM0 RM*XXXRIM3 RIM2 RIM1 RIM0 8000h

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VI for examples.

REV. A

AD1981B

–16–

RIM[3:0] Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the IM bit. Otherwise, this bit will always read “0” and will have no affect when set to “1.”

LIM[3:0] Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB, and the gain range is 0 dB to 22.5 dB.

IM Input Mute. When this bit is set to “1,” both the left and right channels are muted, unless the MSPLT bit in

Table VI. Settings for Record Gain Register

Control Bits

Reg. 76h Record Gain (1Ch)

Left Channel Input Mixer D[11:8] Right Channel Input Mixer D[3:0]

MSPLT*D15 WRITE READBACK Function D7*WRITE READBACK Function

001111 1111 22.5 dB Gain x 1111 1111 22.5 dB Gain

000000 0000 0 dB Gain x 0000 0000 0 dB Gain

01xxxx xxxx – dB Gain, Muted x xxxx xxxx – dB Gain, Muted

101111 1111 22.5 dB Gain 1 xxxx xxxx – dB Gain,

Right Only Muted

11xxxx xxxx – dB Gain, 0 1111 1111 22.5 dB Gain

Left Only Muted

11xxxx xxxx – dB Gain, 1 xxxx xxxx – dB Gain, Right Muted

Left Muted

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect.

x is a wild card and has no effect on the value.

LPBK Loopback Control. ADC/DAC Digital Loopback Mode.

0 = No Loopback (Default).

1 = Loopback PCM Digital Data from ADC Output to DAC.

MS MIC Select. Selects mono MIC input.

0 = Select MIC1.

1 = Select MIC2.

See 2CMIC bit in Register 76h to enable stereo microphone recording.

MIX Mono Output Select. Selects mono output audio source.

0 = Mixer mono output (reset default).

1 = MIC1 channel.

General-Purpose Register (Index 20h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

20h General-Purpose X X X X X X MIX MS LPBK X X X X X X X 0000h

This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an X are assumed

to be reserved.

REV. A

AD1981B

–17–

ADC ADC Sections Ready to Transmit Data

DAC DAC Sections Ready to Accept Data

ANL Analog Amplifiers, Attenuators, and Mixers Ready

REF Voltage References, V

REF

, and V

REFOUT

up to Nominal Level

PR [6:0] Codec Power-Down Modes. The first three bits are to be used individually rather than in combination with each

other. PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via

PR3 unless the ADCs and DACs are also powered down.

Nothing else can be powered up until the reference is up. PR5 has no effect unless all ADCs, DACs, and the ac-link

are powered down. The reference and the mixer can be either up or down, but all power-up sequences must be

allowed to run to completion before PR5 and PR4 are both set.

In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the

slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.

EAPD External Audio Power-Down Control. Controls the state of the EAPD pin.

EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default).

EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.

Power-Down State Set Bits PR [6:0]

ADCs and Input Mux Power-Down PR0 [000 0001]

DACs Power-Down PR1 [000 0010]

Analog Mixer Power-Down (V

REF

and V

REFOUT

On) PR1, PR2 [000 0101]

Analog Mixer Power-Down (V

REF

and V

REFOUT

Off) PR0, PR1, PR3 [000 1011]

AC-Link Interface Power-Down PR4 [001 000]

Internal Clocks Disabled PR0, PR1, PR4, PR5 [011 0011]

ADC and DAC Power-Down PR0, PR1 [000 0011]

REF

Standby Mode PR0, PR1, PR2, PR4, PR5 [011 0111]

Total Power-Down PR0, PR1, PR2, PR3, PR4, PR5, PR6 [111 1111]

Headphone Amp Power-In Standby PR6 [100 0000]

Power-Down Control/Status Register (Index 26h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

26h Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh

The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1981B subsections. If the bit is a “1,” that

subsection is ready. Ready is defined as the subsection able to perform in its nominal state. All registers not shown and bits containing an X are assumed to be reserved.

Extended Audio ID Register (Index 28h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

28h Ext’d Audio ID IDC1 IDC0 X X REVC1 REVC0 AMAP X X X DSA1 DSA0 X SPDF X VRAS X605h

The Extended Audio ID Register identifies which extended audio features are supported. A nonzero Extended Audio ID value indicates that one or more of the

extended audio features are supported. All registers not shown and bits containing an X are assumed to be reserved.

REV. A

AD1981B

–18–

VRAS Variable Rate PCM Audio Support (Read Only). This bit returns a “1” when Read To indicates that the variable

rate PCM audio is supported.

SPDIF SPDIF Support (Read Only). This bit returns a “1” when Read To indicates that the SPDIF transmitter is supported

(IEC958).

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is allowed to be

set high only if the SPDIF pin (48) is pulled down at power-up, enabling the codec transmitter logic. If the SPDIF

pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicat-

ing that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF transmitter

is actually enabled.

DSA[1,0] DAC Slot Assignments (Read/Write) (Reset Default = 00).

00 DACs 1, 2 = 3 and 4.

01 DACs 1, 2 = 7 and 8.

10 DACs 1, 2 = 6 and 9.

11 Reserved.

AMAP Slot DAC Mappings Based on Codec ID (Read Only). This bit returns a “1” when read to indicate that slot/DAC

mappings based on the codec ID are supported.

REVC[1,0] REVC[1,0] = 01 indicates codec is AC ’97 revision 2.2 compliant (Read Only).

IDC[1:0] Indicates Codec Configuration (Read Only).

00 = Primary.

01, 10, 11 = Secondary.

VRA Variable Rate Audio (Read/Write)

VRA = 0 sets fixed sample rate audio at 48 kHz (reset default).

VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ signaling).

SPDIF SPDIF Transmitter Subsystem Enable/Disable Bit (Read/Write)

SPDIF = 1 enables the SPDIF transmitter.

SPDIF = 0 disables the SPDIF transmitter (default).

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed

to be set high if the SPDIF pin (48) is pulled down at power-up enabling the codec transmitter logic. If the

SPDIF pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low,

indicating that the SPDIF transmitter is not available. This bit must always be read back to verify that the SPDIF

transmitter is actually enabled.

SPSA[1:0] SPDIF Slot Assignment Bits (Read/Write). These bits control the SPDIF slot assignment and respective defaults,

depending on the codec ID configuration.

SPCV SPDIF Configuration Valid (Read-Only). Indicates the status of the SPDIF transmitter subsystem, enabling the

driver to determine if the currently programmed SPDIF configuration is supported. SPCV is always valid, independent

of the SPDIF enable bit status.

SPCV = 0 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not valid (not supported).

SPCV = 1 indicates current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid (is supported).

VFORCE Validity Force Bit (Reset Default = 0)

When asserted, this bit forces the SPDIF stream Validity flag (Bit 28 within each SPDIF L/R subframe) to be

controlled by the V bit (D15) in Register 3Ah (SPDIF control register).

VFORCE = 0 and V = 0; the Validity bit is managed by the codec error detection logic.

VFORCE = 0 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.

VFORCE = 1 and V = 0; the Validity bit is forced low, indicating subframe data is valid.

VFORCE = 1 and V = 1; the Validity bit is forced high, indicating subframe data is invalid.

Extended Audio Status and Control Register (Index 2Ah)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ah Ext’d Audio Stat/Ctrl VFORCE X X X X SPCV X X X X SPSA1 SPSA0 X SPDIF X VRA 0000h

All registers not shown and bits containing an X are assumed to be reserved. The Extended Audio Status and Control Register is a read/write register that provides

status and control of the extended audio features.

REV. A

AD1981B

–19–

AC ’97 2.2 AMAP Compliant Default SPDIF Slot Assignments

Codec ID Function SPSA = 00 SPSA = 01 SPSA = 10 SPSA = 11

00 2-Ch Primary w/SPDIF 3 and 4 7 and 8 (default) 6 and 9 10 and 11

00 4-Ch Primary w/SPDIF 3 and 4 7 and 8 6 and 9 (default) 10 and 11

00 6-Ch Primary w/SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 (default)

01 +2-Ch Secondary w/SPDIF 3 and 4 7 and 8 6 and 9 (default)

01 +4-Ch Secondary w/SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 (default)

10 +2-Ch Secondary w/SPDIF 3 and 4 7 and 8 6 and 9 (default)

10 +4-Ch Secondary w/SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 (default)

11 +2-Ch Secondary w/SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 (default)

SR[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.

If “0” is written to VRA, the sample rate is reset to 48k.

SR[15:0] Sample Rate. The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.

If “0” is written to VRA, the sample rate is reset to 48k.

PCM Front DAC Rate Register (Index 2Ch)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

2Ch PCM Front SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 BB80h

DAC Rate

This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.

PCM ADC Rate Register (Index 32h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

32h PCM L/R SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h

ADC Rate

This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.

SPDIF Control Register (Index 3Ah)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

3Ah SPDIF V X SPSR1 SPSR0 L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h

Control

Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the

exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is “0”). This ensures that control and status

information start up correctly at the beginning of SPDIF transmission.

REV. A

AD1981B

–20–

PRO Professional. “1” indicates professional use of channel status.

“0” indicates consumer.

/AUD Non-Audio. “1” indicates data is non-PCM format.

“0” data is PCM.

COPY Copyright. “1” indicates copyright is asserted.

“0” copyright is not asserted.

PRE Pre-Emphasis. “1” indicates filter pre-emphasis is 50 µs/15 µs.

“0” pre-emphasis is none.

CC[6:0] Category Code. Programmed according to IEC standards, or as appropriate.

LGeneration Level. Programmed according to IEC standards, or as appropriate.

SPSR[1:0] SPDIF Transmit Sample Rate.

SPSR[1:0] = 00 transmit sample rate = 44.1 kHz.

SPSR[1:0] = 01 Reserved.

SPSR[1:0] = 10 transmit sample rate = 48 kHz (reset default).

SPSR[1:0] = 11 not supported.

VValidity. This bit affects the Validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the

SPDIF transmitter to maintain connection during error or mute conditions.

V = 1 Each SPDIF subframe (L + R) has Bit 28 set to “1.” This tags both samples as invalid.

V = 0 Each SPDIF subframe (L + R) has Bit 28 set to “0” for valid data and “1” for invalid data (error condition).

Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the

Validity flag low, marking both samples as valid.

EQ Control Register (Index 60h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

60h EQ CTRL EQM MAD X X X X X X SYM CHS BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 8080h

LBEN

Register 60h is a read/write register that controls the equalizer functionality and data setup. This register also contains the Biquad and Coefficient Address pointer,

which is used in conjunction with the EQ Data Register (78h) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients

can be properly set up by the software and sets the Symmetry bit to allow equal coefficients for left and right channels. All registers not shown and bits containing an X

are assumed to be reserved.

REV. A

AD1981B

–21–

BCA[5,0] Biquad and Coefficient Address Pointer

biquad 0 coef a0 BCA[5,0] = 011011

biquad 0 coef a1 BCA[5,0] = 011010

biquad 0 coef a2 BCA[5,0] = 011001

biquad 0 coef b1 BCA[5,0] = 011101

biquad 0 coef b2 BCA[5,0] = 011100

biquad 1 coef a0 BCA[5,0] = 100000

biquad 1 coef a1 BCA[5,0] = 011111

biquad 1 coef a2 BCA[5,0] = 011110

biquad 1 coef b1 BCA[5,0] = 100010

biquad 1 coef b2 BCA[5,0] = 100001

biquad 2 coef a0 BCA[5,0] = 100101

biquad 2 coef a1 BCA[5,0] = 100100

biquad 2 coef a2 BCA[5,0] = 100011

biquad 2 coef b1 BCA[5,0] = 100111

biquad 2 coef b2 BCA[5,0] = 100110

biquad 3 coef a0 BCA[5,0] = 101010

biquad 3 coef a1 BCA[5,0] = 101001

biquad 3 coef a2 BCA[5,0] = 101000

biquad 3 coef b1 BCA[5,0] = 101100

biquad 3 coef b2 BCA[5,0] = 101011

biquad 4 coef a0 BCA[5,0] = 101111

biquad 4 coef a1 BCA[5,0] = 101110

biquad 4 coef a2 BCA[5,0] = 101101

biquad 4 coef b1 BCA[5,0] = 110001

biquad 4 coef b2 BCA[5,0] = 110000

biquad 5 coef a0 BCA[5,0] = 110100

biquad 5 coef a1 BCA[5,0] = 110011

biquad 5 coef a2 BCA[5,0] = 110010

biquad 5 coef b1 BCA[5,0] = 110110

biquad 5 coef b2 BCA[5,0] = 110101

biquad 6 coef a0 BCA[5,0] = 111001

biquad 6 coef a1 BCA[5,0] = 111000

biquad 6 coef a2 BCA[5,0] = 110111

biquad 6 coef b1 BCA[5,0] = 111011

biquad 6 coef b2 BCA[5,0] = 111010

CHS Channel Select.

CHS = 0 selects left channel coefficients data block.

CHS = 1 selects right channel coefficients data block.

SYM Symmetry. When set to “1,” this bit indicates that the left and right channel coefficients are equal. This shortens

the coefficients setup sequence since only the left channel coefficients need to be addressed and set up (the right chan-

nel coefficients are fetched from the left channel memory).

MAD Mixer ADC Loopback Enable. Enables mixer ADC data to be summed into PCM stream.

LBEN 0 = No loopback allowed (default).

1 = Enable loopback.

EQM Equalizer Mute. When set to “1,” this bit disables the equalizer function (allows all data to pass through). The

reset default sets this bit to “1,” disabling the equalizer function until the biquad coefficients can be properly set.

REV. A

AD1981B

–22–

CFD[15:0] Coefficient Data. The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is

the MSB, and the CFD0 bit is the LSB.

RMG[3:0] Right Mixer Gain Control. This register controls the gain into the mixer ADC from 0 dB to a maximum gain of

22.5 dB. The least significant bit represents 1.5 dB.

RM Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately

from the MXM bit. Otherwise, this bit will always read “0” and will have no affect when set to “1.”

LMG[3:0] Left Mixer Gain Control. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB.

The least significant bit represents 1.5 dB.

MXM Mixer Gain Register Mute.

0 = Unmuted.

1 = Muted (reset default).

Table VII. Settings for Mixer ADC, Input Gain

Control Bits

Reg. 76h Mixer ADC, Input Gain (64h)

Left Channel Mixer Gain D[11:8] Right Channel Mixer Gain D[3:0]

MSPLT*D15 WRITE READBACK Function D7*WRITE READBACK Function

001111 1111 22.5 dB Gain x 1111 1111 22.5 dB Gain

000000 0000 0 dB Gain x 0000 0000 0 dB Gain

01xxxx xxxx – dB Gain, Muted x xxxx xxxx – dB Gain, Muted

101111 1111 22.5 dB Gain 1 xxxx xxxx – dB Gain,

Right Only Muted

11xxxx xxxx – dB Gain, Left Only Muted 0 1111 1111 22.5 dB Gain

11xxxx xxxx – dB Gain, Left Muted 1 xxxx xxxx – dB Gain,

Right Muted

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, RM bit has no effect.

x is a wild card and has no effect on the value.

EQ Data Register (Index 62h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h

This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the

BCA bits in the EQ CNTRL Register (60h). Data will be written to memory only if the EQM bit (Register 60h, Bit 15) is asserted.

Mixer ADC, Input Gain Register (Index 64h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

64h Mixer MXM X X X LMG3 LMG2 LMG1 LMG0 RM*XXXRMG3 RMG2 RMG1 RMG0 8000h

Volume

*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right

channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples.

REV. A

AD1981B

–23–

JS0INT Indicates Pin JS0 Has Generated an Interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR

should clear this bit by writing a “0” to it. Note that the interrupt to the system is actually an OR combination of

this bit and JS1INT. Also note that the actual interrupt implementation is selected by the INTS bit (Register 76h).

It is also possible to generate a software system interrupt by writing a “1” to this bit.

JS1INT Indicates Pin JS1 Has Generated an Interrupt. Remains set until the software services JS1 interrupt, i.e., JS1 ISR

should clear this bit by writing a “0” to it. See JS0INT description for additional details.

JS0ST JS0 State. This bit always reports the logic state of JS0 pin.

JS1ST JS1 State. This bit always reports the logic state of JS1 pin.

JS0MD JS0 Mode. This bit selects the operation mode for the JS0 pin.

0 = Jack Sense mode (default).

1 = Interrupt mode.

JS1MD JS1 Mode. This bit selects the operation mode for the JS1 pin.

0 = Jack Sense mode (default).

1 = Interrupt mode.

JS0TMR JS0 Timer Enable. If this bit is set to a “1,” JS0 must be high for greater than 278 ms to be recognized.

JS1TMR JS1 Timer Enable. If this bit is set to a “1,” JS1 must be high for greater than 278 ms to be recognized.

JS0EQB JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass. When this bit is set to “1,” JS0 = 1 will

cause the EQ to be bypassed.

JS1EQB JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass. When this bit is set to “1,” JS1 = 1 will

cause the EQ to be bypassed.

JSMT[2,0] JS Mute Enable Selector. These three bits select and enable the Jack Sense muting action (see Table VIII).

Jack Sense/Audio Interrupt/Status Register (Index 72h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

72h Jack Sense X X X JS JS JS JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 JS1 JS0 0000h

MT2 MT1 MT0 EQB EQB TMR TMR MD MD ST ST INT INT

All register bits are read/write except for JS0ST and JS1ST, which are read only. All registers not shown and bits containing an X are assumed to be reserved.

REV. A

AD1981B

–24–

Table VIII. Jack Sense Mute Select–JSMT [2:0]

JS1 JS0 H.P. LINE MONO

REF HEADPHONE LINE OUT JSMT2 JSMT1 JSMT0 OUT OUT OUT NOTES

0OUT (0) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE JS0 and JS1 Ignored.

1OUT (0) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE

2IN (1) OUT (0) 0 0 0 ACTIVE ACTIVE ACTIVE

3IN (1) IN (1) 0 0 0 ACTIVE ACTIVE ACTIVE

4OUT (0) OUT (0) 0 0 1 FMUTE FMUTE ACTIVE JS0 no mute action;

JS1 mutes Line_Out.

5OUT (0) IN (1) 0 0 1 FMUTE ACTIVE ACTIVE

6IN (1) OUT (0) 0 0 1 ACTIVE FMUTE ACTIVE

7IN (1) IN (1) 0 0 1 ACTIVE FMUTE ACTIVE

8OUT (0) OUT (0) 0 1 0 FMUTE FMUTE ACTIVE JS0 no mute action;

JS1 mutes Mono and

Line_Out.

9OUT (0) IN (1) 0 1 0 FMUTE ACTIVE ACTIVE

10 IN (1) OUT (0) 0 1 0 ACTIVE FMUTE FMUTE

11 IN (1) IN (1) 0 1 0 ACTIVE FMUTE FMUTE

12 OUT (0) OUT (0) 0 1 1 ** ** ** ** Reserved

13 OUT (0) IN (1) 0 1 1 ** ** **

14 IN (1) OUT (0) 0 1 1 ** ** **

15 IN (1) IN (1) 0 1 1 ** ** **

16 OUT (0) OUT (0) 1 0 0 FMUTE FMUTE ACTIVE JS0 mutes Mono;

JS1 no mute action.

17 OUT (0) IN (1) 1 0 0 FMUTE ACTIVE FMUTE

18 IN (1) OUT (0) 1 0 0 ACTIVE FMUTE ACTIVE

19 IN (1) IN (1) 1 0 0 ACTIVE ACTIVE FMUTE

20 OUT (0) OUT (0) 1 0 1 FMUTE FMUTE ACTIVE JS0 mutes Mono;

JS1 mutes Line_Out.

21 OUT (0) IN (1) 1 0 1 FMUTE ACTIVE FMUTE

22 IN (1) OUT (0) 1 0 1 ACTIVE FMUTE ACTIVE

23 IN (1) IN (1) 1 0 1 ACTIVE FMUTE FMUTE

24 OUT (0) OUT (0) 1 1 0 FMUTE FMUTE ACTIVE JS0 mutes Mono;

JS1 mutes Mono and

Line_Out.

25 OUT (0) IN (1) 1 1 0 FMUTE ACTIVE FMUTE

26 IN (1) OUT (0) 1 1 0 ACTIVE FMUTE FMUTE

27 IN (1) IN (1) 1 1 0 ACTIVE FMUTE FMUTE

28 OUT (0) OUT (0) 1 1 1 ** ** ** ** Reserved

29 OUT (0) IN (1) 1 1 1 ** ** **

30 IN (1) OUT (0) 1 1 1 ** ** **

31 IN (1) IN (1) 1 1 1 ** ** **

FMUTE = Output is forced to mute independent of the respective volume register setting.

ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.

OUT = Nothing plugged into the jack and therefore the JS status is low (via the load resistor pull-down).

IN = Jack has plug inserted and therefore the JS status is high (via the codec JS internal pull-up).

REV. A

AD1981B

–25–

SPLNK SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting.

0 = SPDIF and DAC are not linked.

1 = SPDIF and DAC are linked and receive the same data requests (reset default).

SPDZ SPDIF DACZ.

0 = Repeat last sample out of the SPDIF stream if FIFO under-runs (reset default).

1 = Forces midscale sample out the SPDIF stream if FIFO under-runs.

SPAL SPDIF ADC Loop-Around.

0 = SPDIF transmitter is connected to the ac-link stream (reset default).

1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.

INTS Interrupt Mode Select. This bit selects the JS interrupt implementation path.

0 = Bit 0 SLOT 12 (modem interrupt).

1 = Slot 6 valid bit (MIC ADC interrupt).

CHEN Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).

0 = Disable chaining (reset default).

1 = Enable chaining into ID0 pin.

REGM0 Master Codec Register Mask

REGM1 Slave 1 Codec Register Mask

REGM2 Slave 2 Codec Register Mask

SLOT16 Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a

preferred mode for DSP serial port interfacing.

MBG[1:0] MIC Boost Gain Change Register.

These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.

Note: This gain setting takes affect only while bit D6 (M20) on the MIC volume register (0Eh) is set to “1;” otherwise,

the MIC boost block has a gain of 0 dB.

00 = 20 dB gain (reset default).

01 = 10 dB gain.

10 = 30 dB gain.

11 = Reserved.

VREFD V

REFOUT

Disable. Disables V

REFOUT

, placing it into High Z Out mode. Note that this bit overrides the VREFH bit

selection (see below).

0 = V

REFOUT

pin is driven by the internal reference (reset default).

1 = V

REFOUT

pin is placed into High Z Out mode.

VREFH V

REFOUT

High. Changes V

REFOUT

from 2.25 V to 3.70 V for MIC bias applications.

0 = V

REFOUT

pin is set to 2.25 V output (reset default).

1 = V

REFOUT

pin is set to 3.70 V output.

Miscellaneous Control Bit Register (Index 76h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

76th Misc DACZ X MSPLT LODIS DAM X FMXE X MADPD 2CMIC X MADST VREFH VREFD MBG1 MBG0 0000h

Control Bits

All registers not shown and bits containing an X are assumed to be reserved.

Serial Configuration Register (Index 74h)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

74h Serial SLOT16 REGM2 REGM1 REGM0 X X X CHEN XXXINTS X SPAL SPDZ SPLNK 7001h

Configuration

This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.

REV. A

AD1981B

–26–

MADST Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels).

0 = Mixer ADC not ready.

1 = Mixer ADC ready.

MADPD Mixer ADC Power Down. Controls power down for mixer digitizing ADC.

0 = Mixer ADC is powered on (default).

1 = Mixer ADC is powered down.

2CMIC 2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that

use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h.

0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector’s left and right MIC channels as well

as to the mixer (reset default).

1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s

right MIC channel. Note that in this mode the MS bit should be set low and MIC1 can still be enabled into the mixer.

FMXE Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches.

0 = Front DAC outputs are allowed to sum into the mixer (reset default).

1 = Front DAC outputs are muted into the mixer (blocked).

DAM Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.

LODIS Line_out Disable. Disables the Line_out pins (L/R), placing them into High Z mode so that the assigned output

audio jack can be shared for input function (or other function).

0 = Line_out pins have normal audio drive capability (reset default).

1 = Line_out pins are placed into High Z mode.

MSPLT Mute Split. Allows separate mute control bits for master, headphone, line_in, CD, AUX, and PCM volume control

registers as well as record gain register.

0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default).

1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute.

DACZ DAC Zero-Fill. Determines DAC data fill under starved conditions.

0 = DAC data is repeated when DACs are starved for data (reset default).

1 = DAC is zero-filled when DACs are starved for data.

Codec ID and External Clock Selection Table

ID1 ID0 Codec ID Codec Clocking Source

11 (00) Primary 24.576 MHz (Local Xtal or External into XTL_IN)

10 (01) Secondary 12.288 MHz (External into Bit_Clk)

01 (00) Primary 48.000 MHz (External into XTL_IN)

00 (00) Primary 14.31818 MHz (External into XTL_IN)

Note that internally, the ID pins have weak pull-ups and are inverted.

Vendor ID Register (Index 7Ch – 7Eh)

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h

S[7:0] This register is ASCII encoded to “A.”

F[7:0] This register is ASCII encoded to “D.”

Reg

No. Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h

T[7:0] This register is ASCII encoded to “S.”

REV[7:0] Vendor Specific revision number: The AD1981B assigns 74h to this field.

REV. A

AD1981B

–27–

OUTLINE DIMENSIONS

48-Lead Low Profile Quad Flat Package [LQFP]

1.4 mm Thick

(ST-48)

Dimensions shown in millimeters

Revision History

Location Page

2/03—Data Sheet changed from REV. 0 to REV. A.

Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Change to Figure 6 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

0.50

BSC

7.00

BSC

SEATING

PLANE

1.60 MAX

0.75

0.60

0.45

VIEW A

7ⴗ

3.5ⴗ

0ⴗ

0.20

0.09

1.45

1.40

1.35

0.15

0.05 0.08 MAX

COPLANARITY

VIEW A

ROTATED 90ⴗ CCW

PIN 1

INDICATOR

9.00 BSC

COMPLIANT TO JEDEC STANDARDS MS-026BBC

SEATING

PLANE

–28–

C03091–0–2/03(A)

PRINTED IN U.S.A.