IDT71V321L25TFG - Integrated Device Technology

OCTOBER 2008

DSC-3026/11

HIGH SPEED 3.3V

2K X 8 DUAL-PORT

STATIC RAM WITH

INTERRUPTS

IDT71V321S/L

IDT71V421S/L

Features

◆◆

◆High-speed access

– Commercial: 25/35/55ns (max.)

– Industrial: 25ns (max.)

◆◆

◆Low-power operation

– IDT71V321/IDT71V421S

—Active: 325mW (typ.)

—Standby: 5mW (typ.)

– IDT71V321/V421L

—Active: 325mW (typ.)

—Standby: 1mW (typ.)

◆◆

◆Two INT flags for port-to-port communications

◆◆

◆MASTER IDT71V321 easily expands data bus width to 16-

or-more-bits using SLAVE IDT71V421

Functional Block Diagram

NOTES:

1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.

2. BUSY and INT are totem-pole outputs.

◆◆

◆On-chip port arbitration logic (IDT71V321 only)

◆◆

◆BUSY output flag on IDT71V321; BUSY input on IDT71V421

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation—2V data retention (L only)

◆◆

◆TTL-compatible, single 3.3V power supply

◆◆

◆Available in 52-pin PLCC, 64-pin TQFP and STQFP

packages

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆◆

◆Green parts available, see ordering information

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

R/W

BUSY

10L

3026 drw 01

I/O

-I/O

R/W

INT

BUSY

I/O

-I/O

10R

INT

(2)

(1,2) (1,2)

(2)

R/W

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

IDT71V321/421J

J52-1

(4)

52-Pin PLCC

Top View

(5)

NDEX

I/O

GND

I/O

10L

INT

BUSY

R/W

BUSY

INT

10R

234567474849505152

20 27262524232221 333231302928

3026 drw 02

Pin Configurations(1,2,3)

Description

The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port

Static RAMs with internal interrupt logic for interprocessor communica-

tions. The IDT71V321 is designed to be used as a stand-alone 8-bit

Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the

IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-

plications results in full speed, error-free operation without the need for

additional discrete logic.

The device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

for reads or writes to any location in memory. An automatic power

down feature, controlled by CE, permits the on chip circuitry of each

port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these

devices typically operate on only 325mW of power. Low-power (L)

versions offer battery backup data retention capability, with each Dual-

Port typically consuming 200µW from a 2V battery.

The IDT71V321/IDT71V421 devices are packaged in a 52-pin

PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP

(super thin quad flatpack).

NDEX

IDT71V321/421PF or TF

PP64-1

(4)

PN64-1

(4)

64-Pin STQFP

64-Pin TQFP

Top View

(5)

I/O

N/C

I/O

N/C

I/O

N/C

GND

I/O

N/C

GND

N/C

10R

BUSY

R/W

BUSY

N/C

10L

N/C

INT

3026 drw 03

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J52-1 package body is approximately .75 in x .75 in x .17 in.

PP64-1 package body is approximately 10mm x 10mm x 1.4mm.

PN64-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Recommended DC Operating

Conditions

Absolute Maximum Ratings(1) Recommended Operating

Temperature and Supply Voltage(1,2)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.

NOTES:

1. VIL (min.) = -1.5V for pulse width less than 20ns.

2. VTERM must not exceed Vcc + 0.3V.

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

Symbol Rating Commercial

& Industrial Unit

TERM

(2)

Terminal Voltage

with Re sp ec t

to G ND

-0.5 to +4.6 V

Operating

Temperature 0 to +70 °C

BIAS

Temperature

Und e r Bias -55 to +125

STG

Storage

Temperature -65 to + 150

OUT

DC Outp ut

Current 50 mA

3026 tbl 01

Grade Ambient

Temperature GND Vcc

Commercial 0

C to + 70

C0V3.3V

0.3V

Industrial -40

C to + 85

C0V 3.3V

0.3V

3026 tbl 02

Symbol Parameter Min. Typ. Max. Unit

Supply Voltage 3.0 3.3 3.6 V

GND Ground 0 0 0 V

Input High Voltage 2.0

____

+0.3

(2)

Inp ut Lo w Vol tag e -0.3

(1)

____

0.8 V

3026 tbl 03

Capacitance(1)

(TA = +25°C, f = 1.0MHz) TQFP Only

Symbol Parameter Conditions

(2)

Max. Unit

Inp ut Cap ac itanc e V

= 3dV 9 pF

OUT

Outp ut Cap ac itance V

OUT

= 3dV 10 pF

3026 tbl 04

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dv references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

Symbol Parameter Test Conditions

71V321S

71V421S 71V321L

71V421L

UnitMin. Max. Min. Max.

|In p ut L e akage Cur re n t

(1)

= 3.6V,

= 0V to V

___

5µA

| Output Le ak age Current CE = V

, V

OUT

= 0V to V

= 3.6V

___

5µA

Outp ut Lo w Vo ltag e I

= 4mA

___

0.4

___

0.4 V

Output Hig h Voltag e I

= -4mA 2.4

___

2.4

___

3026 tbl 05

NOTE:

1. At VCC < 2.0V input leakages are undefined.

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1,2) (VCC = 3.3V ± 0.3V)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).

3 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels

of GND to 3V.

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Symbol Parameter Test Conditi on Version

71V321X25

71V421X25

Com'l

& Ind

71V321X35

71V421X35

Co m'l On ly

71V321X55

71V421X55

Com'l Only

UnitTyp. Max. Typ. Max. Typ. Max.

Dynamic Op erating

Current

(Bo th Po rts Active )

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L S

L55

55 130

100 55

55 125

95 55

55 115

85 mA

IND S

L55

55 150

130

___ ___ ___ ___

SB1

Stand by Curre nt

(Bo th Po rts - TTL

Le v e l Inp uts )

= CE

= V

SEM

= SEM

= V

f = f

MAX

(3)

COM'L S

L15

15 35

20 15

15 35

20 15

15 35

20 mA

IND S

L15

15 50

___ ___ ___ ___

SB2

Stand by Curre nt

(One P o rt - TTL

Le v e l Inp uts )

"A"

= V

and CE

"B"

= V

(5)

Ac ti v e P o rt Outputs Dis ab l e d ,

f=f

MAX

(3)

SEM

= SEM

= V

COM'L S

L25

25 75

55 25

25 70

50 25

25 60

40 mA

IND S

L25

25 95

___ ___ ___ ___

SB3

Full S tand by Curre nt

(Bo th P orts - Al l

CM O S L e v e l Inpu ts )

Bo th Ports CE

and

> V

- 0.2V

> V

- 0. 2V o r

< 0.2V, f = 0(4)

SEM

= SEM

> V

- 0. 2V

COM'L S

L1.0

0.2 5

31.0

0.2 5

31.0

0.2 5

3mA

IND S

L1.0

0.2 10

___ ___ ___ ___

SB4

Full S tand by Curre nt

(One P o rt - A ll

CM O S L e v e l Inpu ts )

"A"

< 0. 2V and

"B"

> V

- 0.2V(5)

SEM

= SEM

> V

- 0. 2V

> V

- 0.2V or V

< 0. 2V

Active Port Outputs Disabled

f = f

MAX

(3)

COM'L S

L25

25 70

55 25

25 65

50 25

25 55

40 mA

IND S

L25

25 85

___ ___ ___ ___

3026 tbl 06

Data Retention Characteristics (L Version Only)

Symbol P arameter Test Con dition Mi n. Typ.

(1)

Max. Unit

VCC for Data Re te ntio n 2. 0

___

CCDR

Data Re te ntio n Current V

= 2V, CE > V

- 0.2V COM' L.

___

100 1500 µA

CDR

(3)

Chip De se le ct to Data

Re te ntio n Ti me V

> V

- 0. 2V o r V

< 0.2V IND.

___

100 4000 µA

___ ___

(3)

Op eration Recovery Time t

(2)

___ ___

3026 tbl 07

NOTES:

1. VCC = 2V, TA = +25°C, and is not production tested.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization but not production tested.

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Data Retention Waveform

3.0V 3.0V

CDR

≥2.0V

3026 drw 04

AC Test Conditions

590Ω

30pF

435Ω

DATA

OUT

590Ω

435Ω5pF

DATA

OUT

3026 drw 05

3.3V

BUSY

INT

Figure 1. AC Output Test Load Figure 2. Output Test Load

(for tHZ, tLZ, tWZ, and tOW)

* Including scope and jig.

Inp ut Puls e Le ve ls

Inp ut Ris e /Fall Time s

Inp ut Ti ming Refe re nce Le ve ls

Outp ut Re fe re nc e Le ve ls

Outp ut Load

GND to 3 . 0V

5ns

1.5V

Fi g ure s 1 and 2

3026 tbl 08

AC Electrical Characteristics Over the

Operating Temperature Supply Voltage Range(2)

71V321X25

71V421X25

Com'l

& Ind

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com 'l Only

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

Re ad Cycl e Time 25

____

Address Access Time

____

55 ns

ACE

Chip Enable Access Time

____

55 ns

AOE

Outp ut Enab le Acce ss Ti me

____

25 ns

Outp ut Hold fro m Ad d re ss Chang e 3

____

O ut p u t L o w -Z Ti m e

(1,2)

____

Output High-Z Time

(1,2)

____

30 ns

Chip Enab le to Power Up Time

(2)

____

Chi p Dis ab le to Po wer Down Time

(2)

____

50 ns

3026 tbl 0 9

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part numbers indicates power rating (S or L).

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

ACE

VALID DATA

50%

DATA

OUT

CURRENT

50%

3026 drw 07

(4)

(1)

(1) (2)

(2)

(4)

AOE

Timing Wa v eform of R ead Cyc le No. 2, Either Side (3)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.

4 . Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

Timing Wa veform of Read Cy c le No. 1, Either Side(1)

NOTES:

1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

3026 drw 06

BDD

(2,3)

BUSY

OUT

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over

voltage and temperature, the actual tDH will always be smaller than the actual tOW.

4. 'X' in part numbers indicates power rating (S or L).

5. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.

Symbol Parameter

71V321X25

71V421X25

Com'l

& I nd

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

UnitMin. Max. Min. Max. Min. Max.

WRI TE CYCLE

Write Cycle Time

(5)

____

Chip Enab le to End -o f-Write 20

____

Address Valid to End-of-Write 20

____

Address Set-up Time 0

____

Write Pulse Width 20

____

Write Rec ove ry Time 0

____

Data Valid to End-of-Write 12

____

Output Hig h-Z Time

(1,2)

____

30 ns

Data Ho l d Time

(3)

____

Write Enable to Output in High-Z

(1,2)

____

30 ns

Output Active from End-of-Write

(1,2)

____

3026 t bl 10

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Timing Wa v eform of Write Cyc le No. 2, (CE Controlled Timing)(1,5)

Timing Wav eform of Write Cyc le No. 1, (R/W Controlled Timing)(1,5,8)

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test

Load (Figure 2).

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be

placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified tWP.

ADDRESS

R/W

DATA

OUT

DATA

(2)

(4) (4)

3026 drw 08

(6)

(7)

(3) (7)

ADDRESS

R/W

DATA

3026 drw 09

(6) (2) (3)

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

NOTES:

1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

71V321X25

71V421X25

Com'l

& Ind

71V321X35

71V421X35

Com ' l Only

71V321X55

71V421X55

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

BUSY Ti m ing (For Master IDT7 1V321 Onl y)

BAA

BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns

BDA

BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns

BAC

BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 30 ns

BDC

BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 30 ns

Wri te Ho l d A fte r BUSY(5) 12 ____ 15 ____ 20 ____ ns

WDD

Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns

DDD

Wri te Data Val id to Re ad Da ta Del ay(1) ____ 35 ____ 45 ____ 65 ns

APS

Arbitratio n Prio ri ty Se t-up Ti me (2) 5____ 5____ 5____ ns

BDD

BUSY Disable to Valid Data(3) ____ 30 ____ 30 ____ 45 ns

BUSY Ti m ing (For S lave IDT71 V421 Onl y)

BUSY In p ut to Wri te (4) 0____ 0____ 0____ ns

Wri te Ho l d A fte r BUSY(5) 12 ____ 15 ____ 20 ____ ns

WDD

Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns

DDD

Wri te Data Val id to Re ad Da ta Del ay(1) ____ 35 ____ 45 ____ 65 ns

3 026 tb l 1

BDD

DDD

BDA

WDD

ADDR

"B"

ATA

OUT"B"

DATA

IN "A"

ADDR

"A"

MATCH

VALID

MATCH

VALID

R/W

"A"

BUSY

"B"

APS

3026 drw 10

(1)

BAA

Timing W av eform of Write with P ort-to-P ort Read and BUSY(2,3,4)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbritration Controlled

by Address Match Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).

NOTES:

1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.

3. tWB is for the slave version (71V421).

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".

Timing Wa veform of Write with BUSY(4)

BUSY

"B"

3026 drw 11

R/W

"A"

R/W

"B" (2)

(1)

(3)

APS

(2)

ADDR

A" AND "B" ADDRESSES MATCH

BAC

BDC

"B"

"A"

BUSY

"A"

3026 drw 12

BUSY

"B"

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

APS

DDR

"A"

DDR

"B"

RC OR

3026 drw 13

(2)

BAA

BDA

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

71V321X25

71V421X25

Com'l

& Ind

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

Address Set-up Time 0

____

Write Rec ove ry Time 0

____

INS

Inte rrup t S e t Time

____

45 ns

INR

In te r ru p t R e s et Ti m e

____

45 ns

3026 t bl 12

Timing Waveform of Interrupt Mode(1)

SET INT

CLEAR INT

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

INS

ADDR

"A"

INT

"B"

INTERRUPT ADDRESS

R/W

"A"

3026 drw 14

(3)

(2)

(4)

INTERRUPT CLEAR ADDRESS

DDR

"B"

INR

INT

"B"

3026 drw 15

(3)

(2)

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Table III — Address BUSY Arbitration

Table I. Non-Contention

Read/Write Control(4)

NOTES:

1. Pins BUSYL and BUSYR are both outputs for IDT71V321 (master). Both are inputs

for IDT71V421 (slave). BUSYX outputs on the IDT71V321 are totem-pole. On

slaves the BUSYX input internally inhibits writes.

2 . 'L' if the inputs to the opposite port were stable prior to the address and enable

inputs of this port. 'H' if the inputs to the opposite port became stable after the

address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR

= LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSYR outputs are driving LOW regardless of actual logic level

on the pin.

Truth Tables

T able II. Interrupt Flag(1,4)

NOTES:

1. A0L – A10L ≠ A0R – A10R.

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.

4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.

NOTES:

1. Assumes BUSYL = BUSYR = VIH

2. If BUSYL = VIL, then No Change.

3. If BUSYR = VIL, then No Change.

4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE

Left P ort Ri ght P ort

FunctionR/W

10L

-A

INT

R/W

10R

-A

INT

LLX7FFXXXX X L

(2)

S e t Ri g h t INT

Flag

XXX X XXLL 7FFH

(3)

Re s et Ri g ht INT

Flag

XXX XL

(3)

LLX7FEXSet Left INT

Flag

XLL7FEH

(2)

X X X X X Reset Left INT

Flag

3026 tbl 14

Inputs Outputs

Function

-A

10L

-A

10R

BUSY

(1)

BUSY

(1)

XX NO MATCH H H Normal

H X MATCH H H Normal

X H MATCH H H Normal

L L MATCH (2) (2) Write Inhib i t

(3)

3026 tbl 15

Left or Right Port

(1)

R/WCE OE D

0-7

Function

XHX Z Port Deselected and in Power-

Down Mode. I

SB2

or I

SB4

XHX Z CE

= CE

= V

IH,

Power-Down Mode I

SB1

or I

SB3

LLXDATA

Data o n P o rt Writte n Into Me m o ry

(2)

HLLDATA

OUT

Data in Memory Output o n Port

(3)

H L H Z High-impedance Outputs

3026 tbl 13

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

being expanded in depth, then the BUSY indication for the resulting array

requires the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an SRAM array in width while using BUSY logic, one

master part is used to decide which side of the SRAM array will receive

a BUSY indication. Any number of slaves to be addressed in the same

address range as the master, use the BUSY signal as a write inhibit signal.

Thus on the IDT71V321/IDT71V421 SRAMs the BUSY pin is an output

if the part is Master (IDT71V321), and the BUSY pin is an input if the part

is a Slave (IDT71V421) as shown in Figure 3.

Functional Description

The IDT7V1321/IDT71V421 provides two ports with separate control,

address and I/O pins that permit independent access for reads or writes

to any location in memory. The IDT71V321/IDT71V421 has an automatic

power down feature controlled by CE. The CE controls on-chip power

down circuitry that permits the respective port to go into a standby mode

when not selected (CE = VIH). When a port is enabled, access to the entire

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 7FE

(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table

II. The left port clears the interrupt by accessing address location 7FE when

CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt

flag (INTR) is asserted when the left port writes to memory location 7FF

(HEX) and to clear the interrupt flag (INTR), the right port must access the

memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,

since it is an addressable SRAM location. If the interrupt function is not used,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a busy indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY Logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation.

The BUSY outputs on the IDT71V321 RAM master are totem-pole type

outputs and do not require pull-up resistors to operate. If these RAMs are

3026 drw 16

MASTER

Dual Port

RAM

BUSY

MASTER

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

SLAVE

Dual Port

RAM

BUSY

DECODER

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

array and another master indicating BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and

inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a Master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with either the R/W signal or the byte enables. Failure

to observe this timing can result in a glitched internal write inhibit signal and

corrupted data in the slave.

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Ordering Information

NOTES:

1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

52-pin PLCC (J52-1)

64-pin TQFP (PN64-1)

64-pin STQFP (PP64-1)

XXXX

Device Type A999 A A

Power Speed Package Process/

Temperature

Range

16K (2K x 8-Bit) MASTER 3.3V

Dual-Port RAM w/ Interrupt

16K (2K x 8-Bit) SLAVE 3.3V

Dual-Port RAM w/ Interrupt

Speed in nanoseconds

3026 drw 17

Blank

(1)

71V321

71V421

Low Power

Standard Power

Commercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

Commercial & Industrial

Commercial Only

GGreen

(2)

Datasheet Document History

03/24/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 Added additional notes to pin configurations

06/15/99: Changed drawing format

10/15/99: Page 12 Changed open drain to totem-pole in Table III, note 1

10/21/99: Page 13 Deleted 'does not' in copy from Busy Logic

11/12/99: Replaced IDT logo

01/12/01: Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts

Page 3 Increased storage temperature parameters

Clarified TA parameter

Page 4 DC Electrical parameters–changed wording from "open" to "disabled"

Changed ±200mV to 0mV in notes

08/22/01: Pages 4, 5, 7, Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns

9 & 11

01/17/06: Page 1 Added green availability to features

Page 14 Added green indicator to ordering information

Page 1 & 14 Replaced old IDTTM with new IDTTM logo

Datasheet document history continued on page 15

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

Datasheet Document History (con't)

08/25/06: Page 11 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode

10/23/08: Page 14 Removed "IDT" from orderable part number