DGK-8DGN-8 D-8 DRB-8
1
2
3
4
8
7
6
5
NC
IN-
IN+
VS-
NC
VS+
VOUT
NC
THS4211
_
+
392
+5 V
49.9
VI
-5 V
50 Source
Low-Distortion, Wideband Application Circuit
NOTE: Power supply decoupling capacitors not shown
VO
392
50
THS4211
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
1 10 100
Harmonic Distortion - dBc
HARMONIC DISTORTION
vs
FREQUENCY
f - Frequency - MHz
Gain = 2
Rf = 392
RL = 150
VO = 2 VPP
VS = ±5 V
HD2
HD3
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
LOW-DISTORTION, HIGH-SPEED, VOLTAGE FEEDBACK AMPLIFIER
Check for Samples: THS4211 THS4215
1FEATURES DESCRIPTION
23 Unity-Gain Stability
Wide Bandwidth: 1 GHz The THS4211 and THS4215 are high slew rate,
unity-gain stable, voltage feedback amplifiers
High Slew Rate: 970 V/µs designed to run from supply voltages as low as 5 V
Low Distortion: and as high as 15 V. The THS4215 offers the same
–90 dBc THD at 30 MHz performance as the THS4211 with the addition of
power-down capability. The combination of high slew
130-MHz Bandwidth (0.1 dB, G = 2) rate, wide bandwidth, low distortion, and unity-gain
0.007% Differential Gain stability make the THS4211 and THS4215
0.003° Differential Phase high-performance devices across multiple ac
specifications.
High Output Drive, IO= 170 mA
Excellent Video Performance: Designers using the THS4211 are rewarded with
higher dynamic range over a wider frequency band
130-MHz Bandwidth (0.1 dB, G = 2) without the stability concerns of decompensated
0.007% Differential Gain amplifiers. These devices are available in SOIC,
0.003° Differential Phase MSOP with PowerPAD™, and leadless MSOP with
PowerPAD packages.
Supply Voltages
+5 V, ±5 V, +12 V, +15 V RELATED DEVICES
Power Down Functionality (THS4215) DEVICE DESCRIPTION
Evaluation Module Available THS4271 1.4-GHz voltage feedback amplifier
THS4503 Wideband, fully differential amplifier
APPLICATIONS THS3202 Dual, wideband current feedback amplifier
High Linearity ADC Preamplifier
Differential to Single-Ended Conversion
DAC Output Buffer
Active Filtering
Video Applications
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
UNIT
Supply voltage, VS16.5 V
Input voltage, VI±VS
Output current, IO250 mA
Continuous power dissipation See Dissipation Ratings Table
Maximum junction temperature, TJ(2) +150°C
Maximum junction temperature, continuous operation, long-term reliability TJ(3) +125°C
Storage temperature range, Tstg –65°C to +150°C
HBM 4000 V
ESD ratings CDM 1500 V
MM 200 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS(1)
POWER RATING (3)
θJC θJA (2)
PACKAGE (°C/W) (°C/W) TA+25°C TA= +85°C
D (8-pin) 38.3 97.5 1.02 W 410 mW
DGN (8-pin)(1) 4.7 58.4 1.71 W 685 mW
DGK (8-pin) 54.2 260 385 mW 154 mW
DRB (8-pin) 5 45.8 2.18 W 873 mW
(1) The THS4211/5 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
(2) This data was taken using the JEDEC standard High-K test PCB.
(3) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long
term reliability.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Dual supply ±2.5 ±7.5
Supply voltage, (VS+ and VS–) V
Single supply 5 15
Input common-mode voltage range VS– + 1.2 VS+ 1.2 V
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Product Folder Link(s): THS4211 THS4215
(TOP VIEW) D, DRB, DGK, DGN
(TOP VIEW) D, DRB, DGK, DGN
1
NC NC
THS4211
2
3
4
8
7
6
5
IN-
IN+
VS-
VS+
VOUT
NC
1
REF PD
THS4215
2
3
4
8
7
6
5
IN-
IN+
VS-
VS+
VOUT
NC
NC = No Connetion NC = No Connection
See Note A.
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
PACKAGING/ORDERING INFORMATION(1)
PACKAGED DEVICES PACKAGE TYPE PACKAGE MARKING TRANSPORT MEDIA, QUANTITY
Non-power-down
THS4211D Rails, 75
SOIC-8
THS4211DR Tape and Reel, 2500
THS4211DGK Rails, 100
MSOP-8 BEJ
THS4211DGKR Tape and Reel, 2500
THS4211DRBT Tape and Reel, 250
QFN-8-PP(2) BET
THS4211DRBR Tape and Reel, 3000
THS4211DGN Rails, 80
MSOP-8-PP(2) BFN
THS4211DGNR Tape and Reel, 2500
Power-down
THS4215D Rails, 75
SOIC-8
THS4215DR Tape and Reel, 2500
THS4215DGK Rails, 100
MSOP-8 BEZ
THS4215DGKR Tape and Reel, 2500
THS4215DRBT Tape and Reel, 250
QFN-8-PP(2) BEU
THS4215DRBR Tape and Reel, 3000
THS4215DGN Rails, 80
MSOP-8-PP(2) BFQ
THS4215DGNR Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The PowerPAD is electrically isolated from all other pins.
PIN ASSIGNMENTS
NOTE A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= ±5 V
At RF= 392 , RL= 499 , and G = +2, unless otherwise noted. TYP OVER TEMPERATURE MIN/
–40°C
PARAMETER TEST CONDITIONS TYP/
0°C to
+25°C +25°C to UNITS MAX
+70°C +85°C
AC PERFORMANCE
G = 1, POUT = –7 dBm 1 GHz Typ
G = –1, POUT = –16 dBm 325 MHz Typ
Small-signal bandwidth G = 2, POUT = –16 dBm 325 MHz Typ
G = 5, POUT = –16 dBm 70 MHz Typ
G = 10, POUT = –16 dBm 35 MHz Typ
0.1-dB flat bandwidth G = 1, POUT = –7 dBm 70 MHz Typ
Gain bandwidth product G > 10, f = 1 MHz 350 MHz Typ
Full-power bandwidth G = –1, VO= 2 Vp77 MHz Typ
G = 1, VO= 2 V Step 970 V/µs Typ
Slew rate G = –1, VO= 2 V Step 850 V/µs Typ
Settling time to 0.1% 22 ns Typ
G = –1, VO= 4 V Step
Settling time to 0.01% 55 ns Typ
Harmonic distortion RL= 150 –78 dBc Typ
2nd-order harmonic distortion RL= 499 –90 dBc Typ
G = 1, VO= 1 VPP,
f = 30 MHz RL= 150–100 dBc Typ
3rd-order harmonic distortion RL= 499 –100 dBc Typ
Harmonic distortion RL= 150 –68 dBc Typ
2nd-order harmonic distortion RL= 499 –70 dBc Typ
G = 2, VO= 2 VPP,
f = 30 MHz RL= 150–80 dBc Typ
3rd-order harmonic distortion RL= 499 –82 dBc Typ
3rd-order intermodulation (IMD3) G = 2, VO= 2 VPP, RL= 150 , f = 70 MHz –53 dBc Typ
3rd-order output intercept (OIP3) G = 2, VO= 2 VPP, RL= 150 , f = 70 MHz 32 dBm Typ
Differential gain (NTSC, PAL) 0.007 % Typ
G = 2, RL= 150
Differential phase (NTSC, PAL) 0.003 ° Typ
Input voltage noise f = 1 MHz 7 nV/Hz Typ
Input current noise f = 10 MHz 4 pAHz Typ
DC PERFORMANCE
Open-loop voltage gain (AOL) VO= ±0.3 V, RL= 499 70 65 62 60 dB Min
Input offset voltage 3 12 14 14 mV Max
Average offset voltage drift ±40 ±40 µV/°C Typ
Input bias current 7 15 18 20 µA Max
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C Typ
Input offset current 0.3 6 7 8 µA Max
Average offset current drift ±10 ±10 nA/°C Typ
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THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS: VS= ±5 V (continued)
At RF= 392 , RL= 499 , and G = +2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/
–40°C
PARAMETER TEST CONDITIONS TYP/
0°C to
+25°C +25°C to UNITS MAX
+70°C +85°C
INPUT CHARACTERISTICS
Common-mode input range ±4 ±3.8 ±3.7 ±3.6 V Min
Common-mode rejection ratio VCM = ± 1 V 56 52 50 48 dB Min
Input resistance Common-mode 4 MTyp
Input capacitance Common-mode/differential 0.3/0.2 pF Typ
OUTPUT CHARACTERISTICS
Output voltage swing ±4.0 ±3.8 ±3.7 ±3.6 V Min
Output current (sourcing) 220 200 190 180 mA Min
RL= 10
Output current (sinking) 170 140 130 120 mA Min
Output impedance f = 1 MHz 0.3 Typ
POWER SUPPLY
Specified operating voltage ±5 ±7.5 ±7.5 ±7.5 V Max
Maximum quiescent current 19 22 23 24 mA Max
Minimum quiescent current 19 16 15 14 mA Min
Power-supply rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 5 V 64 58 54 54 dB Min
Power-supply rejection (–PSRR) VS+ = 5 V, VS– = –5.5 V to –4.5 V 65 60 56 56 dB Min
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
Enable REF+1.8 V Min
REF = 0 V, or VS– Power-down REF+1 V Max
Power-down voltage level Enable REF–1 V Min
REF = VS+ or Floating Power-down REF–1.5 V Max
PD = Ref +1.0 V, Ref = 0 V 650 850 900 1000 µA Max
Power-down quiescent current PD = Ref –1.5 V, Ref = 5 V 450 650 800 900 µA Max
Turn-on time delay(t(ON)) 50% of final supply current value 4 µs Typ
Turn-off time delay (t(Off)) 50% of final supply current value 3 µs Typ
Input impedance 4 GTyp
Output impedance f = 1 MHz 250 kTyp
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= 5 V
At RF= 392 , RL= 499 , and G = +2, unless otherwise noted. TYP OVER TEMPERATURE MIN/
–40°C
PARAMETER TEST CONDITIONS TYP/
0°C to
+25°C +25°C to UNITS MAX
+70°C +85°C
AC PERFORMANCE
G = 1, POUT = –7 dBm 980 MHz Typ
G = –1, POUT = –16 dBm 300 MHz Typ
Small-signal bandwidth G = 2, POUT = –16 dBm 300 MHz Typ
G = 5, POUT = –16 dBm 65 MHz Typ
G = 10, POUT = –16 dBm 30 MHz Typ
0.1-dB flat bandwidth G = 1, POUT = –7 dBm 90 MHz Typ
Gain bandwidth product G > 10, f = 1 MHz 300 MHz Typ
Full-power bandwidth G = –1, VO= 2 Vp64 MHz Typ
G = 1, VO= 2 V Step 800 V/µs Typ
Slew rate G = –1, VO= 2 V Step 750 V/µs Typ
Settling time to 0.1% 22 ns Typ
G = –1, VO= 2 V Step
Settling time to 0.01% 84 ns Typ
Harmonic distortion RL= 150 –60 dBc Typ
2nd-order harmonic distortion RL= 499 –60 dBc Typ
G = 1, VO= 1 VPP,
f = 30 MHz RL= 150 –68 dBc Typ
3rd-order harmonic distortion RL= 499 –68 dBc Typ
3rd-order intermodulation (IMD3) –70 dBc Typ
G = 1, VO= 1 VPP, RL= 150 , f = 70 MHz
3rd-order output intercept (OIP3) 34 dBm Typ
Input-voltage noise f = 1 MHz 7 nV/Hz Typ
Input-current noise f = 10 MHz 4 pA/Hz Typ
DC PERFORMANCE
Open-loop voltage gain (AOL) VO= ± 0.3 V, RL= 499 68 63 60 60 dB Min
Input offset voltage 3 12 14 14 mV Max
Average offset voltage drift ±40 ±40 µV/°C Typ
Input bias current 7 15 17 18 µA Max
VCM = VS/2
Average bias current drift ±10 ±10 nA/°C Typ
Input offset current 0.3 6 7 8 µA Max
Average offset current drift ±10 ±10 nA/°C Typ
INPUT CHARACTERISTICS
Common-mode input range 1/4 1.2/3.8 1.3/3.7 1.4/3.6 V Min
Common-mode rejection ratio VCM = ± 0.5 V, VO= 2.5 V 54 50 48 45 dB Min
Input resistance Common-mode 4 MTyp
Input capacitance Common-mode/differential 0.3/0.2 pF Typ
OUTPUT CHARACTERISTICS
Output voltage swing 1/4 1.2/3.8 1.3/3.7 1.4/3.6 V Min
Output current (sourcing) 230 210 190 180 mA Min
RL= 10
Output current (sinking) 150 120 100 90 mA Min
Output impedance f = 1 MHz 0.3 Typ
6Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS: VS= 5 V (continued)
At RF= 392 , RL= 499 , and G = +2, unless otherwise noted.
TYP OVER TEMPERATURE MIN/
–40°C
PARAMETER TEST CONDITIONS TYP/
0°C to
+25°C +25°C to UNITS MAX
+70°C +85°C
POWER SUPPLY
Specified operating voltage 5 15 15 15 V Max
Maximum quiescent current 19 22 23 24 mA Max
Minimum quiescent current 19 16 15 14 mA Min
Power-supply rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 0 V 63 58 54 54 dB Min
Power-supply rejection (–PSRR) VS+ = 5 V, VS– = –0.5 V to 0.5 V 65 60 56 56 dB Min
POWER-DOWN CHARACTERISTICS (THS4215 ONLY)
Enable REF+1.8 V Min
REF = 0 V, or VS– Power down REF+1 V Max
Power-down voltage level Enable REF–1 V Min
REF = VS+ or floating Power down REF–1.5 V Max
Power-down quiescent current PD = Ref +1.0 V, Ref = 0 V 450 650 750 850 µA Max
Power-down quiescent current PD = Ref –1.5 V, Ref = 5 V 400 650 750 850 µA Max
Turn-on-time delay(t(ON)) 4 µs Typ
50% of final value
Turn-off-time delay (t(Off)) 3 µs Typ
Input impedance 6 GTyp
Output impedance f = 1 MHz 75 kTyp
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs 5 V)
FIGURE
Small-signal unity-gain frequency response 1
Small-signal frequency response 2
0.1-dB gain flatness frequency response 3
Large-signal frequency response 4
Slew rate vs Output voltage 5
Harmonic distortion vs Frequency 6, 7, 8, 9
Harmonic distortion vs Output voltage swing 10, 11, 12, 13
Third-order intermodulation distortion vs Frequency 14, 16
Third-order output intercept point vs Frequency 15, 17
Voltage and current noise vs Frequency 18
Differential gain vs Number of loads 19
Differential phase vs Number of loads 20
Settling time 21
Quiescent current vs supply voltage 22
Output voltage vs Load resistance 23
Frequency response vs Capacitive load 24
Open-loop gain and phase vs Frequency 25
Open-loop gain vs Case temperature 26
Rejection ratios vs Frequency 27
Rejection ratios vs Case temperature 28
Common-mode rejection ratio vs Input common-mode range 29
Input offset voltage vs Case temperature 30
Input bias and offset current vs Case temperature 31
Small-signal transient response 32
Large-signal transient response 33
Overdrive recovery 34
Closed-loop output impedance vs Frequency 35
Power-down quiescent current vs Supply voltage 36
Power-down output impedance vs Frequency 37
Turn-on and turn-off delay times 38
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THS4215
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................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
Table of Graphs (5 V)
FIGURE
Small-signal unity-gain frequency response 39
Small-signal frequency response 40
0.1-dB gain flatness frequency response 41
Large-signal frequency response 42
Slew rate vs Output voltage 43
Harmonic distortion vs Frequency 44, 45, 46, 47
Harmonic distortion vs Output voltage swing 48, 49, 50, 51
Third-order intermodulation distortion vs Frequency 52, 54
Third-order intercept point vs Frequency 53, 55
Voltage and current noise vs Frequency 56
Settling time 57
Quiescent current vs Supply voltage 58
Output voltage vs Load resistance 59
Frequency response vs Capacitive load 60
Open-loop gain and phase vs Frequency 61
Open-loop gain vs Case temperature 62
Rejection ratios vs Frequency 63
Rejection ratios vs Case temperature 64
Common-mode rejection ratio vs Input common-mode range 65
Input offset voltage vs Case temperature 66
Input bias and offset current vs Case temperature 67
Small-signal transient response 68
Large-signal transient response 69
Overdrive recovery 70
Closed-loop output impedance vs Frequency 71
Power-down quiescent current vs Supply voltage 72
Power-down output impedance vs Frequency 73
Turn-on and turn-off delay times 74
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): THS4211 THS4215
-4
-3
-2
-1
0
1
2
3
4
5
100 k 1 M 10 M 100 M 1 G 10 G
f - Frequency - Hz
Small Signal Gain - dB
Gain = 1
RL = 499
VO = 250 mV
VS = ±5 V
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Small Signal Gain - dB
Gain = 10
Gain = 5
Gain = 2
Gain = -1
RL = 499
Rf = 392
VO = 250 mV
VS = ±5 V
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
Gain = 1
RL = 499
VO = 250 mV
VS = ±5 V
f - Frequency - Hz
Small Signal Gain - dB
1 M 10 M 100 M 1 G
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Large Signal Gain - dB
Gain = 1
RL = 499
VO = 2 VPP
VS = ±5 V
-4
-3
-2
-1
0
1
-100
-95
-90
-85
-80
-75
-70
-65
-60
1 10 100
Harmonic Distortion - dBc
f - Frequency - MHz
Gain = 1
VO = 1 VPP
VS = ±5 V
HD2, RL = 150
HD3, RL = 150
and RL = 499
HD2, RL = 499
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VO - Output Voltage - V
SR - Slew Rate - sµ
V/
RL = 499
Rf = 392
VS = ±5 V
0
200
400
600
800
1000
1200
1400
Fall, Gain = 1
Rise, Gain = 1
Fall, Gain =- 1
Rise, Gain = -1
HD3, RL = 150Ω,
and RL = 499
Harmonic Distortion - dBc
f - Frequency - MHz
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
1 10 100
HD2, RL = 150
HD2, RL = 499
Gain = 2
Rf = 392
VO = 2 VPP
VS = ±5 V
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
1 10 100
Harmonic Distortion - dBc
f - Frequency - MHz
Gain = 2
Rf = 392
VO = 1 VPP
VS = ±5 V
HD2, RL = 499
HD2, RL = 150
HD3, RL = 150Ω,
and RL = 499
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNITY GAIN SMALL-SIGNAL FREQUENCY 0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
SLEW RATE HARMONIC DISTORTION
LARGE-SIGNAL FREQUENCY vs vs
RESPONSE OUTPUT VOLTAGE FREQUENCY
Figure 4. Figure 5. Figure 6.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 7. Figure 8. Figure 9.
10 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
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-100
-95
-90
-85
-80
-75
-70
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - ±V
HD2, RL = 499
HD3, RL = 150
HD2, RL = 150
HD3, RL = 499
Gain = 1
f= 8 MHz
VS = ±5 V
Harmonic Distortion - dBc
VO - Output Voltage Swing - ±V
Gain = 1
f= 32 MHz
VS = ±5 V
HD2, RL = 499
HD2, RL = 150
HD3, RL = 150
HD3, RL = 499
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-100
-95
-90
-85
-80
-75
-70
-65
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - ±V
Gain = 2
Rf = 249
f = 8 MHz
VS = ±5 V
HD3, RL = 150
HD2, RL = 499
HD3, RL = 499
HD2, RL = 150
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
0 1 2 3 4 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - ±V
Gain = 2
Rf = 249
f = 32 MHz
VS = ±5 V
HD3, RL = 150
HD2, RL = 499
HD2, RL = 150
HD3, RL = 499
0.5 1.5 2.5 3.5 4.5
30
35
40
45
50
55
60
0 20 40 60 80 100
VO = 2 VPP
VO = 1 VPP
Gain = 1
RL = 150
VS = ±5 V
200 kHz Tone Spacing
Third-Order Output Intersept Point - dBm
f - Frequency - MHz
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
10 100
Third-Order Intermodulation Distortion - dBc
f - Frequency - MHz
VO = 2 VPP
VO = 1 VPP
Gain = 1
RL = 150
VS = ±5 V
200 kHz Tone Spacing
1
10
100
1 k 10 k 100 k 1 M 10 M 100 M
1
10
100
Vn
In
f - Frequency - Hz
- Voltage Noise - nV/ Hz
Vn
- Current Noise - pA/ Hz
In
Third-Order Intermodulation Distortion - dBc
f - Frequency - MHz
Gain = 2
RL = 150
VS = ±5 V
200 kHz Tone Spacing
VO = 2 VPP
VO = 1 VPP
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
10 100
20
25
30
35
40
45
50
55
60
0 20 40 60 80 100
Third-Order Output Intersept Point - dBm
f - Frequency - MHz
Gain = 2
RL = 150
VS = ±5 V
200 kHz Tone Spacing
VO = 1 VPP
VO = 2 VPP
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 10. Figure 11. Figure 12.
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT
HARMONIC DISTORTION DISTORTION INTERCEPT POINT
vs vs vs
OUTPUT VOLTAGE SWING FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT
DISTORTION INTERCEPT POINT VOLTAGE AND CURRENT NOISE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 16. Figure 17. Figure 18.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): THS4211 THS4215
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0 1 2 3 4 5 6 7 8
Number of Loads - 150
Differential Phase -
Gain = 2
Rf = 392
VS = ±5 V
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
NTSC
PAL
°
-5
-4
-3
-2
-1
0
1
2
3
4
5
10 100 1000
RL - Load Resistance -
- Output Voltage - VVO
TA = -40 to 85°C
10
12
14
16
18
20
22
2.5 3 3.5 4 4.5 5
TA = -40°C
VS - Supply Voltage - ±V
Quiescent Current - mA
TA = 85°CTA = 25°C
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
100 k 1 M 10 M 100 M 1 G
Capacitive Load - Hz
Normalized Gain - dB
R(ISO) = 15
CL = 50 pF
VS =±5 V
R(ISO) = 10
CL = 100 pF
R(ISO) = 25
CL = 10 pF
60
65
70
75
80
85
90
2.5 3 3.5 4 4.5 5
Open-Loop Gain - dB
Case Temperature - °C
TA = -40°C
TA = 85°CTA = 25°C
0
10
20
30
40
50
60
70
100 k 1 M 10 M 100 M 1 G
CMRR
VS = ±5 V
Rejection Ratios - dB
f - Frequency - Hz
PSRR+
PSRR-
80
-10
0
10
20
30
40
50
60
70
10 k 100 k 1 M 10 M 100 M 1 G
0
20
40
60
80
100
120
160
180
Open-Loop Gain - dB
f - Frequency - Hz
VS = ±5 V
Phase - °
140
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: ±5 V (continued)
DIFFERENTIAL GAIN DIFFERENTIAL PHASE
vs vs
NUMBER OF LOADS NUMBER OF LOADS SETTLING TIME
Figure 19. Figure 20. Figure 21.
QUIESCENT CURRENT OUTPUT VOLTAGE FREQUENCY RESPONSE
vs vs vs
SUPPLY VOLTAGE LOAD RESISTANCE CAPACITIVE LOAD
Figure 22. Figure 23. Figure 24.
OPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN REJECTION RATIOS
vs vs vs
FREQUENCY CASE TEMPERATURE FREQUENCY
Figure 25. Figure 26. Figure 27.
12 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
0
10
20
30
40
50
60
70
80
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios - dB
Case Temperature - °C
VS = ±5 V PSRR-
CMMR
PSRR+
0
5
10
15
20
25
30
35
40
45
50
55
60
-4.5 -3 -1.5 0 1.5 3 4.5
Input Common-Mode Range - V
CMRR - Common-Mode Rejection Ratio - dB
VS = ±5 V
TA = 25°C
0
1
2
3
4
5
6
7
8
9
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
VS = 5 V
VS = ±5 V
TC - Case Temperature - °C
- Input Offset Voltage - mV
VOS
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
6.6
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
- Input Bias Current -
TC - Case Temperature - °C
VS = ±5 V
- Input Offset Current -
IIB-
IIB Aµ
IOS Aµ
IIB+
IOS
-1.5
-1
-0.5
0
0.5
1
1.5
-2 0 2 4 6 8 10 12 14 16 18 20
t - Time - ns
- Output Voltage - VVO
Gain = -1
RL = 499
Rf = 392
tr/tf = 300 ps
VS = ±5 V
0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-3
-2.5
-2
-1.5
-1
-0.5
0.5
1
1.5
2
2.5
3
t - Time - µs
Single-Ended Output Voltage - V
- Input Voltage - VVI
VS = ±5 V
0.01
0.1
1
10
100
1 k
10 k
100 k
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Closed-Loop Output Impedance -
RL = 499 ,
RF = 392 ,
PIN = -4 dBm
VS = ±5 V
0
100
200
300
400
500
600
700
800
2.5 3 3.5 4 4.5 5
VS - Supply Voltage - ±V
Power-Down Quiescent Current -
TA = 85°C
TA = 25°C
Aµ
TA = -40°C
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: ±5 V (continued)
REJECTION RATIOS COMMON-MODE REJECTION RATIO INPUT OFFSET VOLTAGE
vs vs vs
CASE TEMPERATURE INPUT COMMON-MODE RANGE CASE TEMPERATURE
Figure 28. Figure 29. Figure 30.
INPUT BIAS AND OFFSET
CURRENT
vs SMALL-SIGNAL TRANSIENT LARGE-SIGNAL TRANSIENT
CASE TEMPERATURE RESPONSE RESPONSE
Figure 31. Figure 32. Figure 33.
CLOSED-LOOP OUTPUT POWER-DOWN QUIESCENT
IMPEDANCE CURRENT
vs vs
OVERDRIVE RECOVERY FREQUENCY SUPPLY VOLTAGE
Figure 34. Figure 35. Figure 36.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
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-0.005
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
-0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
-7.5
-6
-4.5
-3
-1.5
0
1.5
3
4.5
6
t - Time - ns
- Output Voltage Level - VVO
Gain = -1
RL = 499
VS = ±5 V
- Input Voltage Level - VVI
0
0.001
0.1
10
1000
100 k 1 M 10 M 100 M 1 G 10 G
f - Frequency - Hz
Power-Down Output Impedance -
Gain = 1
RL = 499
PIN = -1 dBm
VS = ±5 V
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Small Signal Gain - dB
Gain = 10
Gain = 5
Gain = 2
Gain = -1
RL = 499
Rf = 392
VO = 250 mV
VS = 5 V
1 G
-4
-3
-2
-1
0
1
2
3
4
100 k 1 M 10 M 100 M 10 G
f - Frequency - Hz
Gain = 1
RL = 499
VO = 250 mV
VS = 5 V
Small Signal Gain - dB
0
100
200
300
400
500
600
700
800
900
1000
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
SR - Slew Rate - V/
VO - Output Voltage -V
sµ
RL = 499
Rf = 392
VS = 5 V
Fall, G = 1
Rise, G = 1
Fall, G = -1
Rise, G = -1
-4
-3
-2
-1
0
1
100 K 1 M 10 M 100 M 1 G
f - Frequency - Hz
Large Signal Gain - dB
Gain = 1
RL = 499
VO = 2 VPP
VS = 5 V
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: ±5 V (continued)
POWER-DOWN
OUTPUT IMPEDANCE
vs TURN-ON AND TURN-OFF TIMES
FREQUENCY DELAY TIME
Figure 37. Figure 38.
TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY GAIN SMALL-SIGNAL 0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 39. Figure 40. Figure 41.
SLEW RATE HARMONIC DISTORTION
LARGE-SIGNAL vs vs
FREQUENCY RESPONSE OUTPUT VOLTAGE FREQUENCY
Figure 42. Figure 43. Figure 44.
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Product Folder Link(s): THS4211 THS4215
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
110 100
HD2
HD3
Harmonic Distortion - dBc
f - Frequency - MHz
Gain = 1
VO = 2 VPP
RL = 150 , and 499
VS = 5 V
-100
-90
-80
-70
-60
-50
-40
110 100
HD2
HD3
Harmonic Distortion - dBc
f - Frequency - MHz
Gain = 2
VO = 1 VPP
Rf = 392
RL = 150 and 499
VS = 5 V
-90
-80
-70
-60
-50
-40
-30
1 10 100
HD2
HD3
Harmonic Distortion - dBc
f - Frequency - MHz
Gain = 2
VO = 2 VPP
Rf = 392
RL = 150 and 499
VS = 5 V
-100
-95
-90
-85
-80
-75
-70
-65
-60
0 0.5 1 1.5 2 2.5
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
HD2
HD3
Gain = 1
RL = 150 , and 499 ,
f = 8 MHz
VS = 5 V
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
0 0.5 1 1.5 2 2.5
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
HD2
HD3
Gain = 2
Rf = 392
RL = 150 and 499
f = 8 MHz
VS = 5 V
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
0 0.5 1 1.5 2 2.5
HD2
HD3
Gain = 1
RL = 150 , and 499 ,
f = 32 MHz
VS = 5 V
Harmonic Distortion - dBc
VO - Output Voltage Swing - V
HD2
HD3
Gain = 2
Rf = 392
RL = 150 and 499
f = 32 MHz
VS = 5 V
-80
-75
-70
-65
-60
-55
-50
-45
-40
0 0.5 1 1.5 2 2.5
30
35
40
45
50
0 10 20 30 40 50 60 70 80
Third-Order Output Intersept Point - dBm
f - Frequency - MHz
Gain = 1
RL = 150
VS = 5 V
200 kHz Tone Spacing
VO = 2VPP
VO = 1VPP
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
10 100
Third-Order Intermodulation Distortion - dBc
f - Frequency - MHz
Gain = 1
RL = 150
VS = 5 V
200 kHz Tone
Spacing
VO = 2VPP
VO = 1VPP
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 45. Figure 46. Figure 47.
HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 48. Figure 49. Figure 50.
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION DISTORTION POINT
vs vs vs
OUTPUT VOLTAGE SWING FREQUENCY FREQUENCY
Figure 51. Figure 52. Figure 53.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
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1
10
100
1 k 10 k 100 k 1 M 10 M 100 M
1
10
100
Vn
In
f - Frequency - Hz
- Voltage Noise - nV/ Hz
Vn
- Current Noise - pA/ Hz
In
-100
-90
-80
-70
-60
-50
-40
-30
10 100
Third-Order Intermodulation Distortion - dBc
f - Frequency - MHz
Gain = 1
RL = 150
VS = 5 V
200 kHz Tone
Spacing
VO = 2 VPP
VO = 1 VPP
10
15
20
25
30
35
40
45
50
0 20 40 60 80 100
Third-Order Output Intersept Point - dBm
f - Frequency - MHz
Gain = 2
RL = 150
VS = 5 V
200 kHz Tone Spacing
VO = 2 VPP
VO = 1 VPP
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
10 100 1000
RL - Load Resistance -
- Output Voltage - VVO
TA = -40 to 85°C
-1.5
-1
-0.5
0
0.5
1
1.5
0 5 10 15 20 25
t - Time - ns
- Output Voltage - VVO
Rising Edge
Falling Edge
Gain = -1
RL = 499
Rf = 392
f= 1 MHz
VS = 5 V
10
12
14
16
18
20
22
2.5 3 3.5 4 4.5 5
TA = -40°C
VS - Supply Voltage - ±V
Quiescent Current - mA
TA = 85°CTA = 25°C
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
100 k 1 M 10 M 100 M 1 G
Capacitive Load - Hz
Normalized Gain - dB
R(ISO) = 15
CL = 50 pF
VS = 5 V
R(ISO) = 10
CL = 100 pF
R(ISO) = 25 Ω, CL = 10 pF
60
65
70
75
80
85
90
2.5 3 3.5 4 4.5 5
Open-Loop Gain - dB
Case Temperature - °C
TA = -40°C
TA = 85°CTA = 25°C
80
-10
0
10
20
30
40
50
60
70
10 k 100 k 1 M 10 M 100 M 1 G
0
20
40
60
80
100
120
160
180
Open-Loop Gain - dB
f - Frequency - Hz
VS = 5 V
Phase - °
140
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
THIRD-ORDER INTERMODULATION THIRD-ORDER OUTPUT INTERCEPT
DISTORTION POINT VOLTAGE AND CURRENT NOISE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 54. Figure 55. Figure 56.
QUIESCENT CURRENT OUTPUT VOLTAGE
vs vs
SETTLING TIME SUPPLY VOLTAGE LOAD RESISTANCE
Figure 57. Figure 58. Figure 59.
FREQUENCY RESPONSE OPEN-LOOP GAIN AND PHASE OPEN-LOOP GAIN
vs vs vs
CAPACITIVE LOAD FREQUENCY CASE TEMPERATURE
Figure 60. Figure 61. Figure 62.
16 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
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0
10
20
30
40
50
60
70
80
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
Rejection Ratios - dB
Case Temperature - °C
VS = 5 V PSRR-
CMMR
PSRR+
0
5
10
15
20
25
30
35
40
45
50
55
60
012345
Input Common-Mode Voltage Range - V
CMRR - Common-Mode Rejection Ratio - dB
VS = 5 V
5.6
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
6.6
-40-30-20-10 0 10 20 30 40 50 60 70 80 900.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
- Input Bias Current -
TC - Case Temperature - °C
VS = 5 V
- Input Offset Current -
IIB-
IIB Aµ
IOS Aµ
IIB+
IOS
0
1
2
3
4
5
6
7
8
9
-40-30-20-10 0 10 20 30 40 50 60 70 80 90
VS = 5 V
VS = ±5 V
TC - Case Temperature - °C
- Input Offset Voltage - mV
VOS
0
-3
-2
-1
0
1
2
3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1.5
-1
-0.5
0.5
1
1.5
t - Time - µs
Single-Ended Output Voltage - V
- Input Voltage - VVI
VS = 5 V
-1.5
-1
-0.5
0
0.5
1
1.5
-2 0 2 4 6 8 10 12 14 16 18 20
t - Time - ns
- Output Voltage - VVO
Gain = -1
RL = 499
Rf = 392
tr/tf = 300 ps
VS = 5 V
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS: 5 V (continued)
REJECTION RATIOS REJECTION RATIOS COMMON-MODE REJECTION RATIO
vs vs vs
FREQUENCY CASE TEMPERATURE INPUT COMMON-MODE RANGE
Figure 63. Figure 64. Figure 65.
INPUT BIAS AND OFFSET
INPUT OFFSET VOLTAGE CURRENT
vs vs SMALL-SIGNAL TRANSIENT
CASE TEMPERATURE CASE TEMPERATURE RESPONSE
Figure 66. Figure 67. Figure 68.
CLOSED-LOOP OUTPUT
IMPEDANCE
LARGE-SIGNAL TRANSIENT vs
RESPONSE OVERDRIVE RECOVERY FREQUENCY
Figure 69. Figure 70. Figure 71.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS4211 THS4215
t - Time - ns
- Output Voltage Level - VVO
Gain = -1
RL = 499
VS = 5 V
- Input Voltage Level - VVI
-0.005
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
-0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
-7.5
-6
-4.5
-3
-1.5
0
1.5
3
4.5
0
100
200
300
400
500
600
700
800
2.5 3 3.5 4 4.5 5
VS - Supply Voltage - ±V
TA = 85°C
TA = 25°C
TA = -40°C
Power-Down Quiescent Current - Aµ
0.001
0.1
10
1000
100 k 1 M 10 M 100 M 1 G 10 G
f - Frequency - Hz
Gain = 1
RL = 499
PIN = -1 dBm
VS = 5 V
Power-Down Output Impedance -
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN QUIESCENT POWER-DOWN OUTPUT
CURRENT IMPEDANCE
vs vs TURN-ON AND TURN-OFF TIMES
SUPPLY VOLTAGE FREQUENCY DELAY TIME
Figure 72. Figure 73. Figure 74.
18 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
_
+
THS4211
Rf
392
49.9
100 pF
0.1 µF 6.8 µF
-VS
-5 V
Rg
50 Source
+
VI
100 pF 0.1 µF 6.8 µF
+
+VS
5 V
VO
499
392
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
APPLICATION INFORMATION
HIGH-SPEED OPERATIONAL AMPLIFIERS WIDEBAND, NONINVERTING OPERATION
The THS4211 and the THS4215 operational The THS4211 and the THS4215 are unity-gain
amplifiers set new performance levels, combining low stable, 1-GHz voltage-feedback operational
distortion, high slew rates, low noise, and a unity-gain amplifiers, with and without power-down capability,
bandwidth in excess of 1 GHz. To achieve the full designed to operate from a single 5-V to 15-V power
performance of the amplifier, careful attention must supply.
be paid to printed-circuit board (PCB) layout and Figure 75 shows the noninverting gain configuration
component selection. of 2 V/V used to demonstrate the typical performance
The THS4215 provides a power-down mode, curves. Most of the curves were characterized using
providing the ability to save power when the amplifier signal sources with 50-source impedance, and with
is inactive. A reference pin is provided to allow the measurement equipment presenting a 50-load
user the flexibility to control the threshold levels of the impedance. In Figure 75, the 49.9-shunt resistor at
power-down control pin. the VIN terminal matches the source impedance of the
test generator. The total 499-load at the output,
combined with the 784-total feedback-network
Applications Section Contents load, presents the THS4211 and THS4215 with an
Wideband, Noninverting Operation effective output load of 305 for the circuit shown in
Wideband, Inverting Gain Operation Figure 75.
Single-Supply Operation Voltage-feedback amplifiers, unlike current-feedback
Saving Power with Power-Down Functionality and designs, can use a wide range of resistors values to
Setting Threshold Levels with the Reference Pin set their gain with minimal impact on their stability
Power Supply Decoupling Techniques and and frequency response. Larger-valued resistors
Recommendations decrease the loading effect of the feedback network
Using the THS4211 as a DAC Output Buffer on the output of the amplifier, but this enhancement
comes at the expense of additional noise and
Driving an ADC with the THS4211 potentially lower bandwidth. Feedback-resistor values
Active Filtering with the THS4211 between 392 and 1 kare recommended for most
Building a Low-Noise Receiver with the THS4211 applications.
Linearity: Definitions, Terminology, Circuit
Techniques and Design Tradeoffs
An Abbreviated Analysis of Noise in Amplifiers
Driving Capacitive Loads
Printed-Circuit Board Layout Techniques for
Optimal Performance
Power Dissipation and Thermal Considerations
Performance vs Package Options
Evaluation Fixtures, Spice Models, and
Applications Support
Additional Reference Material
Mechanical Package Drawings
space
space
space Figure 75. Wideband, Noninverting Gain
Configuration
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4211 THS4215
_
+
THS4211
Rg
392
RT
200
100 pF
0.1 µF 6.8 µF
-VS
-5 V
50 Source
+
VI
100 pF 0.1 µF 6.8 µF
+
+VS
5 V
VO
CT
0.1 µF
Rf
392
RM
57.6
499
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
WIDEBAND, INVERTING GAIN OPERATION dealing with low inverting gains, as the resultant
feedback resistor value can present a significant load
Since the THS4211 and THS4215 are to the amplifier output. For an inverting gain of 2,
general-purpose, wideband voltage-feedback setting Rgto 49.9 for input matching eliminates the
amplifiers, several familiar operational-amplifier need for RMbut requires a 100-feedback resistor.
applications circuits are available to the designer. This has the advantage that the noise gain becomes
Figure 76 shows a typical inverting configuration equal to 2 for a 50-source impedance—the same
where the input and output impedances and noise as the noninverting circuit in Figure 75. However, the
gain from Figure 75 are retained in an inverting circuit amplifier output now sees the 100-feedback
configuration. Inverting operation is a common resistor in parallel with the external load. To eliminate
requirement and offers several performance benefits. this excessive loading, it is preferable to increase
The inverting configuration shows improved slew both Rgand Rf, values, as shown in Figure 76, and
rates and distortion due to the pseudo-static voltage then achieve the input matching impedance with a
maintained on the inverting input. third resistor (RM) to ground. The total input
impedance becomes the parallel combination of Rg
and RM.
The next major consideration is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For example,
the RMvalue combines in parallel with the external
50-source impedance (at high frequencies),
yielding an effective source impedance of 50 || 57.6
= 26.8 . This impedance is then added in series
with Rgfor calculating the noise gain. The result is
1.9 for Figure 76, as opposed to the 1.8 if RMis
eliminated. The bandwidth is lower for the inverting
gain-of-2 circuit in Figure 76 (NG=+1.9), than for the
noninverting gain of 2 circuit in Figure 75.
The last major consideration in inverting amplifier
design is setting the bias-current cancellation resistor
on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the
Figure 76. Wideband, Inverting Gain inverting terminal, the output dc error, due to the input
Configuration bias currents, is reduced to (input offset current) × Rf
in Figure 76, the dc source impedance looking out of
In the inverting configuration, some key design the inverting terminal is 392 || (392 + 26.8 ) =
considerations must be noted. One is that the gain 200 . To reduce the additional high-frequency noise
resistor (Rg) becomes part of the signal-channel input introduced by the resistor at the noninverting input,
impedance. If input impedance matching is desired and power-supply feedback, RTis bypassed with a
(beneficial when the signal is coupled through a capacitor to ground.
cable, twisted pair, long PCB trace, or other
transmission line conductor), Rgmay be set equal to
the required termination value and Rfadjusted to give
the desired gain. However, care must be taken when
20 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
_
+
THS4211
49.9
50 Source
VI
+VS
VO
Rf
392
Rg
392
+VS
2
+VS
2
_
+
THS4211
392
50 Source
VI
VS
VO
Rf
392
+VS
2
57.6
Rg
499
RT
499
RT
+VS
2
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
SINGLE-SUPPLY OPERATION Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
The THS4211 is designed to operate from a single mode. The power-down mode is not intended to
5-V to 15-V power supply. When operating from a provide a high- impedance output. In other words, the
single power supply, care must be taken to ensure power-down functionality is not intended to allow use
the input signal and amplifier are biased appropriately as a 3-state bus driver. When in power-down mode,
to maximize output voltage swing. The circuits shown the impedance looking back into the output of the
in Figure 77 demonstrate methods to configure an amplifier is dominated by the feedback and gain
amplifier for single-supply operation. setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
Power-Down Reference Pin Operation
In addition to the power-down pin, the THS4215 also
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. Operation of the
reference pin as it relates to the power-down pin is
described below.
In most split-supply applications, the reference pin will
be connected to ground. In some cases, the user
may want to connect it to the negative or positive
supply rail. In either case, the user needs to be aware
of the voltage level thresholds that apply to the
power-down pin. The table below illustrates the
relationship between the reference voltage and the
Figure 77. DC-Coupled Single Supply Operation power-down thresholds.
POWER-DOWN PIN VOLTAGE
Saving Power with Power-Down REFERENCE
Functionality and Setting Threshold Levels DEVICE DEVICE
VOLTAGE DISABLED ENABLED
with the Reference Pin VS– to 0.5 (VS– + VS+)Ref + 1.0 V Ref + 1.8 V
The THS4215 features a power-down pin (PD) which 0.5 (VS– + VS+) to VS+ Ref 1.5 V Ref 1 V
lowers the quiescent current from 19-mA down to
650-µA, ideal for reducing system power. The recommended mode of operation is to tie the
The power-down pin of the amplifiers defaults to the reference pin to mid-rail, thus setting the threshold
positive supply voltage in the absence of an applied levels to mid-rail +1.0 V and midrail +1.8 V.
voltage, putting the amplifier in the power-on mode of
operation. To conserve power, the amplifier is turned NO. OF CHANNELS PACKAGES
off by driving the power-down pin towards the Single (8-pin) THS4215D, THS4215DGN, and
negative rail. The threshold voltages for power-on THS4215DRB
and power-down are relative to the supply rails, and
are given in the specification tables. Above the
Enable Threshold Voltage, the device is on. Below
the Disable Threshold Voltage, the device is off.
Behavior between these threshold voltages is not
specified.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS4211 THS4215
_
+
THS4211
50
Source 392
_
+
-5 V
196
15 pF
392
196 24.9
15 pF 14-Bit, 62 Msps
ADS5422
(1:4 )
1:2
5 V
24.9
THS4211
VCM
VCM
_
+
THS4211
392
ADS807
12-Bit,
53 Msps
Rf
+5 V
392
49.9
VI
Rg
-5 V
50
Source
RISO 0.1 µF
16.5 68 pf
0.1 µF
IN
IN
CM
1.82 k
RT
NOTE: For best performance, high-speed ADCs should be driven
differentially. See the THS4500 family of devices for more
information.
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
Power-Supply Decoupling Techniques and
Recommendations
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably, improved distortion performance). The
following guidelines ensure the highest level of
performance.
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths, with the
exception of the areas underneath the input and
output pins. Figure 78. A Linear, Low-Noise, High-Gain
4. Recommended values for power-supply ADC Preamplifier
decoupling include a bulk decoupling capacitor
(6.8 µF to 22 µF), a mid-range decoupling The second circuit depicts single-ended ADC drive.
capacitor (0.1 µF) and a high-frequency While not recommended for optimum performance
decoupling capacitor (1000 pF) for each supply. using converters with differential inputs, satisfactory
A 100-pF capacitor can be used across the performance can sometimes be achieved with
supplies as well for extremely high-frequency single-ended input drive. An example circuit is shown
return currents, but often is not required. in Figure 79 for reference.
APPLICATION CIRCUITS
Driving an Analog-to-Digital Converter with the
THS4211
The THS4211 can be used to drive high-performance
analog-to-digital converters. Two example circuits are
presented below.
The first circuit (in Figure 78) uses a wideband
transformer to convert a single-ended input signal into
a differential signal. The differential signal is then
amplified and filtered by two THS4211 amplifiers.
This circuit provides low intermodulation distortion,
suppressed even-order distortion, 14 dB of voltage
gain, a 50-input impedance, and a single-pole filter
at 100 MHz. For applications without signal content at
dc, this method of driving ADCs can be very useful. Figure 79. Driving an ADC With a
Where dc information content is required, the Single-Ended Input
THS4500 family of fully differential amplifiers may be
applicable.
22 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
_
+
THS4211 49.9
50 Source 392
3.9 pF
5 V
-5 V
33 pF
VO
392
57.6
VI
392
_
+
THS4211 49.9
100
392
100 +5 V
-5 V
14-Bit,
400 MSps
DAC5675 RF
LO
196
392
392
3.3 V3.3 V
392
_
+
49.9
100
100
14-Bit,
400 MSps
DAC5675
3.3 V3.3 V
CF1 nF
392 49.9
1 nF
1 nF CF
392
392
_
+
THS4211
THS4211
RF(out)
IF+
IF-
100
1 nF
_
+49.9
100
VO+
VI+
_
+
49.9
100
VO-
787 392
392
100
VI-
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
Using the THS4211 as a DAC Output Buffer Active Filtering with the THS4211
Two example circuits are presented here showing the High-frequency active filtering with the THS4211 is
THS4211 buffering the output of a digital-to-analog achievable due to the amplifier's high slew-rate, wide
converter. The first circuit (Figure 80) performs a bandwidth, and voltage feedback architecture.
differential to single-ended conversion with the Several options are available for high-pass, low-pass,
THS4211 configured as a difference amplifier. The bandpass, and bandstop filters of varying orders. A
difference amplifier can double as the termination simple two-pole low pass filter is presented in
mechanism for the DAC outputs as well. Figure 82 as an example, with two poles at 100 MHz.
Figure 82. A Two-Pole Active Filter With
Two Poles Between 90 MHz and 100 MHz
Figure 80. Differential to Single-Ended
Conversion of a High-Speed DAC Output A Low-Noise Receiver with the THS4211
For cases where a differential signaling path is A combination of two THS4211 amplifiers can create
desirable, a pair of THS4211 amplifiers can be used a high-speed, low-distortion, low-noise differential
as output buffers. The circuit in Figure 81 depicts a receiver circuit as depicted in Figure 83. With both
differential drive into a mixer's IF inputs, coupled with amplifiers operating in the noninverting mode of
additional signal gain and filtering. operation, the circuit presents a high load impedance
to the source. The designer has the option of
controlling the impedance through termination
resistors if a matched termination impedance is
desired.
Figure 81. Differential Mixer Drive Circuit
Using the DAC5675 and the THS4211 Figure 83. A High Input Impedance, Low-Noise,
Differential Receiver
space
space
space
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): THS4211 THS4215
_
+
100
VO
VI+
_
+
Rg1
Rf1
100
VI-
_
+
Rf2
49.9
Rf1
Rg2
Rg2
Rf2
49.9
THS4211
THS4211
THS4211
VO+1
2ǒ1)2Rf1
Rg1 ǓǒVi)–Vi–ǓǒRf2
Rg2Ǔ
IMD3 = PS - PO
PS
PO
PO
fc = fc - f1
fc = f2 - fc
PS
fc - 3f f1 fcf2 fc + 3f
Power
f - Frequency - MHz
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
A modification on this circuit to include a difference LINEARITY: DEFINITIONS, TERMINOLOGY,
amplifier turns this circuit into a high-speed CIRCUIT TECHNIQUES, AND DESIGN
instrumentation amplifier, as shown in Figure 84.TRADEOFFS
The THS4211 features execllent distortion
performance for monolithic operational amplifiers.
This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of operational
amplifiers to desired linearity specifications in RF
receiver chains.
Amplifiers are generally thought of as linear devices.
The output of an amplifier is a linearly-scaled version
of the input signal applied to it. However, amplifier
transfer functions are nonlinear. Minimizing amplifier
nonlinearity is a primary design goal in many
applications.
Intercept points are specifications long used as key
design criteria in the RF communications world as a
metric for the intermodulation distortion performance
Figure 84. A High-Speed Instrumentation of a device in the signal chain (e.g., amplifiers,
Amplifier mixers, etc.). Use of the intercept point, rather than
strictly the intermodulation distortion, allows simpler
system-level calculations. Intercept points, like noise
(1) figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver chain's intermodulation distortion
THEORY AND GUIDELINES performance. The relationship between
intermodulation distortion and intercept point is
Distortion Performance depicted in Figure 85 and Figure 86.
The THS4211 provides excellent distortion
performance into a 150-load. Relative to alternative
solutions, it provides exceptional performance into
lighter loads, as well as exceptional performance on a
single 5-V supply. Generally, until the fundamental
signal reaches very high frequency or power levels,
the 2nd harmonic dominates the total harmonic
distortion with a negligible 3rd harmonic component.
Focusing then on the 2nd harmonic, increasing the
load impedance directly improves distortion. The total
load includes the feedback network; in the
noninverting configuration (Figure 75) this is the sum
of Rfand Rg, while in the inverting configuration
(Figure 76), only Rfneeds to be included in parallel
with the actual load.
space
space
Figure 85.
24 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
OIP3+PO)ǒŤIMD3Ť
2Ǔwhere
PO+10 logǒV2
P
2RL 0.001Ǔ
IMD3
OIP3
IIP3
3X
PIN
(dBm)
1X
POUT
(dBm)
PO
PS
_
+
Rf
4kT = 1.6E-20J
at 290K
THS4211/THS4215
IBN EO
ERF
RS
ERS
IBI
Rg
ENI
4kTRS
4kT
Rg4kTRf
EO+ǒE2
NI )ǒIBNRSǓ2)4kTRSǓNG2)ǒIBIRfǓ2)4kTRfNG
Ǹ
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
(2)
(3)
NOTE: POis the output power of a single tone, RLis
the load resistance, and VPis the peak voltage for a
single tone.
NOISE ANALYSIS
High slew rate, unity-gain stable, voltage-feedback
operational amplifiers usually achieve their slew rate
at the expense of a higher input noise voltage. The
7-nV/Hz input voltage noise for the THS4211 and
THS4215 is, however, much lower than comparable
amplifiers. The input-referred voltage noise and the
two input-referred current noise terms (4 pA/Hz)
combine to give low output noise under a wide variety
Figure 86. of operating conditions. Figure 87 shows the amplifier
noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
Due to the intercept point's ease of use in system be noise voltage or current density terms in either
level calculations for receiver chains, it has become nV/Hz or pA/Hz.
the specification of choice for guiding
distortion-related design decisions. Traditionally,
these systems use primarily class-A, single-ended RF
amplifiers as gain blocks. These RF amplifiers are
typically designed to operate in a 50-environment.
Giving intercept points in dBm implies an associated
impedance (50 ).
However, with an operational amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of an operational amplifier. The
THS4211 yields optimum distortion performance
when loaded with 150 to 1 k, very similar to the Figure 87. Noise Analysis Model
input impedance of an analog-to-digital converter
over its input frequency band. The total output shot noise voltage can be computed
As a result, terminating the input of the ADC to 50 as the square of all square output noise voltage
can actually be detrimental to system performance. contributors. Equation 4 shows the general form for
The discontinuity between open-loop, class-A the output noise voltage using the terms shown in
amplifiers and closed-loop, class-AB amplifiers Equation 4:
becomes apparent when comparing the intercept
points of the two types of devices. Equation 2 and
Equation 3 define an intercept point, relative to the (4)
intermodulation distortion.
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): THS4211 THS4215
EO+E2
NI )ǒIBNRSǓ2)4kTRS)ǒIBIRf
NGǓ2
)4kTRf
NG
Ǹ
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
100 k 1 M 10 M 100 M 1 G
Capacitive Load - Hz
Normalized Gain - dB
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
R(ISO) = 15
CL = 50 pF
VS =±5 V
R(ISO) = 10
CL = 100 pF
R(ISO) = 25
CL = 10 pF
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
Dividing this expression by the noise gain [NG= (1 +
Rf/Rg) ] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased Figure 88. Isolation Resistor Diagram
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is BOARD LAYOUT
considered, this capacitive load introduces an
additional pole in the signal path that can decrease Achieving optimum performance with a high
the phase margin. When the primary considerations frequency amplifier like the THS4211 requires careful
are frequency response flatness, pulse response attention to board layout parasitics and external
fidelity, or distortion, the simplest and most effective component types.
solution is to isolate the capacitive load from the Recommendations that optimize performance include
feedback loop by inserting a series isolation resistor the following:
between the amplifier output and the capacitive load. 1. Minimize parasitic capacitance to any ac
This does not eliminate the pole from the loop ground for all of the signal I/O pins. Parasitic
response, but rather shifts it and adds a zero at a capacitance on the output and inverting input pins
higher frequency. The additional zero acts to cancel can cause instability: on the noninverting input, it
the phase lag from the capacitive load pole, thus can react with the source impedance to cause
increasing the phase margin and improving stability. unintentional band limiting. To reduce unwanted
The Typical Characteristics show the recommended capacitance, a window around the signal I/O pins
isolation resistor vs capacitive load and the resulting should be opened in all of the ground and power
frequency response at the load. Parasitic capacitive planes around those pins. Otherwise, ground and
loads greater than 2 pF can begin to degrade the power planes should be unbroken elsewhere on
performance of the THS4211. Long PCB traces, the board.
unmatched cables, and connections to multiple 2. Minimize the distance (< 0.25”) from the
devices can easily cause this value to be exceeded. power supply pins to high frequency 0.1-µF
Always consider this effect carefully, and add the decoupling capacitors. At the device pins, the
recommended series resistor as close as possible to ground and power plane layout should not be in
the THS4211 output pin (see Board Layout close proximity to the signal I/O pins. Avoid
Guidelines). narrow power and ground traces to minimize
The criterion for setting this R(ISO) resistor is a inductance between the pins and the decoupling
maximum bandwidth, flat frequency response at the capacitors. The power supply connections should
load. For a gain of +2, the frequency response at the always be decoupled with these capacitors.
output pin is already slightly peaked without the Larger (2.2-µF to 6.8-µF) decoupling capacitors,
capacitive load, requiring relatively high values of effective at lower frequency, should also be used
R(ISO) to flatten the response at the load. Increasing on the main supply pins. These may be placed
the noise gain also reduces the peaking. somewhat farther from the device and may be
shared among several devices in the same area
of the PCB.
space
space
26 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
3. Careful selection and placement of external layout techniques). A 50-environment is
components preserves the high frequency normally not necessary onboard, and in fact a
performance of the THS4211. Resistors should higher impedance environment improves
be a very low reactance type. Surface-mount distortion as shown in the distortion versus load
resistors work best and allow a tighter overall plots. With a characteristic board trace
layout. Metal-film and carbon composition, impedance defined on the basis of board material
axially-leaded resistors can also provide good and trace dimensions, a matching series resistor
high frequency performance. Again, keep their into the trace from the output of the THS4211 is
leads and PCB trace length as short as possible. used as well as a terminating shunt resistor at the
Never use wire-wound type resistors in a input of the destination device. Remember also
high-frequency application. Since the output pin that the terminating impedance is the parallel
and inverting input pin are the most sensitive to combination of the shunt resistor and the input
parasitic capacitance, always position the impedance of the destination device: this total
feedback and series output resistor, if any, as effective impedance should be set to match the
close as possible to the output pin. Other network trace impedance. If the 6-dB attenuation of a
components, such as noninverting doubly-terminated transmission line is
input-termination resistors, should also be placed unacceptable, a long trace can be
close to the package. Where double-side series-terminated at the source end only. Treat
component mounting is allowed, place the the trace as a capacitive load in this case and set
feedback resistor directly under the package on the series resistor value as shown in the plot of
the other side of the board between the output R(ISO) vs capacitive load (See Figure 88). This
and inverting input pins. Even with a low parasitic setting does not preserve signal integrity or a
capacitance shunting the external resistors, doubly-terminated line. If the input impedance of
excessively high resistor values can create the destination device is low, there is some signal
significant time constants that can degrade attenuation due to the voltage divider formed by
performance. Good axial metal-film or the series output into the terminating impedance.
surface-mount resistors have approximately 0.2 5. Socketing a high speed part like the THS4211
pF in shunt with the resistor. For resistor values > is not recommended. The additional lead length
2.0 k, this parasitic capacitance can add a pole and pin-to-pin capacitance introduced by the
and/or a zero below 400 MHz that can effect socket can create a troublesome parasitic
circuit operation. Keep resistor values as low as network which can make it almost impossible to
possible, consistent with load driving achieve a smooth, stable frequency response.
considerations. A good starting point for design is Best results are obtained by soldering the
to set the Rfto 249 for low-gain, noninverting THS4211 onto the board.
applications. This setting automatically keeps the
resistor noise terms low and minimizes the effect PowerPAD™ DESIGN CONSIDERATIONS
of their parasitic capacitance. The THS4211 and THS4215 are available in a
4. Connections to other wideband devices on thermally-enhanced PowerPAD family of packages.
the board may be made with short direct These packages are constructed using a downset
traces or through onboard transmission lines. leadframe upon which the die is mounted [see
For short connections, consider the trace and the Figure 89(a) and Figure 89(b)]. This arrangement
input to the next device as a lumped capacitive results in the lead frame being exposed as a thermal
load. Relatively wide traces (50 mils to 100 mils) pad on the underside of the package [see
should be used, preferably with ground and Figure 89(c)]. Because this thermal pad has direct
power planes opened up around them. Estimate thermal contact with the die, excellent thermal
the total capacitive load and set RISO from the performance can be achieved by providing a good
plot of recommended RISO vs capacitive load thermal path away from the thermal pad.
(See Figure 88). Low parasitic capacitive loads (<
4 pF) may not need an R(ISO), since the THS4211 The PowerPAD package allows both assembly and
is nominally compensated to operate with a 2-pF thermal management in one manufacturing operation.
parasitic load. Higher parasitic capacitive loads During the surface-mount solder operation (when the
without an R(ISO) are allowed as the signal gain leads are being soldered), the thermal pad can also
increases (increasing the unloaded phase be soldered to a copper area underneath the
margin). If a long trace is required, and the 6-dB package. Through the use of thermal paths within this
signal loss intrinsic to a doubly-terminated copper area, heat can be conducted away from the
transmission line is acceptable, implement a package into either a ground plane or other heat
matched impedance transmission line using dissipating device.
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): THS4211 THS4215
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
PD+Tmax *TA
qJA
where
PD = Maximum power dissipation of THS4211 (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to the case
θCA = Thermal coefficient from the case to ambient air
(°C/W).
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ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Single or Dual
68 Mils x 70 Mils
(Via Diameter = 13 Mils)
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
The PowerPAD package represents a breakthrough transfer. Therefore, the holes under the THS4211
in combining the small area and ease of assembly of and THS4215 PowerPAD package should make
surface mount with the heretofore awkward their connection to the internal ground plane, with
mechanical methods of heatsinking. a complete connection around the entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
Figure 89. Views of Thermally area and all of the IC terminals.
Enhanced Package 8. With these preparatory steps in place, the IC is
simply placed in position and run through the
Although there are many ways to properly heatsink solder reflow operation as any standard
the PowerPAD package, the following steps illustrate surface-mount component. This results in a part
the recommended approach. that is properly installed.
For a given θJA, the maximum power dissipation is
PowerPAD PCB LAYOUT CONSIDERATIONS shown in Figure 91 and is calculated by Equation 6:
1. Prepare the PCB with a top side etch pattern as
shown in Figure 90. There should be etching for
the leads as well as etch for the thermal pad.
(6)
The next consideration is the package constraints.
Figure 90. PowerPAD PCB Etch and The two sources of heat within an amplifier are
Via Pattern quiescent power and output power. The designer
should never forget about the quiescent heat
2. Place five holes in the area of the thermal pad. generated within the device, especially multi-amplifier
These holes should be 13 mils in diameter. Keep devices. Because these devices have linear output
them small so that solder wicking through the stages (Class AB), most of the heat dissipation is at
holes is not a problem during reflow. low output voltages with high output currents.
3. Additional vias may be placed anywhere along The other key factor when dealing with power
the thermal plane outside of the thermal pad dissipation is how the devices are mounted on the
area. They help dissipate the heat generated by PCB. The PowerPAD devices are extremely useful
the THS4211 and THS4215 IC. These additional for heat dissipation. But, the device should always be
vias may be larger than the 13-mil diameter vias soldered to a copper plane to fully use the heat
directly under the thermal pad. They can be dissipation properties of the PowerPAD. The SOIC
larger because they are not in the thermal pad package, on the other hand, is highly dependent on
area to be soldered, so wicking is not a problem. how it is mounted on the PCB. As more trace and
4. Connect all holes to the internal ground plane. copper area is placed around the device, θJA
5. When connecting these holes to the ground decreases and the heat dissipation capability
plane, do not use the typical web or spoke via increases. For a single package, the sum of the RMS
connection methodology. Web connections have output currents and voltages should be used to
a high thermal resistance connection that is choose the proper package.
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
28 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
PDmax +Tmax–TA
qJA
where
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
-4
-2
10
12
10 M 100 M 1 G
f - Frequency - Hz
Normalized Gain - dB
0
8
6
4
2
SOIC, Rf = 0
PIN = -7 dB
VS =±5 V Leadless MSOP, &
MSOP Rf = 0
SOIC, Rf = 100
_
+
Rf
49.9
499
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
THERMAL ANALYSIS When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
The THS4211 device does not incorporate automatic important to consider not only quiescent power
thermal shutoff protection, so the designer must take dissipation, but also dynamic power dissipation. Often
care to ensure that the design does not violate the maximum power dissipation is difficult to quantify
absolute maximum junction temperature of the because the signal pattern is inconsistent, but an
device. Failure may result if the absolute maximum estimate of the RMS power dissipation can provide
junction temperature of 150°C is exceeded. visibility into a possible problem.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power DESIGN TOOLS
dissipation for a given package can be calculated
using Equation 7:Performance vs Package Options
The THS4211 and THS4215 are offered in a different
package options. However, performance may be
limited due to package parasitics and lead inductance
in some packages. In order to achieve maximum
performance of the THS4211 and THS4215, Texas
Instruments recommends using the leadless MSOP
(DRB) or MSOP (DGN) packages, in addition to
proper high-speed PCB layout. Figure 92 shows the
unity-gain frequency response of the THS4211 using
the leadless MSOP, MSOP, and SOIC package for
comparison. Using the THS4211 and THS4215 in a
(7) unity-gain with the SOIC package may result in the
For systems where heat dissipation is more critical, device becoming unstable. In higher gain
the THS4211 is offered in an 8-pin MSOP with configurations, this effect is mitigated by the reduced
PowerPAD. The thermal coefficient for the MSOP bandwidth. As such, the SOIC is suitable for
PowerPAD package is substantially improved over application with gains equal to or higher than +2 V/V
the traditional SOIC. Maximum power dissipation or (–1 V/V).
levels are depicted in the graph for the two packages.
The data for the DGN package assumes a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application notes in the Additional Reference Material
section at the end of the data sheet.
Figure 92. Effects of Unity-Gain Frequency
Response for Differential Packages
Figure 91. Maximum Power Dissipation vs
Ambient Temperature
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): THS4211 THS4215
-4
-3
-2
-1
0
1
2
3
4
5
100 k 1 M 10 M 100 M 1 G 10 G
f - Frequency - Hz
Small Signal Gain - dB
_
+
49.9
499
PIN = -7 dBm
VS = ±5 V
L(nH) +Kȏƪln 2ȏ
W)T)0.223W)T
ȏ)0.5ƫ
where
W = Width of trace in inches.
= Length of the trace in inches.
T = Thickness of the trace in inches.
K = 5.08 for dimensions in inches, and K = 2 for dimensions
in cm.
ȏ
-5
-3
-1
1
3
5
7
9
11
13
15
17
10 M 100 M 1 G
f - Frequency - Hz
Small Signal Gain - dB
10 G
_
+
Rf
49.9
499
PIN = -7 dBm
VS = ±5 V
Rf = 200
Rf = 100
Rf = 0
Rf = 50
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
Evaluation Fixtures, SPICE Models, and
Applications Support
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, evaluation boards have
been developed for the THS4211 operational
amplifier. Three evaluation boards are available: one
THS4211 and one THS4215, both configurable for
different gains, and a third for untiy gain (THS4211
only). These boards are easy to use, allowing for
straightforward evaluation of the device. These
evaluation boards can be ordered through the Texas
Instruments web site at www.ti.com, or through your
local Texas Instruments sales representative.
Schematics for the evaluation boards are shown Figure 94. Frequency Response Using the
below. EDGE #6443547 G = +1 EVM
The THS4211/THS4215 EVM board shown in
Figure 95 through Figure 99 accommodates different The frequency-response peaking is due to the lead
gain configurations. Its default component values are inductance in the feedback path. Each pad and trace
set to give a gain of 2. The EVM can be configured on a PCB has an inductance associated with it, which
for unity-gain; however, it is strongly not in conjunction with the inductance associated with the
recommended. Evaluating the THS4211/THS4215 in package may cause frequency-response peaking,
unity-gain using this EVM may cause the device to causing the device to become unstable.
become unstable. The stability of the device can be
controlled by adding a large resistor in the feedback In order to achieve the maximum performance of the
path, but performance is sacrificed. Figure 93 shows device, PCB layout is very critical. Texas Instruments
the small-signal frequency response of the THS4211 has developed an EVM for the evaluation of the
with different feedback resistors in the feedback path. THS4211 configured for a gain of 1. The EVM is
Figure 94 is the small frequency response of the shown in Figure 100 through Figure 104. This EVM is
THS4211 using the unity-gain EVM. designed to minimize peaking in the unity-gain
configuration.
Minimizing the inductance in the feedback path is
critical for reducing the peaking of the frequency
response in unity-gain. The recommended maximum
inductance allowed in the feedback path is 4 nH. This
inductance can be calculated using Equation 8:
(8)
space
Figure 93. Frequency Response vs Feedback
Resistor Using the EDGE #6439527 EVM
30 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
R1
R5
J2
Vin+
R6
Vs+
U1
2
36
7
4 1
8
J8
Power Down Ref
Vs+
R8
C8
Vs-
R4
R7
C7
J9
Power Down
R2
J4
Vout
Vs-
R9
R3
J1
Vin-
TP1
+C1
VS-
J7
C6C5 C2
VS+
J5
+
FB2
C4C3
FB1
VS- GND
VS+
J6
_
+
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
Figure 96. THS4211/THS4215 EVM Board Layout
(Top Layer)
Figure 95. THS4211/THS4215 EVM
Circuit Configuration
Figure 97. THS4211/THS4215 EVM Board Layout
(Second Layer, Ground)
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): THS4211 THS4215
J2
Vin+
R6
U1
2
36
7
4 1
8
Vs+
R4
R7
J4
Vout
Vs-
TP1
+C1
VS-
J7
C6C5 C2
VS+
J5
+
FB2
C4C3
FB1
VS- GND
VS+
J6
_
+
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
Figure 100. THS4211 Unity-Gain EVM
Circuit Configuration
Figure 98. THS4211/THS4215 EVM Board Layout
(Third Layer, Power)
Figure 101. THS4211 Unity-Gain EVM Board
Layout (Top Layer)
Figure 99. THS4211/THS4215 EVM Board Layout
(Bottom Layer)
32 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
www.ti.com
................................................................................................................................... SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009
Figure 102. THS4211 Unity-Gain EVM Board Figure 103. THS4211 Unity-Gain EVM Board
Layout (Second Layer, Ground) Layout (Third Layer, Power)
Figure 104. THS4211 Unity-Gain EVM
Board Layout (Bottom Layer)
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): THS4211 THS4215
THS4211
THS4215
SLOS400E SEPTEMBER 2002REVISED SEPTEMBER 2009 ...................................................................................................................................
www.ti.com
Computer simulation of circuit performance using The Product Information Center (PIC) is available for
SPICE is often useful when analyzing the design assistance and detailed product information.
performance of analog circuits and systems. This is These models do a good job of predicting
particularly true for video and RF amplifier circuits, small-signal ac and transient performance under a
where parasitic capacitance and inductance can have wide variety of operating conditions. They are not
a major effect on circuit performance. A SPICE model intended to model the distortion characteristics of the
for the THS4500 family of devices is available amplifier, nor do they attempt to distinguish between
through the Texas Instruments web site (www.ti.com). the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
ADDITIONAL REFERENCE MATERIAL
PowerPAD Made Easy, application brief
(SLMA004)
PowerPAD Thermally-Enhanced Package,
technical brief (SLMA002)
space REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November, 2004) to Revision E .......................................................................................... Page
Updated document format to current standards ................................................................................................................... 1
Changed high output drive (IO) bullet in Features list from 200 mA to 170 mA ................................................................... 1
Changed Absolute Maximum Ratings table; increased output current specification, deleted lead temperature
specification .......................................................................................................................................................................... 2
Corrected typo in Turn-off-time delay parametric units; changed to µs ............................................................................... 7
34 Submit Documentation Feedback Copyright © 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4211 THS4215
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4211D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4211DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4211DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4211DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4211DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4211DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4215DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4215DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4215DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4215DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4215DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS4215DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4211DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4211DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4211DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
THS4211DRBT SON DRB 8 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
THS4215DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4215DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
THS4215DRBT SON DRB 8 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4211DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4211DR SOIC D 8 2500 367.0 367.0 35.0
THS4211DRBR SON DRB 8 3000 338.1 338.1 20.6
THS4211DRBT SON DRB 8 250 338.1 338.1 20.6
THS4215DR SOIC D 8 2500 367.0 367.0 35.0
THS4215DRBR SON DRB 8 3000 338.1 338.1 20.6
THS4215DRBT SON DRB 8 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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