22uF
1.8V / 2A
10uF
2.2 µH
(3 .. 17)V
3.3nF
TPS62141
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
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SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
3-V to 17-V 2-A Step-Down Converter in 3x3 QFN Package
Check for Samples: TPS62140,TPS62140A,TPS62141,TPS62142,TPS62143
1FEATURES DESCRIPTION
The TPS6214X family is an easy-to-use synchronous
• DCS-ControlTM Topology step-down dc-dc converter optimized for applications
• Input Voltage Range: 3 V to 17 V with high power density. A high switching frequency
• Up to 2-A Output Current of typically 2.5MHz allows the use of small inductors
and provides fast transient response by use of the
• Adjustable Output Voltage from 0.9 V to 6 V DCS-Control™ topology.
• Pin-Selectable Output Voltage (Nominal, +5%) With its wide operating input voltage range of 3V to
• Programmable Soft Start and Tracking 17V, the devices are ideally suited for systems
• Seamless Power-Save Mode Transition powered from either a Li-Ion or other batteries, as
• Quiescent Current of 17 µA (typ.) well as from 12-V intermediate power rails. It
supports up to 2A of continuous output current at
• Selectable Operating Frequency output voltages between 0.9V and 6V (with 100%
• Power-Good Output duty-cycle mode).
• 100% Duty-Cycle Mode The output voltage start-up ramp is controlled by the
• Short-Circuit Protection soft-start pin, which allows operation as either a
• Over Temperature Protection standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
• Available in a 3-mm × 3-mm, QFN-16 Package Enable (EN) and open-drain Power Good (PG) pins.
APPLICATIONS In power-save mode, the devices show quiescent
current of about 17μA from VIN. Power Save Mode,
• Standard 12-V Rail Supplies entered automatically and seamlessly if load is small,
• POL Supply From Single or Multiple Li-Ion maintains high efficiency over the entire load range.
Battery In Shutdown Mode, the device is turned off and
• Solid-State Disk Drives shutdown current consumption is less than 2μA.
• Embedded Systems The device, available in adjustable and fixed output
voltage versions, is packaged in a 16-pin QFN
• LDO Replacement package measuring 3 × 3 mm (RGT).
• Mobile PCs, Tablet, Modems, Cameras
spacing
Figure 1. Typical Application and Efficiency
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TAOUTPUT VOLTAGE PART NUMBER(2) PACKAGE ORDERING PACKAGE MARKING
adjustable TPS62140 TPS62140RGT QTZ
adjustable TPS62140A(3) TPS62140ARGT PA7I
–40°C to 85°C 1.8 V TPS62141 16-Pin QFN TPS62141RGT QWA
3.3 V TPS62142 TPS62142RGT QWB
5 V TPS62143 TPS62143RGT QWC
(1) For detailed ordering information, see the PACKAGE OPTION ADDENDUM section at the end of this data sheet.
(2) Contact the factory to check availability of other fixed output voltage versions.
(3) While TPS6214X has PG=High Z, TPS62140A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
AVIN, PVIN –0.3 20 V
EN, SS/TR –0.3 VIN+0.3
Pin voltage range(2) SW –0.3 VIN+0.3 V
DEF, FSW, FB, PG, VOS –0.3 7 V
Power-good sink current PG 10 mA
Operating junction temperature range, TJ–40 125
Temperature range °C
Storage temperature range, Tstg –65 150
HBM Human-body model 2 kV
ESD rating(3) CDM Charged-device model 0.5 kV
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION TPS6214X
THERMAL METRIC(1) UNITS
RGT 16 PINS
θJA Junction-to-ambient thermal resistance 29.1
θJC(TOP) Junction-to-case(top) thermal resistance 15
θJB Junction-to-board thermal resistance 11 °C/W
ψJT Junction-to-top characterization parameter 0.5
ψJB Junction-to-board characterization parameter 10
θJC(BOTTOM) Junction-to-case(bottom) thermal resistance 3.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
Supply voltage, VIN (at AVIN and P VIN) 3 17 V
Operating free-air temperature, TA–40 85 °C
Operating junction temperature, TJ–40 125 °C
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SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=AVIN=PVIN=12V and TA=25°C (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range(1) 3 17 V
EN = High, IOUT = 0 mA, device not
IQOperating quiescent current 17 25 µA
switching
ISD Shutdown current(2) EN = Low 1.5 4 µA
VUVLO Falling input voltage 2.6 2.7 2.8 V
Undervoltage lockout threshold Hysteresis 200 mV
TSD Thermal shutdown temperature 160 °C
Thermal shutdown hysteresis 20
CONTROL (EN, DEF, FSW, SS/TR, PG)
High-level input threshold voltage (EN, DEF,
VH0.9 V
FSW)
VLLow-level input threshold voltage (EN, DEF, 0.3 V
FSW)
ILKG Input leakage current (EN, DEF, FSW) EN, DEF, FSW = VIN or GND 0.01 1 µA
Rising (%VOUT) 92 95 98
VTH_PG Power-good threshold voltage %
Falling (%VOUT) 87 90 93
VOL_PG Power-good output low IPG= –2 mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG = 1.8 V 1 400 nA
ISS/TR SS/TR pin source current 2.3 2.5 2.7 µA
POWER SWITCH
VIN ≥6 V 90 170
High-side MOSFET ON-resistance mΩ
VIN = 3 V 120
rDS(on) VIN ≥6 V 40 70
Low-side MOSFET ON-resistance mΩ
VIN = 3 V 50
ILIMF High-side MOSFET forward current limit(3) VIN = 12 V, TA= 25°C 2.45 3 3.5 A
OUTPUT
VREF Internal reference voltage(4) 0.8 V
ILKG_FB Input leakage current (FB) TPS62140, VFB = 0.8 V 1 100 nA
Output voltage range (TPS62140) VIN ≥VOUT 0.9 6.0 V
DEF (output voltage programming) DEF = 0 (GND) VOUT
DEF = 1 (VOUT) VOUT + 5%
PWM mode operation, VIN ≥VOUT + 1 V –1.8 1.8
PWM mode operation, VIN ≥VOUT +1 V,
Initial output voltage accuracy(5) -1.5 1.6 %
VOUT TA= –10°C to 85°C
Power-save mode operation, COUT=22µF –2.3 2.8
Load regulation(6) VIN = 12 V, VOUT = 3.3 V, PWM mode 0.05 %/A
operation
Line regulation(6) 3 V ≤VIN ≤17 V, VOUT = 3.3 V, IOUT = 1 A, 0.02 %/V
PWM mode operation
(1) The device is still functional down to undervoltage lockout (see parameter VUVLO).
(2) Current into AVIN + PVIN pins
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short
Circuit Protection section).
(4) This is the voltage regulated at the FB pin.
(5) This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed-voltage versions the
(internal) resistive divider is included.
(6) Line and load regulation depend on external component selection and layout (see Figure 17 and Figure 18).
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3
Exposed
Thermal Pad
9
10
11
12
8
765
4
2
1
16 15 14 13
PVIN
PVIN
AVIN
SS/TR
SW
SW
SW
PG
PGND
PGND
VOS
EN
FB
AGND
FSW
DEF
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
DEVICE INFORMATION
RGT PACKAGE
(TOP VIEW)
Terminal Functions
PIN(1) I/O DESCRIPTION
NAME NO.
SW 1, 2 ,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG 4 O Output power-good (High = VOUT ready, Low = VOUT below nominal regulation); open-drain (requires
pullup resistor; goes high-impedance when device is switched off)
FB 5 I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. Its recommended to
connect FB to AGND on fixed output-voltage versions for improved thermal performance.
AGND 6 – Analog ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
FSW 7 I Switching frequency select (Low ≈2.5 MHz, High ≈1.25 MHz(2) for typical operation)(3)
DEF 8 I Output voltage scaling (Low = nominal, High = nominal + 5%)(3)
Soft-start / tracking pin. An external capacitor connected to this pin sets the internal voltage-reference rise
SS/TR 9 I time. It can be used for tracking and sequencing.
AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN.
PVIN 11, 12 I Supply voltage for power stage. Connect to same source as AVIN.
EN 13 I Enable input (High = enabled, Low = disabled)(3)
VOS 14 I Output-voltage sense pin and connection for the control loop circuitry.
PGND 15, 16 – Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Exposed – Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane(4). Must be soldered
thermal pad to achieve appropriate power dissipation and mechanical reliability.
(1) For more information about connecting pins, see the DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
(2) Connect FSW to VOUT or PG in this case.
(3) An internal pulldown resistor keeps the logic level low, if pin is floating.
(4) See Figure 41.
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control logic
Soft
start
Thermal
Shtdwn UVLO PG control
power
control
error
amplifier
gate
drive
HS lim
LS lim
PVINPVINAVINPG
PGNDPGND
AGND
comp
comp
+
_
timer tON
DCS - ControlTM
direct control
&
compensation
comparator
ramp
SW
SW
SW
EN*
SS/TR
DEF*
FSW*
VOS
FB
*This pin is connected to a pull down resistor internally
(see Detailed Description section).
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
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SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
FUNCTIONAL BLOCK DIAGRAM
Figure 2. TPS62140 (Adjustable Output Voltage)
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control logic
Soft
start
Thermal
Shtdwn UVLO PG control
power
control
error
amplifier
gate
drive
HS lim
LS lim
PVINPVINAVINPG
PGNDPGND
AGND
comp
comp
+
_
timer tON
DCS - ControlTM
direct control
&
compensation
comparator
ramp
SW
SW
SW
EN*
SS/TR
DEF*
FSW*
VOS
FB*
*This pin is connected to a pull down resistor internally
(see Detailed Description section).
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
Figure 3. TPS62141/2/3 (Fixed Output Voltage)
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COUT
VOUT
CIN
L1
VIN
FB
PG
TPS62140
R1
R2
CSS
R3
VIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
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SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
PARAMETER MEASUREMENT INFORMATION
List of Components
REFERENCE DESCRIPTION MANUFACTURER
IC 17-V, 2-A step-down converter, QFN TPS62140RGT, Texas Instruments
L1 2.2-µH, 3.1-A, 0.165 in × 0.165 in XFL4020-222MEB, Coilcraft
Cin 10-µF, 25-V, ceramic Standard
Cout 22-µF, 6.3-V, ceramic Standard
Cs 3300-pF, 25-V, ceramic
R1 Dependent on Vout
R2 Dependent on Vout
R3 100-kΩ, chip, 0603, 1/16W, 1% Standard
Figure 4. Measurement Setup
TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION FIGURE
Efficiency vs Output Current, vs Input Voltage 5–16
vs Output current (Load regulation), vs Input Voltage
Output voltage 17, 18
(Line regulation)
vs Input Voltage 19
Switching Frequency vs Output Current 20
Quiescent Current vs Input Voltage 21
Shutdown Current vs Input Voltage 22
Power FET RDS(on) vs Input Voltage (High-Side, Low-Side) 23, 24
Output Voltage Ripple vs output Current 25
Maximum Output Current vs Input Voltage 26
Power Supply Rejection Ratio (PSSR) vs Frequency 27, 28
PWM-PSM-PWM Mode Transition 29
Load Transient Response 30–32
Waveforms Start-Up 33, 34
Typical PWM Mode Operation 35
Typical Power Save Mode Operation 36
vs Load Current 37
Maximum Ambient Temperature vs Power Dissipation 38
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0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=5V
VIN=12V VIN=17V
Output Current (A)
Efficiency (%)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mAIOUT=10mAIOUT=100mAIOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=12V VIN=17V
Output Current (A)
Efficiency (%)
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
G001
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
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EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 5. Efficiency With 1.25 MHz, Vout = 5 V Figure 6. Efficiency With 1.25 MHz, Vout = 5 V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 7. Efficiency With 2.5 MHz, Vout = 5 V Figure 8. Efficiency With 2.5 MHz, Vout = 5 V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 9. Efficiency With 1.25 MHz, Vout = 3.3 V Figure 10. Efficiency With 1.25 MHz, Vout = 3.3 V
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0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=5V
VIN=12V VIN=17V
Output Current (A)
Efficiency (%)
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=5V
VIN=12V VIN=17V
Output Current (A)
Efficiency (%)
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1 10
VIN=5V
VIN=12V VIN=17V
Output Current (A)
Efficiency (%)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=1A
Input Voltage (V)
Efficiency (%)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
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SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 11. Efficiency With 2.5 MHz, Vout = 3.3 V Figure 12. Efficiency With 2.5 MHz, Vout = 3.3 V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 13. Efficiency With 1.25 MHz, Vout = 1.8 V Figure 14. Efficiency With 1.25 MHz, Vout = 1.8 V
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 15. Efficiency With 1.25 MHz, Vout = 0.9 V Figure 16. Efficiency With 1.25 MHz, Vout = 0.9 V
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0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C
25°C 85°C
Input Voltage (V)
Input Current (µA)
G001
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C 25°C
85°C
Input Voltage (V)
Input Current (µA)
G001
0
0.5
1
1.5
2
2.5
3
3.5
4
4 6 8 10 12 14 16 18
IOUT=0.5A IOUT=1A
IOUT=2A
Input Voltage (V)
Switching Frequency (MHz)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G000
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.5 1 1.5 2
Output Current (A)
Switching Frequency (MHz)
VIN=12V, VOUT=3.3V
L=2.2uH (XFL4020)
FSW=Low
G000
3.20
3.25
3.30
3.35
3.40
0.0001 0.001 0.01 0.1 1 10
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
3.20
3.25
3.30
3.35
3.40
4 7 10 13 16
IOUT=1mA IOUT=10mA
IOUT=100mAIOUT=1A
Input Voltage (V)
Output Voltage (V)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G001
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
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OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 17. Output Voltage Accuracy (Load Regulation) Figure 18. Output Voltage Accuracy (Line Regulation)
SWITCHING FREQUENCY SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE OUTPUT CURRENT
Figure 19. Switching Frequency Figure 20. Switching Frequency
INPUT CURRENT INPUT CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 21. Quiescent Current Figure 22. Shutdown Current
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0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M
VIN=5V
VIN=12V
VIN=17V
Frequency (Hz)
PSRR (dB)
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
G000
0
10
20
30
40
50
60
70
80
90
100
10 100 1k 10k 100k 1M
VIN=5V
VIN=12V
VIN=17V
Frequency (Hz)
PSRR (dB)
VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
G000
0
0.01
0.02
0.03
0.04
0.05
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Output Voltage Ripple (V)
VOUT=3.3V,
L=2.2uH (XFL4020)
Cout=22uF
G000
0
0.5
1
1.5
2
2.5
3
3.5
4
4 5 6 7 8 9 10 11 12 13 14 15 16 17
−40°C 25°C
85°C
Input Voltage (V)
Output Current (A)
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
G000
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
180.0
200.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C
−10°C
25°C
85°C
125°C
Input Voltage (V)
RDSon High−Side (mΩ)
G001
0.0
20.0
40.0
60.0
80.0
100.0
0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0
−40°C
−10°C
25°C
85°C
125°C
Input Voltage (V)
RDSon Low−Side (mΩ)
G001
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
STATIC DRAIN-SOURCE-RESISTANCE (RDSon) STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 23. High-Side Switch Resistance Figure 24. Low-Side Switch Resistance
OUTPUT VOLTAGE OUTPUT CURRENT
vs vs
OUTPUT CURRENT INPUT VOLTAGE
Figure 25. Output Voltage Ripple Figure 26. Maximum Output Current
POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 27. Power-Supply Rejection Ratio, fSW = 2.5 MHz Figure 28. Power-Supply Rejection Ratio, fSW = 2.5 MHz
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
TIME TIME
Figure 29. PWM-PSM-Transition (VIN=12 V, VOUT = 3.3 V With Figure 30. Load Transient Response (IOUT= 0.5 to 2 to 0.5 A,
50 mV/div) VIN = 12 V, VOUT = 3.3 V)
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
TIME TIME
Figure 31. Line Transient Response of Figure 30, Rising Figure 32. Line Transient Response of Figure 30, Falling
Edge Edge
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TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
TIME TIME
Figure 33. Start-Up Into 100 mA (VIN = 12 V, VOUT = 3.3 V) Figure 34. Start-Up into 2 A (VIN = 12 V, VOUT = 3.3 V)
PWM SIGNALS POWER SAVE MODE SIGNALS
vs vs
TIME TIME
Figure 35. Typical Operation in PWM Mode (IOUT = 1 A) Figure 36. Typical Operation in Power-Save Mode (IOUT = 10
mA)
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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
75
85
95
105
115
125
0 0.5 1 1.5 2 2.5
Output Current (A)
Free−Air Temperature (°C)
TPS62140 EVM
L=2.2uH (XFL4020)
VIN=12V, VOUT=3.3V
G000
55
65
75
85
95
105
115
125
0 2 4 6 8 10 12
Output Power (W)
Free−Air Temperature (°C)
TPS62140 EVM
L=2.2uH (XFL4020)
VIN=12V, VOUT=3.3V
G000
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
AMBIENT TEMPERATURE AMBIENT TEMPERATURE
vs vs
OUTPUT CURRENT OUTPUT POWER
Figure 37. Maximum Ambient Temperature (fSW = 2.5 MHz) Figure 38. Maximum Ambient Temperature (fSW = 2.5 MHz)
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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
ON
OUTIN
peakLPSM t
L
VV
I×
-
=
)(
)(
ns
V
V
t
IN
OUT
ON 400×=
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
DETAILED DESCRIPTION
Device Operation
The TPS6214X synchronous switched-mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power-Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage-mode and current-mode control including an ac loop directly associated with the output
voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady-state operating conditions, and
provides immediate response to dynamic load changes. To get accurate dc load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low-ESR capacitors.
The DCS-Control topology supports pulse-width modulation (PWM) mode for medium and heavy load conditions
and a power-save mode at light loads. During PWM, it operates at its nominal switching frequency in continuous-
conduction mode. This frequency is typically about 2.5 MHz with a controlled frequency variation depending on
the input voltage. If the load current decreases, the converter enters power-save mode to sustain high efficiency
down to very light loads. In power-save mode, the switching frequency decreases linearly with the load current.
Because DCS-Control supports both operation modes within one single building block, the transition from PWM
to power-save mode is seamless without effects on the output voltage.
Fixed output-voltage versions provide the smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 2A.
The TPS6214X family offers both excellent dc voltage and superior load transient regulation, combined with very
low output voltage ripple, minimizing interference with RF circuits.
Pulse-Width Modulation (PWM) Operation
The TPS6214X operates with pulse-width modulation in continuous-conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters
power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current
becomes smaller than half the inductor ripple current.
Power-Save Mode Operation
The TPS6214X enters its built-in power-save mode seamlessly if the load current decreases. This secures a high
efficiency in light-load operation. The device remains in power-save mode as long as the inductor current is
discontinuous.
In power-save mode, the switching frequency decreases linearly with the load current, maintaining high
efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is
seamless in both directions.
TPS6214X includes a fixed-on-time circuit. The on-time, in steady-state operation, can be estimated as:
(1)
For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical
peak inductor current in power-save mode can be approximated by:
(2)
When VIN decreases to typically 15% above VOUT, the TPS6214X does not enter power-save mode, regardless
of the load current. The device maintains output regulation in PWM mode.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
PD
L
LIMFtyppeak t
L
V
II ×+=
)(
( )
L)on(DSOUT(min)OUT(min)IN RRIVV ++=
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty-cycle operation, turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input-to-output voltage differences, e.g., for longest operation time
of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
(3)
where
IOUT is the output current.
RDS(on) is the RDS(on) of the high-side FET.
RLis the dc resistance of the inductor used.
Enable / Shutdown (EN)
When the enable pin (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5 µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. An internal pulldown resistor of about 400 kΩis connected and keeps EN logic Low if
the pin is floating. It is disconnected if the pin is High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
Soft-Start / Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 33 and Figure 34 for typical start-up operation.
The slope can be controlled by an external capacitor connected to the SS/TR pin. Connecting SS/TR directly to
AVIN provides fastest start-up behavior. The TPS6214X can start into a pre-biased output. During monotonic
pre-biased startup, both the power MOSFETs are not allowed to turn on until the device internal ramp sets an
output voltage above the pre-bias voltage. As long as the output is below about 0.5 V, a reduced current limit of
typically 1.6 A is set internally. If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal
shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states
causes a new start-up sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in
both directions, up and down (see APPLICATION INFORMATION).
Current Limit and Short Circuit Protection
The TPS6214X devices are protected against heavy load and short-circuit events. If a short circuit is detected
(VOUT drops below 0.5 V), the current limit is reduced to 1.6 A, typically. If the output voltage rises above 0.5 V,
the device runs in normal operation again. At heavy loads, the current limit determines the maximum output
current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot-through current, the low-
side FET is switched on to sink the inductor current. The high-side FET turns on again only if the current in the
low-side FET has decreased below the low-side current-limit threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:
(4)
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( ) ns
L
VV
II OUTIN
LIMFtyppeak 30
)( ×
-
+=
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
where
ILIMF is the static current limit, specified in the ELECTRICAL CHARACTERISTICS
L is the inductor value
VLis the voltage across the inductor (VIN – VOUT)
tPD is the internal propagation delay
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
(5)
Power Good (PG)
The TPS6214X has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an
open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic-low level. It is high-impedance when the device is turned off due to EN, UVLO, or
thermal shutdown. TPS62140A features PG=Low in this case and can be used to actively discharge Vout (see
Figure 51). VIN must remain present for the PG pin to stay Low.
Pin-Selectable Output Voltage (DEF)
The output voltage of the TPS6214X devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6214X can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.
Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).
Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents incorrect operation of the device by switching off
both the power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational
for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.
Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJexceeds 160°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG
goes high-impedance. When TJdecreases below the hysteresis amount, the converter resumes normal
operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shutdown temperature.
(1) Maximum allowed voltage is 7 V. Therefore it is recommended to connect it to VOUT or PG, not VIN.
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2
(max)
(max)(max)
L
OUTL
I
II
D
+=
÷
÷
ø
ö
ç
ç
è
æ-= 1
21
REF
OUT
V
V
RR
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power-supply design process.
Programming the Output Voltage
While the output voltage of the TPS62140 is adjustable, the TPS62141/2/3 are programmed to fixed output
voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is
recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed
for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to AGND. The voltage at the FB pin
is regulated to 800 mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6 (see Figure 4). It is recommended to choose resistor values which allow a current of at least 2 µA,
meaning the value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for highest
accuracy and most-robust design. For applications requiring lowest current consumption, the use of fixed output-
voltage versions is recommended.
(6)
In case the FB pin is opened, the device clamps the output voltage at the VOS pin internally to about 7.4 V.
External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6214X is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter and Loop Stabilitysection). Table 1 can be used to simplify
the output filter component selection.
Table 1. Recommended LC Output Filter Combinations(1)
4.7 µF 10 µF 22 µF 47 µF 100 µF 200 µF 400 µF
0.47 µH
1 µH √√√√
2.2 µH √ √(2) √√√
3.3 µH √√√√
4.7 µH
(1) The values in the table are nominal values.
(2) This LC combination is the standard value and recommended for most applications.
spacing
TPS6214X can be run with an inductor as low as 1 µH or 2.2 µH. FSW should be set Low in this case. However,
for applications running with the low-frequency setting (FSW = High) or with low input voltages, 3.3 µH is
recommended. More detailed information on further LC combinations can be found in SLVA463.
Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation
current and dc resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static
load conditions.
spacing
(7)
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LPSMload II D=
2
1
)(
÷
÷
÷
÷
÷
ø
ö
ç
ç
ç
ç
ç
è
æ
×
-
×=D
SW
IN
OUT
OUTL fL
V
V
VI
(min)
(max)
(max)
1
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
(8)
where
IL(max) is the maximum inductor current
ΔILis the peak-to-peak inductor ripple current
L(min) is the minimum effective inductor value
fSW is the actual PWM switching frequency
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum required
inductor saturation current. It is recommended to add a margin of about 20%. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6214X and are recommended for use:
Table 2. List of Inductors
Type Inductance [µH] Current [A](1) Dimensions [L x B x H] MANUFACTURER
mm
XFL4020-222ME_ 2.2 µH, ±20% 3.5 4 x 4 x 2.1 Coilcraft
XFL4020-332ME_ 3.3 µH, ±20% 2.9 4 x 4 x 2.1 Coilcraft
IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay
IHLP1616AB-11 2.2 µH, ±20% 2.75 4.05 x 4.45 x 1.2 Vishay
DEM4518C 1235AS-H-3R3M 3.3 µH, ±20% 2.5 4.5 x 4.7 x 1.9 Toko
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.
spacing
The inductor value also determines the load current at which the power-save mode is entered:
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
Capacitor Selection
Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6214X allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output-
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value
can have some advantages, like smaller voltage ripple and a tighter dc output accuracy in power-save mode (see
SLVA463).
Note: In power-save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input-current ripple
further. The input capacitor buffers the input voltage for transient events and also decouples the converter from
the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it is recommended to place a capacitance of 0.1 uF from AVIN to AGND, to avoid
potential noise coupling.
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VFB [V]
VSS/TR
[V]
0.2 0.4 0.6 0.8
0.4
1.2
0.8
TRSSFB VV /
64.0 ×»
[ ]
F
V
A
tC SSSS 251
52
.
.m
×=
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
Soft-Start Capacitor
A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the
output voltage. A constant-current source provides 2.5 µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
(10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).
spacing
NOTE
DC bias effect: High-capacitance ceramic capacitors have a dc bias effect, which has a
strong influence on the final effective capacitance. Therefore, the right capacitor value
must be chosen carefully. Package size and voltage rating in combination with dielectric
material are responsible for differences between the rated capacitor value and the
effective capacitance.
spacing
Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the
FB pin tracks the SS/TR pin voltage as described in Equation 11 and shown in Figure 39.
spacing (11)
Figure 39. Voltage Tracking Relationship
Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero,
independent of the tracking voltage. Figure 40 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
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pFR
fzero 252
1
1××
=
p
CL
fLC
×
=
p2
1
TPS62140
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
TPS62140
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
R1
R2
VOUT1
VOUT2
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
Figure 40. Sequence for Ratiometric and Simultaneous Startup
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as
VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric
start-up sequence happens if both supplies are sharing the same soft-start capacitor. Equation 10 calculates the
soft-start time, though the SS/TR current must be doubled. Details about these and other tracking and
sequencing circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a
wider tolerance than specified.
Output Filter and Loop Stability
The devices of the TPS6214X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
(12)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care must be taken on the loop stability, which is affected. More information
including a detailed L-C stability matrix can be found in SLVA463.
The TPS6214X devices, both fixed and adjustable versions, include an internal 25 pF feed-forward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14:
spacing
(13)
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÷
÷
ø
ö
ç
ç
è
æ+×
×
=
21
11
252
1
RRpF
fpole p
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
spacing
(14)
spacing
Though the TPS6214X devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in power-save mode and/or
improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion
on the optimization for stability vs transient response can be found in SLVA289 and SLVA466.
Layout Considerations
A proper layout is critical for the operation of a switched-mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6214X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
See Figure 41 for the recommended layout of the TPS6214X, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to the
IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct
an alternating current should outline an area as small as possible, as this area is proportional to the energy
radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (that
is, SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.
22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
1
2
3
4
16151413
12
11
10
9
7 6 5
L1
CIN
R1R2
COUT
VOUT
GND
GND
AVIN
8
EN
PG
to
AGND
PVIN
to GND
plane
C
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
Figure 41. Layout Example
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6214X is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the
size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal
resistance. To get improved thermal behavior, it is recommended to use top layer metal to connect the device
with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved
thermal performance.
If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
Experimental data, taken from the TPS62140 EVM, shows the maximum ambient temperature (without additional
cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see
Figure 37).
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
22uF
5V / 2A
10uF
2.2 µH
(5 .. 17)V
3.3nF
TPS62143
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
TRSSFB RAV /
.. ××= m52640
22uF
10uF
2.2 µH(4 .. 17) V
0.15R187k
ADIM
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
TPS62140
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
Application Example As Power LED Supply
The TPS62140 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Because this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an external
resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62140.
Figure 42 shows an application circuit, tested with analog dimming:
spacing
Figure 42. Single Power LED Supply
spacing
The resistor at SS/TR sets the FB voltage to a level of about 300 mV and is calculated from Equation 15.
spacing
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage must be rated according to the forward voltage needed by the LED
used. More information is available in the application note SLVA451.
spacing
Typical Applications
spacing
spacing
Figure 43. 5-V/2-A Power Supply
spacing
spacing
spacing
spacing
24 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
22uF
1.8V / 2A
10uF
2.2 µH
(3 .. 17)V
3.3nF
TPS62141
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
22uF
2.5V / 2A
10uF
2.2 µH
(3 .. 17)V
3.3nF
TPS62140
390k
180k
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
22uF
3.3V / 2A
10uF
2.2 µH
(3.3 .. 17)V
3.3nF
TPS62142
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
spacing
spacing
spacing
Figure 44. 3.3-V/2-A Power Supply
spacing
spacing
spacing
Figure 45. 2.5-V/2-A Power Supply
spacing
spacing
spacing
Figure 46. 1.8-V/2-A Power Supply
spacing
spacing
spacing
spacing
spacing
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
22uF
1V / 2A
10uF
2.2 µH
3.3nF
TPS62140
51k
200k
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
22uF
1.2V / 2A
10uF
2.2 µH
(3 .. 17)V
3.3nF
TPS62140
75k
150k
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
22uF
1.5V / 2A
10uF
2.2 µH
(3 .. 17)V
3.3nF
TPS62140
130k
150k
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
100k
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
spacing
spacing
spacing
Figure 47. 1.5-V/2-A Power Supply
spacing
spacing
spacing
Figure 48. 1.2-V/2-A Power Supply
spacing
spacing
spacing
Figure 49. 1-V/2-A Power Supply
26 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
22uF
Vout / 2A
10uF
1 / 2.2 µH
(3 .. 17)V
3.3nF
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
R3
R1
R2
TPS62140A
TPS62140
PVIN
AVIN
EN
SS/TR
DEF
FSW
SW
VOS
PG
FB
AGND
PGND
2.2µH
(3 .. 13.7)V
10uF
383k
1.21M
22uF
-3.3V
10uF
3.3nF
maxINOUTIN VVV £+
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
www.ti.com
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
Application Example As Inverting Power Supply
spacing
The TPS62140 can be used as inverting power supply by rearranging external circuitry as shown in Figure 50.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing (16)
spacing
Figure 50. –3.3V Inverting Power Supply
spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
spacing
Active Output Discharge
spacing
The TPS62140A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 51). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10mA.
spacing
Figure 51. Discharge Vout through PG pin
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
TPS62140, TPS62140A
TPS62141, TPS62142, TPS62143
SLVSAJ0B –NOVEMBER 2011–REVISED JUNE 2013
www.ti.com
REVISION HISTORY
Changes from Original (November 2011) to Revision A Page
• Added values to the Initial output voltage accuracy for TA= –10°C to 85°C ........................................................................ 3
• Changed the description of the AGND pin, and added Note 3. ........................................................................................... 4
• Added text to the Power-Save Mode Operation section following Equation 1 ................................................................... 15
• Changed the Layout Considerations section ...................................................................................................................... 22
• Changed Figure 41 ............................................................................................................................................................. 23
Changes from Revision A (October 2012) to Revision B Page
• Added new device version TPS62140A to the data sheet ................................................................................................... 1
• Added device TPS62140A to Ordering Info table ................................................................................................................. 2
• Added text to Power Good section regarding the TPS62140A function ............................................................................. 17
• Added pin option to the footnote for Pin-Selectable Output (DEF) section. ....................................................................... 17
• Added text to Frequency Selection (FSW) section regarding pin control. .......................................................................... 17
• Added text to Tracking Function section for clarification. ................................................................................................... 20
• Added application example with regard to new version TPS62140A. ................................................................................ 27
28 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS62140ARGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PA7I
TPS62140ARGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PA7I
TPS62140RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QTZ
TPS62140RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QTZ
TPS62141RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWA
TPS62141RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWA
TPS62142RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWB
TPS62142RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWB
TPS62143RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWC
TPS62143RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 QWC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2013
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62140ARGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62140ARGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62140RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62140RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62141RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62141RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62142RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62142RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62143RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS62143RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62140ARGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62140ARGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62140RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62140RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62141RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62141RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62142RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62142RGTT QFN RGT 16 250 552.0 185.0 36.0
TPS62143RGTR QFN RGT 16 3000 552.0 367.0 36.0
TPS62143RGTT QFN RGT 16 250 552.0 185.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2013
Pack Materials-Page 2
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