MC74HC273ADT - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

3–1 REV 6

 Motorola, Inc. 1995

10/95

    ! 

   

High–Performance Silicon–Gate CMOS

The MC54/74HC273A is identical in pinout to the LS273. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and Reset

inputs. Each flip–flop is loaded with a low–to–high transition of the Clock

input. Reset is asynchronous and active low.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 264 FETs or 66 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

CLOCK

D7 18

RESET

PIN 20 = VCC

PIN 10 = GND

NONINVERTING

OUTPUTS

ÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎÎ

5.0

ÎÎÎ

µW

ÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎÎ

.0075

ÎÎÎ

*Equivalent to a two–input NAND gate.



PIN ASSIGNMENT

RESET

GND

Q1 5

VCC

CLOCK

FUNCTION TABLE

Inputs Output

Reset Clock D Q

L X X L

H H H

H L L

H L X No Change

H X No Change

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

MC74HCXXXADT

Ceramic

Plastic

SOIC

TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

MC54/74HC273A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.5

1.35

1.8

ÎÎÎÎ

0.5

1.35

1.8

ÎÎÎÎ

0.5

1.35

1.8

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.7

5.2

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC273A

High–Speed CMOS Logic Data

DL129 — Rev 6 3–3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

– 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.4

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

4.0

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

6.0

ÎÎÎÎ

5.0

ÎÎÎÎ

4.0

ÎÎÎ

MHz

ÎÎÎÎ

tPLH

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

145

ÎÎÎÎ

180

ÎÎÎÎ

220

ÎÎÎ

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to Q

(Figures 2 and 4)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

145

ÎÎÎÎ

180

ÎÎÎÎ

220

ÎÎÎ

ÎÎÎÎ

tTLH

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Enabled Output)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC273A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎ

VCC

Volts

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎ

VCC

Volts

ÎÎÎÎÎ

– 55 to 25

ÎÎÎÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎ

VCC

Volts

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Data to Clock

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock to Data

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎ

ÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to

Clock

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

5.0

ÎÎÎ

5.0

ÎÎÎ

5.0

ÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Reset

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

ÎÎÎ

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1000

500

400

ÎÎÎ

1000

500

400

ÎÎÎ

ÎÎ

1000

500

400

ÎÎÎ

MC54/74HC273A

High–Speed CMOS Logic Data

DL129 — Rev 6 3–5 MOTOROLA

SWITCHING WAVEFORMS

Figure 1.

CLOCK

trtfVCC

GND

90%

50%

10%

90%

50%

10%

tPLH tPHL

tTLH tTHL

50%

DATA

CLOCK

VCC

Figure 2.

VALID

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3.

1/fmax

VCC

GND

tsu th

50%

RESET

CLOCK

50%

VCC

GND

VCC

GND

tPHL

Figure 4. Test Circuit

trec

EXPANDED LOGIC DIAGRAM

DRQ

D0 32Q0

DRQ

D1 45Q1

DRQ

D2 76Q2

DRQ

D3 89Q3

DRQ

D4 13 12 Q4

DRQ

D5 14 15 Q5

DRQ

D6 17 16 Q6

DRQ

D7 18 19 Q7

DATA

INPUTS

NONINVERTING

OUTPUTS

MC54/74HC273A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE

POSITION AT SEATING PLANE, AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A23.88 25.15 0.940 0.990

B6.60 7.49 0.260 0.295

C3.81 5.08 0.150 0.200

D0.38 0.56 0.015 0.022

F1.40 1.65 0.055 0.065

G2.54 BSC 0.100 BSC

H0.51 1.27 0.020 0.050

J0.20 0.30 0.008 0.012

K3.18 4.06 0.125 0.160

L7.62 BSC 0.300 BSC

M0 15 0 15

N0.25 1.02 0.010 0.040

_ _ _ _

1 10

SEATING

PLANE

HGK

NJM

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

J20 PL

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A25.66 27.171.010 1.070

B6.10 6.600.240 0.260

C3.81 4.570.150 0.180

D0.39 0.550.015 0.022

G2.54 BSC0.100 BSC

J0.21 0.380.008 0.015

K2.80 3.550.110 0.140

L7.62 BSC0.300 BSC

M0 15 0 15

N0.51 1.010.020 0.040

_ __ _

E1.27 1.770.050 0.070

–A–

SEATING

PLANE

D20 PL

–T–

0.25 (0.010) T

F1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

0.010 (0.25) B S

D20X

0.010 (0.25)

P10X

18X K

–T–

SEATING

PLANE

RX 45

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A12.65 12.95 0.499 0.510

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.50 0.90 0.020 0.035

G1.27 BSC 0.050 BSC

J0.25 0.32 0.010 0.012

K0.10 0.25 0.004 0.009

M0 7 0 7

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

_ _ _ _

MC54/74HC273A

High–Speed CMOS Logic Data

DL129 — Rev 6 3–7 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

DIM

AMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

_ _ _ _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

ÍÍÍÍ

1 10

1120

PIN 1

IDENT

–T–

0.100 (0.004)

DGH

SECTION N–N

J J1

–W–

SEATING

PLANE

–V–

–U–

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

––– –––

U0.15 (0.006) T

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MC54/74HC273A/D

*MC54/74HC273A/D*

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