Freescale Semiconductor, Inc. Data Sheet: Technical Data KL17P64M48SF6 Rev. 4, 03/2015 Kinetis KL17 Microcontroller MKL17Z128Vxx4 MKL17Z256Vxx4 48 MHz ARM(R) Cortex(R)-M0+ and 128/256 KB Flash The KL17 series is optimized for cost-sensitive and batterypowered applications requiring low-power general-purpose connectivity. The product offers: * Embedded ROM with boot loader for flexible program upgrade * High accuracy internal voltage and clock reference * FlexIO to support any standard and customized serial peripheral emulation * Down to 54uA/MHz in very low power run mode and 1.96uA in deep sleep mode (RAM + RTC retained) Core Processor * ARM(R) Cortex(R)-M0+ core up to 48 MHz Memories * 128/256 KB program flash memory * 32 KB SRAM * 16 KB ROM with build-in bootloader * 32-byte backup register System * 4-channel asynchronous DMA controller * Watchdog * Low-leakage wakeup unit * Two-pin Serial Wire Debug (SWD) programming and debug interface * Micro Trace Buffer * Bit manipulation engine * Interrupt controller Clocks * 48MHz high accuracy (up to 0.5%) internal reference clock * 8MHz/2MHz high accuracy (up to 3%) internal reference clock * 1KHz reference clock active under all low-power modes (except VLLS0) * 32-40KHz and 3-32MHz crystal oscillator 32 QFN 5x5 mm P 0.5 mm 48 QFN 7x7 mm P 0.5 mm 64 LQFP 10x10 mm P 0.5 mm 64 BGA 5x5 mm P 0.5 mm Peripherals * One UART module supporting ISO7816, operating up to 1.5 Mbit/s * Two low-power UART modules supporting asynchronous operation in low-power modes * Two I2C modules and I2C0 supporting up to 1 Mbit/s * Two 16-bit SPI modules supporting up to 24 Mbit/s * One FlexIO module supporting emulation of additional UART, IrDA, SPI, I2C, I2S, PWM and other serial modules, etc. * One serial audio interface I2S * One 16-bit 818 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 16 channels * High-speed analog comparator containing a 6-bit DAC for programmable reference input * One 12-bit DAC * 1.2 V internal voltage reference Timers * One 6-channel Timer/PWM module * Two 2-channel Timer/PWM modules * One low-power timer * Periodic interrupt timer * Real time clock Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) 2012-2015 Freescale Semiconductor, Inc. All rights reserved. Operating Characteristics * Voltage range: 1.71 to 3.6 V * Flash write voltage range: 1.71 to 3.6 V * Temperature range: -40 to 105 C Security and Integrity * 80-bit unique identification number per chip * Advanced flash security I/O Packages * 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm thickness * 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm thickness * 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness * 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness * Up to 54 general-purpose input/output pins (GPIO) and 6 high-drive pad Low Power * Down to 54uA/MHz in very low power run mode * Down to 1.96uA in VLLS3 mode (RAM + RTC retained) * Six flexible static modes Ordering Information Product Memory Package IO and ADC channel Part number Marking (Line1/ Line2) Flash (KB) SRAM (KB) Pin count Package GPIOs GPIOs (INT/HD)1 ADC channels (SE/DP) MKL17Z128VFM4 M17P7V 128 32 32 QFN 28 19/6 11/2 MKL17Z256VFM4 M17P8V 256 32 32 QFN 28 19/6 11/2 MKL17Z128VFT4 M17P7V 128 32 48 QFN 40 24/6 18/3 MKL17Z256VFT4 M17P8V 256 32 48 QFN 40 24/6 18/3 MKL17Z128VLH4 MKL17Z128V//LH4 128 32 64 LQFP 54 31/6 20/4 MKL17Z256VLH4 MKL17Z256V//LH4 256 32 64 LQFP 54 31/6 20/4 MKL17Z128VMP4 M17P7V 128 32 64 MAPBGA 54 31/6 20/4 MKL17Z256VMP4 M17P8V 256 32 64 MAPBGA 54 31/6 20/4 1. INT: interrupt pin numbers; HD: high drive pin numbers Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KL1XPB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL17P64M48SF6RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for KINETIS_L_1N71K1 a particular device mask set. Package drawing Package dimensions are provided in package drawings. 64-LQFP: 98ASS23234W1 64 MAPBGA: 98ASA00420D132 QFN: 98ASA00615D1 48 QFN: 98ASA00616D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 3 Freescale Semiconductor, Inc. Table of Contents 1 Ratings.................................................................................... 5 1.1 Thermal handling ratings................................................. 5 1.2 Moisture handling ratings................................................ 5 1.3 ESD handling ratings....................................................... 5 1.4 Voltage and current operating ratings............................. 5 2 General................................................................................... 6 2.1 AC electrical characteristics.............................................6 2.2 Nonswitching electrical specifications..............................6 2.2.1 Voltage and current operating requirements....... 7 2.2.2 LVD and POR operating requirements................7 2.2.3 Voltage and current operating behaviors.............8 2.2.4 Power mode transition operating behaviors........ 9 2.2.5 Power consumption operating behaviors............ 10 2.2.6 EMC radiated emissions operating behaviors..... 20 2.2.7 Designing with radiated emissions in mind..........21 2.2.8 Capacitance attributes.........................................21 2.3 Switching specifications...................................................21 2.3.1 Device clock specifications..................................21 2.3.2 General switching specifications......................... 22 2.4 Thermal specifications..................................................... 22 2.4.1 Thermal operating requirements......................... 22 2.4.2 Thermal attributes................................................23 3 Peripheral operating requirements and behaviors.................. 24 3.1 Core modules.................................................................. 24 3.1.1 SWD electricals .................................................. 24 3.2 System modules.............................................................. 25 3.3 Clock modules................................................................. 25 3.3.1 MCG-Lite specifications.......................................25 3.3.2 Oscillator electrical specifications........................26 3.4 Memories and memory interfaces................................... 29 3.4.1 Flash electrical specifications.............................. 29 3.5 Security and integrity modules........................................ 30 3.6 Analog............................................................................. 30 3.6.1 4 5 6 7 8 9 3.6.2 Voltage reference electrical specifications.......... 35 3.6.3 CMP and 6-bit DAC electrical specifications....... 36 3.6.4 12-bit DAC electrical characteristics....................38 3.7 Timers..............................................................................41 3.8 Communication interfaces............................................... 41 3.8.1 SPI switching specifications................................ 41 3.8.2 I2C....................................................................... 46 3.8.3 UART...................................................................48 3.8.4 I2S/SAI switching specifications.......................... 48 Dimensions............................................................................. 52 4.1 Obtaining package dimensions....................................... 52 Pinouts and Packaging........................................................... 53 5.1 KL17 Signal Multiplexing and Pin Assignments...............53 5.2 KL17 Family Pinouts........................................................55 Ordering parts......................................................................... 59 6.1 Determining valid orderable parts....................................59 Part identification.....................................................................60 7.1 Description.......................................................................60 7.2 Format............................................................................. 60 7.3 Fields............................................................................... 60 7.4 Example...........................................................................61 Terminology and guidelines.................................................... 61 8.1 Definition: Operating requirement....................................61 8.2 Definition: Operating behavior......................................... 61 8.3 Definition: Attribute.......................................................... 62 8.4 Definition: Rating............................................................. 62 8.5 Result of exceeding a rating............................................ 63 8.6 Relationship between ratings and operating requirements....................................................................63 8.7 Guidelines for ratings and operating requirements..........63 8.8 Definition: Typical value...................................................64 8.9 Typical value conditions.................................................. 65 Revision History...................................................................... 65 ADC electrical specifications............................... 30 4 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature -55 150 C 1 TSDR Solder temperature, lead-free -- 260 C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2. Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes -- 3 -- 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Table 3. ESD handling ratings Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 Latch-up current at ambient temperature of 105 C -100 +100 mA 3 ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 5 Freescale Semiconductor, Inc. General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage -0.3 3.8 V IDD Digital supply current -- 120 mA VIO IO pin input voltage -0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) -25 25 mA VDD - 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. VIH Input Signal High Low 80% 50% 20% Midpoint1 Fall Time VIL Rise Time The midpoint is VIL + (VIH - VIL) / 2 Figure 1. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics. * CL=30 pF loads * Slew rate disabled * Normal drive strength 2.2 Nonswitching electrical specifications 6 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD - VDDA VDD-to-VDDA differential voltage -0.1 0.1 V VSS - VSSA VSS-to-VSSA differential voltage -0.1 0.1 V * 2.7 V VDD 3.6 V 0.7 x VDD -- V * 1.7 V VDD 2.7 V 0.75 x VDD -- V * 2.7 V VDD 3.6 V -- 0.35 x VDD V * 1.7 V VDD 2.7 V -- 0.3 x VDD V 0.06 x VDD -- V -3 -- mA -25 -- mA VIH VIL Input high voltage Input low voltage VHYS Input hysteresis IICIO IO pin negative DC injection current -- single pin 1 * VIN < VSS-0.3V IICcont Notes Contiguous pin DC injection current --regional limit, includes sum of negative injection currents of 16 contiguous pins * Negative current injection VODPU Open drain pullup voltage level VDD VDD V VRAM VDD voltage required to retain RAM 1.2 -- V 2 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD. 2.2.2 LVD and POR operating requirements Table 6. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit Notes VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V -- VLVDH Falling low-voltage detect threshold -- high range (LVDV = 01) 2.48 2.56 2.64 V -- Low-voltage warning thresholds -- high range 1 Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 7 Freescale Semiconductor, Inc. General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW1H Description * Level 1 falling (LVWV = 00) 2.62 2.70 2.78 V VLVW2H * Level 2 falling (LVWV = 01) 2.72 2.80 2.88 V VLVW3H * Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H * Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V -- 60 -- mV -- 1.54 1.60 1.66 V -- VHYSH Low-voltage inhibit reset/recover hysteresis -- high range VLVDL Falling low-voltage detect threshold -- low range (LVDV=00) Low-voltage warning thresholds -- low range VLVW1L * Level 1 falling (LVWV = 00) VLVW2L * Level 2 falling (LVWV = 01) VLVW3L * Level 3 falling (LVWV = 10) VLVW4L * Level 4 falling (LVWV = 11) VHYSL Low-voltage inhibit reset/recover hysteresis -- low range Notes 1 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.16 V -- 40 -- mV -- VBG Bandgap voltage reference 0.97 1.00 1.03 V -- tLPO Internal low power oscillator period -- factory trimmed 900 1000 1100 s -- 1. Rising thresholds are falling threshold + hysteresis voltage 2.2.3 Voltage and current operating behaviors Table 7. Voltage and current operating behaviors Symbol VOH VOH Description Min. Unit Output high voltage -- normal drive pad VDD - 0.5 -- V * 1.71 V VDD 2.7 V, IOH = -1.5 mA VDD - 0.5 -- V Output high voltage -- high drive pad 1 * 2.7 V VDD 3.6 V, IOH = -18 mA VDD - 0.5 -- V * 1.71 V VDD 2.7 V, IOH = -6 mA VDD - 0.5 -- V -- 100 mA -- 0.5 V -- 0.5 V Output high current total for all ports VOL Output low voltage -- normal drive pad * 2.7 V VDD 3.6 V, IOL = 5 mA * 1.71 V VDD 2.7 V, IOL = 1.5 mA Notes 1 * 2.7 V VDD 3.6 V, IOH = -5 mA IOHT VOL Max. Output low voltage -- high drive pad 1 1 -- 0.5 V Table continues on the next page... 8 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Table 7. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit -- 0.5 V Output low current total for all ports -- 100 mA IIN Input leakage current (per pin) for full temperature range -- 1 A 2 IIN Input leakage current (per pin) at 25 C -- 0.025 A 2 IIN Input leakage current (total all pins) for full temperature range -- 64 A 2 IOZ Hi-Z (off-state) leakage current (per pin) -- 1 A RPU Internal pullup resistors 20 50 k * 2.7 V VDD 3.6 V, IOL = 18 mA Notes * 1.71 V VDD 2.7 V, IOL = 6 mA IOLT 3 1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSxRUN recovery times in the following table assume this clock configuration: * CPU and system clocks = 48 MHz * Bus and flash clock = 24 MHz * HIRC clock mode Table 8. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit Notes -- -- 300 s 1 -- 152 166 s -- 152 166 s -- 93 104 s -- 7.5 8 s * VLLS0 RUN * VLLS1 RUN * VLLS3 RUN * LLS RUN Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 9 Freescale Semiconductor, Inc. General Table 8. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit -- 7.5 8 s -- 7.5 8 s Notes * VLPS RUN * STOP RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11) 2.2.5 Power consumption operating behaviors The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE The while (1) test is executed with flash cache enabled. Table 9. Power consumption operating behaviors Symbol IDDA Description Analog supply current IDD_RUNCO Running CoreMark in flash in compute operation mode--48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V * at 25 C Min. Typ. Max. Unit Notes -- -- See note mA 1 2 -- * at 105 C IDD_RUNCO Running While(1) loop in flash in compute operation mode--48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V * at 25 C -- * at 105 C IDD_RUN Run mode current--48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C * at 105 C IDD_RUN 5.76 6.40 6.04 6.68 3.21 3.85 3.49 4.13 mA mA 2 -- 6.45 7.09 -- 6.75 7.39 mA Run mode current--48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V 2 * at 25 C mA * at 105 C -- 3.95 4.59 -- 4.23 4.87 Table continues on the next page... 10 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. IDD_RUN Run mode current--48M HIRC mode, running CoreMark in Flash all peripheral clock disable 12 MHz core/6 MHz flash, VDD = 3.0 V * at 25 C Run mode current--48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C -- Run mode current--48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C -- -- * at 105 C IDD_RUN Run mode current--48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V * at 25 C -- * at 105 C IDD_RUN Run mode current--48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V * at 25 C -- * at 105 C IDD_RUN Run mode current--48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C -- * at 105 C IDD_RUN Run mode current--48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C -- * at 105 C IDD_RUN Unit Notes 2.68 3.32 2.96 3.60 mA 2 * at 105 C IDD_RUN Max. 2 * at 105 C IDD_RUN Typ. 8.08 8.72 8.39 9.03 3.90 4.54 4.21 4.85 2.66 3.30 2.94 3.58 2.03 2.67 2.31 2.95 5.52 6.16 5.83 6.47 5.29 5.93 5.56 6.20 Run mode current--48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V * at 25 C mA mA mA mA mA mA mA * at 105 C -- 6.91 7.55 7.19 7.91 Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 11 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol Min. Typ. Max. Unit IDD_VLPRCO Very Low Power Run Core Mark in Flash in Compute Operation mode: Core@4MHz, Flash @1MHz, VDD = 3.0 V * at 25 C -- 826 907 A IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode-- 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V * at 25 C -- 405 486 A IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:--2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V * at 25 C -- 154 235 A -- 108 189 A -- 39 120 A Very-low-power run mode current-- 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V * at 25 C -- 249 330 A IDD_VLPR Very-low-power run mode current-- 8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V * at 25 C -- 337 418 A IDD_VLPR Very-low-power run mode current-- 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V * at 25 C -- 416 497 A -- 494 575 A -- 166 247 A -- 50 131 A IDD_VLPR IDD_VLPR IDD_VLPR Description Very-low-power run mode current-- 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V * at 25 C Very-low-power run mode current-- 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V * at 25 C IDD_VLPR Very-low-power run mode current-- 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V * at 25 C IDD_VLPR Very-low-power run mode current--2 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V * at 25 C IDD_VLPR Very-low-power run mode current--2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V * at 25 C Notes Table continues on the next page... 12 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit IDD_VLPR Very-low-power run mode current--2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V * at 25 C -- 208 289 A Wait mode current--core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V -- 1.81 2.12 mA Wait mode current--core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V -- 1.22 1.84 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V -- 172 222 A IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V -- 69 105 A IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V -- 36 76 A -- 1.81 2.06 mA -- 1.00 1.25 mA -- 161.93 181.50 -- 181.45 206.95 -- 236.29 315.62 -- 390.33 525.63 -- 3.31 6.32 -- 10.43 26.39 -- 34.14 94.52 -- 104.38 219.39 -- 3.21 6.47 -- 10.26 26.43 -- 33.49 93.09 IDD_WAIT IDD_WAIT Notes IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V IDD_STOP Stop mode current at 3.0 V * at 25 C and below * at 50 C * at 85 C * at 105 C IDD_VLPS Very-low-power stop mode current at 3.0 V * at 25 C and below * at 50 C * at 85 C * at 105 C IDD_VLPS Very-low-power stop mode current at 1.8 V * at 25 C and below * at 50 C A A A Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 13 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol Description * at 85 C Min. Typ. Max. -- 102.92 216.69 -- 2.06 5.32 -- 4.72 9.32 -- 8.13 14.14 -- 13.34 25.75 -- 41.08 59.19 -- 2.46 5.72 -- 5.12 9.72 -- 8.53 14.54 -- 13.74 26.15 -- 41.48 59.59 Unit Notes * at 105 C IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C A A 3 -- 2.35 2.99 -- 4.91 8.43 -- 8.32 14.73 -- 13.44 24.32 -- 40.47 59.45 -- 1.45 1.85 -- 3.37 4.39 -- 5.76 10.29 -- 9.72 16.82 -- 30.41 41.40 A A 3 -- 2.05 2.45 -- 3.97 4.99 -- 6.36 10.89 -- 10.32 17.42 -- 31.01 42.00 A Table continues on the next page... 14 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V * at 25 C and below * at 50 C * at 70 C * at 85 C * at 105 C IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V * at 25 C and below * at 50C * at 70C * at 85C * at 105 C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V * at 25 C and below * at 50C * at 70C * at 85C * at 105 C IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V * at 25 C and below Typ. Max. -- 1.96 2.36 -- 3.86 6.60 -- 6.23 10.91 -- 10.21 17.73 -- 30.25 40.83 -- 0.66 0.87 -- 1.78 5.27 -- 2.55 6.09 -- 4.83 9.67 -- 16.42 23.15 -- 1.26 1.47 -- 2.38 5.87 -- 3.15 6.69 -- 5.43 10.27 -- 17.02 23.75 -- 1.96 2.43 -- 2.78 4.13 -- 4.85 7.65 -- 15.78 19.98 -- 352.69 468.91 * at 50 C -- 1252.80 1439.94 * at 70 C -- 2531.05 3241.52 * at 85 C -- 4400.99 5236.34 * at 105 C -- 16087.21 21895.19 * at 105 C IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V * at 25 C and below A A 3 1.46 * at 85C A 3 1.16 * at 70C Notes 3 -- * at 50C Unit A nA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 15 Freescale Semiconductor, Inc. General Table 9. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. * at 25 C and below -- 179.60 277.81 * at 50 C -- 1086.61 1312.79 * at 70 C -- 2252.84 2944.26 * at 85 C -- 4248.16 5096.24 * at 105 C -- 15948.78 21726.94 -- 1.241 -- 1.271 -- 1.47 -- 1.259 -- 1.271 -- 1.47 IDD_RESET_ Blank flash content (default from factory) with reset pin hold low at 1.7V LOW * at -40 C -- * at 25 C * at 105 C IDD_RESET_ Blank flash content (default from factory) with reset pin hold low at 3V LOW * at -40 C -- * at 25 C * at 105 C Unit Notes nA mA mA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption. Table 10. Low power mode peripheral adders -- typical value Symbol Description Temperature (C) Unit -40 25 50 70 85 105 IIRC8MHz 8 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 8 MHz IRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 93 93 93 93 93 93 A IIRC2MHz 2 MHz internal reference clock (IRC) adder. Measured by entering STOP mode with the 2 MHz IRC enabled, MCG_SC[FCRDIV]=000b, MCG_MC[LIRC_DIV2]=000b. 29 29 29 29 29 29 A IEREFSTEN4MHz External 4 MHz crystal clock adder. Measured by entering STOP or VLPS mode with the crystal enabled. 206 224 230 238 245 253 A IEREFSTEN32KHz External 32 kHz crystal clock adder by means of the OSC0_CR[EREFSTEN and EREFSTEN] bits. Measured by entering all modes with the crystal enabled. * VLLS1 440 490 540 560 570 580 Table continues on the next page... 16 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Table 10. Low power mode peripheral adders -- typical value (continued) Symbol ILPTMR Description Temperature (C) Unit -40 25 50 70 85 105 * VLLS3 440 490 540 560 570 580 * LLS 490 490 540 560 570 680 * VLPS 510 560 560 560 610 680 * STOP 510 560 560 560 610 680 30 30 30 85 100 200 22 22 22 22 22 22 A 114 114 114 114 114 114 A 34 34 34 34 34 34 147 147 147 147 147 147 42 42 42 42 42 42 nA LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. * IRC8M (8 MHz internal reference clock) * IRC2M (2 MHz internal reference clock) ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. * IRC8M (8 MHz internal reference clock) * IRC2M (2 MHz internal reference clock) A IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 A IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 330 330 330 330 330 330 A Kinetis KL17 Microcontroller, Rev.4, 03/2015. 17 Freescale Semiconductor, Inc. General 2.2.5.1 Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: * * * * MCG-Lite in HIRC for run mode, and LIRC for VLPR mode No GPIOs toggled Code execution from flash For the ALLOFF curve, all peripheral clocks are disabled except FTFA Figure 2. Run mode supply current vs. core frequency 18 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General Kinetis KL17 Microcontroller, Rev.4, 03/2015. 19 Freescale Semiconductor, Inc. Current ionon onVDD VDD (A) CurrentC Consumpt onsumption (A) General Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15-50 11 dBV VRE2 Radiated emissions voltage, band 2 50-150 12 dBV VRE3 Radiated emissions voltage, band 3 150-500 10 dBV VRE4 Radiated emissions voltage, band 4 500-1000 6 dBV IEC level 0.15-1000 N -- VRE_IEC 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement 20 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. General of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 C, fOSC = IRC48M, fSYS = 48 MHz, fBUS = 24 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions--TEM Cell and Wideband TEM Cell Method 2.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for "EMC design." 2.2.8 Capacitance attributes Table 12. Capacitance attributes Symbol CIN Description Input capacitance Min. Max. Unit -- 7 pF Min. Max. Unit 2.3 Switching specifications 2.3.1 Device clock specifications Table 13. Device clock specifications Symbol Description Normal run mode fSYS System and core clock -- 48 MHz fBUS Bus clock -- 24 MHz fFLASH Flash clock -- 24 MHz fLPTMR LPTMR clock -- 24 MHz VLPR and VLPS modes1 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 1 MHz fFLASH Flash clock -- 1 MHz fLPTMR LPTMR clock2 -- 24 MHz Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 21 Freescale Semiconductor, Inc. General Table 13. Device clock specifications (continued) Symbol Description Min. Max. Unit -- 16 MHz Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) -- 16 MHz TPM asynchronous clock -- 8 MHz LPUART0/1 asynchronous clock -- 8 MHz fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fLPUART0/1 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or from VLPR. 2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin. 2.3.2 General switching specifications These general-purpose specifications apply to all signals configured for GPIO and UART signals. Table 14. General switching specifications Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1 External RESET and NMI pin interrupt pulse width -- Asynchronous path 100 -- ns 2 GPIO pin interrupt pulse width -- Asynchronous path 16 -- ns 2 Port rise and fall time -- 36 ns 3 1. The synchronous and asynchronous timing must be met. 2. This is the shortest pulse that is guaranteed to be recognized. 3. 75 pF load 2.4 Thermal specifications 2.4.1 Thermal operating requirements Table 15. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature -40 125 C TA Ambient temperature -40 105 C 22 Freescale Semiconductor, Inc. Notes 1 Kinetis KL17 Microcontroller, Rev.4, 03/2015. General 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + JA x chip power dissipation. 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Description 48 QFN 32 QFN 64 LQFP 64 MAPBG A Unit Notes Single-layer (1S) RJA Thermal resistance, junction to ambient (natural convection) 86 101 70 50.3 C/W 1 Four-layer (2s2p) RJA Thermal resistance, junction to ambient (natural convection) 29 33 51 42.9 C/W Single-layer (1S) RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 71 84 58 41.4 C/W Four-layer (2s2p) RJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 24 28 45 38.0 C/W -- RJB Thermal resistance, junction to board 12 13 33 39.6 C/W 2 -- RJC Thermal resistance, junction to case 1.7 1.7 20 27.3 C/W 3 -- JT Thermal characterization parameter, junction to package top outside center (natural convection) 2 3 4 0.4 C/W 4 -- JB Thermal characterization parameter, junction to package bottom (natural convection) - - - 12.6 C/W 5 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions--Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions--Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions--Natural Convection (Still Air). 5. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3 Peripheral operating requirements and behaviors 3.1 Core modules 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.6 V 0 25 MHz 1/J1 -- ns 20 -- ns SWD_CLK frequency of operation * Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width * Serial wire debug J4 SWD_CLK rise and fall times -- 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 -- ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 -- ns J11 SWD_CLK high to SWD_DIO data valid -- 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 -- ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 4. Serial wire clock input timing 24 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG-Lite specifications Table 18. IRC48M specification Symbol Description Min. Typ. Max. Unit Notes IDD Supply current -- 400 500 A -- fIRC Output frequency -- 48 -- MHz -- fIRC_T Output frequency range (trimmed) -- 0.5 1.0 %fIRC -- Tj Period jitter (RMS) -- 35 150 ps -- Tsu Startup time -- 2 3 s -- Kinetis KL17 Microcontroller, Rev.4, 03/2015. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 19. IRC8M/2M specification Symbol Description Min. Typ. Max. Unit Notes IDD_2M Supply current in 2 MHz mode -- 14 17 A -- IDD_8M Supply current in 8 MHz mode -- 30 35 A -- fIRC_2M Output frequency -- 2 -- MHz -- fIRC_8M Output frequency -- 8 -- MHz -- fIRC_T_2M Output frequency range (trimmed) -- -- 3 %fIRC -- fIRC_T_8M Output frequency range (trimmed) -- -- 3 %fIRC -- Tsu_2M Startup time -- -- 12.5 s -- Tsu_8M Startup time -- -- 12.5 s -- Figure 6. IRC8M Frequency Drift vs Temperature curve 3.3.2 Oscillator electrical specifications 26 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 3.3.2.1 Oscillator DC electrical specifications Table 20. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDOSC IDDOSC Supply current -- low-power mode (HGO=0) Notes 1 * 32 kHz -- 500 -- nA * 4 MHz -- 200 -- A * 8 MHz (RANGE=01) -- 300 -- A * 16 MHz -- 950 -- A * 24 MHz -- 1.2 -- mA * 32 MHz -- 1.5 -- mA Supply current -- high gain mode (HGO=1) 1 * 32 kHz -- 25 -- A * 4 MHz -- 400 -- A * 8 MHz (RANGE=01) -- 500 -- A * 16 MHz -- 2.5 -- mA * 24 MHz -- 3 -- mA * 32 MHz -- 4 -- mA Cx EXTAL load capacitance -- -- -- 2, 3 Cy XTAL load capacitance -- -- -- 2, 3 RF Feedback resistor -- low-frequency, low-power mode (HGO=0) -- -- -- M Feedback resistor -- low-frequency, high-gain mode (HGO=1) -- 10 -- M Feedback resistor -- high-frequency, lowpower mode (HGO=0) -- -- -- M Feedback resistor -- high-frequency, high-gain mode (HGO=1) -- 1 -- M Series resistor -- low-frequency, low-power mode (HGO=0) -- -- -- k Series resistor -- low-frequency, high-gain mode (HGO=1) -- 200 -- k Series resistor -- high-frequency, low-power mode (HGO=0) -- -- -- k -- 0 -- k -- 0.6 -- V RS 2, 4 Series resistor -- high-frequency, high-gain mode (HGO=1) 5 Vpp Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, low-power mode (HGO=0) Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 27 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 20. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) -- low-frequency, high-gain mode (HGO=1) -- VDD -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, low-power mode (HGO=0) -- 0.6 -- V Peak-to-peak amplitude of oscillation (oscillator mode) -- high-frequency, high-gain mode (HGO=1) -- VDD -- V Notes 1. VDD=3.3 V, Temperature =25 C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol Oscillator frequency specifications Table 21. Oscillator frequency specifications Description Min. Typ. Max. Unit fosc_lo Oscillator crystal or resonator frequency -- lowfrequency mode (MCG_C2[RANGE]=00) 32 -- 40 kHz fosc_hi_1 Oscillator crystal or resonator frequency -- highfrequency mode (low range) (MCG_C2[RANGE]=01) 3 -- 8 MHz fosc_hi_2 Oscillator crystal or resonator frequency -- high frequency mode (high range) (MCG_C2[RANGE]=1x) 8 -- 32 MHz fec_extal Input clock frequency (external clock mode) -- -- 48 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % Crystal startup time -- 32 kHz low-frequency, low-power mode (HGO=0) -- 750 -- ms Crystal startup time -- 32 kHz low-frequency, high-gain mode (HGO=1) -- 250 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), low-power mode (HGO=0) -- 0.6 -- ms Crystal startup time -- 8 MHz high-frequency (MCG_C2[RANGE]=01), high-gain mode (HGO=1) -- 1 -- ms tcst Notes 1, 2 3, 4 1. Other frequency limits may apply when external clock is being used as a reference for the FLL 2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it remains within the limits of the DCO input clock frequency. 3. Proper PC board layout procedures must be followed to achieve specifications. 28 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 3.4 Memories and memory interfaces 3.4.1 Flash electrical specifications This section describes the electrical characteristics of the flash memory module. 3.4.1.1 Flash timing specifications -- program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 22. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit Notes thvpgm4 Longword Program high-voltage time -- 7.5 18 s -- thversscr Sector Erase high-voltage time -- 13 113 ms 1 -- 52 452 ms 1 Unit Notes thversblk128k Erase Block high-voltage time for 128 KB 1. Maximum time based on expectations at cycling end-of-life. 3.4.1.2 Symbol Flash timing specifications -- commands Table 23. Flash command timing specifications Description Min. Typ. Max. Read 1s Block execution time trd1blk128k 1 * 128 KB program flash -- -- 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) -- -- 60 s 1 tpgmchk Program Check execution time -- -- 45 s 1 trdrsrc Read Resource execution time -- -- 30 s 1 tpgm4 Program Longword execution time -- 65 145 s -- Erase Flash Block execution time tersblk128k * 128 KB program flash 2 -- 88 600 ms tersscr Erase Flash Sector execution time -- 14 114 ms 2 trd1all Read 1s All Blocks execution time -- -- 1.8 ms 1 trdonce Read Once execution time -- -- 25 s 1 Program Once execution time -- 65 -- s -- tpgmonce Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 29 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 23. Flash command timing specifications (continued) Symbol Description Min. Typ. Max. Unit Notes tersall Erase All Blocks execution time -- 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time -- -- 30 s 1 tersallu Erase All Blocks Unsecure execution time -- 175 1300 ms 2 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 Flash high voltage current behaviors Table 24. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 3.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation -- 2.5 6.0 mA Average current adder during high voltage flash erase operation -- 1.5 4.0 mA Reliability specifications Table 25. NVM reliability specifications Description Typ.1 Max. Unit Notes 50 -- years -- 20 100 -- years -- 10 K 50 K -- cycles 2 Min. Program Flash tnvmretp10k Data retention after up to 10 K cycles tnvmretp1k Data retention after up to 1 K cycles nnvmcycp Cycling endurance 5 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C. 3.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 3.6 Analog 30 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 3.6.1 ADC electrical specifications Using differential inputs can achieve better system accuracy than using single-end inputs. 3.6.1.1 16-bit ADC operating conditions Table 26. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 -- 3.6 V -- VDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2 VSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2 VREFH ADC reference voltage high 1.13 VDDA VDDA V 3 VREFL ADC reference voltage low VSSA VSSA VSSA V 3 VADIN Input voltage * 16-bit differential mode VREFL -- 31/32 * VREFH V -- * All other modes VREFL -- * 16-bit mode -- 8 10 pF -- * 8-bit / 10-bit / 12-bit modes -- 4 5 -- 2 5 k -- CADIN RADIN RAS Input capacitance Input series resistance Analog source resistance (external) VREFH 13-bit / 12-bit modes 4 fADCK < 4 MHz -- -- 5 k fADCK ADC conversion 13-bit mode clock frequency 1.0 -- 18.0 MHz 5 fADCK ADC conversion 16-bit mode clock frequency 2.0 -- 12.0 MHz 5 Crate ADC conversion 13-bit modes rate No ADC hardware averaging 6 20.000 -- 818.330 Ksps Continuous conversions enabled, subsequent conversion time Crate ADC conversion 16-bit mode rate No ADC hardware averaging 6 37.037 -- 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 31 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3. VREFH can act as VREF_OUT when VREFV1 module is enabled. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 7. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Symbol Conditions1 Description Min. Typ.2 Max. Unit Notes 0.215 -- 1.7 mA 3 * ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz * ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/fADACK * ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz * ADLPC = 0, ADHSC = 1 4.4 6.2 9.5 MHz LSB4 IDDA_ADC Supply current fADACK ADC asynchronous clock source Sample Time TUE See Reference Manual chapter for sample times Total unadjusted error * 12-bit modes -- 4 6.8 * <12-bit modes -- 1.4 2.1 5 Table continues on the next page... 32 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol DNL INL EFS EQ ENOB Description Differential nonlinearity Integral nonlinearity Full-scale error Quantization error Effective number of bits Conditions1 Typ.2 Min. Max. Unit Notes -1.1 to +1.9 LSB4 5 LSB4 5 LSB4 VADIN = VDDA5 * 12-bit modes -- 0.7 * <12-bit modes -- 0.2 * 12-bit modes -- 1.0 * <12-bit modes -- 0.5 * 12-bit modes -- -4 -5.4 * <12-bit modes -- -1.4 -1.8 * 16-bit modes -- -1 to 0 -- * 13-bit modes -- -- 0.5 -0.3 to 0.5 -2.7 to +1.9 -0.7 to +0.5 16-bit differential mode bits * Avg = 32 12.8 14.5 * Avg = 4 11.9 13.8 * Avg = 4 SINAD THD Signal-to-noise plus distortion See ENOB Total harmonic distortion 16-bit differential mode -- -- bits bits 12.2 13.9 -- 11.4 13.1 -- 6.02 x ENOB + 1.76 * Avg = 32 6 bits 16-bit single-ended mode * Avg = 32 LSB4 dB dB -- -94 7 -- dB 16-bit single-ended mode * Avg = 32 SFDR Spurious free dynamic range -- -85 82 95 16-bit differential mode * Avg = 32 16-bit single-ended mode 78 -- -- dB -- dB 7 90 * Avg = 32 EIL Input leakage error IIn x RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 33 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol VTEMP25 Description Conditions1 Min. Typ.2 Max. Unit Notes Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/C 8 Temp sensor voltage 25 C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input 15.00 14.70 14.40 14.10 ENOB 13.80 13.50 13.20 12.90 12.60 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples 12.30 12.00 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode 34 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Typical ADC 16-bit Single-Ended ENOB vs ADC Clock 100Hz, 90% FS Sine Input 14.00 13.75 13.50 13.25 13.00 ENOB 12.75 12.50 12.25 12.00 11.75 11.50 11.25 11.00 Averaging of 4 samples Averaging of 32 samples 1 2 3 4 5 6 7 8 9 10 11 12 ADC Clock Frequency (MHz) Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 3.6.2 Voltage reference electrical specifications Table 28. VREF full-range operating requirements Symbol Description VDDA Supply voltage TA Temperature CL Output load capacitance Min. Max. Unit Notes 3.6 V -- Operating temperature range of the device C -- 100 nF 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference. 2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of the device. Table 29 is tested under the condition of setting VREF_TRM[CHOPEN], VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 29. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output -- factory trim 1.1584 -- 1.2376 V 1 Vout Voltage reference output -- user trim 1.193 -- 1.197 V 1 Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 35 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 29. VREF full-range operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes Vstep Voltage reference trim step -- 0.5 -- mV 1 Vtdrift Temperature drift (Vmax -Vmin across the full temperature range: 0 to 70C) -- -- 50 mV 1 Ibg Bandgap only current -- -- 80 A 1 Ilp Low-power buffer current -- -- 360 uA 1 Ihp High-power buffer current -- -- 1 mA 1 V 1, 2 VLOAD Load regulation * current = 1.0 mA Tstup Buffer startup time Tchop_osc_st Internal bandgap start-up delay with chop oscillator enabled up Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) -- 200 -- -- -- 100 s -- -- -- 35 ms -- -- 2 -- mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Table 30. VREF limited-range operating requirements Symbol Description Min. Max. Unit Notes TA Temperature 0 50 C -- Table 31. VREF limited-range operating behaviors Symbol Vout Description Voltage reference output with factory trim Min. Max. Unit Notes 1.173 1.225 V -- 3.6.3 CMP and 6-bit DAC electrical specifications Table 32. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 -- 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 200 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- -- 20 A VAIN Analog input voltage VSS - 0.3 -- VDD V VAIO Analog input offset voltage -- -- 20 mV VH Analog comparator hysteresis1 Table continues on the next page... 36 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 32. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit * CR0[HYSTCTR] = 00 -- 5 -- mV * CR0[HYSTCTR] = 01 -- 10 -- mV * CR0[HYSTCTR] = 10 -- 20 -- mV * CR0[HYSTCTR] = 11 -- 30 -- mV VCMPOh Output high VDD - 0.5 -- -- V VCMPOl Output low -- -- 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns -- -- 40 s -- 7 -- A Analog comparator initialization IDAC6b delay2 6-bit DAC current adder (enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB3 DNL 6-bit DAC differential non-linearity -0.3 -- 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 0.08 0.07 CMP Hystereris (V) 0.06 HYSTCTR Setting 0.05 00 0.04 01 10 11 0.03 0.02 0.01 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vin level (V) Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis KL17 Microcontroller, Rev.4, 03/2015. 37 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP Hysteresis (V) 0.12 HYSTCTR Setting 0.1 00 01 10 11 0.08 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 1.9 Vin level (V) 2.2 2.5 2.8 3.1 Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 3.6.4 12-bit DAC electrical characteristics 3.6.4.1 Symbol 12-bit DAC operating requirements Table 33. 12-bit DAC operating requirements Desciption VDDA Supply voltage VDACR Reference voltage Min. Max. Unit 3.6 V Notes 1.13 3.6 V 1 CL Output load capacitance -- 100 pF 2 IL Output load current -- 1 mA 1. The DAC reference can be selected to be VDDA or VREFH. 2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. 38 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 3.6.4.2 Symbol 12-bit DAC operating behaviors Table 34. 12-bit DAC operating behaviors Description IDDA_DACL Supply current -- low-power mode Min. Typ. Max. Unit -- -- 250 A -- -- 900 A Notes P IDDA_DACH Supply current -- high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) -- low-power mode -- 100 200 s 1 tDACHP Full-scale settling time (0x080 to 0xF7F) -- high-power mode -- 15 30 s 1 -- 0.7 1 s 1 tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) -- low-power mode and highspeed mode Vdacoutl DAC output voltage range low -- highspeed mode, no load, DAC set to 0x000 -- -- 100 mV Vdacouth DAC output voltage range high -- highspeed mode, no load, DAC set to 0xFFF VDACR -100 -- VDACR mV INL Integral non-linearity error -- high speed mode -- -- 8 LSB 2 DNL Differential non-linearity error -- VDACR > 2 V -- -- 1 LSB 3 DNL Differential non-linearity error -- VDACR = VREF_OUT -- -- 1 LSB 4 -- 0.4 0.8 %FSR 5 Gain error -- 0.1 0.6 %FSR 5 Power supply rejection ratio, VDDA 2.4 V 60 -- 90 dB TCO Temperature coefficient offset voltage -- 3.7 -- V/C TGE Temperature coefficient gain error -- 0.000421 -- %FSR/C Rop Output resistance (load = 3 k) -- -- 250 SR Slew rate -80h F7Fh 80h VOFFSET Offset error EG PSRR BW 1. 2. 3. 4. 5. 6. 6 V/s * High power (SPHP) 1.2 1.7 -- * Low power (SPLP) 0.05 0.12 -- 3dB bandwidth kHz * High power (SPHP) 550 -- -- * Low power (SPLP) 40 -- -- Settling within 1 LSB The INL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV The DNL is measured for 0 + 100 mV to VDACR -100 mV with VDDA > 2.4 V Calculated by a best fit curve from VSS + 100 mV to VDACR - 100 mV VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Kinetis KL17 Microcontroller, Rev.4, 03/2015. 39 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 12. Typical INL error vs. digital code 40 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 -40 55 25 85 105 125 Temperature C Figure 13. Offset at half scale vs. temperature 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis KL17 Microcontroller, Rev.4, 03/2015. 41 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 35. SPI master mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 Description Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 18 -- ns -- tHI Data hold time (inputs) 0 -- ns -- 8 tv Data valid (after SPSCK edge) -- 15 ns -- 9 tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input 11 tRO Rise time output -- 25 ns -- tFO Fall time output Frequency of operation SPSCK period Clock (SPSCK) high or low time 1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph Table 36. SPI master mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 tHI Description Min. Max. Unit Note fperiph/2048 fperiph/2 Hz 1 2 x tperiph 2048 x tperiph ns 2 Enable lead time 1/2 -- tSPSCK -- Enable lag time 1/2 -- tSPSCK -- tperiph - 30 1024 x tperiph ns -- Data setup time (inputs) 96 -- ns -- Data hold time (inputs) 0 -- ns -- Frequency of operation SPSCK period Clock (SPSCK) high or low time Table continues on the next page... 42 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 36. SPI master mode timing on slew rate enabled pads (continued) Num. Symbol 8 tv 9 Description Min. Max. Unit Note Data valid (after SPSCK edge) -- 52 ns -- tHO Data hold time (outputs) 0 -- ns -- 10 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input 11 tRO Rise time output -- 36 ns -- tFO Fall time output 1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2. tperiph = 1/fperiph SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 11 10 11 4 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 10 5 7 MSB IN2 BIT 6 . . . 1 LSB IN 8 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 9 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI master mode timing (CPHA = 0) Kinetis KL17 Microcontroller, Rev.4, 03/2015. 43 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 11 4 10 11 7 MSB IN2 BIT 6 . . . 1 LSB IN 9 8 MOSI (OUTPUT) 10 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 PORT DATA MASTER LSB OUT 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI master mode timing (CPHA = 1) Table 37. SPI slave mode timing on slew rate disabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead 4 tLag 5 tWSPSCK 6 tSU 7 Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 Enable lead time 1 -- tperiph -- Enable lag time 1 -- tperiph -- tperiph - 30 -- ns -- Data setup time (inputs) 2.5 -- ns -- tHI Data hold time (inputs) 3.5 -- ns -- 8 ta Slave access time -- tperiph ns 3 9 tdis Slave MISO disable time -- tperiph ns 4 10 tv Data valid (after SPSCK edge) -- 31 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 25 ns -- tFO Fall time output 13 1. 2. 3. 4. Description Frequency of operation SPSCK period Clock (SPSCK) high or low time For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state 38 44 Freescale Semiconductor, Inc. <<CLASSIFICATION>> <<NDA MESSAGE>> Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 38. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Frequency of operation SPSCK period Min. Max. Unit Note 0 fperiph/4 Hz 1 4 x tperiph -- ns 2 1 -- tperiph -- 1 -- tperiph -- tperiph - 30 -- ns -- Data setup time (inputs) 2 -- ns -- tHI Data hold time (inputs) 7 -- ns -- 8 ta Slave access time -- tperiph ns 3 9 tdis Slave MISO disable time -- tperiph ns 4 10 tv Data valid (after SPSCK edge) -- 122 ns -- 11 tHO Data hold time (outputs) 0 -- ns -- 12 tRI Rise time input -- tperiph - 25 ns -- tFI Fall time input tRO Rise time output -- 36 ns -- tFO Fall time output 13 1. 2. 3. 4. Description Clock (SPSCK) high or low time For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). tperiph = 1/fperiph Time to data active from high-impedance state Hold time to high-impedance state SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined Figure 16. SPI slave mode timing (CPHA = 0) Kinetis KL17 Microcontroller, Rev.4, 03/2015. 45 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 11 10 MISO (OUTPUT) 12 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 17. SPI slave mode timing (CPHA = 1) 3.8.2 I2C 3.8.2.1 Inter-Integrated Circuit Interface (I2C) timing Table 39. I2C timing Characteristic Symbol Standard Mode Fast Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 4001 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 -- 0.6 -- s LOW period of the SCL clock tLOW 4.7 -- 1.25 -- s HIGH period of the SCL clock tHIGH 4 -- 0.6 -- s Set-up time for a repeated START condition tSU; STA 4.7 -- 0.6 -- s Data hold time for I2C bus devices tHD; DAT 02 3.453 04 0.92 s tSU; DAT 2505 -- 1003, 6 Data set-up time Rise time of SDA and SCL signals tr -- 1000 -- ns 7 300 ns 6 20 +0.1Cb Fall time of SDA and SCL signals tf -- 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 -- 0.6 -- s Bus free time between STOP and START condition tBUF 4.7 -- 1.3 -- s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 46 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors 1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD 2.7 V. 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 7. Cb = total capacitance of the one bus line in pF. To achieve 1MHz I2C clock rates, consider the following recommendations: * To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate. * Use high drive pad and DSE bit should be set in PORTx_PCRn register. * Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching. * Use smaller pull up resistors on SDA and SCL to reduce the RC time constant. Table 40. I 2C 1Mbit/s timing Characteristic Symbol Minimum Maximum Unit MHz SCL Clock Frequency fSCL 0 11 Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 0.26 -- s LOW period of the SCL clock tLOW 0.5 -- s HIGH period of the SCL clock tHIGH 0.26 -- s Set-up time for a repeated START condition tSU; STA 0.26 -- s Data hold time for I2C bus devices tHD; DAT 0 -- s Data set-up time tSU; DAT 50 -- ns Rise time of SDA and SCL signals tr 20 +0.1Cb 120 ns Fall time of SDA and SCL signals tf 20 +0.1Cb 2 120 ns Set-up time for STOP condition tSU; STO 0.26 -- s Bus free time between STOP and START condition tBUF 0.5 -- s Pulse width of spikes that must be suppressed by the input filter tSP 0 50 ns 1. The maximum SCL Clock Frequency of 1Mbit/s can support maximum bus loading when using the High drive pins across the full voltage range. 2. Cb = total capacitance of the one bus line in pF. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 47 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 18. Timing definition for devices on the I2C bus 3.8.3 UART See General switching specifications. 3.8.4 I2S/SAI switching specifications This section provides the AC timing for the I2S/SAI module in master mode (clocks are driven) and slave mode (clocks are input). All timing is given for noninverted serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 3.8.4.1 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 41. I2S/SAI master mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 40 -- ns S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 15.5 ns Table continues on the next page... 48 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 41. I2S/SAI master mode timing (continued) Num. Characteristic Min. Max. Unit S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 19 ns S8 I2S_TX_BCLK to I2S_TXD invalid 0 -- ns S9 I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK 26 -- ns S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 19. I2S/SAI timing -- master modes Table 42. I2S/SAI slave mode timing Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 10 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 33 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 10 -- ns Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 49 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 42. I2S/SAI slave mode timing (continued) Num. S18 Characteristic Min. I2S_RXD hold after I2S_RX_BCLK S19 I2S_TX_FS input assertion to I2S_TXD output valid1 Max. Unit 2 -- ns -- 28 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 20. I2S/SAI timing -- slave modes 3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S1 I2S_MCLK cycle time 62.5 -- ns S2 I2S_MCLK pulse width high/low 45% 55% MCLK period S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 -- ns S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output valid -- 45 ns S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/ I2S_RX_FS output invalid 0 -- ns S7 I2S_TX_BCLK to I2S_TXD valid -- 45 ns Table continues on the next page... 50 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Peripheral operating requirements and behaviors Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic S8 I2S_TX_BCLK to I2S_TXD invalid S9 S10 Min. Unit -- ns I2S_RXD/I2S_RX_FS input setup before I2S_RX_BCLK -- ns I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 -- ns S1 0 Max. S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 21. I2S/SAI timing -- master modes Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.6 V S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 -- ns S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low (input) 45% 55% MCLK period S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 30 -- ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 -- ns S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid -- 87 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 -- ns S17 I2S_RXD setup before I2S_RX_BCLK 30 -- ns S18 I2S_RXD hold after I2S_RX_BCLK 2 -- ns -- 72 ns S19 I2S_TX_FS input assertion to I2S_TXD output Kinetis KL17 Microcontroller, Rev.4, 03/2015. valid1 51 Freescale Semiconductor, Inc. Dimensions 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 22. I2S/SAI timing -- slave modes 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing's document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00615D 48-pin QFN 98ASA00616D 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D 52 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Pinouts and Packaging 5 Pinouts and Packaging 5.1 KL17 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. NOTE It is prohibited to set VREFEN in 32 QFN pin package as 1.2 V on-chip voltage is not available in this package. 64 MAP BGA 48 QFN 32 64 QFN LQFP Pin Name Default ALT0 A1 -- 1 1 PTE0 DISABLED PTE0/ SPI1_MISO CLKOUT32K LPUART1_ TX B1 -- 2 2 PTE1 DISABLED PTE1 SPI1_MOSI LPUART1_ RX -- 1 -- 3 VDD VDD VDD C4 2 -- 4 VSS VSS VSS E1 3 3 5 PTE16 ADC0_DP1/ ADC0_SE1 ADC0_DP1/ ADC0_SE1 PTE16 SPI0_SS UART2_TX TPM_ CLKIN0 D1 4 4 6 PTE17 ADC0_DM1/ ADC0_DM1/ PTE17 ADC0_SE5a ADC0_SE5a SPI0_SCK UART2_RX TPM_ CLKIN1 LPTMR0_ ALT3 FXIO0_D1 E2 5 5 7 PTE18 ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO FXIO0_D2 D2 6 6 8 PTE19 ADC0_DM2/ ADC0_DM2/ PTE19 ADC0_SE6a ADC0_SE6a SPI0_MISO I2C0_SCL SPI0_MOSI FXIO0_D3 G1 7 -- 9 PTE20 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0 LPUART0_ TX FXI00_D4 F1 8 -- 10 PTE21 ADC0_DM0/ ADC0_DM0/ PTE21 ADC0_SE4a ADC0_SE4a TPM1_CH1 LPUART0_ RX FXIO0_D5 G2 -- -- 11 PTE22 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0 UART2_TX FXIO0_D6 F2 -- -- 12 PTE23 ADC0_DM3/ ADC0_DM3/ PTE23 ADC0_SE7a ADC0_SE7a TPM2_CH1 UART2_RX FXIO0_D7 F4 9 7 13 VDDA VDDA VDDA G4 10 -- 14 VREFH VREFH VREFH ADC0_DP2/ ADC0_SE2 ADC0_DP0/ ADC0_SE0 ADC0_DP3/ ADC0_SE3 Kinetis KL17 Microcontroller, Rev.4, 03/2015. ALT1 ALT2 ALT3 ALT4 RTC_ CLKOUT ALT5 ALT6 CMP0_OUT I2C1_SDA SPI1_MISO I2C1_SCL ALT7 FXI00_D0 53 Freescale Semiconductor, Inc. Pinouts and Packaging 64 MAP BGA 48 QFN 32 64 QFN LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 G3 11 -- 15 VREFL VREFL VREFL F3 12 8 16 VSSA VSSA VSSA H1 13 -- 17 PTE29 CMP0_IN5/ CMP0_IN5/ PTE29 ADC0_SE4b ADC0_SE4b TPM0_CH2 TPM_ CLKIN0 H2 14 9 18 PTE30 DAC0_OUT/ DAC0_OUT/ PTE30 ADC0_SE23/ ADC0_SE23/ CMP0_IN4 CMP0_IN4 TPM0_CH3 TPM_ CLKIN1 H3 -- -- 19 PTE31 DISABLED PTE31 TPM0_CH4 H4 15 -- 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL H5 16 -- 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA D3 17 10 22 PTA0 SWD_CLK PTA0 TPM0_CH5 D4 18 11 23 PTA1 DISABLED PTA1 LPUART0_ RX TPM2_CH0 E5 19 12 24 PTA2 DISABLED PTA2 LPUART0_ TX TPM2_CH1 D5 20 13 25 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO G5 21 14 26 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b F5 -- -- 27 PTA5 DISABLED PTA5 TPM0_CH2 I2S0_TX_ BCLK H6 -- -- 28 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0 G6 -- -- 29 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS G7 22 15 30 VDD VDD VDD H7 23 16 31 VSS VSS VSS H8 24 17 32 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_ RX TPM_ CLKIN0 G8 25 18 33 PTA19 XTAL0 XTAL0 PTA19 LPUART1_ TX TPM_ CLKIN1 F8 26 19 34 PTA20 RESET_b F7 27 20 35 PTB0/ LLWU_P5 ADC0_SE8 ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 ADC0_SE9 LPUART1_ TX LPTMR0_ ALT1 LPTMR0_ ALT1 PTA20 RESET_b F6 28 21 36 PTB1 ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 29 -- 37 PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 E8 30 -- 38 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 E6 31 -- 39 PTB16 DISABLED PTB16 SPI1_MOSI LPUART0_ RX TPM_ CLKIN0 SPI1_MISO D7 32 -- 40 PTB17 DISABLED PTB17 SPI1_MISO LPUART0_ TX TPM_ CLKIN1 SPI1_MOSI D6 -- -- 41 PTB18 DISABLED PTB18 TPM2_CH0 I2S0_TX_ BCLK C7 -- -- 42 PTB19 DISABLED PTB19 TPM2_CH1 I2S0_TX_FS D8 33 -- 43 PTC0 ADC0_SE14 ADC0_SE14 PTC0 EXTRG_IN audioUSB_ SOF_OUT Freescale Semiconductor, Inc. ALT7 SWD_CLK E7 54 ALT6 CMP0_OUT I2S0_TXD0 Kinetis KL17 Microcontroller, Rev.4, 03/2015. Pinouts and Packaging 64 MAP BGA 48 QFN 32 64 QFN LQFP Pin Name Default ALT0 ALT1 C6 34 22 44 PTC1/ ADC0_SE15 ADC0_SE15 PTC1/ I2C1_SCL LLWU_P6/ LLWU_P6/ RTC_CLKIN RTC_CLKIN TPM0_CH0 I2S0_TXD0 B7 35 23 45 PTC2 ADC0_SE11 ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS C8 36 24 46 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI1_SCK LPUART1_ RX TPM0_CH2 CLKOUT E3 -- -- 47 VSS VSS VSS E4 -- -- 48 VDD VDD VDD B8 37 25 49 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_SS LPUART1_ TX TPM0_CH3 I2S0_MCLK A8 38 26 50 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 A7 39 27 51 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSI EXTRG_IN I2S0_RX_ BCLK B6 40 28 52 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_MISO audioUSB_ SOF_OUT I2S0_RX_FS SPI0_MOSI A6 -- -- 53 PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2C0_SCL TPM0_CH4 I2S0_MCLK B5 -- -- 54 PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2C0_SDA TPM0_CH5 I2S0_RX_ BCLK B4 -- -- 55 PTC10 DISABLED PTC10 I2C1_SCL I2S0_RX_FS A5 -- -- 56 PTC11 DISABLED PTC11 I2C1_SDA I2S0_RXD0 C3 41 -- 57 PTD0 DISABLED PTD0 SPI0_SS TPM0_CH0 FXI00_D0 A4 42 -- 58 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 C2 43 -- 59 PTD2 DISABLED PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2 B3 44 -- 60 PTD3 DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3 A3 45 29 61 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_SS UART2_RX TPM0_CH4 FXI00_D4 C1 46 30 62 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5 B2 47 31 63 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSI LPUART0_ RX SPI1_MISO FXIO0_D6 A2 48 32 64 PTD7 DISABLED SPI1_MISO LPUART0_ TX SPI1_MOSI FXIO0_D7 C5 -- -- -- NC NC PTD7 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 I2S0_TX_ BCLK CMP0_OUT SPI0_MISO I2S0_MCLK NC 5.2 KL17 Family Pinouts Figure below shows the 32 QFN pinouts: Kinetis KL17 Microcontroller, Rev.4, 03/2015. 55 Freescale Semiconductor, Inc. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Pinouts and Packaging 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 PTA20 VDDA 7 18 PTA19 VSSA 8 17 PTA18 PTA0 PTE30 16 4 VSS PTE17 15 PTC1/LLWU_P6/RTC_CLKIN VDD 22 14 3 PTA4 PTE16 13 PTC2 PTA3 23 12 2 PTA2 PTE1 11 PTC3/LLWU_P7 PTA1 24 10 1 9 PTE0 Figure 23. 32 QFN Pinout diagram Figure below shows the 48 QFN pinouts: 56 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinouts and Packaging VDD 1 36 PTC3/LLWU_P7 VSS 2 35 PTC2 PTE16 3 34 PTC1/LLWU_P6/RTC_CLKIN PTE17 4 33 PTC0 PTE18 5 32 PTB17 PTE19 6 31 PTB16 PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 18 19 20 21 22 23 24 PTA2 PTA3 PTA4 VDD VSS PTA18 PTA19 PTA1 25 17 12 PTA0 VSSA 16 PTA20 PTE25 26 15 PTB0/LLWU_P5 PTE24 27 11 14 10 VREFL PTE30 PTB1 13 28 PTE29 9 VREFH Figure 24. 48 QFN Pinout diagram Figure below shows the 64 MAPBGA pinouts: Kinetis KL17 Microcontroller, Rev.4, 03/2015. 57 Freescale Semiconductor, Inc. Pinouts and Packaging 1 2 3 4 5 6 7 8 A PTE0 PTD7 PTD4/ LLWU_P14 PTD1 PTC11 PTC8 B PTE1 PTD6/ LLWU_P15 PTD3 PTC10 PTC9 PTC7 PTC2 C PTD5 PTD2 PTD0 VSS NC PTC1/ LLWU_P6/ RTC_CLKIN PTB19 PTC3/ LLWU_P7 C D PTE17 PTE19 PTA0 PTA1 PTA3 PTB18 PTB17 PTC0 D E PTE16 PTE18 VSS VDD PTA2 PTB16 PTB2 PTB3 E F PTE21 PTE23 VSSA VDDA PTA5 PTB1 PTB0/ LLWU_P5 PTA20 F G PTE20 PTE22 VREFL VREFH PTA4 PTA13 VDD PTA19 G H PTE29 PTE30 PTE31 PTE24 PTE25 PTA12 VSS PTA18 H 1 2 3 4 5 6 7 8 PTC6/ PTC5/ LLWU_P10 LLWU_P9 PTC4/ LLWU_P8 A B Figure 25. 64 MAPBGA Pinout diagram: Figure below shows the 64 LQFP pinouts: 58 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Ordering parts PTB18 PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 PTA20 VSSA 16 33 PTA19 PTA18 32 41 31 8 VSS PTE19 30 PTB19 VDD 42 29 7 PTA13 PTE18 28 PTC0 PTA12 43 27 6 PTA5 PTE17 26 PTC1/LLWU_P6/RTC_CLKIN PTA4 44 25 5 PTA3 PTE16 24 PTC2 PTA2 45 23 4 PTA1 VSS 22 PTC3/LLWU_P7 PTA0 46 21 3 PTE25 VDD 20 VSS PTE24 47 19 2 PTE31 PTE1 18 VDD PTE30 48 17 1 PTE29 PTE0 Figure 26. 64 LQFP Pinout diagram 6 Ordering parts Kinetis KL17 Microcontroller, Rev.4, 03/2015. 59 Freescale Semiconductor, Inc. Part identification 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the Web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: 7 Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 45. Part number fields descriptions Field Description Values Q Qualification status * M = Fully qualified, general market flow * P = Prequalification KL## Kinetis family * KL17 A Key attribute * Z = Cortex-M0+ FFF Program flash memory size R Silicon revision * (Blank) = Main * A = Revision after main T Temperature range (C) * V = -40 to 105 PP Package identifier * * * * FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) Table continues on the next page... 60 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Terminology and guidelines Table 45. Part number fields descriptions (continued) Field Description Values CC Maximum CPU frequency (MHz) * 4 = 48 MHz N Packaging type * R = Tape and reel 7.4 Example This is an example part number: MKL17Z256VMP4 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 61 Freescale Semiconductor, Inc. Terminology and guidelines 8.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit A 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. -- Max. 7 Unit pF 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: * Operating ratings apply during operation of the chip. * Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage 62 Freescale Semiconductor, Inc. Min. -0.3 Max. 1.2 Unit V Kinetis KL17 Microcontroller, Rev.4, 03/2015. Terminology and guidelines 8.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 8.6 Relationship between ratings and operating requirements .) ) g era Op g tin in rat ) in. (m in. t (m ax t (m n me g tin era Op e uir req en rem g( i g tin era Op u req g tin era Op in rat .) x ma Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure - Operating (power on) g lin nd Ha ng i rat .) ) in. (m ng li nd Ha i rat ng ax (m Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure - Handling (power off) 8.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: * Never exceed any of the chip's ratings. Kinetis KL17 Microcontroller, Rev.4, 03/2015. 63 Freescale Semiconductor, Inc. Terminology and guidelines * During normal operation, don't exceed any of the chip's operating requirements. * If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: * Lies within the range of values specified by the operating behavior * Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Description Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit A 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 64 Freescale Semiconductor, Inc. Kinetis KL17 Microcontroller, Rev.4, 03/2015. Revision History 5000 4500 4000 TJ IDD_STOP (A) 3500 150 C 3000 105 C 2500 25 C 2000 -40 C 1500 1000 500 0 0.95 0.90 1.00 1.05 1.10 VDD (V) 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Table 46. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 C VDD 3.3 V supply voltage 3.3 V 9 Revision History The following table provides a revision history for this document. Table 47. Revision History Rev. No. Date 3 09 August 2014 Substantial Changes Initial Public release * Updated Table 9 - Power consumption operating behaviors. * Added a note related to 32 QFN pin package in Pinouts topic. Table continues on the next page... Kinetis KL17 Microcontroller, Rev.4, 03/2015. 65 Freescale Semiconductor, Inc. Revision History Table 47. Revision History (continued) Rev. No. Date 4 03 March 2015 66 Freescale Semiconductor, Inc. Substantial Changes * Updated the features and completed the ordering information. * Removed thickness dimension from package diagrams. * Updated Related Resources table to include Chip Errata resource name and Package Drawing part numbers in the respective rows. Also updated Product Brief resource references. * Updated Table 7. Voltage and current operating behaviors. * Specified correct max. value for IIN. * Updated Table - 9 Power consumption operating behaviors. * Rows added for IDD for reset pin hold low (IDD_RESET_LOW) at 1.7V and 3V. * Measurement unit updated for IDD_VLLS1 from nA to A. * Footnote 1 was moved in the beginning of the table as text. * Added Table - 11 EMC radiated emissions operating behaviors for 64-pin LQFP package under section 2.2.6. * Updated Table - 18 (IRC48M specification) and Table - 19 (IRC8M/2M specification) under section 3.3.1 - 'MCG-Lite specifications'. * Removed supply voltage (VDD), temperature range (T), untrimmed (fIRC_UT), trim function (fIRC_C, fIRC_F) data from Table - 18 (IRC48M specification). * Removed supply voltage (VDD), temperature range (T) data from Table - 19 (IRC8M/2M specification). * Added Figure 6. IRC8M Frequency Drift vs Temperature curve after Table - 19 (IRC8M/2M specification). * Updated Table 29. VREF full-range operating behaviors. * Removed Ac(Aging coefficient) row. * Added Tchop_osc_stup parameter. * Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I2C. * Added VREF specifications (VREFH and VREFL) to Table 26. 16-bit ADC operating conditions. * Removed note: "This device does not have the USB_CLKIN signal available." Kinetis KL17 Microcontroller, Rev.4, 03/2015. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, Energy Efficient Solutions logo, and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. (c)2014-2015 Freescale Semiconductor, Inc. Document Number KL17P64M48SF6 Revision 4, 03/2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Freescale Semiconductor: MKL27Z256VFT4 MKL27Z256VMP4 MKL27Z256VFM4 MKL27Z256VLH4 MKL17Z256VLH4 MKL17Z256VFT4 MKL17Z256VMP4 MKL17Z256VFM4 MKL33Z256VMP4 MKL33Z256VLH4 MKL43Z256VMP4 MKL43Z256VLH4