Product Brief
November 1999
ORCA
® OR3LxxxB Series
Field-Programmable Gate Arrays
Features
■High-performance, cost-effective, 0.25 µm 5-level
metal techno logy.
■2.5 V internal supply voltage and 3.3 V I/O supply
voltage for speed and compatibility.
■Up to 340,000 usable gates in 0.25 µm.
■Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os
are 5 V tolerant to allow interconnection to both
3.3 V and 5 V devices, selectable on a per-pin
basis, when using 3.3 V I/O supply.)
■Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables (LUTs)
per PFU , organized in two nibb les f or use in nibble-
or byte-wide functions. Allows for mixed arithmetic
and logic functions in a single PFU.
■Nine user registers per PFU, one following each
LUT, plus one extra. All have programmable clock
enable and local set/reset, plus a global set/reset
(GSRN) that can be disabled per PFU.
■Fle xible Input Structure (FINS) of the PFUs pro-
vides a routability enhancement for LUTs with
shared inputs and the logic flexibility of LUTs with
independent inputs.
■Fast-carry logic and routing to adjacent PFUs for
nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
■Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
■Suppleme ntal logi c and int erco nne ct cel l (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and
PAL
*-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell (PLC).
■Abundant hierarchi c al routi ng res ou rces base d o n
routing two data nibbles and two control lines per
set provide for faster place and route implementa-
tions and less routing delay.
■Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source.
■Built-in boundary scan (
IEEE
†1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
■Enhanced system clock routing for low-skew, high-
speed clocks originating on-chip or at any I/O.
■Up to four ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to
internal general clock routing.
■StopCLK feature to glitchlessly stop/start the
ExpressCLKs independently by user command.
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL
-like
functions.
— Output FF and two-signal function generator to
reduce CLK to ou tput pr opa gati on del ay.
■Fast open-drain drive capability.
■New
programmable I/O 3-state FF allows 3-state
buffer control signals to be set up a clock cycle
early f or improved clock to output delays
*
PAL
is a trademark of Adv anced Micro Devices, Inc.
†
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
‡The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU) , and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM
(or 512 gates) per PFU.
Table 1. Lucent Technologies’
ORCA
OR3LxxxB Series FPGAs
Device System
Gates‡LUTs Registers Max User
RAM User I/Os Array Size Process
Technology
OR3L165B 120K—244K 8192 10752 131K 516 32 x 32 0.25 µm/5 LM
OR3L225B 166K—340K 11552 14820 185K 612 38 x 38 0.25 µm/5 LM