AD7537JPZ-REEL - ANALOG DEVICES

FUNCTIONAL BLOCK DIAGRAM

REV.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

MOS

(8+4) Loading Dual 12-Bit DAC

AD7537

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: Fax:

FEATURES

Two 12-Bit DACs in One Package

DAC Ladder Resistance Matching: 0.5%

Space Saving Skinny DIP and Surface Mount Packages

4-Quadrant Multiplication

Low Gain Error (1 LSB max Over Temperature)

Byte Loading Structure

Fast Interface Timing

APPLICATIONS

Automatic Test Equipment

Programmable Filters

Audio Applications

Synchro Applications

Process Control

GENERAL DESCRIPTION

The AD7537 contains two 12-bit current output DACs on one

monolithic chip. A separate reference input is provided for each

DAC. The dual DAC saves valuable board space, and the

monolithic construction ensures excellent thermal tracking.

Both DACs are guaranteed 12-bit monotonic over the full tem-

perature range.

The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.

It is designed for right-justified data format. The control signals

for register loading are A0, A1, CS,WR and UPD. Data is

loaded to the input registers when CS and WR are low. To

transfer this data to the DAC registers, UPD must be taken low

with WR.

Added features on the AD7537 include an asynchronous CLR

line which is very useful in calibration routines. When this is

taken low, all registers are cleared. The double buffering of the

data inputs allows simultaneous update of both DACs. Also,

each DAC has a separate AGND line. This increases the device

versatility; for instance one DAC may be operated with

AGND biased while the other is connected in the standard

configuration.

The AD7537 is manufactured using the Linear Compatible

CMOS (LC

MOS) process. It is speed compatible with most

microprocessors and accepts TTL, 74HC and 5 V CMOS logic

level inputs.

PRODUCT HIGHLIGHTS

1. DAC to DAC Matching:

Since both DACs are fabricated on the same chip, precise

matching and tracking is inherent. Many applications which

are not practical using two discrete DACs are now possible.

Typical matching: 0.5%.

2. Small Package Size:

The AD7537 is packaged in small 24-pin 0.3" DIPs and in

28-terminal surface mount packages.

3. Wide Power Supply Tolerance:

The device operates on a +12 V to +15 V V

, with ±10%

tolerance on this nominal figure. All specifications are

guaranteed over this range.

781/329-4700 781/461-3113

REV.

–2–

AD7537–SPECIFICATIONS

(VDD = +12 V to +15 V, ⴞ10%, VREFA = VREFB = 10 V; IOUTA = AGND = 0 V,

IOUTB = AGNDB = 0 V. All specifications TMIN to TMAX unless otherwise noted.)

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for Design Guidance only and are not subject to test.

(VDD = +12 V to +15 V; VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)

Parameter T

= +25ⴗCT

= T

MIN

, T

MAX

Units Test Conditions/Comments

Output Current Settling Time 1.5 μs max To 0.01% of full-scale range. I

OUT

load = 100 Ω, C

EXT

= 13 pF.

DAC output measured from falling edge of WR.

Typical Value of Settling Time is 0.8 μs.

Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with V

REFA

= V

REFB

= 0 V. I

OUTA

, I

OUTB

load = 100 Ω,

EXT

= 13 pF. DAC registers alternately loaded with all 0s and all 1s.

AC Feedthrough

REFA

to I

OUTA

–70 –65 dB max V

REFA

, V

REFB

= 20 V p-p 10 kHz sine wave.

REFB

to I

OUTB

–70 –65 dB max DAC registers loaded with all 0s.

Power Supply Rejection

ΔGain/ΔV

±0.01 ±0.02 % per % max ΔV

= V

max – V

min

Output Capacitance

OUTA

70 70 pF max DAC A, DAC B loaded with all 0s

OUTB

70 70 pF max

OUTA

140 140 pF max DAC A, DAC B loaded with all 1s

OUTB

140 140 pF max

Channel-to-Channel Isolation

REFA

to I

OUTB

–84 dB typ V

REFA

= 20 V p-p 10 kHz sine wave, V

REFB

= 0 V.

Both DACs loaded with all 1s.

REFB

to I

OUTA

–84 dB typ V

REFB

= 20 V p-p 10 kHz sine wave, V

REFA

= 0 V.

Both DACs loaded with all 1s.

Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s.

OUTA

, I

OUTB

load = 100 Ω, C

EXT

= 13 pF.

Output Noise Voltage Density 25 nV/√Hz typ Measured between R

FBA

and I

OUTA

or R

FBB

and I

OUTB.

(10 Hz–100 kHz) Frequency of measurement is 10 Hz–100 kHz.

Total Harmonic Distortion –82 dB typ V

= 6 V rms, 1 kHz. Both DACs loaded with all 1s.

NOTES

Temperature range as follows: J, K, L Versions: –40°C to +85°C;

A, B, C Versions: –40°C to +85°C;

S, T, U Versions: –55°C to +125°C

Specifications subject to change without notice.

Sample tested at +25°C to ensure compliance.

Functional at V

= 5 V, with degraded specifications.

Pin 12 (DGND) on ceramic DIPs is connected to lid.

J, A K, B L, C S T U

Parameter Versions Versions Versions Version Version Version Units Test Conditions/Comments

ACCURACY

Resolution 12 12 12 12 12 12 Bits

Relative Accuracy ±1±1/2 ±1/2 ±1±1/2 ±1/2 LSB max

Differential Nonlinearity ±1±1±1±1±1±1 LSB max All grades guaranteed mono-

tonic over temperature.

Gain Error ±6±3±1±6±3±2 LSB max Measured using R

FBA

, R

FBB

Both DAC registers loaded

with all 1s.

Gain Temperature Coefficient

;

ΔGain/ΔTemperature ±5±5±5±5±5±5 ppm/°C max Typical value is 1 ppm/°C

Output Leakage Current

OUTA

+25°C 10 10 10 10 10 10 nA max DAC A Register loaded

MIN

to T

MAX

150 150 150 250 250 250 nA max with all 0s

OUTB

+25°C 10 10 10 10 10 10 nA max DAC B Register loaded

MIN

to T

MAX

150 150 150 250 250 250 nA max with all 0s

REFERENCE INPUT

Input Resistance 999999kΩ min Typical Input Resistance = 14 kΩ

20 20 20 20 20 20 kΩ max

REFA

, V

REFB

Input Resistance Match ±3±3±1±3±3±1 % max Typically ±0.5%

DIGITAL INPUTS

(lnput High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min

IIL

(Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max

(Input Current)

+25°C±1±1±1±1±1±1μA max V

= V

MIN

to T

MAX

±10 ±10 ±10 ±10 ±10 ±10 μA max

(lnput Capacitance)

10 10 10 10 10 10 pF max

POWER SUPPLY

10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max

222222mA max

AD7537

REV. –3–

TIMING CHARACTERISTICS

Limit at Limit at

Limit at T

= –40ⴗCT

= +55ⴗC

Parameter T

= +25ⴗC to +85ⴗC to +125ⴗC Units Test Conditions/Comments

15 15 30 ns min Address Valid to Write Setup Time

15 15 25 ns min Address Valid to Write Hold Time

60 80 80 ns min Data Setup Time

25 25 25 ns min Data Hold Time

0 0 0 ns min Chip Select or Update to Write Setup Time

0 0 0 ns min Chip Select or Update to Write Hold Time

80 80 100 ns min Write Pulse Width

80 80 100 ns min Clear Pulse Width

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

= +25°C unless otherwise stated)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V

REFA

, V

REFB

to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V

RFBA

, V

RFBB

to AGNDA, AGNDB . . . . . . . . . . . . . . . . ±25 V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

+0.3 V

OUTA

, I

OUTB

to DGND . . . . . . . . . . . . . . –0.3 V, V

+0.3 V

AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, V

+0.3 V

Power Dissipation (Any Package)

To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW

Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature Range

Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C

Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C

Extended Hermetic (S, T, U Versions) . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7537 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

Figure 1. Timing Diagram

(VDD = +10.8 V to +16.5 V, VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V.)

AD7537

REV.

–4–

PIN FUNCTION DESCRIPTION

PIN MNEMONIC DESCRIPTION

1 AGNDA Analog Ground for DAC A.

OUTA

Current output terminal of DAC A.

FBA

Feedback resistor for DAC A.

REFA

Reference input to DAC A.

5CS Chip Select Input Active low.

6–14 DB0–DB7 Eight data inputs, DB0–DB7.

12 DGND Digital Ground.

15 A0 Address Line 0.

16 A1 Address Line 1.

17 CLR Clear Input. Active low. Clears all

registers.

18 WR Write Input. Active low.

19 UPD Updates DAC Registers from inputs

registers.

20 V

Power supply input. Nominally +12 V

to +15 V, with ±10% tolerance.

21 V

REFB

Reference input to DAC B.

22 R

FBB

Feedback resistor for DAC B.

23 I

OUTB

Current output terminal of DAC B.

24 AGNDB Analog Ground for DAC B.

PLCC

PIN CONFIGURATIONS

CIRCUIT INFORMATION – D/A SECTION

The AD7537 contains two identical 12-bit multiplying D/A

converters. Each DAC consists of a highly stable R-2R ladder

and 12 N-channel current steering switches. Figure 2 shows a

simplified D/A circuit for DAC A. In the R-2R ladder, binary

weighted currents are steered between I

OUTA

and AGNDA. The

current flowing in each ladder leg is constant, irrespective of

switch state. The feedback resistor R

FBA

is used with an op amp

(see Figures 4 and 5) to convert the current flowing in I

OUTA

a voltage output.

Figure 2. Simplified Circuit Diagram for DAC A

EQUIVALENT CIRCUIT ANALYSIS

Figure 3 shows the equivalent circuit for one of the D/A con-

verters (DAC A) in the AD7537. A similar equivalent circuit

can be drawn for DAC B.

OUT

is the output capacitance due to the N-channel switches

and varies from about 50 pF to 150 pF with digital input code.

The current source I

LKG

is composed of surface and junction

leakages and approximately doubles every 10°C. R

is the

equivalent output resistance of the device which varies with

input code.

DIGITAL CIRCUIT INFORMATION

The digital inputs are designed to be both TTL and 5 V CMOS

compatible. All logic inputs are static protected MOS gates with

typical input currents of less than 1 nA.

Table I. AD7537 Truth Table

CLR UPD CS WR A1 A0 FUNCTION

1 1 1 X X X No Data Transfer

1 1 X 1 X X No Data Transfer

0 X X X X X All Registers Cleared

1 1 0 0 0 0 DAC A LS Input Register

Loaded with DB7–DB0 (LSB)

1 1 0 0 0 1 DAC A MS Input Register

Loaded with DB3 (MSB)–DB0

1 1 0 0 1 0 DAC B LS Input Register

Loaded with DB7–DB0 (LSB)

1 1 0 0 1 1 DAC B MS Input Register

Loaded with DB3 (MSB)–DB0

1 0 1 0 X X DAC A, DAC B Registers

Updated Simultaneously from

Input Registers

1 0 0 0 X X DAC A, DAC B Registers are

Transparent

NOTES: X = Don’t care

Figure 3. Equivalent Analog Circuit for DAC A

PDIP and SOIC

(PDIP)

AD7537

REV. –5–

UNIPOLAR BINARY OPERATION

(2-QUADRANT MULTIPLICATION)

Figure 4 shows the circuit diagram for unipolar binary opera-

tion. With an ac input, the circuit performs 2-quadrant multipli-

cation. The code table for Figure 4 is given in Table II.

Operational amplifiers A1 and A2 can be in a single package

(AD644, AD712) or separate packages (AD544, AD711,

AD OP27). Capacitors C1 and C2 provide phase compensation

to help prevent overshoot and ringing when high-speed op amps

are used.

For zero offset adjustment, the appropriate DAC register is

loaded with all 0s and amplifier offset adjusted so that V

OUTA

OUTB

is 0 V. Full-scale trimming is accomplished by loading

the DAC register with all 1s and adjusting R1 (R3) so that

OUTA

OUTB

) = –V

(4095/4096). For high temperature op-

eration, resistors and potentiometers should have a low Tem-

perature Coefficient. In many applications, because of the

excellent Gain T.C. and Gain Error specifications of the

AD7537, Gain Error trimming is not necessary. In fixed refer-

ence applications, full scale can also be adjusted by omitting R1,

R2, R3, R4 and trimming the reference voltage magnitude.

Figure 4. AD7537 Unipolar Binary Operation

Table II. Unipolar Binary Code Table for

Circuit of Figure 4

Binary Number in

DAC Register Analog Output,

MSB LSB V

OUTA

or V

OUTB

1111 1111 1111

−V

4095

4096

⎛

⎝

⎜⎞

⎠

⎟

1000 0000 0000

−V

2048

4096

⎛

⎝

⎜⎞

⎠

⎟=−

0000 0000 0001

−V

4096

⎛

⎝

⎜⎞

⎠

⎟

0000 0000 0000 0 V

BIPOLAR OPERATION

(4-QUADRANT MULTIPLICATION)

The recommended circuit diagram for bipolar operation is

shown in Figure 5. Offset binary coding is used.

With the appropriate DAC register loaded to 1000 0000 0000,

adjust R1 (R3) so that V

OUTA

OUTB

) = 0 V. Alternatively, R1,

R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)

varied for V

OUTA

OUTB

) = 0 V. Full-scale trimming can be ac-

complished by adjusting the amplitude of V

or by varying the

value of R5 (R8).

If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,

R9, R10) should be ratio matched to 0.01% to ensure gain error

performance to the data sheet specification. When operating

over a wide temperature range, it is important that the resistors

be of the same type so that their temperature coefficients match.

The code table for Figure 5 is given in Table III.

Figure 5. Bipolar Operation (Offset Binary Coding)

Table III. Bipolar Code Table for Offset Binary

Circuit of Figure 5

Binary Number in

DAC Register Analog Output,

MSB LSB V

OUTA

or V

OUTB

1111 1111 1111

2047

2048

⎛

⎝

⎜⎞

⎠

⎟

1000 0000 0001

2048

⎛

⎝

⎜⎞

⎠

⎟

1000 0000 0000 0 V

0111 1111 1111

−V

2048

⎛

⎝

⎜⎞

⎠

⎟

0000 0000 0000

−V

2048

⎛

⎝

⎜⎞

⎠

⎟=−V

Applications–

AD7537

REV.

–6–

SEPARATE AGND PINS

The DACs in the AD7537 have separate AGND lines taken to

pins AGNDA and AGNDB on the package. This increases the

applications versatility of the part. Figure 6 is an example of

this. DAC A is connected in standard fashion as a program-

mable attenuator. AGNDA is at ground potential. DAC B is op-

erating with AGND B biased to +5 V by the AD584. This gives

an output range of +5 V to +10 V.

Figure 6. AD7537 DACs Used in Different Modes

PROGRAMMABLE OSCILLATOR

Figure 7 shows a conventional state variable oscillator in which

the AD7537 controls the programmable integrators. The fre-

quency of oscillation is given by:

f=1

2πR6

R5×1

C1×C2×REQ1×REQ2

where R

EQ1

and R

EQ2

are the equivalent resistances of the

DACs. The same digital code is loaded into both DACs.

If C1 = C2 and R5 = R6, the expression reduces to

f=1

2π×1

REQ1×REQ2

Since

×R

LAD

, (R

LAD

= DAC ladder resistance).

f=1

2π×1

C(N/2

)

LAD1

×R

LAD2

2π×D

LAD1

×R

LAD2

D=N

⎛

⎝

⎜⎞

⎠

⎟

2π×D

C×R

LAD m

where m is the DAC ladder resistance mismatch ratio, typically

1.005.

With the values shown in Figure 7, the output frequency varies

from 0 Hz to 1.38 kHz. The amplitude of the output signal at

the A3 output is 10 V peak-to-peak and is constant over the

entire frequency span.

Figure 7. Programmable State Variable Oscillator

AD7537

REV. –7–

APPLICATION HINTS

Output Offset: CMOS D/A converters in circuits such as Fig-

ures 4 and 5 exhibit a code dependent output resistance which

in turn can cause a code dependent error voltage at the output

of the amplifier. The maximum amplitude of this error, which

adds to the D/A converter nonlinearity, depends on V

, where

is the amplifier input offset voltage. To maintain specified

operation, it is recommended that V

be no greater than

(25 ⫻ 10

–6

) (V

REF

) over the temperature range of operation.

Suitable op amps are the AD711C and its dual version, the

AD712C. These op amps have a wide bandwidth and high slew

rate and are recommended for wide bandwidth ac applications.

AD711/AD712 settling time to 0.01% is typically 3 μs.

Temperature Coefficients: The gain temperature coefficient

of the AD7537 has a maximum value of 5 ppm/°C and typical

value of 1 ppm/°C. This corresponds to worst case gain shifts of

2 LSBs and 0.4 LSBs respectively over a 100°C temperature

range. When trim resistors R1 (R3) and R2 (R4) are used to ad-

just full scale range as in Figure 4, the temperature coefficient of

R1 (R3) and R2 (R4) should also be taken into account. For

further information see “Gain Error and Gain Temperature Co-

efficient of CMOS Multiplying DACs”, Application Note, Pub-

lication Number E630c-5-3/86 available from Analog Devices.

High Frequency Considerations: AD7537 output capaci-

tance works in conjunction with the amplifier feedback resis-

tance to add a pole to the open loop response. This can cause

ringing or oscillation. Stability can be restored by adding a

phase compensation capacitor in parallel with the feedback re-

sistor. This is shown as C1 and C2 in Figures 4 and 5.

Feedthrough: The dynamic performance of the AD7537 de-

pends upon the gain and phase stability of the output amplifier,

together with the optimum choice of PC board layout and de-

coupling components. A suggested printed circuit layout for

Figure 4 is shown in Figure 8 which minimizes feedthrough

from V

REFA

, V

REFB

to the output in multiplying applications.

Figure 8. Suggested Layout for AD7537

MICROPROCESSOR INTERFACING

The byte loading structure of the AD7537 makes it very easy to

interface the device to any 8-bit microprocessor system. Figures

9 and 10 show two interfaces: one for the MC6809 and the

other for the MC68008. Figure 11 shows how an AD7537 sys-

tem can be easily expanded by tying all the UPD lines together

and using a single decoder output to control these. This ex-

panded system is shown using a Z80 microprocessor but it is

just as easily configured using any other 8-bit microprocessor

system. Note how the system shown in Figure 11 produces 4

analog outputs with a minimum amount of hardware.

Figure 9. AD7537–MC6809 Interface

Figure 10. AD7537–MC68008 Interface

Figure 11. Expanded AD7537 System

AD7537

–8– REV. A

OUTLINE DIMENSIONS

Figure 12. 24-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-24-1)

Dimensions shown in inches and (millimeters)

Figure 16. 28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28)

Dimensions shown in inches and (millimeters)

CONTROL LI N G DIME NS IONS ARE IN INCHES ; MIL LIME TER DIMENSIO NS

(IN PARENTHESES) ARE ROUNDED-OFF I NCH E Q U IVALENT S FO R

REF ERENCE ONLY AND ARE NOT APPROP RIATE FO R USE IN DESI GN.

CORN E R LEA DS MAY BE CONFI GURED AS W HOL E O R HA LF LEADS.

COMPLIA NT T O JED EC STANDARDS MS-001

071006-A

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.15 0 ( 3.81)

0.13 0 ( 3.30)

0.115 (2.92)

0.07 0 ( 1.78)

0.06 0 ( 1.52)

0.04 5 ( 1.14)

112

0.10 0 ( 2.54)

BSC

1.280 (32.51)

1.250 (31.75)

1.230 (31.24)

0.210 (5.33)

MAX

SEATING

PLANE

0.015

(0.38)

MIN

0.005 (0.13)

MIN

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.06 0 ( 1.52)

MAX

0.430 (10.92)

MAX

0.01 4 ( 0.36)

0.01 0 ( 0.25)

0.00 8 ( 0.20)

0.32 5 (8.26)

0.31 0 (7.87)

0.30 0 (7.62)

0.01 5 ( 0.38)

GAUGE

PLANE

0.19 5 ( 4.95)

0.13 0 ( 3.30)

0.115 (2.92)

COM P LIANT TO JED E C ST AN DARD S MO-047-AB

CON T RO LL ING DI M E NS IO NS ARE I N INCHE S ; M I L LIME T E R DIME NS I ONS

(IN PARENTHESES) ARE ROUNDED-OF F INCH EQUIVALENTS FO R

REF E RE NCE ONL Y AND ARE NO T AP P RO P RIAT E F OR USE I N DE SIG N.

526

1112 19

TOP VIEW

(PI N S DOWN )

0.456 (11.582)

0.450 (11.430)

0.050

(1.27)

BSC

0.04 8 (1.2 2)

0.04 2 (1.0 7)

0.048 (1.22)

0.042 (1.07)

0.495 (12. 57)

0.485 (12. 32)SQ

0.021 (0.53)

0.013 (0.33) 0.430 (10.92)

0.390 (9.91)

0.03 2 ( 0.81)

0.02 6 ( 0.66)

0.120 (3.04)

0.090 (2.29)

0.056 (1.42)

0.042 (1.07) 0.020 (0.51)

MIN

0.180 (4.57)

0.165 (4.19)

BOTTOM

VIEW

(PINS UP)

0.045 (1.14)

0.025 (0.64) R

PIN 1

IDENTIFIER

042508-A

AD7537

REV. A –9–

Figure 17. 24-Lead Standard Small Outline Package [SOIC-W]

Wide Body

(RW-24)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model1, 2, 3 Temperature Range Relative Accuracy Gain Error Package Description Package Option

AD7537JN –40°C to +85°C ±1 LSB ±6 LSB 24-Lead PDIP N-24-1

AD7537JNZ –40°C to +85°C ±1 LSB ±6 LSB 24-Lead PDIP N-24-1

AD7537KN –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead PDIP N-24-1

AD7537KNZ –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead PDIP N-24-1

AD7537LNZ –40°C to +85°C ±1/2 LSB ±1 LSB 24-Lead PDIP N-24-1

AD7537JP –40°C to +85°C ±1 LSB ±6 LSB 28-Lead PLCC P-28

AD7537JP-REEL –40°C to +85°C ±1 LSB ±6 LSB 28-Lead PLCC P-28

AD7537JPZ –40°C to +85°C ±1 LSB ±6 LSB 28-Lead PLCC P-28

AD7537JPZ-REEL –40°C to +85°C ±1 LSB ±6 LSB 28-Lead PLCC P-28

AD7537KP –40°C to +85°C ±1/2 LSB ±3 LSB 28-Lead PLCC P-28

AD7537KPZ –40°C to +85°C ±1/2 LSB ±3 LSB 28-Lead PLCC P-28

AD7537KPZ-REEL –40°C to +85°C ±1/2 LSB ±3 LSB 28-Lead PLCC P-28

AD7537LP-REEL –40°C to +85°C ±1/2 LSB ±1 LSB 28-Lead PLCC P-28

AD7537LPZ –40°C to +85°C ±1/2 LSB ±1 LSB 28-Lead PLCC P-28

AD7537LPZ-REEL –40°C to +85°C ±1/2 LSB ±1 LSB 28-Lead PLCC P-28

AD7537JR –40°C to +85°C ±1 LSB ±6 LSB 24-Lead SOIC_W RW-24

AD7537JR-REEL –40°C to +85°C ±1 LSB ±6 LSB 24-Lead SOIC_W RW-24

AD7537JRZ –40°C to +85°C ±1 LSB ±6 LSB 24-Lead SOIC_W RW-24

AD7537JRZ-REEL –40°C to +85°C ±1 LSB ±6 LSB 24-Lead SOIC_W RW-24

AD7537KRZ –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead SOIC_W RW-24

AD7537KR-REEL –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead SOIC_W RW-24

AD7537BR –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead SOIC_W RW-24

AD7537BR-REEL –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead SOIC_W RW-24

AD7537BRZ –40°C to +85°C ±1/2 LSB ±3 LSB 24-Lead SOIC_W RW-24

1 Z = RoHS Compliant Part.

2 Analog Devices reserves the right to ship side-brazed CERDIP packages (D-24-1) in lieu of CERDIP packages (Q-24-1).

3 To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet.

COMPLIANT TO JEDEC STANDARDS MS-013-AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

15.60 (0.6142)

15.20 (0.5984)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75(0.0295)

0.25(0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10 0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

8°

0°

24 13

1.27 (0.0500)

BSC

12-09-2010-A

AD7537

–10– REV. A

REVISION HISTORY

6/12—Rev. 0 to Rev. A

Added SOIC Package ......................................................... Universal

Removed LCCC Pin Configuration ................................................ 4

Updated Outline Dimensions .......................................................... 8

Changes to Ordering Guide ............................................................. 9

10/87—Revision 0: Initial Version

registered trademarks are the property of their respective owners.

D01138-0-6/12(A)