LM1971M/NOPB - NATIONAL SEMICONDUCTOR

LM1971

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LM1971 Overture™ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator

with/Mute

Check for Samples: LM1971

1FEATURES DESCRIPTION

The LM1971 is a digitally controlled single channel

23• 3-Wire Serial Interface audio attenuator fabricated on a CMOS process.

• Mute Function Attenuation is variable in 1 dB steps from 0 dB to −62

• Click and Pop Free Attenuation Changes dB. A mute function disconnects the input from the

output, providing over 100 dB of attenuation.

• 8-Pin Plastic PDIP and SOIC Packages

Available The performance of the device is exhibited by its

ability to change attenuation levels without audible

APPLICATIONS clicks or pops. In addition, the LM1971 features a low

Total Harmonic Distortion (THD) of 0.0008%, and a

• Communication Systems Dynamic Range of 115 dB, making it suitable for

• Cellular Phones and Pagers digital audio needs. The LM1971 is available in both

• Personal Computer Audio Control 8-pin plastic PDIP or SOIC packages.

• Electronic Music (MIDI) The LM1971 is controlled by a TTL/CMOS compatible

3-wire serial digital interface. The active low LOAD

• Sound Reinforcement Systems line enables the data input registers while the CLOCK

• Audio Mixing Automation line provides system timing. Its DATA pin receives

serial data on the rising edge of each CLOCK pulse,

KEY SPECIFICATIONS allowing the desired attenuation setting to be

selected.

• Total Harmonic Distortion 0.0008 % (Typ)

• Frequency Response > 200 kHz (−3 dB) (Typ)

• Attenuation Range (Excluding Mute) 62 dB

(Typ)

• Dynamic Range 115 dB (Typ)

• Mute Attenuation 102 dB (Typ)

Typical Application

Figure 1. Typical Audio Attenuator Application Circuit

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Overture is a trademark of dcl_owner.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM1971

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Connection Diagram

Figure 2. Dual-In-Line Plastic or Surface Mount Package- Top View

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)(3)

Supply Voltage, VDD 15V

Voltage at any pin (GND −0.2V) to (VDD +0.2V)

ESD Susceptibility(4) 3000V

Soldering Information P Package (10s) 260°C

D Package Vapor Phase (60s) 215°C

Infrared (15s) 220°C

Power Dissipation(5) 150 mW

Junction Temperature 150°C

Storage Temperature −65°C to +150°C

(1) All voltages are measured with respect to the GND pin (pin 3), unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) Human body model, 100 pF discharged through a 1.5 kΩresistor.

(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature

TA. The maximum allowable power dissipation is PD= (TJMAX – TA)/θJA or the number given in the Absolute Maximum Ratings,

whichever is lower. For the LM1971N and LM1971M, TJMAX = +150°C, and the typical junction-to-ambient thermal resistance, θJA, when

board mounted is 102° C/W and 167° C/W, respectively.

Operating Ratings(1)(2)

Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C

D0008A Package, θJA 167°C/W

Thermal Resistance P0008E Package, θJA 102°C/W

Supply Voltage 4.5V to 12V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(2) All voltages are measured with respect to the GND pin (pin 3), unless otherwise specified.

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Electrical Characteristics (1)(2)

The following specifications apply for VDD = +12V (VREFIN = +6V), VIN = 5.5 Vpk, and f = 1 kHz, unless otherwse specified.

Limits apply for TA= 25°C. Digital inputs are TTL and CMOS compatible. LM1971 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

ISSupply Current Digital Inputs Tied to 6V 1.8 3 mA (max)

THD Total Harmonic Distortion VIN = 0.5Vpk@ 0 dB Attenuation 0.0008 0.003 % (max)

eIN Noise Input is AC Grounded @ −12 dB 4.0 μV

Attenuation

A-Weighted(5)

DR Dynamic Range Referenced to Full Scale = +6 Vpk 115 dB

AMMute Attenuation 102 96 dB (min)

Attenuation Step Size Error 0 dB to −62 dB 0.009 0.2 dB (max)

Absolute Attenuation Attenuation @ 0 dB 0.1 0.5 dB (min)

Attenuation @ −20 dB −20.3 −19.0 dB (min)

Attenuation @ −40 dB −40.5 −38.0 dB (min)

Attenuation @ −60 dB −60.6 −57.0 dB (min)

Attenuation @ −62 dB −62.6 −59.0 dB (min)

ILEAK Analog Input Leakage Current Input is AC Grounded 5.8 100 nA (max)

Frequency Response 20 Hz–100 kHz ±0.1 dB

RIN AC Input Impedance Pin 8, VIN = 1.0 Vpk, f = 1 kHz 40 20 kΩ(min)

60 kΩ(max)

IIN Input Current @ Pins 4, 5, 6 @ 0V < VIN < 5V 1.0 100 nA (max)

fCLK Clock Frequency 3 2 MHz (max)

VIH High-Level Input Voltage @ Pins 4, 5, 6 2.0 V (min)

VIL Low-Level Input Voltage @ Pins 4, 5, 6 0.8 V (max)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(2) All voltages are measured with respect to the GND pin (pin 3), unless otherwise specified.

(3) Typicals are measured at 25°C and represent the parametric norm.

(4) Limits are specifications that all parts are tested in production to meet the stated values.

(5) Due to production test limitations, there is no limit for the Noise test. Please refer to Figure 5 and Figure 8 in Typical Performance

Characteristics.

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Pin Descriptions

VREFIN (1): The VREFIN pin provides the reference for the analog input signal. This pin should be biased at half of

the supply voltage, VDD, as shown in Figure 1 and Figure 19.

OUT (2): The attenuated analog output signal comes from this pin.

GND (3): The GND pin references the digital input signals and is the lower voltage reference for the IC.

Typically this pin would be labeled “VSS” but the ground reference for the digital logic input control is tied to

this same point. With a higher pin-count there would generally be separate pins for these functions; VSS

and Logic Ground. It is intended that the LM1971 always be operated using a single voltage supply

configuration, for which pin 3 (GND) should always be at system ground. If a bipolar or split-supply

configuration are desired, level shifting circuitry is needed for the digital logic control pins as they would be

referenced through pin 3 which would be at the negative supply. It is highly recommended, however, that

the LM1971 be used in a unipolar or single-supply configuration.

LOAD (4): The LOAD input accepts a TTL or CMOS level signal. This is the enable pin of the device, allowing

data to be clocked in while this input is low (0V). The GND pin is the reference for this signal.

DATA (5): The DATA input accepts a TTL or CMOS level signal. This pin is used to accept serial data from a

microcontroller that will be latched and decoded to change the channel's attenuation level. The GND pin is

the reference for this signal.

CLOCK (6): The CLOCK input accepts a TTL or CMOS level signal. The clock input is used to load data into the

internal shift register on the rising edge of the input clock waveform. The GND pin is the reference for this

signal.

VDD (7): The positive voltage supply should be placed to this pin.

IN (8): The analog input signal should be placed to this pin.

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Typical Performance Characteristics

Supply Current vs Supply Current vs

Supply Voltage Temperature

Figure 3. Figure 4.

THD + N

Noise Floor vs

Analog Measurement Freq and Amp

Figure 5. Figure 6.

THD + N

Freq and Amp Noise Floor Spectrum by FFT

Figure 7. Figure 8.

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Typical Performance Characteristics (continued)

THD + N THD + N

vs vs

Amplitude Amplitude

Figure 9. Figure 10.

THD

Mute Attenuation vs

vs Frequency Freq by FFT

Figure 11. Figure 12.

THD

vs Output Impedance vs

Freq by FFT Attenuation Level

Figure 13. Figure 14.

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APPLICATION INFORMATION

SERIAL DATA FORMAT

The LM1971 uses a 3-wire serial communication format that is easily controlled by a microcontroller. The timing

for the 3-wire set, comprised of DATA, CLOCK, and LOAD is shown in Figure 15. As depicted in Figure 15, the

LOAD line is to go low at least 150 ns before the rising edge of the first clock pulse and is to remain low

throughout the transmission of the 16 data bits. The serial data is composed of an 8-bit address, which must

always be set to 0000 0000 to select the single audio channel, and 8 bits for attenuation setting. For both

address data and attenuation setting data, the MSB is sent first with the address data preceding the attenuation

data. Please refer to Figure 16 to confirm the serial data format transfer process.

Table 1 shows the various Address and Data byte values for different attenuation settings. Note that Address

bytes other than 0000 0000 are ignored.

μPOT SYSTEM ARCHITECTURE

The μPot's digital interface is essentially a shift register where serial data is shifted in, latched, and then

decoded. Once new data is shifted in, the LOAD line goes high, latching in the new data. The data is then

decoded and the appropriate switch is activated to set the desired attenuation level. This process is continued

each and every time an attenuation change is made. When the µPot is powered up, it is placed into the Mute

mode.

μPOT DIGITAL COMPATIBILITY

The μPot's digital interface section is compatible with TTL or CMOS logic. The shift register inputs act upon a

threshold of two diode drops above the ground level (Pin 3) or approximately 1.4V.

Table 1. Attenuator Register Set Description

Address Register (Byte 0)

MSB LSB

A7–A0

0000 0000 Channel 1

0000 0001 Ignored

0000 0010 Ignored

Data Register (Byte 1)

Contents Attenuation (dB)

MSB LSB

D7–D0

0000 0000 0.0

0000 0001 1.0

0000 0010 2.0

0000 0011 3.0

::::: ::

0001 0000 16.0

0001 0001 17.0

0001 0010 18.0

0001 0011 19.0

::::: ::

0011 1101 61.0

0011 1110 62.0

0011 1111 96 (Mute)

0100 0000 96 (Mute)

::::: ::

1111 1110 96 (Mute)

1111 1111 96 (Mute)

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*Note: Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than

20 ns from the falling edge of load. It is preferrable that the falling edge of clock occurs before the falling edge of load.

Figure 15. Timing Diagram

Figure 16. Serial Data Format Transfer Process

μPOT LADDER ARCHITECTURE

The μPot contains a chain of R1/R2 resistor dividers in a ladder form, as shown in Figure 17. Each R1 is actually

a series of 8 resistors, with a CMOS switch that taps into the resistor chain according to the attenuation level

chosen. For any given attenuation setting, there is only one CMOS switch closed (no paralleling of ladders). The

input impedance therefore remains constant, while the output impedance changes as the attenuation level

changes. It is important to note that the architecture is a series of resistor dividers, and not a straight, tapped

resistor, so the μPot is not a variable resistor; it is a variable voltage divider.

Figure 17. Resistor Ladder Architecture

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ATTENUATION STEP SCHEME

The fundamental attenuation step scheme for the LM1971 is shown in Figure 18. It is also possible to obtain any

integer value attenuation step through programming, in addition to the 2 dB and 4 dB steps shown in Figure 18.

All higher attenuation step schemes can have clickless and popless performance. Although it is possible to “skip”

attenuation points by not sending all of the data, clickless and popless performance will suffer. It is highly

recommended that all of the data points should be sent for each attenuation level. This ensures flawless

operation and performance when making steps larger than 1 dB.

Figure 18. LM 1971 Channel Attenuation

vs Digital Step Value

(1 dB, 2 dB, and 4 dB Steps)

INPUT IMPEDANCE

The input impedance of a μPot is constant at a nominal 40 kΩ. Since the LM1971 is a single-supply operating

device, it is necessary to have both input and output coupling caps as shown in Figure 1. To ensure full low-

frequency response, a 1 μF coupling cap should be used.

OUTPUT IMPEDANCE

The output impedance of a μPot varies typically between 25 kΩand 35 kΩand changes nonlinearly with step

changes. Since a μPot is made up of a resistor ladder network with logarithmic attenuation, the output

impedance is nonlinear. Due to this configuration, a μPot cannot be considered as a linear potentiometer; it is a

logarithmic attenuator.

The linearity of a μPot cannot be measured directly without a buffer because the input impedance of most

measurement systems is not high enough to provide the required accuracy. The lower impedance of the

measurement system would load down the output and an incorrect reading would result. To prevent loading, a

JFET input op amp should be used as the buffer/amplifier.

OUTPUT BUFFERING

There are two performance issues to be aware of that are related to a μPot's output stage. The first concern is to

prevent audible clicks with attenuation changes, while the second is to prevent loading and subsequent linearity

errors. The output stage of a μPot needs to be buffered with a low input bias current op amp to keep DC shifts

inaudible. Additionally, the output of μPot needs to see a high impedance to keep linearity errors low.

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Attenuation level changes cause changes in the output impedance of a μPot. Output impedance changes in the

presence of a large input bias current for a buffer/amplifier will cause a DC shift to occur. Neglecting amplifier

gains and speaker sensitivities, the audibility of a DC shift is dependent upon the output impedance change

times the required input bias current. As an example, a 5 kΩimpedance change times a 1 μA bias current results

in a 5 mV DC shift; a level that is barely audible without any music material in the system. An op amp with a bias

current of 200 pA for the same 5 kΩchange results in an inaudible 1 μV DC shift. Since the worst case output

impedance changes are on the order of several kΩ, a bias current much less than 1 μA is required for highest

performance. In order to further quantify DC shifts, please refer to Figure 14 in Typical Performance

Characteristics and relate worst case impedance changes to the selected buffer/amplifier input bias current.

Without the use of a high input impedance (> 1 MΩ) op amp for the buffer/amplifier, loading will occur that

causes linearity errors in the signal. To ensure the highest level of performance, a JFET or CMOS input high

input impedance op amp is required.

One common application that requires gain at the output of a μPot is input signal volume control. Depending

upon the input source material, the LM1971 provides a means of controlling the input signal level. With a supply

voltage range of 4.5V to 12V, the LM1971 has the ability of controlling fairly inconsistent input source signal

levels. Using an op amp with gain at the μPot's output, as shown in Figure 20, will also allow the system dynamic

range to be increased. JFET op amps like the LF351 and the LF411 are well suited for this application. If active

half-supply buffering is also desired, dual op amps like the LF353 and the LF412 could be used.

For low voltage supply applications, op amps like the CMOS LMC6041 are preferred. This part has a supply

operating range from 4.5V–15.5V and also comes in a surface mount package.

μPOT HALF-SUPPLY REFERENCING

The LM1971 operates off of a single supply, with half-supply biasing supplied at the VREFIN terminal (Pin 1). The

easiest and most cost effective method of providing this half-supply is a simple resistor divider and bypass

capacitor network shown in Figure 1. The capacitor not only stabilizes the half-supply node by “holding” the

voltage nearly constant, but also decouples high frequency signals on the supply to ground. Signal feedthrough,

power supply ripple and fluctuations that are not properly filtered could cause the performance of the LM1971 to

be degraded.

A more stable half-supply node can be obtained by actively buffering the resistor divider network with a voltage

follower as shown in Figure 19. Supply fluctuations are then isolated by the high input impedance/low output

impedance mismatch associated with effective filtering. Since the LM1971 is a single channel device, using a

dual JFET input op amp is optimum for both output buffering and half-supply biasing.

A 10 μF capacitor or larger is recommended for better half-supply stabilization. For added rejection of higher

frequency power supply fluctuations, a smaller capacitor (0.01 μF–0.1 μF) could be added in parallel to the 10 μF

capacitor.

Figure 19. Higher Performance

Active Half-Supply Buffering

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Figure 20. Active Reference with Active Gain Buffering

LOGARITHMIC GAIN AMPLIFIER

The μPot is capable of being used in the feedback loop of an op amp to create a gain controlled amplifier as

shown in Figure 21. In this configuration the attenuation levels from Table 1 become gain levels with the largest

possible gain value being 62 dB. For most applications, 62 dB of gain will cause signal clipping to occur.

However, this can be controlled through programming. It is important to note that when in mute mode the input is

disconnected from the output, thus placing the amplifier in open-loop gain state. In this mode, the amplifier will

behave as a comparator. Care should be taken with the programming and design of this type of circuit. To

provide the best overall performance, a high input impedance, low input bias current op amp should be used.

Figure 21. Logarithmic Gain Amplifier Circuit

MUTE FUNCTION

A major feature of the LM1971 is its ability to mute the input signal to an attenuation level of 102 dB. This is

accomplished internally by physically disconnecting the output from the input while also grounding the output pin

through approximately 2 kΩ.

The mute function is obtained during power-up of the device or by sending any binary data of 0011 1111 and

above serially to the device. The device may be placed into mute at any time during operation, allowing the

designer to make the mute command accessible to the end-user.

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DC INPUTS

Although the μPot was designed to be used as an attenuator for signals within the audio spectrum, it is also

capable of tracking and attenuating an input DC voltage. The device will track voltages to either supply rail.

One point to remember about DC tracking is that with a buffer at the output of the μPot, the resolution of DC

tracking will depend upon the gain configuration of that output buffer and its supply voltage. Also, the output

buffer's supply voltage does not have to be the same as the μPot's supply voltage. Giving the buffer some gain

can provide more resolution when tracking small DC voltages.

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REVISION HISTORY

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM1971M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM19

71M

LM1971M/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM19

71M

LM1971MX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM19

71M

LM1971MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM19

71M

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM1971MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM1971MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Oct-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM1971MX SOIC D 8 2500 367.0 367.0 35.0

LM1971MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Oct-2013

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

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