TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer Transceiver Check for Samples: TLK110 1 Introduction 1.1 Features 1 * Low Power Consumption: <205mW PHY and 275mW with Center Tap (Typical) * Cable Diagnostics * Programmable Fast Link Down Modes, <10s reaction time * Fixed TX Clock to XI, with programmable phase shift * 3.3V MAC Interface * Auto-MDIX for 10/100Mbs * Energy Detection Mode * 25 MHz Clock Out * MII and RMII Interfaces * Serial Management Interface * IEEE 802.3u MII * IEEE 802.3u Auto-Negotiation and Parallel Detection * IEEE 802.3u ENDEC, 10Base-T Transceivers and Filters * IEEE 802.3u PCS, 100Base-TX Transceivers 1.3 * IEEE 1149.1 JTAG * Error-Free Operation up to 150 Meters Under Typical Conditions * Integrated ANSI X3.263 Compliant TP-PMD Physical Sublayer with Adaptive Equalization and Baseline Wander Compensation * Programmable LED Support Link, 10/100Mbs Mode, Activity, and Collision Detect * 10/100Mbs Packet BIST (Built in Self Test) * Bus I/O Protection - 16kV JEDEC HBM * Enable implementation of IEEE1588 Time Stamping at the MAC * 48-pin LQFP Package (7mm) x (7mm) * HBM ESD protection on RD and TD of 16kV 1.2 * * * Applications Industrial Networks and Factory Automation Motor and Motion Control General Embedded Applications Device Overview The TLK110 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. It integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. This device supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC). The TLK110 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V and 1.5V power supplies for reduced power operation. The TLK110 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. It not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com MII Option RMII Option MII/RMII Interface Figure 1-1. TLK110 Functional Block Diagram 2 Introduction Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 1 2 3 4 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 .............................................. 1 ............................................. 1 1.2 Applications .......................................... 1 1.3 Device Overview ..................................... 1 Pin Descriptions ......................................... 4 2.1 Pin Layout ........................................... 4 2.2 Serial Management Interface (SMI) ................. 5 2.3 MAC Data Interface .................................. 5 2.4 10Mbs and 100Mbs PMD Interface .................. 6 2.5 Clock Interface ....................................... 6 2.6 LED Interface ........................................ 6 2.7 JTAG Interface ....................................... 7 2.8 Reset and Power Down ............................. 7 2.9 Power and Bias Connections ........................ 7 Hardware Configuration ............................... 8 3.1 Bootstrap Configuration .............................. 9 3.2 Power Supply Configuration ........................ 10 3.3 IO Pins Hi-Z State During Reset ................... 12 3.4 Auto-Negotiation .................................... 12 3.5 Auto-MDIX .......................................... 13 3.6 MII Isolate Mode .................................... 13 3.7 PHY Address ....................................... 14 3.8 Software Strapping Mode .......................... 14 3.9 LED Interface ....................................... 16 3.10 Loopback Functionality ............................. 17 3.11 BIST ................................................ 18 3.12 Cable Diagnostics .................................. 19 Interfaces ................................................ 20 4.1 Media Independent Interface (MII) ................. 20 4.2 Reduced Media Independent Interface (RMII) ..... 20 4.3 Serial Management Interface ....................... 23 Architecture ............................................. 27 Introduction 5 1.1 ......................... ......................... 5.3 10Base-T Receive Path ............................ 5.4 Auto MDI/MDI-X Crossover ........................ 5.5 Auto Negotiation .................................... 5.6 Link Down Functionality ............................ 6 Reset and Power Down Operation ................. 6.1 Hardware Reset .................................... 6.2 Software Reset ..................................... 6.3 Power Down/Interrupt .............................. 6.4 Power Save Modes ................................. 7 Design Guidelines ..................................... 7.1 TPI Network Circuit ................................. 7.2 Clock In (XI) Requirements ......................... 7.3 Thermal Vias Recommendation .................... 8 Register Block ......................................... 8.1 Register Definition .................................. 8.2 Extended Register Addressing ..................... 8.3 Extended Registers ................................. 8.4 Cable Diagnostic Registers ......................... 8.5 Cable Diagnostic Configuration/Result Registers .. 9 Electrical Specifications ............................. 9.1 ABSOLUTE MAXIMUM RATINGS ................. 9.2 THERMAL CHARACTERISTICS ................... 9.3 RECOMMENDED OPERATING CONDITIONS .... 9.4 DC CHARACTERISTICS ........................... 9.5 POWER SUPPLY CHARACTERISTICS ........... 9.6 AC Specifications ................................... Revision History ............................................ Features 5.1 100Base-TX Transmit Path 27 5.2 100Base-TX Receive Path 30 Contents Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 32 33 34 37 38 38 38 38 39 40 40 40 42 43 48 62 63 72 74 80 80 80 80 81 82 83 99 3 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 2 Pin Descriptions The TLK110 pins are classified into the following interface categories (each interface is described in the sections that follow): * Serial Management Interface * MAC Data Interface * Clock Interface * LED Interface * JTAG Interface * Reset and Power Down * Bootstrap Configuration Inputs * 10/100Mbs PMD Interface * Special Connect Pins * Power and Ground pins Note: Configuration pin option. See Section 3.1 for Jumper Definitions. The definitions below define the functionality of each pin. Input Type: O Output Type: I/O Input/Output Type: OD Open Drain Type: PD, PU Internal Pulldown/Pullup Type: S Configuration Pin (All configuration pins have weak internal pullups or pulldowns. If a different default value is needed, then use an external 2.2k resistor. See Section 3.1 for details.) MDIO RESETN LED_LINK/AN0 LED_SPEED/AN1 LED_ACT/COL/AN_EN CLKOUT 33 VDD33_IO 34 MDC 35 XI IOGND 36 XO DGND Pin Layout 32 31 30 29 28 27 26 25 PFBIN2 37 2 4 RBIAS RX_CLK 38 2 3 PFBOUT RX_DV/MII_MODE 39 2 2 AVDD33 CRS/CRS_DV/LED_CFG 40 2 1 SW_STRAPN RX_ER/MDIX_EN 41 2 0 RESERVED COL/PHYAD0 42 1 9 AGND RXD_0/PHYAD 1 43 RXD_1/PHYAD2 TLK110 1 4 RD+ VDD33_IO 48 1 3 RD- 2 3 TXD_0 1 4 5 6 7 8 9 10 11 12 JTAG_TDI 47 JTAG_TRSTN AGND IOGND JTAG_TMS TD- 1 5 JTAG_TDO 1 6 46 JTAG_TCK 45 RXD_3/PHYAD 4 PWR_DWN / INTN RXD_2/PHYAD 3 TXD_2 TD+ TXD_3 1 7 TXD_1 PFBIN1 44 TX_EN 1 8 TX_CLK 2.1 Type: I Figure 2-1. TLK110 PIN DIAGRAM, TOP VIEW 4 Pin Descriptions Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 2.2 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Serial Management Interface (SMI) PIN NAME NO. TYPE DESCRIPTION MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The maximum MDC rate is 25 MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the MII_TX_CLK or the MII_RX_CLK. MDC 31 I MDIO 30 I/O 2.3 MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local controller or the TLK110 may drive the MDIO signal. This pin requires a pull-up resistor with value 1.5 k. MAC Data Interface PIN NAME TX_CLK NO. 1 TYPE DESCRIPTION O, PD MII TRANSMIT CLOCK: : MII Transmit Clock provides 25MHz or 2.5MHz reference clock depending on the speed. Note that in MII mode, this clock has constant phase referenced to REF_CLK. This may be used by application requried such constant phase. Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and receive. TX_EN 2 I, PD TRANSMIT ENABLE: MII_TX_EN is presented on the rising edge of the MII_TX_CLK . It indicates the presence of valid data inputs on MII_TXD[3:0] in MII mode, and on TXD [1:0] in the RMII mode. It is an active high signal. TXD_0 TXD_1 TXD_2 TXD_3 3 4 5 6 I, PD TRANSMIT DATA: In MII mode, it is the transmit data nibble received from the MAC that is synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] is received from MAC that is synchronous to 50MHz reference clock on XI. RX_CLK 38 O RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz reference clock, depending on the speed, that is derived from the received data stream. RX_DV 39 S, O, PD RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode or on RXD [1:0] for RMII mode, independently from Carrier Sense. 41 RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to S, O, PU RX_CLK and in RMII mode, synchronously to XI This pin is not required to be used by the MAC, in either MII or RMII, since the PHY is corrupting data on a receive error. RX_ER/MDIX_EN RXD_0/PHYAD1 RXD_1/PHYAD2 RXD_2/PHYAD3 RXD_3/PHYAD4 43 44 45 46 RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0] is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode. S, O, PD PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0 (LSB of the address) is multiplexed with COL on pin 42, and is pulled up. If no external pullup/pulldown is present, the default address is 0x01. CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle. CRS/LED_CFG 40 S, O, PU COL/PHYAD0 42 COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10BaseS, O, PU T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and receive media are non-idle. This pin is not used in RMII mode. CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications. Pin Descriptions Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 5 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 2.4 www.ti.com 10Mbs and 100Mbs PMD Interface PIN NAME NO. TYPE DESCRIPTION Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10Base-T or 100Base-TX signaling. TD-, TD+ 16, 17 I/O In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100Base-TX or 10Base-T signaling. RD-, RD+ 13, 14 I/O In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3V bias for operation. 2.5 Clock Interface PIN NAME NO. TYPE DESCRIPTION CRYSTAL/OSCILLATOR INPUT: XI 34 MII reference clock Reference clock. 25MHz 50ppm-tolerance crystal reference or oscillator input. The TLK110 supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator source connected to pin XI only. I RMII reference clock Primary clock reference input for the RMII mode. It must be connected to a 50MHz 50ppm-tolerance CMOS-level oscillator source. XO 33 O CRYSTAL OUTPUT: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when an oscillator input is connected to XI. CLKOUT 25 O CLOCK OUTPUT: In MII mode, this pin provides a 25 MHz clock output to the system. In RMII mode, this pin provides a 50MHz clock output. This allows other devices to use the reference clock from the TLK110 without requiring additional clock sources. 2.6 LED Interface (See Table 3-3 for LED Mode Selection) PIN NAME NO . TYPE DESCRIPTION LED Pin to indicate status. LED_LINK/AN_0 LED_SPEED/AN_1 28 27 Mode 1 LINK Indication LED; indicates the status of the link. When the link is good, the LED will be ON. Mode 2 and Mode 3 ACT indication LED and indicates transmit and receive activity in addition to the status of the Link. The LED is ON when Link is good. It will blink when the transmitter or receiver is active. S, O, PU S, O, PU LED Pin to indicate the speed of the link. SPEED Indication LED indicates whether the link is 100Mb/s or 10Mb/s. It is ON when the link speed is 100Mbs and OFF when it is 10Mbs. LED Pin to indicate status. LED_ACT/AN_EN 6 26 Mode 1 ACT indication LED, and indicates if there is any activity on the link. It is ON (pulse) when activity is present on either Transmit or Receive channel. Mode 2 COL indication LED, and indicates collision detection. Mode 3 may be programmed to DUPLEX Indication LED and indicates Full-duplex status. S, O, PU Pin Descriptions Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 2.7 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 JTAG Interface PIN NAME NO. TYPE DESCRIPTION JTAG_TCK 8 I, PU JTAG Test Clock: This pin has a weak internal pullup. JTAG_TDI 12 I, PU JTAG Test Data Input: This pin has a weak internal pullup. JTAG_TDO 9 O JTAG_TMS 10 I, PU JTAG Test Mode Select: This pin has a weak internal pullup. JTAG_TRSTN 11 I, PU JTAG Reset: This pin is an active low asynchronous test reset. This pin has a weak internal pullup. 2.8 JTAG Test Data Output Reset and Power Down PIN NAME TYPE NO. RESETN 29 I, PU DESCRIPTION This pin is an active-low reset input that initializes or re-initializes all the internal registers of the TLK110. Asserting this pin low for at least 1 s will force a reset process to occur. All jumper options are reinitialized as well. . Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down. PWR_DNN/INT 7 I, OD, PU When this pin is configured for a power down function, an active low signal on this pin places the device in power down mode. When this pin is configured as an interrupt pin then this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pull-up. Some applications may require an external pull-up resistor. 2.9 Power and Bias Connections PIN NAME NO. TYPE DESCRIPTION RBIAS 24 I Bias Resistor Connection. Use a 4.87k 1% resistor connected from RBIAS to GND. PFBOUT 23 O Power Feedback Output. 10f and 0.1F capacitors (ceramic preferred), should be placed close to PFBOUT. In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1 for proper placement In multiple supply operation, this pin is not used. PFBIN1 18 PFBIN2 37 Power Feedback Input. These pins are fed with power from PFBOUT (pin 23) in single supply operation. I In multiple supply operation a 1.5V external power should be connected to these pins. A small capacitor of 0.1F should be connected close to each pin. The internal linear regulator is powered down by writing to register 0x00d0. VDD33_IO 32, 48 P I/O 3.3V Supply IOGND 35, 47 P I/O ground DGND 36 P Digital ground AVDD33 22 P Analog 3.3V power supply 15, 19 P Analog ground 20 I/O AGND RESERVED RESERVED: This pin must be pulled-up through 2.2 k resistor to AVDD33 supply Pin Descriptions Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 7 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 3 Hardware Configuration This section includes information on the various configuration options available with the TLK110. The configuration options described below include: * Bootstrap Configuration * Power Supply Configuration * IO Pins Hi-Z State During Reset * Auto-Negotiation * Auto-MDIX * MII Isolate mode * PHY Address * Software Strapping Mode * LED Interface * Loopback Functionality * BIST * Cable Diagnostics 8 Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 3.1 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Bootstrap Configuration Bootstrap configuration is a convenient way to configure the TLK110 into specific modes of operation. Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. The table below describes bootstrap configuration. A 2.2k resistor is used for pull-down or pull-up to change the default configuration. If the default option is desired, then there is no need for external pull-up or pull down resistors. Because these pins may have alternate functions after reset is deasserted, they must not be connected directly to VCC or GND. PIN NAME PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 (COL) (RXD_0) (RXD_1) (RXD_2) (RXD_3) SW_STRAPN TYPE NO. DESCRIPTION 42 43 44 45 46 S, O, PD PHY Address [4:0]: The TLK110 provides five PHY address pins, the states of which are latched into an internal register at system hardware reset. The TLK110 supports PHY Address values 0 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal pull-down resistors, and PHYAD[0] has weak internal pull-up resistor, setting the default PHYAD if no external resistors are connected. I Software Strapping Mode: The TLK110 provides a mechanism to extend the number of configuration pins to allow wider system programmability of PHY functions. An external pull-down will cause the device to enter SW Strapping Mode. In this mode the device will wake up after Power-up/Reset in Power-Down mode, this will allow the system processor to access dedicated Strapping Registers and configure modes of operation. An access to SW Strapping Mode Release register must be done to take the device out of power-down mode. See Section 3.8 for more details. An external pull-up resistor should be used to disable Software Strapping Mode. 21 AN_EN: When high, this puts the part into advertised Auto-Negotiation mode with the capability set by AN_0 and AN_1 pins. When low, this puts the part into Forced Mode with the capability set by AN_0 and AN_1 pins. AN_0 / AN_1: These input pins control the forced or advertised operating mode of the TLK110 according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 k resistors. DO NOT connect these pins directly to GND or VCC. The status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 since these pins have internal pull-ups. AN_EN (LED_ACT) AN_1 (LED_SPEED) AN_0 (LED_LINK) 26 27 28 S, O, PU AN_EN AN_1 AN_0 0 0 0 10Base-T, Half-Duplex Forced Mode 0 0 1 10Base-T, Full-Duplex 0 1 0 100Base-TX, Half-Duplex 0 1 1 100Base-TX, Full-Duplex AN_EN AN_1 AN_0 1 0 0 10Base-T, Half/Full-Duplex 1 0 1 100Base-TX, Half/Full-Duplex 1 1 0 10Base-T, Half-Duplex 100Base-TX, Half-Duplex 1 1 1 10Base-T, Half/Full-Duplex 100Base-TX, Half/Full-Duplex Advertised Mode LED_CFG (CRS) 40 S, O, PU This option, along with the LEDCR register bit, selects the mode of operation of the LED pins. Default is Mode 1. All modes are also configurable via register access. See the table in the LED Interface Section. MDIX_EN (RX_ER) 41 S, O, PU This option sets the Auto-MDIX mode. By default, it enables MDIX. An external pull-down disables Auto-MDIX mode. MII_MODE (RX_DV) 39 S, O, PD MII Mode Select: This option selects the operating mode of the MAC data interface. This pin has a weak internal pull-down, and it defaults to normal MII operation mode. An external pull-up causes the device to operate in RMII mode. Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 9 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.2 www.ti.com Power Supply Configuration The TLK110 provides best-in-class flexibility of power supplies. 3.2.1 Single Supply Operation If a single 3.3V power supply is desired, the internal regulator of TLK110 is used to provide the necessary core supply voltages. Ceramic capacitors of 10f and 0.1f should be placed close to the PFBOUT (pin 23) which is the output of the internal regulator. The PFBOUT pin should be connected to the PFBIN1 and PFBIN2 on the board. A small capacitor of 0.1F should be placed close to the PFBIN1 (pin 18) and PFBIN2 (pin 37). To operate in this mode the TLK110 supply pins should be connected as shown in Figure 3-1 3.3V Supply 3.3V Supply Pin 13 (RD-) Pin 22 (AVDD33) 49.9W 3.3V Supply 1:1 0.1mF 49.9W 0.1F 0.1F Pin 14 (RD+) Pin 18 (PFBIN1) Pin 23 (PFBOUT) 10F Pin 37 (PFBIN2) TLK110 RD - RD + 0.1mF* Pin 16 (TD-) 49.9W TD - 3.3V Supply TD + 0.1mF* 0.1F 1:1 49.9W T1 RJ45 0.1mF* Pin 17 (TD+) 3.3V Supply Pin 32 (VDD33_IO) Pin 48 (VDD33_IO) Figure 3-1. Power Connections for Single Supply Operation 10 Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 3.2.2 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Dual Supply Operation When a 1.5V external power rail is available, the TLK110 can be configured as shown in Figure 3-2. PFBOUT (pin 23) is left floating. The 1.5V external supply is connected to PFBIN1 (pin 18) and PFBIN2 (pin 37). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing `1' to bit 15 of the VRCR register (0x00d0h). 3.3V Supply 3.3V Supply Pin 22 (AVDD33) Pin 13 (RD-) 49.9 W Floating 3.3V Supply 1:1 Pin 23 (PFBOUT) 0.1mF RD- 49.9 W Pin 14 (RD+) 1.5V Supply Pin 18 (PFBIN1) Pin 37 (PFBIN2) RD+ 0.1mF* Pin 16 (TD-) TLK 110 49.9 W TD- 3.3V Supply TD+ 0.1mF* 1:1 T1 RJ45 0.1mF 49.9 W Pin 17 (TD+) 3.3V Supply Pin 32 (VDD33_IO) Pin 48 (VDD33_IO) Figure 3-2. Power Connections for Dual Supply Operation When operating with multiple supplies, it is recommended that the 3.3V supply ramps up at least 200ms before the 1.5V supply ramps up. In power down it required to shut down 1.5V supply at least 10ms before the shutting down 3.3V supply. Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 11 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.3 www.ti.com IO Pins Hi-Z State During Reset The following IO or output pins are in hi-Z state when RESETN is active (Low). Type Internal PU/PD MII_TXD_3 IO PD MII_TX_EN IO PD PWRDNN IO PU LED_ACT IO PU LED_SPEED IO PU LED_LINK IO PU MDIO IO MII_RX_DV IO PD MII_CRS IO PU MII_RX_ER IO PU MII_COL IO PU MII_RXD_0 IO PD MII_RXD_1 IO PD MII_RXD_2 IO PD MII_RXD_3 IO PD MII_TX_CLK O CLK25MHZ_OUT O MII_RX_CLK O Pin Name 3.4 Auto-Negotiation The TLK110 device can auto-negotiate to operate in 10Base-T or 100Base-TX. If Auto-Negotiation is enabled, the TLK110 negotiates with the link partner to determine the speed and duplex mode with which to operate. If the link partner is unable to Auto-Negotiate, the TLK110 device goes into parallel-detect mode to determine the speed of the link partner. Under parallel-detect mode, the duplex mode is fixed at half-duplex. The TLK110 supports four different Ethernet protocols (10Mbs Half-Duplex, 10Mbs Full-Duplex, 100Mbs Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the highest performance protocol based on the advertised ability of the Link Partner. The Auto-Negotiation function within the TLK110 can be controlled either by internal register access or by configuring the AN_EN, AN_1 and AN_0 pins. The state of the AN_EN, AN_0 and AN_1 pins determine whether the TLK110 is forced into a specific mode, or if Auto-Negotiation advertises a specific ability (or set of abilities) as given in Table 3-1. These pins allow configuration options to be selected without requiring internal register access. The state of AN_EN, AN_0 and AN_1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register (0x04h). Table 3-1. Auto-Negotiation Modes 12 AN_EN AN_1 AN_0 0 0 0 10Base-T, Half-Duplex 0 0 1 10Base-T, Full-Duplex 0 1 0 100Base-TX, Half-Duplex 100Base-TX, Full-Duplex 0 1 1 AN_EN AN_1 AN_0 1 0 0 Forced Mode Advertised Mode 10Base-T, Half/Full-Duplex Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 3-1. Auto-Negotiation Modes (continued) AN_EN AN_1 AN_0 1 0 1 Forced Mode 100Base-TX, Half/Full-Duplex 1 1 0 10Base-T, Half Duplex 100Base-TX, Half Duplex 1 1 1 10Base-T, Half/Full-Duplex 100Base-TX, Half/Full-Duplex The Auto-Negotiation function can also be controlled by internal register access using registers as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u specification. 3.5 Auto-MDIX The TLK110 device automatically determines whether or not it needs to cross over between pairs so that an external crossover cable is not required. If the TLK110 interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which device performs the crossover. Auto-MDIX is enabled by default and can be configured via jumper, SW Strap register SWSCR1 (0x09h), bit 14 or via register PHYCR (0x19h), bit 15. The crossover can be manually forced through bit 14 of the PHYCR (0x19h) register. Neither AutoNegotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Auto-MDIX can be used in the forced 100Base-TX mode. Because in modern networks all the nodes are 100Base-TX, having the Auto-MDIX working in the forced 100Base-TX mode resolves the link faster without the need for the long Auto-Negotiation period. 3.6 MII Isolate Mode The TLK110 can be put into MII-Isolate mode by writing bit 10 of the BMCR register. When in the MII-Isolate mode, the TLK110 does not respond to packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in isolate mode, the TLK110 continues to respond to all management transactions. When in isolate mode, the PMD output pair does not transmit packet data, but continues to source 100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK110 can auto-negotiate or parallel detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the TLK110 is in Isolate mode. Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 13 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.7 www.ti.com PHY Address The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-2. Table 3-2. PHY Address Mapping PIN # PHYAD FUNCTION 42 PHYAD0 RXD FUNCTION COL 43 PHYAD1 RXD_0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 Each TLK110 or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK110 can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is 00001 (0x01h). PHYAD4 = 0 PHYAD3 = 0 PHYAD2 = 0 COL RXD_0 RXD_1 RXD_3 RXD_2 See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the PHYAD configuration results in address 00011 (0x03h). PHYAD1 = 1 PHYAD0 = 1 2.2 kW VCC Figure 3-3. PHYAD Configuration Example 3.8 Software Strapping Mode The TLK110 provides a mechanism to extend the number of configuration pins to allow wider system programmability of PHY functions. Connecting an external pull-down to pin 21 causes the device to enter SW Strapping Mode after power-up or a hardware reset event. In this mode the device wakes up after power-up/hardware reset in power down mode. While in power down (in SW strap mode only) the PHY allows the system processor to access the dedicated Strapping Registers and configure modes of operation. Once the dedicated Strapping Registers are programmed, setting the SW Strapping Mode Release register bit ("Configuration done"), bit 15 of register SWSCR1(0x0009), must be done in order to take the device out of power-down mode. An internal reset pulse is generated and the SW Strap Register values are latched into internal registers. Unless a new Power-up/HW reset was applied, the configured SW Strap Register values will function as default values. Generation of Software Reset/Software Restart - bits 15/14 of register PHYRCR (0x001F) will not clear the configured SW Strap bit values. There are 3 Software Strapping control registers: SWSCR1 (0x0009), SWSCR2 (0x000A) and SWSCR3(0x000B) contain the configuration bits used as strapping options or virtual strapping pins during HW Reset or Power-Up. The TLK110 Software Strap mechanism behavior is shown in Figure 3-4. 14 Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 SW_STRAPN Pin tied to Ground Power up or Reset event Thrugh HW_RESENT pin Data = FFFF Software Polls OUI Register value (0x0002) to detect end of PHY reset Data = 2000 PHY in Power Down State Software configures SW_STRAP registers: SWSCR1-3 (0x0009,0x000A,0x000B) Software sets Config_Done - bit [15] at SWSCR1 Register (0x0009) 200 ms PHY starts power up sequence using SW Strapping configuration values PHY in Operating mode and tries to establish link Figure 3-4. TLK110 SW Strap Programming Figure 3-5 shows the timing relationship for typical SW Strapping programming. SW_STRAPN HW_RESETN Config_Done 200 ms MDIO PHY State Write/Read Transactions Reset Power Down Wake up Try to establish Link Figure 3-5. TLK110 SW Strap Timing Diagram Connecting an external pull-up resistor to pin 21 disables Software Strapping Mode during power up and/or HW Reset. Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 15 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.9 www.ti.com LED Interface The TLK110 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes. The LEDs can be controlled by configuration pin and/or internal register bits. Bits 6:5 of the LED Direct Control register (LEDCR) selects the LED mode as described in Table 3-3. Table 3-3. LED Mode Select Mode LED_CFG[1] (bit 6) LED_CFG[0] (bit 5) or (pin 22) 1 don't care 1 ON for Good Link OFF for No Link ON in 100Mbs OFF in 10Mbs ON Pulse for Activity OFF for No Activity 2 0 0 ON for Good Link BLINK for Activity ON in 100Mbs OFF in 10Mbs ON for Collision OFF for No Collision 3 1 0 ON for Good Link BLINK for Activity ON in 100Mbs OFF in 10Mbs ON for Full Duplex OFF for Half Duplex LED_LINK LED_SPEED LED_ACT The LED_LINK pin in Mode 1 indicates the link status of the port. It is OFF when no link is present. In Mode 2 and Mode 3 it is ON to indicate that the link is good; BLINK indicates that activity is present on either transmit or receive channel. The blink rate is controlleded by bits 9:8 of the LEDCR register (0x18). The default blink rate is 5Hz. The LED_SPEED pin indicates the data rate of the port, 10Mbs or 100Mbs. This LED is ON when the device is operating in 100Mbs operation. The functionality of this LED is independent of mode selected. The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED is ON (Pulse) for Activity and OFF for No Activity. The width of the pulse is determined by bits 14:13 of the LEDCR register (0x18). The default pulse width is 200ms. In mode 2 this pin indicates the collision status of the port. The LED is ON when there is a collision and OFF when there is no collision. In mode 3 this pin indicates the Duplex status of operation. The LED is ON for Full Duplex and OFF for Half Duplex. Bits 8:6 of the LEDCR register define the polarity of the signals on the LED pins. Because the Auto-Negotiation (AN) configuration options share the LED output pins, the external components required for configuration-pin programming and those for LED usage must be considered in order to avoid contention. AN_EN = 1 2.2 kW LED_LINK LED_SPEED LED_ACT/COL See Figure 3-6 for an example of AN connections to external components. In this example, the AN configuration results in Auto-Negotiation with 10/100 Full-Duplex advertised. AN1 = 1 2.2 kW 470 W AN0 = 1 2.2 kW 470 W 470 W VCC B0315-01 Figure 3-6. AN Pin Configuration and LED Loading Example 16 Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.10 Loopback Functionality The TLK110 provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK110 digital and analog data path. Generally, the TLK110 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. 3.10.1 Near-End Loopback Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. Figure 3-7 shows the PHY near-end loopback functionality. PCS Loopback Analog Loopback M MAC/ Switch I I Signal Process PCS PHY AFE PHY Digital MII Loopback Digital Loopback XFMR RJ45 1 2 3 4 5 6 7 8 External Loopback Figure 3-7. Block Diagram, Near-End Loopback Mode The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at address 0x0000, bit [14]. The Near-end Loopback can be selected according to the following: * Reg 0x0000, Bit [14]: MII Loopback * Reg 0x0016, Bit [0]: PCS input Loopback * Reg 0x0016, Bit [1]: PCS output Loopback (100Base-TX only) * Reg 0x0016, Bit [2]: Digital Loopback (100Base-TX only) * Reg 0x0016, Bit [3]: Analog Loopback (Valid only at force 100/10 mode) While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. To ensure proper operation in Analog Loopback mode, 100 terminations should be attached to the RJ45 connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This is not relevant for external-loopback mode. For selected loopback Delay propagation timing please see Section 9.6.21. Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 17 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.10.2 www.ti.com Far-End Loopback Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-8 shows Far-end loopback functionality. MAC/ Switch M I I PCS Signal Process PHY AFE XFMR CAT5 Cable & Link Partner RJ45 PHY Digital Reverse Loopback Figure 3-8. Block Diagram, Far-End Loopback Mode The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII register address 0x0016. While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface and all data signals that come from the MAC are ignored. 3.11 BIST The TLK110 incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loop back using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets and IPG on the lines. The BIST allows full control of the packet lengths and of the Inter-Packet Gap (IPG). The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo-random sequence. The TLK110 generates a 15-bit pseudo-random sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker received is stored in the BICSR1 register (0x001Bh). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be read from the BISCR register (0x0016h). The PRBS test can be put in a continuous mode or single mode by using bit 14 of the BISCR register (0x0016h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again. In single mode, when the PRBS counter reaches its maximum value, the PRBS checker stops counting. TLK110 allows the user to control the length of the PRBS packet. By programming the BICSR2 register (0x001Ch) one can set the length of the PRBS packet. There is also an option to generate a single-packet transmission of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016h). The single generated packet is composed of a constant data. 18 Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 3.12 Cable Diagnostics With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides extensive information about cable integrity. The TLK110 offers the following capabilities in its Cable Diagnostic tools kit: 1. Time Domain Reflectometry (TDR). 2. Active Link Cable Diagnostic (ALCD). 3.12.1 TDR The TLK110 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross shorts and any other discontinuities along the cable. The TLK110 transmits a test pulse of known amplitude (+1/2.5V) down each of the two pairs of an attached cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector, and from the end of the cable itself. After the pulse transmission the TLK110 measures the return time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude (impedance) of non-terminated cables (open or short), discontinuities (bad connectors), and improperly-terminated cables with 1m accuracy. The TLK110 also uses data averaging to reduce noise and improve accuracy. The TLK110 can record up to five reflections within the tested pair. If more than 5 reflections are recorded, the TLK110 saves the first 5 of them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the tested channel. The TLK110 TDR can measure cables up to 200m in length. For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (e.g. CAT5/CAT5e/CAT6). TDR measurement is allowed in the TLK110 in the following scenarios: * While Link partner is disconnected - cable is unplugged at the other side * Link partner is connected but remains "quiet" (I.e. in power down mode) * TDR could be automatically activated when the link fails or is dropped by setting bit 8 of register 0x0009 (SWSCR1). The results of the TDR run after the link fails will be saved in the TDR registers. The SW could read these registers at any time to apply post processing on the TDR results. This mode is designed for cases in which the link dropped due to cable disconnections, in which after link failure, the line will be quiet to allow a proper function of the TDR. 3.12.2 ALCD The TLK110 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. It uses passive digital signal processing based on adapted data, thus enabling measurement of cable length with an active link partner. The ALCD also uses pre-defined parameters according to the cable properties (e.g. CAT5/CAT5e/CAT6) in order to achieve higher accuracy in the estimated cable length. The ALCD Cable length measurement accuracy is 5m for the pair used in the Rx path (due to the passive nature of the test, only the receive path is measured). Hardware Configuration Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 19 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 4 Interfaces 4.1 Media Independent Interface (MII) The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22. The MII signals are summarized below. Data signals MII_TXD [3:0] RXD [3:0] Transmit and receive-valid signals MII_TX_EN MII_RX_DV Line-status signals CRS (carrier sense) COL (collision) Figure 4-1 shows the MII-mode signals. PHY MAC TX_CLK TX_CLK TX_EN TX_EN TXD [3:0] TXD [3:0] RX_CLK RX_CLK RX_DV RX_DV RX_ER RX_ERR RXD [3:0] RXD [3:0] CRS CRS COL COL Figure 4-1. MII Signaling The isolate register 0.10 defined in IEEE802.3-2002 used to electrically isolate the PHY from the MII (if set, all transactions on the MII interface are ignored by the PHY). Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both transmit and receive operation occur simultaneously. 4.2 Reduced Media Independent Interface (RMII) TLK110 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u [2] MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. 20 Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 The RMII specification has the following characteristics: * It is capable of supporting 10Mb/s and 100Mb/s data rates * A single clock reference is sourced from the MAC to PHY (or from an external source) * It provides independent 2 bit wide (di-bit) transmit and receive data paths * It uses TTL signal levels, compatible with common digital CMOS ASIC processes In this mode, data is transferred two bits at a time using the 50MHz RMII_REF clock for both transmit and receive. The following pins are used in the RMII mode: Signal Pin XI (RMII reference clock is 50MHz) 34 TXD_0 3 TXD_1 4 TX_EN 2 CRS_DV 40 RX_ER 41 RXD_0 43 RXD_1 44 Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50 MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks. In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RMII mode requires a 50MHz oscillator to be connected to the device XI pin. The TLK110 supports a special mode called "RMII receive clock" mode. This mode, which is not part of RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50Mhz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DV and RX_ER signals to this clock. Setting register 0x000A bit [0] is required to activate this mode. Figure 4-2 describes the RMII signals connectivity between the TLK110 and any MAC device. Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 21 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com PHY TX_EN TXD[1:0] RX_CLK RX_DV RX_ER RXD[1:0] CRS/RX_DV MAC TX_EN TXD[1:0] RX_CLK (optional) RX_DV (optional) RX_ER RXD[1:0] CRS/RX_DV XI 50Mhz Clock Source Figure 4-2. TLK110 RMII/MAC Connection RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy. Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy. Table 4-1. Recommended RMII Packet Sizes 22 Start Threshold RBR[1:0] Latency Tolerance Recommended packet size at 50ppm Recommended packet size at 100ppm 1(4-bits) 2 bits 2400 bytes 1200 bytes 2(8-bits) 6 bits 7200 bytes 3600 bytes 3(12-bits) 10 bits 12000 bytes 6000 bytes 0(16-bits) 14 bits 16800 bytes 8400 bytes Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 4.3 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Serial Management Interface The Serial Management Interface (SMI), provides access to the TLK110 internal registers space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002 in addition to several others, providing additional visibility and controllability of the TLK110 device. The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity (also referred to as STA), and can run at maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle. The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (1.5k) which, during IDLE and turnaround, pulls MDIO high. Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK110 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to determine its address. The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus should remain inactive at least one MDC cycle after hard reset is de-asserted. In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK110 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the TLK110 (PHY) for a typical register read access. Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 23 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com For write transactions, the station-management entity writes data to the addressed TLK110, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4. Table 4-2. Typical MDIO Frame Format MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle> Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle> MDC Z MDIO Z (STA) Z MDIO (PHY) 0 Z Idle 1 Start 1 0 0 Opcode (Read) 1 1 0 0 0 PHY Address (PHYAD = 0Ch) 0 0 0 Z 0 Z 0 Register Address (00h = BMCR) 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Register Data TA Z Idle Figure 4-3. Typical MDC/MDIO Read Operation MDC MDIO (STA) Z Z Idle Z 0 1 Start 0 1 Opcode (Read) 0 1 1 0 PHY Address (PHYAD = 0Ch) 0 0 0 0 0 0 Register Address (00h = BMCR) 1 0 0 0 0 0 TA 0 0 0 0 0 Register Data 0 0 0 0 0 0 0 Z Idle Figure 4-4. Typical MDC/MDIO Write Operation 24 Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 4.3.1 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Extended Address Space Access The TLK110 SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set. Accessing the standard register set, i.e. MDIO registers 0 to 31, can be performed using the normal direct MDIO access or the indirect method, except for register REGCR(0x000Dh) and ADDAR(0x000Eh) which can be accessed only using the normal MDIO transaction. The SMI function will ignore indirect accesses to these registers. REGCR(0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR(0x000Eh) register to the appropriate MMD. Specifically, the TLK110 uses the vendor specific DEVAD[4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR should use this DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data with post increment on read and writes (10) and data with post increment on writes only (11). * ADDAR is the address/data MMD register. It is used in conjunction with REGCR to provide the access to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended register set address register. This address register should always be initialized in order to access any of the register within the extended register set. * When REGCR[15:14] is set to 01, accesses to register ADDAR access the register within the extended register set selected by the value in the address register. * When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented. * When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged. The following sections describe how to perform operations on the extended register set using register REGCR and ADDAR. 4.3.1.1 Write Address Operation To set the address register: 1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. 2. Write the desired register address to register ADDAR. Subsequent writes to register ADDAR (step 2) continue to write the address register. 4.3.1.2 Read Address Operation To read the address register: 1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. 2. Read the register address from register ADDAR. Subsequent reads to register ADDAR (step 2) continue to read the address register. Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 25 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 4.3.1.3 To 1. 2. 3. 4. www.ti.com Write (no post increment) Operation write an extended register set register: Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. Write the desired register address to register ADDAR. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR. Write the content of the desired extended register set register to register ADDAR. Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the address register. Note: steps (1) and (2) can be skipped if the address register was previously configured. 4.3.1.4 To 1. 2. 3. 4. Read (no post increment) Operation read an extended register set register: Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. Write the desired register address to register ADDAR. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR. Read the content of the desired extended register set register to register ADDAR. Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the address register. Note: steps (1) and (2) can be skipped if the address register was previously configured. 4.3.1.5 Write (post increment) Operation 1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. 2. Write the register address from register ADDAR. 3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) or the value 0xC01F (data, post increment on writes function field = 11. DEVAD = 31) to register REGCR. 4. Write the content of the desired extended register set register to register ADDAR. Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the value of the address register, i.e address register is incremented after each access. 4.3.1.6 Read (post increment) Operation To read an extended register set register and automatically increment the address register to the next higher value following the write operation: 1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. 2. Write the desired register address to register ADDAR. 3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) to register REGCR. 4. Read the content of the desired extended register set register to register ADDAR. Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value of the address register, i.e address register is incremented after each access. 26 Interfaces Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 5 Architecture The TLK110 Fast Ethernet transceiver is physical layer core for Ethernet 100Base-TX and 10Base-T applications. It contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII), as well as the Reduced Media Independent Interface (RMII), for direct connection to a MAC/Switch port. The TLK110 uses mixed signal processing to perform equalization, data recovery and error correction to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The TLK110 architecture not only meets the requirements of IEEE802.3, but maintains a high level of margin over the IEEE requirements for NEXT, Alien and External noise. 4B/5B encoding Scrambler NRZ to NRZI Convertor MLT-3 encoding D/A Convertor 100Base TX Line Driver 10Base T Filter 10Base T Line Driver Transmit Manchester encoding Adv. Link Monitor MII Receive 10Base T Receive Filter Manchester decoding 4B/5B decoding DeScrambler NRZI to NRZ Convertor 100Base TX 10Base-T MLT-3 decoding DSP (BLW Correction, Adapt. Equal) ADC (Filter, Amplifierl) Figure 5-1. PHY Architecture 5.1 100Base-TX Transmit Path In 100Base-TX, the MAC feeds the 100Mbps transmit data in 4-bit wide nibbles through the MII interface. The data is encoded into 5-bit code groups, encapsulated with control code symbols and serialized. The control-code symbols indicate the start and end of the frame and code other information such as transmit errors. When no data is available from the MAC, IDLE symbols are constantly transmitted. The serialized bit stream is fed into a scrambler. The scrambled data stream passes through an NRZI encoder and then through an MLT3 encoder. Finally, it is fed to the DAC and transmitted through one of the twisted pairs of the cable. 5.1.1 MII Transmit Error Code Forwarding According to IEEE 802.3: "If TX_EN is de-asserted on an odd nibble boundary, PHY should extend TX_EN by one TX_CLK cycle and behave as if TX_ER were asserted during that cycle". The TLK110 supports Error Forwarding in MII transmission from the MAC to the PHY allows adding information to the frame, to be used as an error code between the 2 MACs. The error code is used to inform the receiving MAC on the link partner side, the reason for the error from the transmitting side. If an odd number of nibbles are transmit from the MAC, an additional error nibble is added to the transmitted frame just before the end of the transmission. Transmit Error Forwarding can be turned off by writing to bit 1 of register SWSCR2 (0x000A). By disabling Error Forwarding, packets will be delivered containing either odd or even numbers of nibbles. In Figure 5-2, Error Code Forwarding functionality is illustrated. The wave diagram demonstrates MAC's transmitted signals in one side and MAC's reception signals on link partner side. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 27 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com TX_CLK TX_EN TXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code RX_CLK RX_DV RXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code Don't Care RX_ERR Figure 5-2. Transmit Code Error Forwarding Diagram 5.1.2 4B/5B Encoding The transmit data that is received from the MAC first passes through the 4B/5B encoder. This block encodes 4-bit nibble into 5-bit code-groups according to the Table 5-1. Each 4-bit data nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or they are considered as not valid. The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4-bit preamble and data nibbles with corresponding 5-bit code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder adds the T/R codegroup pair (01101 00111) indicating the end of the frame. After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data stream until the next transmit packet is detected. 28 Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 5-1. 4B/5B Code Table 4-Bit Code Symbol 5-Bit Code 0000 0 11110 Receiver Interpretation 0001 1 01001 0010 2 10100 0011 3 10101 0100 4 01010 0101 5 01011 0110 6 01110 0111 7 01111 1000 8 10010 1001 9 10011 1010 A 10110 1011 B 10111 1100 C 11010 1101 D 11011 1110 E 11100 1111 F 11101 DESCRIPTION Symbol (1) 5-Bit Code Inter-Packet IDLE I 11111 IDLE First nibble of SSD J 11000 First nibble of SSD, translated to "0101" following /I/ (IDLE), else RX_ER asserted high Second nibble of SSD K 10001 Second nibble of SSD, translated to "0101" following /J/, else RX_ER asserted high First nibble of ESD T 01101 First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RX_ER Second nibble of ESD R 00111 Second nibble of ESD, causes de-assertion of CRS if following /T/, else assertion of RX_ER Transmit Error Symbol H 00100 RX_ER Invalid Symbol V 00000 V 00001 INVALID RX_ER asserted high If during RX_DV V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 Data IDLE AND CONTROL CODES (1) Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted. 5.1.3 Scrambler The purpose of the scrambler is to flatten the power spectrum of the transmitted signal, thus reduce EMI. The scrambler seed is generated with reference to the PHY address so that multiple PHYs that reside within the system will not use the same scrambler sequence. 5.1.4 NRZI and MLT-3 Encoding To comply with the TP-PMD standard for 100Base-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 29 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 5.1.5 www.ti.com Digital to Analog Converter The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers. Digital pulse-shape filtering is also applied in order to conform to the pulse masks defined by standard and to reduce EMI and high frequency signal harmonics. 5.2 100Base-TX Receive Path In 100B-TX, the ADC sampled data is passed to an adaptive equalizer. The adaptive equalizer drives the received symbols to the MLT3 decoder. The decoded NRZ symbols are transferred to the descrambler block for descrambling and deserialization. 5.2.1 Analog Front End The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. It consists of an Analog to Digital Converter (ADC), receive filters and a Programmable Gain Amplifier (PGA). The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input while maintaining high power-supply rejection ratio and low power consumption. There is only one ADC in the TLK110, which receives the analog input data from the relevant cable pair, according to MDI-MDIX resolution. The PGA, digitally controlled by the adaptive equalizer, fully uses the dynamic range of the ADC by adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and amplifies long-cable weak signals. 5.2.2 Adaptive Equalizer The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the channel and analog Tx/Rx filters. The TLK110 includes both Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE). The combination of both adaptive modules with the adaptive gain control results in a powerful equalizer that can eliminate ISI and compensate for cable attenuation for longer-reach cables. In addition, the Equalizer includes a Shift Gear Step mechanism to provide fast convergence on the one hand and small residual-adaptive noise in steady state on the other hand. 5.2.3 Baseline Wander Correction The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because of this phenomenon, the receiver corrects the baseline wander and can receive the ANSI TP-PMD-defined "killer packet" with no bit errors. 5.2.4 NRZI and MLT-3 Decoding The TLK110 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler. 30 Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 5.2.5 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Descrambler The descrambler is used to descramble the received NRZ data. It is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100BTX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason, synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE symbols. 5.2.6 5B/4B Decoder and nibble alignment The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair preceded by IDLE code-groups at the start of a packet. Once the code group alignment is determined, it is stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble. Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups. 5.2.7 Timing Loop and Clock Recovery The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing. The timing loop recovers the far-end clock frequency and offset from the received data samples and tracks instantaneous phase drifts caused by timing jitter. The TLK110 has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the FarEnd TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an advanced tracking mechanism that when combined with different available phases, always keeps track of the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and Jitter. The TLK110 is capable of dealing with PPM and jitter at levels far higher than those defined by the standard. 5.2.8 Phase-Locked Loops (PLL) In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the received Manchester signal The DPLL is able to combat clock jitter of up to 18ns and frequency drifts of 500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a decoded serial bit stream. The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal oscillator, or at XI with an external reference clock). 5.2.9 Link Monitor The TLK110 implements the link monitor SM as defined by the IEEE 802.3 100Base-TX Standard. In addition, the TLK110 enables several add-ons to the link monitor State Machine(SM) activated by configuration bits. The new add-ons include the recovery state which enables the PHY to attempt recovery in the event of a temporary energy-loss situation before entering the LINK_FAIL state, and thus, restarting the whole link establishment procedure. This allows significant reduction of the recovery time in scenarios where the link loss is temporal. In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time. These add-ons are supplementary to the IEEE standard and are bypassed by default. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 31 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 5.2.10 Signal Detect The signal detect function of the TLK110 is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters. The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to predefined thresholds in order to decide the presence or absence of an incoming signal. The energy detector also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required. 5.2.11 Bad SSD Detection A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the TLK110 asserts RX_ER, and presents RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the FCSCR register (0x14h) is incremented by one for every error in the nibble. When at least two IDLE code groups are detected, RX_ER and CRS are de-asserted. 5.3 10Base-T Receive Path In 10B-T, after the far-end clock is recovered, the received Manchester symbols pass to the Manchester decoder. The serial decoded bit stream is aligned to the start of the frame, de-serialized to 4-bit wide nibbles and sent to the MAC through the MII. 5.3.1 10M Receive Input and Squelch The squelch feature determines when valid data is present on the differential receive inputs. The TLK110 implements a squelch to prevent impulse noise on the receive inputs from being mistaken for a valid signal. Squelch operation is independent of the 10Base-T operating mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs. The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present. At this time, the squelch circuitry is reset. 5.3.2 Collision Detection When in Half-Duplex mode, a 10Base-T collision is detected when receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected, it is reported immediately (through the COL pin). 5.3.3 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity after valid data is detected via the squelch function. For 10Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10Mb/s Full Duplex operation, CRS is asserted only during receive activity. CRS is de-asserted following an end-of-packet. 32 Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 5.3.4 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Jabber Function Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK110 output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms. When disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal must be de-asserted for approximately 500ms (the unjab time) before the Jabber function re-enables the transmit outputs. The Jabber function is only available and active in 10Base-T mode. 5.3.5 Automatic Link Polarity Detection and Correction Swapping the wires within the twisted pair causes polarity errors. Wrong polarity affects the 10B-T PHYs. The 100B-TX is immune to polarity problems because it uses MLT3 encoding. The 10B-T automatically detects reversed polarity according to the received link pulses or data. 5.3.6 10Base-T Transmit and Receive Filtering External 10Base-T filters are not required when using the TLK110, because the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30dB. 5.3.7 10Base-T Operational Modes The TLK110 has two basic 10Base-T operational modes: * Half Duplex mode - In Half Duplex mode the TLK110 functions as a standard IEEE 802.3 10Base-T transceiver supporting the CSMA/CD protocol. * Full Duplex mode - In Full Duplex mode the TLK110 is capable of simultaneously transmitting and receiving without asserting the collision signal. The TLK110 10Mbs ENDEC is designed to encode and decode simultaneously. 5.4 Auto MDI/MDI-X Crossover The auto MDI/MDI-X crossover function detects wire crossover (also referred to as MDI/MDI-X). It automatically performs the pair swaps such that each transmitter is connected to its link partner receiver and vice versa, without using an external crossed cable. The auto MDI/MDI-X crossover function is capable of establishing a link with PHYs that do not implement a crossover mechanism. Table 5-2. MDI/MDI-X Pair Swaps Combinations PIN MDI 10B-T MDI-X 100B-TX 10B-T 100B-TX TD (pin 8,9) TD TD RD RD RD (pin 5,6) RD RD TD TD Detecting link pulses or energy on one or more of the MDI pins determines the crossover state and whether there is a need to perform a swap. If both link partners implement the MDI/MDI-X crossover, then a random algorithm, compliant with one described in IEEE 802.3 section 40.4.4 is used. If the other link partner is a legacy 10B-T PHY, then the same algorithm is used. If the other link partner is a legacy 100BTX PHY, then the crossover state is determined according to the signal detection function. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 33 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com As described, the link partner configuration and abilities, whether they use the auto negotiation and/or activate a crossover mechanism, greatly influence the method picked by the crossover function to determine if and how to cross. While in 10BT all possible configurations will results link establishment, in 100BT several configurations may not results link establishment. Table 5-3 describes all possible configurations for 100BT and the link establishment results accordingly. In Table 5-3, when not in ANEG, the link partner is assumed to be in force-100BT mode. Table 5-3. Link-Pair Scenarios PHY1 PHY2 ANEG AMDIX ANEG AMDIX Link Established + + + + V Full automated link establishment + + + - V Full Automated since one of the link partners is in AMDIX Remarks + - + - V Link will be established only if both sides are configured in Force MDI or MDIX in a matched manner: * MDI vs. MDIX for non-crossed cables * MDIX vs. MDIX for crossed cables * MDI vs. MDI for crossed cables + + - - V When one of the sides is in Force 100BT and the other side is in ANEG, the Force 100BT side must also be at force MDI or MDIX according to IEEE in order to establish a link. This case is fully Automated since one of the link partners is in AMDIX mode. V Link will be established only if both sides are configured in Force MDI or MDIX in a matched manner: * MDI vs. MDIX for non-crossed cables * MDIX vs. MDIX for crossed cables * MDI vs. MDI for crossed cables V Link will be established only if both sides are configured in Force MDI or MDIX in a matched manner: * MDI vs. MDIX for non-crossed cables * MDIX vs. MDIX for crossed cables * MDI vs. MDI for crossed cables V* According to IEEE spec, a link could not be established in this scenario. However, the TLK110 offers a unique mode, Enhanced AMDIX Mode, that allows link establishment in this scenario as well. In this mode PHY2 (TLK110) while configured to force 100BT mode will adjust the AMDIX mechanism timers to allow link establishment. When operating in this mode, the TLK110 will be able to establish a link in all other scenarios as well. This mode is not IEEE compliant and can be configured by setting bit 5 of register 0x0009 (SWSCR1) + - + - - +/- - - - - - + The crossover mechanism can be turned off and forced to the MDI or MDI-X state by setting configuration pin MDIX_EN (Pin 31), whose state is latched during power-up reset. When MDIX_EN is set to `0', then the crossover mechanism is disabled and the PHY operates in MDI or MDI/X mode respectively. If the pin is set to '1', then the crossover mechanism is enabled and MDI/MDI-X state is selected during operation. The auto-MDI/MDI-X crossover function is controlled by register PHYCR (0x0019) bits [15:14]. MDI/MDI-X status can be read through register PHYSTS (0x0010) bit 14. 5.5 Auto Negotiation The auto-negotiation function, described in detail in IEEE802.3 chapter 28, provides the means to exchange information between two devices and automatically configure both of them to take maximum advantage of their abilities. 34 Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 5.5.1 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Operation Auto negotiation uses the 10B-T link pulses. It encapsulates the transmitted data in sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word that identifies the operational modes supported by the remote device, as well as some information used for the auto negotiation function's handshake mechanism. The information exchanged between the devices during the auto-negotiation process consists of the devices' abilities such as duplex support and speed. It allows higher levels of the network (MAC) to send to the other link partner vendor-specific data (via the Next Page mechanism, see below), and provides the mechanism for both parties to agree on the highest performance mode of operation. When auto negotiation has started, the TLK110 transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information. If the other link partner is a legacy PHY or does not activate the auto negotiation, then the TLK110 uses the parallel detection function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation modes. 5.5.2 Initialization and Restart The TLK110 initiates the auto negotiation function if it is enabled through the configuration jumper options AN_EN, AN_1 and AN_0 (pins 34,35,36) and one of the following events has happened: 1. Hardware reset de-assertion. 2. Software reset (via register). 3. Auto negotiation restart (via register BMCR (0x0000h) bit 9). 4. Power-up sequence (via register BMCR (0x0000h) bit 11 ). The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR (0x0000h) bit 12 and one of the following events has happened: 1. Software restart. 2. Transitioning to link_fail state, as described in IEEE802.3. To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK110 operation. For the changes to take place, issue a restart command through register BMCR (0x0000h) bit 9. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 35 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 5.5.3 www.ti.com Configuration Bits The auto-negotiation options can be configured through the configuration bits AN_EN, AN_1 and AN_0 as described in Table 5-4. The configuration bits allow the user to disable/enable the auto negotiation, and select the desirable advertisement features. During hardware/software reset, the values of these configuration bits are latched into the auto-negotiation registers and available for user read and modification. Table 5-4. Auto-Negotiation Modes 5.5.4 AN_EN AN_1 AN_0 Forced Mode 0 0 0 10Base-T, Half-Duplex 0 0 1 10Base-T, Full-Duplex 0 1 0 100Base-TX, Half-Duplex 0 1 1 100Base-TX, Full-Duplex AN_EN AN1 AN0 1 0 0 10Base-T, Half/Full-Duplex 1 0 1 10Base-TX, Half/Full-Duplex 1 1 0 10Base-T,Half-Duplex 100Base-TX, Half-Duplex 1 1 1 10Base-T,Half/Full-Duplex 100Base-TX, Half/Full-Duplex Advertised Mode Next Page Support The TLK110 supports the optional feature of the transmission and reception of auto-negotiation additional (vendor specific) next pages. If next pages are needed, the user must set register ANAR(0x0004h) bit 15 to '1'. The next pages are then sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively. The user must poll register ANER(0x0006h) bit 1 to check whether a new page has been received, and then read register ANLNPTR for the received next page's content. Only after register ANLNPTR is read may the user write to register ANNPTR the next page to be transmitted. After register ANNPTR is written, new next pages overwrite the contents of register ANLNPTR. If register ANAR(0x0004h) bit 15 is set, then the next page sequence is controlled by the user, meaning that the auto-negotiation function always waits for register ANNPTR to be written before transmitting the next page. If additional user-defined next pages are transmitted and the link partner has more next pages to send, it is the user's responsibility to keep writing null pages (of value 0x2001) to register ANNPTR until the link partner notifies that it has sent its last page (by setting bit 15 of its transmitted next page to zero). 36 Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 5.6 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Link Down Functionality The TLK110 includes advanced link-down capabilities that support various real-time applications. The linkdown mechanism of the TLK110 is configurable and includes enhanced modes that allow extremely fast reaction times to link-drops. First Link Failure Occurrence Valid Data LOW Quality Data / Link Loss Signal Link Drop T1 Link Loss Indication (Link LED) Figure 5-3. TLK110 Link Loss Mechanism As described in Figure 5-3, the TLK110 link loss mechanism is based on a time window search period, in which the signal behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms. The TLK110 supports enhanced modes that shorten the window called Fast Link Down mode. In this mode, which can be configured in Software Strap Control Register 3 (SWSCR3), address 0x000B, bits 3:0, the T1 window is shortened significantly, in most cases less than 10s. In this period of time there are several criteria allowed to generate link loss event and drop the link: 1. Count RX Error in the MII interface: When a predefined number of 32 RX Error occurrences in time window of 10s is reached the link will drop. 2. Count MLT3 Errors at the signal processing output (100BT uses MLT3 coding, and when a violation of this coding is detected, an MLT3 error is declared). When a predefined number of 20 errors occurrences in 10s is reached the link will drop. 3. Count Low Signal Quality Threshold crossing (When the signal quality is under a certain threshold that allows proper link conditions). When a predefined number of 20 occurrences in 10s is reached, the link will drop. 4. Signal/Energy loss indications. When Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10s The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note that since this mode enables extremely quick reaction time, it is more exposed to temporary bad linkquality scenarios. Architecture Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 37 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 6 Reset and Power Down Operation The TLK110 includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up. At power-up, if required by the system, the RESETN pin (active low) should be de-asserted 200s after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If required during normal operation, the device can be reset by a hardware or software reset. 6.1 Hardware Reset A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1s, to RESETN. This resets the device such that all registers are reinitialized to default values, and the hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally is approximately 200s. 6.2 Software Reset An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x0000h). This bit only resets the IEEE-defined standard registers in the address space 0x00h to 0x07h. A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to `1'. This bit resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the extended registers. The global software reset resets the device such that all registers are reset to default values and the hardware configuration values are maintained. A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to `1'. This resets all the PHY circuits except the registers in the Register File. The time from the point when the resets/restart bits are set to the point when the software resets/restart has concluded is approximately 200s. It is recommended that the software driver code must wait 500s following software reset before allowing further serial MII operations with the TLK110. 6.3 Power Down/Interrupt The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 0 (INTN_OE) to `1' PHYSCR (0x0011h) register. Same PHYSCR register is also used to enable and set the polarity of the interrupt. 6.3.1 Power Down Control Mode The PWRDNN pin can be asserted low to put the device in a Power Down mode. An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDNN pin. 6.3.2 Interrupt Mechanisms The interrupt function is controlled via register access. All interrupt sources are disabled by default. The MISR1 (0x0012) and MISR2 (0x0013) registers provide independent interrupt enable bits for the various interrupts supported by the TLK110. The INTN pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the interrupt status registers MISR1 (0x0012h) and MISR2 (0x0013). One or more bits in the MISR registers will be set, indicating all currently-pending interrupts. Reading the MISR registers clears ALL pending interrupts. 38 Reset and Power Down Operation Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 6.4 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Power Save Modes The TLK110 supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the PWRDNN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available). To enable and activate all other power save modes through register access, use register PHYSCR (0x0011h). Setting bit 14 enables all power-save modes; bits [13:12] select between them. Setting bits [13:12] to "01" powers down the PHY, forcing it into IEEE power down mode (Similar to BMCR bit 11 functionality). Setting bits [13:12] to "10" puts the PHY in Low Power Active WOL (Wake-On-LAN) mode. Setting bits [13:12] to "11" puts the PHY in Low Power Passive WOL (Wake-On-LAN) mode. When these bits are cleared, the PHY powers up and returns to the last state it was in before it was powered down. Reset and Power Down Operation Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 39 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 7 Design Guidelines 7.1 TPI Network Circuit Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application. * Pulse H1102 * Pulse HX1188 Vdd Common-mode chokes may be required. RD- 49.9 W Vdd 1:1 0.1 mF 49.9 W RD- RD+ RD+ 0.1 mF* TD- TD- 49.9 W Vdd TD+ 0.1 mF* 1:1 49.9 W T1 RJ45 0.1 mF Note: Center tap is connected to Vdd * Place capacitors close to the transformer center taps TD+ Place resistors and capacitors close to the device. All values are typical and are 1% S0339-01 Figure 7-1. 10/100Mbs Twisted Pair Interface 7.2 Clock In (XI) Requirements The TLK110 supports an external CMOS-level oscillator source or an internal oscillator with an external crystal. 7.2.1 Oscillator If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The amplitude of the oscillator should be a nominal voltage of 3.3V. 40 Design Guidelines Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 7.2.2 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Crystal The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100W and a maximum of 500W. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between XO and the crystal. As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for CL1 and CL2 at 33pF, and R1 should be set at 0. Specifications for a 25MHz crystal are listed in Table 7-3. XI XO R1 CL1 CL2 S0340-01 Figure 7-2. Crystal Oscillator Circuit Table 7-1. 25 MHz Oscillator Specification PARAMETER TEST CONDITIONS MIN Frequency TYP MAX 25 UNIT MHz Frequency Tolerance Operational Temperature 50 Frequency Stability 1 year aging 50 ppm Rise / Fall Time 10%-90% 8 nsec Jitter (Short term) Cycle-to-cycle Jitter (Long term) Accumulative over 10 ms Symmetry Duty Cycle 50 psec 1 40% Load Capacitance ppm nsec 60% 15 30 TYP MAX pF Table 7-2. 50 MHz Oscillator Specification PARAMETER TEST CONDITIONS MIN Frequency 50 UNIT MHz Frequency Tolerance Operational Temperature 50 Frequency Stability 1 year aging 50 ppm Rise / Fall Time 10%-90% 6 nsec Jitter (Short term) Cycle-to-cycle Jitter (Long term) Accumulative over 10 ms Symmetry Duty Cycle 50 psec 1 40% ppm nsec 60% Table 7-3. 25 MHz Crystal Specification PARAMETER TEST CONDITIONS MIN Frequency Frequency Tolerance Frequency Stability TYP MAX 25 UNIT MHz Operational Temperature 50 ppm At 25C 50 ppm 5 ppm 40 pF 1 year aging Load Capacitance 10 Design Guidelines Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 41 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 7.3 www.ti.com Thermal Vias Recommendation (Extended temperature (125C) grade only) The following thermal via guidelines apply to GNDPAD, pin 49: 1. Thermal via size = 0.2 mm 2. Recommend 4 vias 3. Vias have a center to center separation of 2 mm. Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 7-3 illustrates an example layout. M0117-01 Figure 7-3. Example Layout 42 Design Guidelines Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8 Register Block Table 8-1. Register Map OFFSET HEX ACCESS TAG DESCRIPTION 00h RW BMCR Basic Mode Control Register 01h RO BMSR Basic Mode Status Register 02h RO PHYIDR1 PHY Identifier Register #1 03h RO PHYIDR2 PHY Identifier Register #2 04h RW ANAR 05h RO ANLPAR 06h RO ANER 07h RW ANNPTR Auto-Negotiation Next Page TX 08h RO ANLNPTR Auto-Negotiation Link Partner Ability Next Page Register 09h RW SWSCR1 Software Strap Control Register #1 0Ah RW SWSCR2 Software Strap Control Register #2 0Bh RW SWSCR3 Software Strap Control Register #3 0Ch RW RESERVED 0Dh RW REGCR Register control register 0Eh RW ADDAR Address or Data register 0Fh RW RESERVED Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register RESERVED RESERVED EXTENDED REGISTERS 0x0010 RO PHYSTS PHY Status Register 0x0011 RW PHYSCR PHY Specific Control Register 0x0012 RW MISR1 MII Interrupt Status Register #1 0x0013 RW MISR2 MII Interrupt Status Register #2 0x0014 RO FCSCR False Carrier Sense Counter Register 0x0015 RO RECR Receive Error Count Register 0x0016 RW BISCR BIST Control Register 0x0017 RO RBR 0x0018 RW LEDCR RMII and Status Register LED Control Register 0x0019 RW PHYCR PHY Control Register 0x001A RW 10BTSCR 0x001B RW BICSR1 BIST Control and Status Register #1 0x001C RO BICSR2 BIST Control and Status Register #2 0x001D RW RESERVED 0x001E RW CDCR 0x001F RW PHYRCR 0x0020- 0x0041 RW RESERVED 10Base-T Status/Control Register RESERVED Cable Diagnostic Control Register PHY Reset Control Register RESERVED 0x0042 RO TXCPS 0x0043- 0x00CF RW RESERVED TX_CLK Phase Shift Register 0x00D0 RW VRCR 0x00D1- 0x016F RW RESERVED 0x0170 RW CDSCR 0x0171- 0x017F RW RESERVED 0x0180 RO CDLRR1 Cable Diagnostic Location Result Register #1 0x0181 RO CDLRR2 Cable Diagnostic Location Result Register #2 0x0182 RO CDLRR3 Cable Diagnostic Location Result Register #3 0x0183 RO CDLRR4 Cable Diagnostic Location Result Register #4 0x0184 RO CDLRR5 Cable Diagnostic Location Result Register #5 RESERVED Voltage Regulator Control Register RESERVED Cable Diagnostic Control Register RESERVED Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 43 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com Table 8-1. Register Map (continued) 44 OFFSET HEX ACCESS TAG 0x0185 RO CDLAR1 Cable Diagnostic Amplitude Result Register #1 DESCRIPTION 0x0186 RO CDLAR2 Cable Diagnostic Amplitude Result Register #2 0x0187 RO CDLAR3 Cable Diagnostic Amplitude Result Register #3 0x0188 RO CDLAR4 Cable Diagnostic Amplitude Result Register #4 0x0189 RO CDLAR5 Cable Diagnostic Amplitude Result Register #5 0x018A RW CDGRR Cable Diagnostic General Result Register Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-2. Register Table Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Basic Mode Control Register Register Name 00h BMCR Reset Loopback Speed Selection Auto-Neg Enable IEEE Power Down Isolate Restart Auto-Neg Duplex Mode Collision Test Basic Mode Status Register 01h BMSR 100Base T4 100Base TX FDX 100Base TX HDX 10Base-T FDX 10Base-T HDX PHY Identifier Register 1 02h PHYIDR 1 PHY Identifier Register 2 03h PHYIDR 2 Auto-Negotiation Advertisement Register 04h ANAR Next Page Ind Reserved Remote Fault Reserved ASM_DI R PAUSE 100B-T4 100BTX_FD 100B-TX 10B-T_FD 10B-T Protocol Selection[4:0] (number like this?) Auto-Negotiation Link Partner Ability Register (Base Page) 05h ANLPAR Next Page Ind ACK Remote Fault Reserved ASM_DI R PAUSE 100B-T4 100BTX_FD 100B-TX 10B-T_FD 10B-T Protocol Selection Auto-Negotiation Expansion Register 06h ANER Auto-Negotiation Next Page TX Register 07h ANNPTR Next Page Ind Reserved Message Page ACK2 TOG_TX CODE Auto-Negotiate Link Partner Ability Page Register 08h ANLNPTR Next Page Ind Reserved Message Page ACK2 TOG_TX CODE Software Strap Control Register 1 09h SWSCR1 Config Done Auto MDIX Enable Auto-Neg Enable AN1 AN0 Software Strap Control Register 2 0Ah SWSCR2 Software Strap Control Register 3 0Bh SWSCR3 RESERVED 0Ch Reserved Register Control Register 0Dh REGCR Address or Data Register 0Eh ADDAR Addr/ Data RESERVED 0Fh Reserved Reserved Reserved Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Link Status Jabber Detect Extended Capability Reserved MF Preamble Suppress Auto-Neg Complete Remote Fault Auto-Neg Ability OUI MSB OUI LSB VNDR_ MDL MDL_ REV Reserved LED_ CFG PDF RMII Enhance Mode TDR Auto Run Link Loss Recovery Fast Auto MDI/X Robust Auto MDI/X Fast AN Enable Reserved Fast LinkUp in PD Extended FD Ability Enhance LED Link Reserved Polarity Swap MDI/X Swap Bypass 4B/5B LP_NP_ ABLE NP_ ABLE PAGE_ RX LP_AN_AB LE Fast AN Select Isolate MII in 100BT HD RXERR During IDLE Fast RXDV Detect INT OE Odd Nibbl Detect Disable RMII Receive Clock Fast Link Down Sel Reserved Function Reserved DEVICE ADDRESS space Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 45 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com Table 8-3. Register Table, Extended Registers Register Name Addr Tag Bit 15 Bit 14 PHY Status Register 10h PHYSTS Reserved MDI-X Mode PHY Control Register 11h PHYCR Disable PLL Power Save Enable MII Interrupt Status Register 1 12h MISR1 MII Interrupt Status Register 2 13h MISR2 MII Interrupt Control Register 14h FCSCR Receive Error Counter Register 15h RECR Reserved Reserved Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Polarity Status False Carrier Sen Latch Signal Detect Descramb Lock Page Receive MII Interrupt Remote Fault Jabber Detect Auto-Neg Status Loopback Status Duplex Status Speed Status Link Status Power Save Mode Scrambler Bypass Reserved Loopback Fifo Depth COL FD Enable INT POL TINT INT_EN INT_OE Link Status Speed INT INT Duplex Mode INT Auto-Neg Comp INT FC HF INT RE HF INT Duplex Mode En Auto-Neg Comp En FC HF En RE HF En MDI Crossover INT Sleep Polarity INT Jabber INT Mode INT MDI Crossover EN Sleep Mode EN Polarity EN Jabber EN Receive Err Latch Page Received INT Loopback FIFO O/U INT Reserved Link Status Speed EN En Reserved Reserved Auto-Neg Error EN Page Received EN Loopback FIFO O/U EN Reserved FCS Count RX Err Count BIST Control Register 16h BISCR RMII Control & Status Register 17h RCSR LED Control Register 18h LEDCR PHY Control Register 19h PHYCR BIST Packet Length register 1Ah 10BTSCR BIST Control & Status Register 1 1Bh BICSR1 BIST Control & Status Register 2 1Ch BICSR2 RESERVED 1Dh Reserved Cable Diagnostic Control Register 1Eh CDCR Diagnostic Start Power Down Register 1Fh PDR Software Reset TX_CLK 42h TXCPSR Voltage Regulator Control Register D0h VRCR VRPD Cable Diagnostic Specific Control Register 170h CDSCR Reserved 46 Auto-Neg Error INT Bit 13 Reserved PRBS Count Mode Generate PRBS Packets Packet Gen Enable PRBS Checker Lock PRBS Packet Gen Checker Status SyncLoss Power Mode Reserved Transmit in MII Loopback Reserved Reserved Auto MDI/X Enable Force MDI/X Reserved Pause RX Status Blink Rate Pause TX Status MI Link Status Receiver TH LED Speed Polarity Reserved Squelch Reserved LED Link Polarity LED Activity Polarity Reserved Loopback Mode RMII Mode RMII Revision Drive LED Speed Drive LED Link Bypass LED Stretching LED CFG NLP Disable Reserved RMII OVF Status RMII UNF Status Drive LED Speed LED Activity ON/OFF ELAST BUF Link LED ON/OFF Activity LED ON/OFF PHY ADDR Polarity Status BIST Err Count Jabber Disable Reserved BIST IPG Length Reserved Packet Length Reserved Reserved Link Quality Link Quality Software Restart Diagnostic Done Reserved Reserved Phase Shift En Reserved Reserved Cross Disable Diagnostic Fail TPTD Bypass TPRD Bypass Reserved Average Cycles Register Block Phase Shift Value VR Control Reserved Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-3. Register Table, Extended Registers (continued) Register Name Cable Diagnostic Location Results Register 1-5 Cable Diagnostic Amplitude Results Register 1-5 Addr Tag 180h CDLRR1 181h CDLRR2 182h CDLRR3 183h CDLRR4 184h CDLRR5 185h CDLAR1 186h CDLAR2 187h CDLAR3 188h CDLAR4 189h CDLAR5 Cable Diagnostic General Results Register 18Ah CDGRR ALCD Control and Results 2 Register 215h ALCDRR2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved TPTD/RD Peak Location Reserved TPTD/RD Peak Amplitude Reserved TPTD/RD Peak Amplitude Cross TPTD Peak TPTD Peak TPTD Peak TPTD Peak TPTD Peak TPRD Peak TPRD Peak TPRD Peak TPRD Peak TPRD Peak Detect on Polarity 5 Polarity 4 Polarity 3 Polarity 2 Polarity 1 Polarity 5 Polarity 4 Polarity 3 Polarity 2 Polarity 1 TPTD alcd_out2 Cross Detect on TPRD Above 5 TPTD Peaks Above 5 TPTD Peaks alcd_out3 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 47 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1 www.ti.com Register Definition In * * * * * * * * * * * the register definitions under the `Default' heading, the following definitions hold true: COR = Clear on Read Jumper = Default value is loaded from strapping pin after reset LH = Latched High and held until read, based upon the occurrence of the corresponding event LL = Latched Low and held until read, based upon the occurrence of the corresponding event RO = Read Only access RO/COR = Read Only, Clear on Read RO/P = Read Only, Permanently set to a default value RW = Read Write access RW/SC = Read Write Access/Self Clearing bit SC = Register sets on event occurrence and Self-Clears when event ends SRW = Software Strap Mode RW - Bit is accessible only at Software strap mode, value of bit is latched after applying Config Done * SWS = Software Strap bit - Bit is always accessible. Written when accessed at soft strap mode; value is latched after applying Config Done, Otherwise, bit content is latched immediately 8.1.1 Basic Mode Control Register (BMCR) Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 BIT 15 BIT NAME Reset DEFAULT 0, RW/SC DESCRIPTION PHY Software Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. Writing a 1 to this bit resets the PHY . When the reset operation is done, this bit is cleared to 0 automatically. The configuration is relatched. 14 MII Loopback 0, RW MII Loopback: 1 = MII Loopback enabled. 0 = Normal operation. When MII loopback mode is activated, the transmitter data presented on MII TXD is looped back to MII RXD internally 13 Speed Selection Jumper, RW Speed Select: When auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100Mbs 0 = 10Mbs 12 Auto-Negotiation Enable Jumper, RW Auto-Negotiation Enable: Configuration pin (jumper) controls initial value at reset. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. 11 IEEE Power Down 0, RW Power Down: 1 = Enables IEEE power down mode 0 = Normal operation Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition. To control the power down mechanism, this bit is ORed with the input from the PWR_DWN/INT pin. When the active low PWR_DWN/INT is asserted, this bit is set. 10 48 Isolate 0, RW Isolate: Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 (continued) BIT BIT NAME DEFAULT DESCRIPTION 1 = Isolates the Port from the MII with the exception of the serial management. 0 = Normal operation. 9 Restart AutoNegotiation 0, RW/SC Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 8 Duplex Mode Jumper, RW Duplex Mode: When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. 7 Collision Test 0, RW Collision Test: 1 = Collision test enabled. 0 = Normal operation When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 49 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.2 www.ti.com Basic Mode Status Register (BMSR) Table 8-5. Basic Mode Status Register (BMSR), address 0x0001 BIT BIT NAME DEFAULT 15 100Base-T4 0, RO/P 14 100Base-TX Full Duplex 1, RO/P 100Base-TX Half Duplex 1, RO/P 10Base-T Full Duplex 1, RO/P 10Base-T Half Duplex 1, RO/P DESCRIPTION 100Base-T4 Capable: This protocol is not available. Always 0 = Device does not perform 100Base-T4 mode. 100Base-TX Full Duplex Capable: 1 = Device able to perform 100Base-TX in full duplex mode. 0 = Device not able to perform 100Base-TX in full duplex mode. 13 100Base-TX Half Duplex Capable: 1 = Device able to perform 100Base-TX in half duplex mode. 0 = Device not able to perform 100Base-TX in half duplex mode. 12 10Base-T Full Duplex Capable: 1 = Device able to perform 10Base-T in full duplex mode. 0 = Device not able to perform 10Base-T in full duplex mode. 11 10Base-T Half Duplex Capable: 1 = Device able to perform 10Base-T in half duplex mode. 0 = Device not able to perform 10Base-T in half duplex mode. 10: RESERVED 7 6 MF Preamble Suppression 0, RO RESERVED: Write as 0, read as 0. 1, RO/P Preamble suppression Capable: 1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. 0 = Device will not perform management transaction with preambles suppressed. 5 AutoNegotiation Complete 0, RO Auto-Negotiation Complete: 1 = Auto-Negotiation process complete. 0 = Auto-Negotiation process not complete (either still in process, disabled, or reset) 4 Remote Fault 0, RO/LH Remote Fault: 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault. 0 = No remote fault condition detected. 3 AutoNegotiation Ability 1, RO/P Link Status 0, RO/LL Auto Negotiation Ability: 1 = Device is able to perform Auto-Negotiation. 0 = Device is not able to perform Auto-Negotiation. 2 Link Status: 1 = Valid link established (for either 10 or 100Mbs operation). 0 = Link not established. 1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10Mbs mode. 1 = Jabber condition detected. 0 = No Jabber. condition detected. This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset. 0 Extended Capability 1, RO/P Extended Capability: 1 = Extended register capabilities. 0 = Basic register set capabilities only. The PHY Identifier Registers #1 and #2 together form a unique identifier for the TLK110. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. The IEEE-assigned OUI for Texas Instruments is 080028h. 50 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.1.3 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 PHY Identifier Register #1 (PHYIDR1) The PHY Identifier Registers #1 and #2 together form a unique identifier for the TLK110. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. The Texas Instruments IEEE-assigned OUI is 080028h. Table 8-6. PHY Identifier Register #1 (PHYIDR1), address 0x0002 BIT BIT NAME 15:0 OUI_MSB 8.1.4 DEFAULT DESCRIPTION <0010 0000 0000 0000>, RO/P OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h) are stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). PHY Identifier Register #2 (PHYIDR2) Table 8-7. PHY Identifier Register #2 (PHYIDR2), address 0x0003 BIT 15:10 9:4 3:0 BIT NAME OUI_LSB VNDR_MDL MDL_REV DEFAULT DESCRIPTION <101000>, RO/P OUI Least Significant Bits: <100001>, RO/P Vendor Model Number: <0001>, RO/P Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of this register respectively. The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). Model Revision Number: Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field is incremented for all major device changes. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 51 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.5 www.ti.com Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation. Table 8-8. Auto Negotiation Advertisement Register (ANAR), address 0x0004 BIT 15 BIT NAME DEFAULT NP 0, RW DESCRIPTION Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired. 14 RESERVED 13 RF 0, RO/P 0, RW RESERVED by IEEE: Writes ignored, Read as 0. Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected. 12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0 11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported. 1 = Asymmetric PAUSE implemented. . Advertise that the DTE/MAC has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of IEEE802.3u. 0 = Asymmetric PAUSE not implemented. Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B3, respectively. Pause resolution status is reported in PHYCR[13:12]. 10 PAUSE 0, RW PAUSE Support for Full Duplex Links: The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B. 1 = MAC PAUSE implemented. Advertise that the DTE (MAC) has implemented both the optional MAC control sub-layer and the pause function as specified in clause 31 and annex 31B of 802.3u. 0 = MAC PAUSE not implemented Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B3, respectively. Pause resolution status is reported in PHYCR[13:12]. 9 T4 0, RO/P 100Base-T4 Support: 1 = 100Base-T4 is supported by the local device. 0 = 100Base-T4 not supported. 8 TX_FD Jumper, RW 100Base-TX Full Duplex Support: 1 = 100Base-TX Full Duplex is supported by the local device. 0 = 100Base-TX Full Duplex not supported. 7 TX Jumper, RW 100Base-TX Support: 1 = 100Base-TX is supported by the local device. 0 = 100Base-TX not supported. 6 10_FD Jumper, RW 10Base-T Full Duplex Support: 1 = 10Base-T Full Duplex is supported by the local device. 0 = 10Base-T Full Duplex not supported. 5 10 Jumper, RW 10Base-T Support: 1 = 10Base-T is supported by the local device. 0 = 10Base-T not supported. 4:0 Selector <00001>, RW Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this port. <00001> indicates that this device supports IEEE 802.3u. 52 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.1.6 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 8-9. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x0005 BIT 15 BIT NAME NP DEFAULT 0, RO DESCRIPTION Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. 13 RF 0, RO Remote Fault: 1 = Remote Fault indicated by Link Partner. 0 = No Remote Fault indicated by Link Partner. 12 RESERVED 0, RO RESERVED for Future IEEE use: Write as 0, read as 0. 11 ASM_DIR 0, RO ASYMMETRIC PAUSE: 1 = Asymmetric pause is supported by the Link Partner. 0 = Asymmetric pause is not supported by the Link Partner. 10 PAUSE 0, RO PAUSE: 1 = Pause function is supported by the Link Partner. 0 = Pause function is not supported by the Link Partner. 9 T4 0, RO 100Base-T4 Support: 1 = 100Base-T4 is supported by the Link Partner. 0 = 100Base-T4 is not supported by the Link Partner. 8 TX_FD 0, RO 100Base-TX Full Duplex Support: 1 = 100Base-TX Full Duplex is supported by the Link Partner. 0 = 100Base-TX Full Duplex is not supported by the Link Partner. 7 TX 0, RO 100Base-TX Support: 1 = 100Base-TX is supported by the Link Partner. 0 = 100Base-TX is not supported by the Link Partner. 6 10_FD 0, RO 10Base-T Full Duplex Support: 1 = 10Base-T Full Duplex is supported by the Link Partner. 0 = 10Base-T Full Duplex is not supported by the Link Partner. 5 10 0, RO 10Base-T Support: 1 = 10Base-T is supported by the Link Partner 0 = 10Base-T is not supported by the Link Partner. 4:0 Selector <0 0000>, RO Protocol Selection Bits: Link Partner's binary encoded protocol selector. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 53 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.7 www.ti.com Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 8-10. Auto-Negotiate Expansion Register (ANER), address 0x0006 BIT BIT NAME 15:5 RESERVED 4 PDF DEFAULT DESCRIPTION 0, RO RESERVED: Writes ignored, Read as 0. 0, RO Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected. 3 LP_NP_ABLE 0, RO Link Partner Next Page Able: 1 = Link Partner does support Next Page. 0 = Link Partner does not support Next Page. 2 NP_ABLE 1, RO/P Next Page Able: 1 = Indicates local device is able to send additional Next Pages. 0 = Indicates local device is not able to send additional Next Pages. 1 PAGE_RX 0, RO/COR Link Code Word Page Received: 1 = Link Code Word has been received, cleared on a read. 0 = Link Code Word has not been received. 0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able: 1 = indicates that the Link Partner supports Auto-Negotiation. 0 = indicates that the Link Partner does not support Auto-Negotiation. 54 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.1.8 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Auto-Negotiate Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x0007 BIT BIT NAME 15 NP DEFAULT 0, RW DESCRIPTION Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired. 14 RESERVE D 0, RO RESERVED: Writes ignored, read as 0. 13 MP 1, RW Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RW Acknowledge2: 1 = Will comply with message. 0 = Cannot comply with message. Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. 11 TOG_TX 0, RO Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was 0. 0 = Value of toggle bit in previously transmitted Link Code Word was 1. Toggle is used by the Arbitration function within Auto-Negotiation to synchronize with the Link Partner during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word. 10:0 CODE <000 0000 0001>, RW This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 55 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.9 www.ti.com Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-12. Auto-Negotiation Link Partner Ability Register Next Page (ANLNPTR), address 0x0008 BIT 15 BIT NAME DEFAULT NP 0, RO DESCRIPTION Next Page Indication: 1 = No other Next Page Transfer desired. 0 = Another Next Page desired 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Auto-Negotiation state machine automatically controls this bit based on the incoming FLP bursts. Software should not attempt to write to this bit. 13 MP 1, RO Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RO Acknowledge2: 1 = Link Partner has the ability to comply to next-page message. 0 = Link Partner cannot comply to next-page message. Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. 11 Toggle 0, RO Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was 0. 0 = Value of toggle bit in previously transmitted Link Code Word was 1. Toggle is used by the Arbitration function within Auto-Negotiation to synchronize with the Link Partner during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word. 10:0 CODE <000 0000 0001>, RO Code: This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u. 56 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.10 SW Strap Control register 1 (SWSCR1) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the "Config Done" - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers. Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 BIT BIT NAME 15 SW Strap Config Done DEFAULT 0, RW DESCRIPTION Software Strap Configuration Done: 1 = SW Strap configuration is complete, and the PHY can continue and complete its internal reset sequence. 0 = SW strap configuration process is not complete. 14 Auto MDI-X Enable Jumper, SRW Auto MDI/MDIX Enable: 1 = Enable automatic crossover. 0 = Disable automatic crossover. This bit determines whether Automatic MDI/MDIX crossover is enabled or not. If Strapping Pin configuration is override, the value of this register is latched at RESET to bit 15 of PHYCR register (0x0019) and defines its value. 13 AutoNegotiation Enable Jumper, SRW Auto-Negotiation Enable: 1 = Auto-Negotiation Enabled. 0 = Auto-Negotiation Disabled - Force mode is active. This bit determines whether Auto-negotiation is enabled. 12:11 AN[1:0] Jumper, SRW Auto-Negotiation Mode [1:0]: ANEN AN1 AN0 0 0 0 10Base-T, Half-Duplex Forced Mode 0 0 1 10Base-T, Full-Duplex 0 1 0 100Base-TX, Half-Duplex 0 1 1 100Base-TX, Full-Duplex ANEN AN1 AN0 1 0 0 10Base-T, Half/Full-Duplex 1 0 1 100Base-TX, Half/Full-Duplex 1 1 0 10Base-T,Half-Duplex 100Base-TX, Half-Duplex 1 1 1 10Base-T,Half/Full-Duplex 100Base-TX, Half/Full-Duplex Advertised Mode If the Strapping Pin configuration is override, the decoded value of these 3 register bits are latched at RESET to the appropriate bits of BMCR (0x0000) and ANAR (0x0004) and define their values. 10 LED_CFG Jumper, SRW LED Configuration: 1 = Select LED configuration Mode 1 0 = Select LED configuration Mode 2 or 3 according to LEDCR register (0x0018) bit 5 and 6. If the Strapping Pin configuration is override, the value of this register is latched at RESET to bit 5 of LEDCR register (0x0018) and defines its value. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 57 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 (continued) BIT 9 BIT NAME RMII Enhanced Mode DEFAULT 0, SWS, RW DESCRIPTION RMII Enhanced Mode: 1 = Enable RMII Enhanced Mode. 0 = RMII operates in normal mode. In normal mode, If the line is not idle CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to "2". This situation remains for the duration of the receive event. While in enhanced mode, CRS_DV is disqualified and de-asserted when the False Carrier detected. This also remains for the duration of the receive event. In addition in normal mode, the start of the packet is intact. Each symbol error is indicated by setting RX_ER high. The data on RXD is replaced with "1" starting with the first symbol error. While in enhanced mode, the CRS_DV is de-asserted with the first symbol error. 8 TDR AUTORUN 0, SWS, RW TDR Auto Run at link down: 1 = Enable execution of TDR procedure after link down event. 0 = Disable automatic execution of TDR. 7 Link Loss Recovery 0, SWS, RW Link Loss Recovery: 1 = Enable Link Loss Recovery mechanism. This mode allow recovery from short interference and continue to hold the link up for period of additional few mSec till the short interference will gone and the signal is OK. 0 = Normal Link Loss operation. Link status will go down approximately 250uSec from signal loss. 6 Fast Auto MDI-X 0, SWS, RW Fast Auto MDI/MDIX: 1 = Enable Fast Auto MDI/MDIX mode. 0 = Normal Auto MDI/MDIX mode. If both link partners are configured to work in Force 100Base-TX mode (Auto-Negotiation is disabled), this mode enables Automatic MDI/MDIX resolution in a short time. 5 Robust Auto MDI-X 0, SWS, RW Robust Auto MDI-X : 1 = Enable Robust Auto MDI/MDIX resolution. 0 = Normal Auto MDI/MDIX mode. If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg vs. Force 100Base-TX or Force 100Base-TX vs. Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock. 4 Fast AN En 0, SWS, RW Fast AN En: 1 = Enabe Fast Auto-Negotiation mode - The PHY auto-negotiates using Timer setting according to Fast AN Sel bits (bits 3:2 this register) 0 = Disabe Fast Auto-Negotiation mode - The PHY auto-negotiates using normal Timer setting Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. Note: When using this option care must be taken to maintain proper operation of the system. While shortening these timer intervals may not cause problems in normal operation, there are certain situations where this may lead to problems. 58 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 (continued) BIT BIT NAME 3:2 Fast AN Sel DEFAULT 0, SWS, RW DESCRIPTION Fast Auto-Negotiation Select bits: Fast AN Select Break Link Timer Link Fail Inhibit Timer Auto-Neg Wait Timer <00> 80 50 35 <01> 120 75 50 <10> 240 150 100 <11> NA NA NA Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. In Fast AN mode, both PHYs should be configured to the same configuration. These 2 bits define the duration for each state of the Auto Negotiation process according to the table above. The new duration time must be enabled by setting "Fast AN En" - bit 4 of this register. Note: Using this mode in cases where both link partners are not configured to the same Fast Auto-negotiation configuration might produce scenarios with unexpected behavior. 1 Fast RXDV Detection 0, SWS, RW Fast RXDV Detection: 1 = Enable assertion high of RXDV on receive packet due to detection of /J/ symbol only. If a consecutive /K/ does not appear, RXERR is generated. 0 = Disable Fast RXDV detection. The PHY operates in normal mode - RXDV assertion after detection of /J/K/. 0 INT OE Jumper, SRW CodINTN Enableve: 1 = PWR_DWN/INTN Pin is an open-drain Interrupt Output. 0 = PWR_DWN/INTN Pin is active-low Power Down input. The value of this register bit is latched at RESET to bit 0 of MICR register (0x0011) and defines its value. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 59 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 8.1.11 SW Strap Control register 2 (SWSCR2) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the "Config Done" - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers. Table 8-14. SW Strap Control register 2 (SWSCR2), address 0x000A BIT BIT NAME DEFAULT DESCRIPTION 15:14 RESERVED 0, RO 13:7 RESERVED 0, SWS, RW RESERVED Fast Link-Up in Parallel Detect 0, SWS, RW Fast Link-Up in Parallel Detect Mode: 6 RESERVED: Writes ignored, read as 0. 1 = Enable Fast Link-Up time During Parallel Detection 0 = Normal Parallel Detection link establishment In Fast Auto MDI-X and in Robust Auto MDI-X modes (bits 6 and 5 in register SWSCR1), this bit is automatically set. 5 Extended FD Ability 0, SWS, RW Extended Full-Duplex Ability: 1 = Force Full-Duplex while working with link partner in forced 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated in Force 100B-TX, the link is always Full Duplex 0 = Disable Extended Full Duplex Ability. Decision to work in Full Duplex or Half Duplex mode follows IEEE specification. 4 Enhanced LED Link 0, SWS, RW Enhanced LED Link Functionality: 1 = LED Link is ON only when link is established in 100B-TX Full Duplex mode. 0 = LED Link is ON when link is established. 3 Isolate MII in 100BT HD 0, SWS, RW Isolate MII outputs when FD Link @ 100BT is not achievable: 1 = When HD link established in 100B-TX MII outputs are isolated. 0 = Normal MII outputs operation 2 RXERR During IDLE 1, SWS, RW Detection of Receive Symbol Error During IDLE State: 1 = Enable detection of Receive symbol error during IDLE state. 0 = Disable detection of Receive symbol error during IDLE state. 1 Odd-Nibble Detection Disable 0, SWS, RW Detection of Transmit Error: 1 = Disable detection of transmit error in odd-nibble boundary. 0 = Enable detection of de-assertion of TX_EN on an odd-nibble boundary. In this case TX_EN is extended by one additional TX_CLK cycle and behaves as if TX_ERR were asserted during that additional cycle. 0 RMII Receive Clock 0, SWS, RW RMII Receive Clock: 1 = RMII Data (RXD [1:0]) is sampled and referenced to RXCLK. 0 = RMII Data (RXD [1:0]) is sampled and referenced to XI. 60 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.1.12 Software Strap Control Register 3 (SWSCR3) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the "Config Done" - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers. Table 8-15. SW Strap Control register 3 (SWSCR3), address 0x000B BIT BIT NAME 15:7 RESERVED 6 Polarity Swap DEFAULT 0, RO 0, SWS, RW DESCRIPTION RESERVED: Writes ignored, read as 0. Polarity Swap: 1 = Inverted polarity on both pairs: TPTD+ TPTD-, TPRD+ TPRD0 = Normal polarity Port Mirror function: To Enable port mirroring, set bit 5 and this bit high. 5 MDI/MDIX Swap 0, SWS, RW MDI/MDIX Swap: 1 = Swap MDI pairs (Receive on TPTD pair, Transmit on TPRD pair) 0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair) Port Mirror function: To Enable port mirroring, set this bit and bit 6 high. 4 Bypass 4B/5B 0, SWS, RW Bypass 4B/5B Encoder/Decoder Functionality: 1 = Bypass the 4B/5B Encoder in TX path and the Decoder in RX path to allow direct 5-bit TX and 5-bit RX interface to/from the MAC. In the TX path, the additional TXD [4] input pin is the TDI (pin 12) and in the RX path, the additional RXD [4] output pin is the RXERR (pin 41). Note: The PHY must be configured to operate in MII mode. 0 = Normal operation 3:0 Fast Link Down Mode 0, SWS, RW Fast Link Down Modes: Bit 3 Drop the link based on RX Error count of the MII interface - When a predefined number of 32 RX Error occurrences in a 10s interval is reached, the link will be dropped. Bit 2 Drop the link based on MLT3 Errors count (Violation of the MLT3 coding in the DSP output) - When a predefined number of 20 MLT3 Error occurrences in a 10s interval is reached, the link will be dropped. Bit 1 Drop the link based on Low SNR Threshold - When a predefined number of 20 Threshold crossing occurrences in a 10s interval is reached, the link will be dropped. Bit 0 Drop the link based on Signal/Energy loss indication - When the Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10s. The Fast Link Down function is an OR of all these 4 options, so the designer can enable combinations of these conditions. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 61 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.2 www.ti.com Extended Register Addressing REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set using indirect addressing. * REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set. * REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. The address register contents (pointer) remain unchanged. * REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented. * REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged. 8.2.1 Register Control Register (REGCR) This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of ADDAR (0x000E) register to the appropriate MMD. It also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. It also contains selection bits (15:14) for the address auto-increment mode of ADDAR. Table 8-16. Register Control Register (REGCR), address 0x000D BIT BIT NAME 15:1 Function 4 DEFAULT DESCRIPTION 0, RW 00 01 10 11 13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 4:0 0, RW Device Address: In general, these bits [4:0] are the device address DEVAD that directs any accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the TLK110 uses the vendor specific DEVAD [4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR should use this DEVAD. Transactions with other DEVAD are ignored. 8.2.2 DEVAD = Address = Data, no post increment = Data, post increment on read and write = Data, post increment on write only Address or Data Register (ADDAR) This register is the address/data MMD register. It is used in conjunction with REGCR register (0x000D) to provide the access by indirect read/write mechanism to the extended register set. Table 8-17. Data Register (ADDAR), address 0x000E BIT BIT NAME 15:0 Addr/data 62 DEFAULT 0, RW DESCRIPTION If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data register Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.3 8.3.1 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Extended Registers PHY Status Register (PHYSTS) This register provides quick access to commonly accessed PHY control status and general information. Table 8-18. PHY Status Register (PHYSTS), address 0x0010 BIT NAME DEFAULT 15 RESERVED 0, RO RESERVED: Writes ignored, read as 0. DESCRIPTION 14 MDI-X Mode 0,RO MDI-X mode as reported by the Auto-Negotiation state machine: 1= MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) 0= MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX algorithm swaps between MDI and MDI-X configurations. 13 Receive Error Latch 0,RO/LH Receive Error Latch: 1= Receive error event has occurred since last read of RXERCNT register (0x0015). 0= No receive error event has occurred. This bit will be cleared upon a read of the RECR register. 12 Polarity Status 0,RO Polarity Status: 1= Inverted Polarity detected. 0= Correct Polarity detected. This bit is a duplication of bit 4 in the 10BTSCR register (0x001A). This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register. 11 False Carrier Sense Latch 0,RO/LH False Carrier Sense Latch: 1= False Carrier event has occurred since last read of FCSCR register (0x0014). 0= No False Carrier event has occurred. This bit will be cleared upon a read of the FCSR register. 10 Signal Detect 0,RO/LL Signal Detect: Active high 100Base-TX unconditional Signal Detect indication from PMD. 9 Descrambler Lock 0,RO/LL Descrambler Lock: Active high 100Base-TX Descrambler Lock indication from PMD. 8 Page Received 0,RO Link Code Word Page Received: 1= A new Link Code Word Page has been received. This is a duplicate of Page Received (bit 1) in the ANER register and it is cleared on read of the ANER register (0x0006). 0= Link Code Word Page has not been received. This bit will not be cleared upon a read of the PHYSTS register. 7 6 5 MII Interrupt Remote Fault Jabber Detect 0,RO 0,RO 0,RO MII Interrupt Pending: 1= Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the MISR Register (0x0012). Reading the MISR will clear this Interrupt bit indication. 0= No interrupt pending. Remote Fault: 1= Remote Fault condition detected. Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. Cleared on read of BMSR register (0x0001) or by reset. 0= No remote fault condition detected. Jabber Detect: 1= Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of the Jabber Detect bit in the BMSR register (0x0001). 0= No Jabber. This bit will not be cleared upon a read of the PHYSTS register. 4 Auto-Neg Status 0,RO Auto-Negotiation Status: Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 63 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com Table 8-18. PHY Status Register (PHYSTS), address 0x0010 (continued) BIT NAME DEFAULT DESCRIPTION 1= 0= 3 MII Loopback Status 0,RO MII Loopback: 1= 0= 2 Duplex Status 0,RO Auto-Negotiation complete. Auto-Negotiation not complete. Loopback active (enabled). Normal operation. Duplex Status: 1= Full duplex mode. 0= Half duplex mode. This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. Therefore, it is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 1 Speed Status 0,RO Speed Status: 1= 10 Mb/s mode. 0= 100 Mb/s mode. This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes. It is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 0 Link Status 0,RO Link Status: 1= Valid link established (for either 10 or 100 Mb/s operation). This bit is a duplicate of the Link Status bit in the BMSR register (0x0001), 0= Link not established. This bit will not be cleared upon a read of the PHYSTS register. 8.3.2 PHY Specific Control Register (PHYSCR) This register implements the PHY Specific Control register. This register allows access to general functionality inside the PHY to enable operation in reduced power modes and control interrupt mechanism. Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011 BIT NAME DEFAULT DESCRIPTION 15 Disable PLL 0,RW Disable PLL: 1= Disable internal clocks Circuitries 0= Normal mode of operation Note: Clocks Circuitries could be disabled only in IEEE power down mode 14 PS Enable 13:12 PS Modes 64 0,RW <00>,RW Power Save Modes Enable: 1= Enable power save modes 0= Normal mode of operation Power Saves Modes: Power Mode Name Description <00> Normal Normal operation mode. PHY is fully functional <01> IEEE power down Low Power mode that shut down all internal circuitry beside SMI functionality. <10> Active Sleep Low Power Active WOL mode that shut down all internal circuitry beside SMI and energy detect functionalities. In this mode the PHY sends NLP every 1.4 Sec to wake up link-partner. Automatic power-up is done when link partner is detected. <11> Passive Sleep Low Power WOL mode that shut down all internal circuitry beside SMI and energy detect functionalities. Automatic power-up is done when link partner is detected. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011 (continued) BIT NAME DEFAULT DESCRIPTION 11 Scrambler Bypass 0,RW Scrambler Bypass: 1= Scrambler bypass enabled. 0= Scrambler bypass disabled 10 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 9:8 Loopback FIFO Depth <01>,RW Far-End Loopback FIFO Depth: <00> = 4 nibbles FIFO. <01> = 5 nibbles FIFO. <10> = 6 nibbles FIFO. <11> = 8 nibbles FIFO. This FIFO is used to adjust RX (recovered) clock rate to TX clock rate. FIFO depth need to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles. 7:5 4 3 2 RESERVED <000>, RO RESERVED: Writes ignored, read as 0. COL FD Enable 0, RW Collision in Full-Duplex Mode: INT POL tint 1,RW 0,RW 1= Enable generating Collision signaling in Full Duplex 0= Disable Collision indication in Full Duplex mode. Collision will be active in Half Duplex only. Interrupt Polarity: 1= Steady state (normal operation) is 1 logic and during interrupt is 0 logic. 0= Steady state (normal operation) is 0 logic and during interrupt is 1 logic. Test Interrupt: 1= Generate an interrupt 0= Do not generate interrupt Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set. 1 INT_EN 0,RW Interrupt Enable: 1= Enable event based interrupts 0= Disable event based interrupts Enable interrupt dependent on the event enables in the MISR register (0x0012). 0 INT_OE 0,RW Interrupt Output Enable: 1= PWR_DOWN/INT is an Interrupt Output 0= PWR_DOWN/INT is a Power Down Enable active low interrupt events via the PWR_DOWN/INTN pin by configuring the PWR_DOWN/INT pin as an output. 8.3.3 MII Interrupt Status Register 1 (MISR1) This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled. Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 BIT 15:14 NAME DEFAULT RESERVED <00>, RO DESCRIPTION RESERVED: Writes ignored, read as 0. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 65 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 (continued) BIT DEFAULT DESCRIPTION 13 Link Status Changed INT NAME 0,RO, COR Change of Link Status interrupt: 1 = Change of link status interrupt is pending. 0 = No change of link status. 12 Speed Changed INT 0,RO, COR Change of Speed Status interrupt: 1 = Change of speed status interrupt is pending. 0 = No change of speed status. 11 Duplex Mode Changed INT 0,RO, COR Change of duplex status interrupt: 1 = Duplex status change interrupt is pending. 0 = No change of duplex status. 10 Auto-Negotiation Completed INT 0,RO, COR Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending. 0 = No Auto-negotiation complete event is pending. 9 FC HF INT 0,RO, COR False Carrier Counter half-full interrupt: 1 = False carrier counter (Register FCSCR, address 0x0014) exceeds halffull interrupt is pending. 0 = False carrier counter half-full event is not pending. 8 RE HF INT 0,RO, COR Receive Error Counter half-full interrupt: 1 = Receive error counter (Register RECR, address 0x0015) exceeds half full interrupt is pending. 0 = No Receive error counter half full event pending. 7:6 RESERVED <00>, RO RESERVED: Writes ignored, read as 0. 5 Link Status Changed EN 0, RW Enable Interrupt on change of link status 4 Speed Changed EN 0, RW Enable Interrupt on change of speed status 3 Duplex Mode Changed EN 0, RW Enable Interrupt on change of duplex status 2 Auto-Negotiation Completed EN 0, RW Enable Interrupt on Auto-negotiation complete event 1 FC HF EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event 0 RE HF EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event 8.3.4 MII Interrupt Status Register 2 (MISR2) This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled. Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013 BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0, RO 14 AN Error INT 0,RO, COR Auto-Negotiation Error Interrupt: 1 = Auto-negotiation error interrupt is pending. 0 = No Auto-negotiation error event pending. 13 Page Rec INT 0,RO, COR Page Receive Interrupt: 1 = Page has been received. 0 = Page has not been received. 12 Loopback FIFO OF/UF INT 0,RO, COR Loopback FIFO Overflow/Underflow Event Interrupt: 1 = FIFO Overflow/Underflow event interrupt pending. 0 = No FIFO Overflow/Underflow event pending. 11 MDI Crossover Changed INT 0,RO, COR MDI/MDIX Crossover Status Changed Interrupt: 1 = MDI crossover status changed interrupt is pending. 0 = MDI crossover status has not changed. 10 Sleep Mode INT 0,RO, COR Sleep Mode Event Interrupt: 1 = Sleep Mode event interrupt is pending. 0 = No sleep mode event pending. 66 RESERVED: Writes ignored, read as 0. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013 (continued) BIT NAME DEFAULT Polarity Changed INT 8 Jabber Detect INT 0,RO Jabber Detect Event Interrupt: 1 = Jabber detect event interrupt pending. 0 = No Jabber detect event pending 7 RESERVED 0,RW RESERVED: Writes ignored, read as 0. 6 AN Error EN 0,RW Enable Interrupt on Auto-Negotiation error event 5 Page Rec EN 0,RW Enable Interrupt on page receive event 4 Loopback FIFO OF/UF EN 0,RW Enable Interrupt on loopback FIFO overflow/underflow event 3 MDI Crossover Changed EN 0,RW Enable Interrupt on change of MDI/X status 2 Sleep Mode Event EN 0,RW Enable Interrupt sleep mode event 1 Polarity Changed EN 0,RW Enable Interrupt on change of polarity status 0 Jabber Detect EN 0,RW Enable Interrupt on Jabber detection event 8.3.5 0,RO, COR DESCRIPTION 9 Polarity Changed Interrupt: 1 = Data polarity changed interrupt pending. 0 = No Data polarity event pending. False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the "False Carriers" attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 8-22. False Carrier Sense Counter Register (FCSCR), address 0x0014 BIT NAME 15:8 RESERVED 7:0 FCSCNT DEFAULT DESCRIPTION <0000 0000>, RO RESERVED: Writes ignored, read as 0. 0,RO / COR False Carrier Event Counter: This 8-bit counter increments on every false carrier event. This counter stops when it reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt event is generated. This register is cleared on read. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 67 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.3.6 www.ti.com Receiver Error Counter Register (RECR) This counter provides information required to implement the "Symbol Error During Carrier" attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification. Table 8-23. Receiver Error Counter Register (RECR), address 0x0015 BIT 15:0 8.3.7 BIT NAME RX Error Count DEFAULT DESCRIPTION 0, RO, / COR RX_ER Counter: When a valid carrier is present (only while RXDV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in MII loopback mode. The counter stops when it reaches its maximum count of FFFFh. When the counter exceeds half-full (7FFFh), an interrupt is generated. This register is cleared on read. BIST Control Register (BISCR) This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register. Table 8-24. BIST Control Register (BISCR), address 0x0016 BIT NAME DEFAULT DESCRIPTION 15 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 14 PRBS Count Mode 0, RW PRBS Single/Continues Mode: 1 = Continuous mode, the PRBS counters reaches max count value, pulse is generated and counter starts counting from zero again. 0 = Single mode, When BIST Error Counter reaches its max value, PRBS checker stops counting. 13 Generate PRBS Packets 0, RW Generated PRBS Packets: 1 = When packet generator is enabled, generate continuous packets with PRBS data. When packet generator is disabled, PRBS checker is still enabled. 0 = When packet generator is enabled, generate single packet with constant data. PRBS gen/check is disabled. 12 Packet Generation Enable 0, RW Packet Generation Enable: 1 = Enable packet generation with PRBS data 0 = Disable packet generator 11 PRBS Checker Lock 0,RO PRBS Checker Lock Indication: 1 = PRBS checker is locked and synced on received bit stream 0 = PRBS checker is not locked 10 PRBS Checker Sync Loss 0,RO,LH PRBS Checker Sync Loss Indication: 1 = PRBS checker lose sync on received bit stream - This is an error indication. 0 = PRBS checker is not locked 9 Packet Gen Status 0,RO Packet Generator Status Indication: 1 = Packet Generator is active and generate packets. 0 = Packet Generator is off. 8 Power Mode 0,RO Sleep Mode Indication: 1 = Indicate that the PHY is in normal power mode. 0 = Indicate that the PHY is in one of the sleep modes, either active or passive. 7 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 6 Transmit in MII Loopback 0, RW Transmit Data in MII Loop-back Mode (valid only at 100BT): 1 = Enable transmission of the data from the MAC received on the TX pins to the line in parallel to the MII loopback to RX pins. This bit may be set only in MII Loopback mode - setting bit 14 in BMCR register (0x0000). 0 = Data is not transmitted to the line in MII loopback 68 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-24. BIST Control Register (BISCR), address 0x0016 (continued) BIT 5 4:0 NAME DEFAULT DESCRIPTION RESERVED 0, RO RESERVED: Must be 0 Loopback Mode 0, RW Loop-back Mode Select: The PHY provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK110 digital and analog data path Near-end Loopbacks [00001] - PCS Input Loopback [00010] - PCS Output Loopback (In 100Base-TX only) [00100] - Digital Loopback [01000] - Analog Loopback (requires 100 termination) Far-end Loopback: [10000] - Reverse Loopback 8.3.8 RMII Control and Status Register (RCSR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 8-25. RMII Control and Status Register (RCSR), address 0x0017 BIT NAME 15:6 RESERVED <0000 0000 00>0,RO RESERVED: Writes ignored, read as 0. 5 RMII Mode 0,RW, Strap RMII Mode Enable: 1 = Enable RMII (Reduced MII) mode of operation 0 = Enable MII mode of operation 4 RMII Revision Select 0,RW RMII Revision Select: 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet. 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS. 3 RMII OVFL Status 0,COR RX FIFO Over Flow Status: 1 = Normal 0 = Overflow detected 2 RMII OVFL Status 0,COR RX FIFO Under Flow Status: 1 = Normal 0 = Underflow detected 1:0 ELAST_FUB DEFAULT <01>,RW DESCRIPTION Receive Elasticity Buffer Size: This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at 50ppm accuracy for both RMII and Receive clocks. For greater frequency tolerance the packet lengths may be scaled (i.e. for 100ppm, the packet lengths need to be divided by 2). <00> = 14 bit tolerance (up to 16800 byte packets) <01> = 2 bit tolerance (up to 2400 byte packets) <10> = 6 bit tolerance (up to 7200 byte packets) <11> = 10 bit tolerance (up to 12000 byte packets) Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 69 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.3.9 www.ti.com LED Control Register (LEDCR) This register provides the ability to directly manually control any or all LED outputs. Table 8-26. LED Control Register (LEDCR), address 0x0018 BIT NAME 15:11 RESERVED 10:9 Blink Rate DEFAULT DESCRIPTION <0000 0>, ro RESERVED: Writes ignored, read as 0. <10>,RW LED Blinking Rate (ON/OFF duration): 00 = 20 Hz (50mSec) 01 = 10 Hz (100mSec) 10 = 5 Hz(200mSec) 11 = 2 Hz(500mSec) 8 LED Speed Polarity 1,RW, Strap LED Speed Polarity Setting: 1 = Active High polarity setting. 0 = Active Low polarity setting. Speed LED's polarity defined by strapping value of this pin. This register allows override of this strapping value. 7 LED Link Polarity 1,RW, Strap LED Link Polarity Setting: 1 = Active High polarity setting. 0 = Active Low polarity setting. Link LED's polarity defined by strapping value of this pin. This register allows override of this strapping value. 6 LED Active Polarity 1,RW, Strap LED Activity Polarity Setting: 1 = Active High polarity setting. 0 = Active Low polarity setting. Activity LED's polarity defined by strapping value of this pin. This register allows override of this strapping value. 5 Drive Speed LED 0,RW Drive LED Speed to the forced On/Off setting defied in bit 2: 1 = Drive value of On/Off bit onto LED_SPEED output pin. 0 = Normal operation. 4 Drive Link LED 0,RW Drive LED Link to the forced On/Off setting defied in bit 1: 1 = Drive value of On/Off bit onto LED_LINK output pin. 0 = Normal operation. 3 Drive Active LED 0,RW Drive LED Activity to the forced On/Off setting defied in bit 0: 1 = Drive value of On/Off bit onto LED_ACT output pin. 0 = Normal operation. 2 Speed LED On/Off Setting 0,RW Value to force on Speed LED output 1 Link LED On/Off Setting 0,RW Value to force on Link LED output 0 Act LED On/Off Setting 0,RW Value to force on Activity LED output 8.3.10 PHY Control Register (PHYCR) This register provides the ability to control and set general functionality inside the PHY. Table 8-27. PHY Control Register (PHYCR), address 0x0019 BIT NAME DEFAULT 15 Auto MDI/X Enable 1,RW,Strap Auto-MDIX Enable: 1 = Enable Auto-negotiation Auto-MDIX capability. 0 = Disable Auto- negotiation Auto-MDIX capability. 14 Force MDI/X 0,RW Force MDIX: 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair) 0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair) 13 Pause RX Status 0,RO Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. 12 Pause TX Status 0,RO Pause Transmit Negotiated Status: Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiated Highest Common Denominator is a full duplex technology. 70 DESCRIPTION Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued) BIT NAME DEFAULT 11 MI Link Status 0,RO MII Link Status: 1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation. 0 = No active link of 100BT Full-duplex, established using Auto-Negotiation. 10:8 RESERVED <000>, RO RESERVED: Writes ignored, read as 0. 7 Bypass LED Stretching 0,RW Bypass LED Stretching: 1 = Bypass LED stretching. 0 = Normal LED operation. This will bypass the LED stretching and the LEDs will reflect the internal value. 6:5 LED CFG <0>,RW <0>,RW,Strap LED Configuration Modes: 4:0 PHY ADDR <0000 0>,RO DESCRIPTION Mode LED_CFG[1] LED_CFG[0] LED_LINK 1 Don't Care 1 ON for Good Link OFF for No Link LED_SPEED ON Pulse for Activity OFF for No Activity LED_ACT 2 0 0 ON for Collision OFF for No Collision 3 1 0 ON in 100 Mb/s ON for Good Link OFF in 10 Mb/s BLINK for Activity ON for Full Duplex OFF for Half Duplex PHY Address: Strapping configuration for PHY Address. 8.3.11 10Base-T Status/Control Register (10BTSCR) This register provides the ability to control and read status of the PHY's internal 10Base-T functionality. Table 8-28. 10Base-T Status/Control Register (10BTSCR), address 0x001A BIT NAME DEFAULT 15:14 RESERVED <000>, RO RESERVED: Writes ignored, read as 0. 13 Receiver TH 0,RW Lower Receiver Threshold Enable: 1 = Enable 10Base-T lower receiver threshold to allow operation with longer cables 0 = Normal 10Base-T operation. Squelch <0000>,RW Squelch Configuration: Used to set the Peak Squelch `ON' threshold for the 10Base-T receiver. Every step is equal to 50mV and allow raising/lowering the Squelch threshold from 200mV to 600mV. The default Squelch threshold is set to 200mV. 8 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 7 NLP Disable 0,RW NLP Transmission Control: 1 = Disable transmission of NLPs. 0 = Enable transmission of NLPs. 6:5 RESERVED <00>, RO RESERVED: Writes ignored, read as 0. Polarity Status 0,RO 10Mb Polarity Status: 1 = Inverted Polarity detected. 0 = Correct Polarity detected. This bit is a duplication of bit 12 in the PHYSTS register (0x0010). Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register. RESERVED <000>, RO RESERVED: Writes ignored, read as 0. 12:9 4 3:1 0 Jabber Disable 0,RW DESCRIPTION Jabber Disable: 1 = Jabber function disabled. 0 = Jabber function enabled. Note: This function is applicable only in 10Base-T Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 71 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 8.3.12 BIST Control and Status Register 1 (BICSR1) This register provides the total number of error bytes that was received by the PRBS checker and defines the Inter packet Gap (IPG) for the packet generator. Table 8-29. BIST Control and Status Register 1 (BICSR1), address 0x001B DEFAULT DESCRIPTION 15:8 BIT BIST Error Count BIT NAME 0, RO BIST Error Count: Holds number of erroneous bytes that were received by the PRBS checker. Value in this register is locked when write is done to bit[0] or bit[1] (see below). When PRBS Count Mode set to zero, count stops on 0xFF. See BISCR register (0x0016) for further details Note: Writing "1" to bit 15 will lock counter's value for successive read operation and clear the BIST Error Counter. 7:0 BIST IPG Length <0111 1101>, RW BIST IPG Length: Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D which is equal to 125 bytes 8.3.13 BIST Control and Status Register2 (BICSR2) This register allows programming the length of the generated packets in bytes for the BIST mechanism. Table 8-30. BIST Control and Status Register 2 (BICSR2), address 0x001C BIT BIT NAME DEFAULT DESCRIPTION 15:11 RESERVED <0000 0>, RO 10:0 BIST Packet Length 0X5DC,RW 8.4 8.4.1 RESERVED: Writes ignored, read as 0. BIST Packet Length: Length of the generated BIST packets. The value of this register defines the size (in bytes) of every packet that generated by the BIST. Default value is 0x5DC which is equal to 1500 bytes Cable Diagnostic Registers Cable Diagnostic Control Register (CDCR) This register provides ability to the system to reset or restart the PHY by register access. Table 8-31. Cable Diagnostic Control Register (CDCR), address 0x001E BIT NAME DEFAULT FUNCTION 15 Diagnostic Start 0,RW Cable Diagnostic Process Start: 1 = Start execute cable measurement 0 = Cable Diagnostic is disabled Diagnostic Start bit is cleared with raise of Diagnostic Done indication. <000 00>,RO RESERVED: Writes ignored, read as 0. 14:10 RESERVED 72 9:8 Link Quality <<00>,RO Link Quality Indication <00> = Reserved <01> = Good Quality Link Indication <10> = Mid Quality Link Indication <11> = Poor Quality Link Indication The value of these bits are valid only when link is active - While reading "1" from "Link Status" bit 0 on PHYSTS register (0x0010). 7:4 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 3:2 RESERVED 00>,RO RESERVED: Writes ignored, read as 0. 1 Diagnostic Done 0,RO Cable Diagnostic Process Done: 1 = Indication that cable measurement process completed 0 = Diagnostic has not completed 0 Diagnostic Fail Cable Diagnostic Process Fail: 1 = Indication that cable measurement process failed 0 = Diagnostic has not failed 0,RO Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.4.2 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 PHY Reset Control Register (PHYRCR) This register provides ability to the system to reset or restart the PHY by register access. Table 8-32. PHY Reset Control Register (PHYRCR), address 0x001F BIT NAME DEFAULT FUNCTION 15 Software Reset 0, RW,SC Software Reset: 1 = Reset PHY. Allow the system to reset the PHY using register access. This bit is self cleared and has same effect as Hardware reset pin. 0 = Normal Operation. 14 Software Restart 0, RW,SC Software Restart: 1 = Reset PHY. Allow the system to restart the PHY using register access. This bit is self cleared and resets all PHY circuitry except the registers. 0 = Normal Operation. <00 0000 0000 0000>, RO Writes ignored, read as 0. 13:0 RESERVED 8.4.3 TX_CLK Phase Shift Register (TXCPSR) This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems, therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value greater than 10 is written, the update value will be the written value modulo 10. Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042 BIT NAME DEFAULT 15:5 RESERVED <0000 0000 000>, RO FUNCTION RESERVED: Writes ignored, read as 0. 4 Phase Shift Enable 0,RW,SC TX Clock Phase Shift Enable: 1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits [4:0]. 0 = No change in TX Clock phase 3:0 Phase Shift Value <0000>,RW TX Clock Phase Shift Value: The value of this register represents the current phase shift between Reference clock at XI and MII Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4 times the difference (in nSec). For example, if the value of this register was 0x2, Writing 0x9 to this register will shift TX_CLK by 28nS (4 times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of 10) in case of writing value bigger than 10, the updated value will be the written value modulo 10. 8.4.4 Voltage Regulator Control Register (VRCR) This register gives the host processor the ability to power down the voltage-regulator block of the PHY via register access. This power-down operation is available in systems operating with an external power supply. Table 8-34. Voltage Regulator Control Register (VRCR), address 0x00D0 BIT NAME DEFAULT FUNCTION 15 VRPD 0, RW, SC Voltage Regulator Power Down: 1 = Power Down. Allow the system to power down the voltage regulator block of the PHY using register access. 0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT pin. 14:4 RESERVED <000 0000 0000>, RW RESERVED: Must be written as 0. 3:0 VR Control <0000>, RW Voltage Regulator Control This value should be ignored on read. To write to this register, perform a read followed by a write with the desired value. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 73 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.5 8.5.1 www.ti.com Cable Diagnostic Configuration/Result Registers ALCD Registers Control and Results 1 Table 8-35. ALCD Control and Results 1 Register, address 0x0155 BIT 15 BIT NAME alcd_start 14:13 DEFAULT <0>, SC DESCRIPTION alcd_start: <00>, RO RESERVED: Writes ignored, read as 0. 12 alcd_done <0>, RO TPTD Diagnostic Bypass 1 = Bypass TPTD diagnostic. TDR on TPTD pair will not be executed. 0 = TDR is executed on TPTD pair 11:4 alcd_out1 <0000 0000>, RO 3 2:0 8.5.2 RESERVED alcd_ctrl <0>, RO <000>,RW alcd_out1 RESERVED: Writes ignored, read as 0. alcd_ctrl <000>: <001>: <010>: <011>: <100>: <101>: <110>: <111>: Cable Diagnostic Specific Control Register (CDSCR) This register is used to select the channel for which cable diagnostics test needs to be done. It has the enable/bypass bits for the diagnostic tests and also allows defining the number of executed and averaged TDR sequences. Table 8-36. Cable Diagnostic Specific Control Register (CDSCR), address 0x0170 BIT BIT NAME DESCRIPTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 14 Diagnostic Cross Disable 0,RW Cross TDR Diagnostic mode 1 = Disable TDR Cross mode - TDR will be executed in regular mode only 0 = Diagnostic of crossing pairs is enabled In Cross Diagnostic mode, the TDR mechanism is looking for reflection on the other pair to check short between pairs. 13 Diagnostic TPTD Bypass 0,RW TPTD Diagnostic Bypass 1 = Bypass TPTD diagnostic. TDR on TPTD pair will not be executed. 0 = TDR is executed on TPTD pair In bypass TPTD, results are available in TPRD slots. 12 Diagnostic TPRD Bypass 0,RO TPRD Diagnostic Bypass 1 = Bypass TPRD diagnostic. TDR on TPRD pair will not be executed. 0 = TDR is executed on TPRD pair 11 RESERVED 1,RW RESERVED: Must be Set to 1. 10:8 Diagnostics Average Cycles 7:0 RESERVED 74 DEFAULT <110>,RW 0,RO Number Of TDR Cycles to Average: <000>: 1 TDR cycle <001>: 2 TDR cycles <010>: 4 TDR cycles <011>: 8 TDR cycles <100>: 16 TDR cycles <101>: 32 TDR cycles <110>: 64 TDR cycles (default) <111>: Reserved RESERVED: Writes ignored, read as 0. Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 8.5.3 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Cable Diagnostic Location Results Register 1 (CDLRR1) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-37. Cable Diagnostic Location Results Register 1 (CDLRR1), address 0x0180 DEFAULT FUNCTION 15:8 TPTD Peak Location 2 BIT <0000 0000>, RO Location of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY 7:0 <0000 0000>, RO Location of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY 8.5.4 NAME TPTD Peak Location 1 Cable Diagnostic Location Results Register 2 (CDLRR2) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-38. Cable Diagnostic Location Results Register 2 (CDLRR2), address 0x0181 DEFAULT FUNCTION 15:8 TPTD Peak Location 4 BIT <0000 0000>, RO Location of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY. 7:0 <0000 0000>, RO Location of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY. 8.5.5 NAME TPTD Peak Location 3 Cable Diagnostic Location Results Register 3 (DDLRR3) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-39. Cable Diagnostic Location Results Register 3 (DDLRR3), address 0x0182 BIT DEFAULT FUNCTION 15:8 TPRD Peak Location 1 <0000 0000>, RO Location of the First peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY. 7:0 <0000 0000>, RO Location of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY. 8.5.6 NAME TPTD Peak Location 5 Cable Diagnostic Location Results Register 4 (CDLRR4) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-40. Cable Diagnostic Location Results Register 4 (CDLRR4), address 0x0183 DEFAULT FUNCTION 15:8 TPRD Peak Location 3 BIT NAME <0000 0000>, RO Location of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY. 7:0 <0000 0000>, RO Location of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY. TPRD Peak Location 2 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 75 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 8.5.7 www.ti.com Cable Diagnostic Location Results Register 5 (CDLRR5) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-41. Cable Diagnostic Location Results Register 5 (CDLRR5), address 0x0184 DEFAULT FUNCTION 15:8 TPRD Peak Location 5 BIT <0000 0000>, RO Location of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY. 7:0 <0000 0000>, RO Location of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY. 8.5.8 NAME TPRD Peak Location 4 Cable Diagnostic Amplitude Results Register 1 (CDARR1) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-42. Cable Diagnostic Amplitude Results Register 1 (CDARR1), address 0x0185 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. <000 0000>,RO Amplitude of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [15:8] in register CDLRR1 (0x180) 14:8 TPTD Peak Amplitude 2 7 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 6:0 TPTD Peak Amplitude 1 <000 0000>,RO Amplitude of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [7:0] in register CDLRR1 (0x180) 8.5.9 Cable Diagnostic Amplitude Results Register 2 (CDARR2) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-43. Cable Diagnostic Amplitude Results Register 2 (CDARR2), address 0x0186 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. <000 0000>,RO Amplitude of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [15:8] in register CDLRR2 (0x181) 14:8 TPTD Peak Amplitude 4 7 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 6:0 TPTD Peak Amplitude 3 <000 0000>,RO Amplitude of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [7:0] in register CDLRR2 (0x181) 8.5.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-44. Cable Diagnostic Amplitude Results Register 3 (CDARR3), address 0x0187 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. <000 0000>,RO Amplitude of the First peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [15:8] in register CDLRR3 (0x182) 14:8 TPRD Peak Amplitude 1 76 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-44. Cable Diagnostic Amplitude Results Register 3 (CDARR3), address 0x0187 (continued) BIT NAME DEFAULT FUNCTION 7 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 6:0 TPTD Peak Amplitude 5 <000 0000>,RO Amplitude of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [7:0] in register CDLRR3 (0x182) Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 77 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 8.5.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-45. Cable Diagnostic Amplitude Results Register 4 (CDARR4), address 0x0188 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. <000 0000>,RO Amplitude of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [15:8] in register CDLRR4 (0x183) 14:8 TPRD Peak Amplitude 3 7 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 6:0 TPRD Peak Amplitude 2 <000 0000>,RO Amplitude of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [7:0] in register CDLRR4 (0x183) 8.5.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-46. Cable Diagnostic Amplitude Results Register 5 (CDARR5), address 0x0189 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0. <000 0000>,RO Amplitude of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [15:8] in register CDLRR4 (0x184) 14:8 TPRD Peak Amplitude 5 7 RESERVED 0,RO RESERVED: Writes ignored, read as 0. 6:0 TPRD Peak Amplitude 4 <000 0000>,RO Amplitude of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and/or interference. This amplitude value refers to peak location stored in bits [7:0] in register CDLRR4 (0x184) 8.5.13 Cable Diagnostic General Results Register (CDGRR) This register provides general measurement results after the execution of the TDR. The Cable Diagnostic software should post process this result together with other Peaks' location and amplitude results. Table 8-47. Cable Diagnostic General Results Register (CDGRR), address 0x018A BIT NAME DEFAUL T FUNCTION 15 TPTD Peak Polarity 5 0,RO Polarity of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD). 14 TPTD Peak Polarity 4 0,RO Polarity of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD). 13 TPTD Peak Polarity 3 0,RO Polarity of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD). 12 TPTD Peak Polarity 2 0,RO Polarity of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD). 11 TPTD Peak Polarity 1 0,RO Polarity of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). 10 TPRD Peak Polarity 5 0,RO Polarity of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD). 9 TPRD Peak Polarity 4 0,RO Polarity of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD). 8 TPRD Peak Polarity 3 0,RO Polarity of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD). 78 Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Table 8-47. Cable Diagnostic General Results Register (CDGRR), address 0x018A (continued) BIT NAME DEFAUL T FUNCTION 7 TPRD Peak Polarity 2 0,RO Polarity of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD). 6 TPRD Peak Polarity 1 0,RO Polarity of the First peak discovered by the TDR mechanism on Receive Channel (TPRD). 5 Cross Detect on TPTD 0,RO Cross Reflection were detected on TPTD. Indicate on Short between TPTD and TPRD. 4 Cross Detect on TPRD 0,RO Cross Reflection were detected on TPRD. Indicate on Short between TPTD and TPRD. 3 Above 5 TPTD Peaks 0,RO More than 5 reflections were detected on TPTD. 2 Above 5 TPRD Peaks 0,RO More than 5 reflections were detected on TPRD. RESERVED <00>,RO RESERVED: Writes ignored, read as 0. 1:0 8.5.14 ALCD Register, Results 2 Table 8-48. ALCD Control and Results 2 Register, address 0x0215 BIT BIT NAME DEFAULT DESCRIPTION 15:12 alcd_out2 <0011>, SC alcd_out2 11:0 alcd_out3 <0110 0000 alcd_out3 0000>, RW Register Block Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 79 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9 Electrical Specifications All parameters are derived by test, statistical analysis, or design. ABSOLUTE MAXIMUM RATINGS (1) 9.1 VDD33_IO, AVDD33 Supply voltage PFBIN1, PFBIN2 DC Input voltage V -0.3 to 6 Other Inputs -0.3 to 3.8 XO DC Output voltage -0.3 to 3.8 Other outputs V -0.3 to 3.8 TJ Maximum die temperature 125 C 4 kV (2) Human-Body Model All pins Ethernet network pins (TD+, TD-, RD+, RD-) (3) 16 Charged-Device Model All pins (4) 750 ESD (4) V -0.3 to 3.8 TD-, TD+, RD-, RD+ (2) (3) UNIT -0.3 to 1.8 XI (1) VALUE -0.3 to 3.8 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance to JEDEC Standard 22, Test Method A114. Test method based upon JEDEC Standard 22 Test Method A114, Ethernet network pins (TD+, TD-, RD+, RD-) pins stressed with respect to GND. Tested in accordance to JEDEC Standard 22, Test Method C101. 9.2 THERMAL CHARACTERISTICS 9.2.1 48-Pin Industrial Device Thermal Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS JA Junction-to-ambient thermal resistance (no airflow) JEDEC high-K model JB Junction-to-board thermal resistance 28.5 JC Junction-to-case thermal resistance 23.1 9.2.2 MIN TYP MAX UNIT 65.3 C/W 48-Pin Extended Temperature (125C) Device Thermal Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS JA Junction-to-ambient thermal resistance (no airflow) JEDEC high-K model JB Junction-to-board thermal resistance 20.0 JC Junction-to-case thermal resistance 24.7 9.3 I/O and Analog 3.3V Supply PFBIN1, PFBIN2 Core Supply voltage TA Ambient temperature PD Power dissipation (2) 80 TYP MAX UNIT 41.8 C/W RECOMMENDED OPERATING CONDITIONS VDD33_IO, AVDD33 (1) (2) MIN (1) MIN NOM MAX 3.0 3.3 3.6 V 1.43 1.5 1.58 V -40 85 270 UNIT C mW Provided that GNDPAD, pin 49, is soldered down. See Thermal Vias Recommendation for more detail. For 100Base-TX, When internal 1.5V is used. Device is operated from single 3.3V supply only. Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 9.4 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 DC CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VIH Input high voltage VIL Input low voltage IIH Input high current IIL (1) TEST CONDITIONS Nominal VCC = VDD33_IO = 3.3V MIN TYP MAX UNIT 2.0 V (1) 0.8 V VIN = VCC 10 A Input low current VIN = GND 10 A VOL Output low voltage IOL = 4 mA 0.4 V VOH Output high voltage IOH = -4 mA IOZ 3-State leakage VOUT = VCC, VOUT = GND 10 A RPULLUP ntegrated Pullup Resistance 49.7 23.7 14.7 k RPULLDOWN Integrated Pulldown Resistance 48.1 24.9 14.5 k VTPTD_100 100M transmit voltage 0.95 1 1.05 V VTPTDsym 100M transmit voltage symmetry VTPTD_10 10M transmit voltage 2.2 2.5 CIN1 CMOS input capacitance 5 pF COUT1 CMOS output capacitance 5 pF VTH1 10Base-T Receive threshold (1) VCC - 0.5 V 2% 2.8 585 V mV Nominal VCC of VDD33_IO = 3.3V Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 81 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.5 www.ti.com POWER SUPPLY CHARACTERISTICS The data was measured using a TLK110 evaluation board. The current from each of the power supply is measured and the power dissipation is computed. For the single 3.3V external supply case the power dissipation across the internal linear regulator is also included. All the power dissipation numbers are measured at the nominal power supply and typical temperature of 25C. The power needed is given both for the device only, and including the center tap of the transformer for a total system power requirement. The center tap of the transformer is normally connected to the 3.3V supply, thus the current needed may also be easily calculated. 9.5.1 Active Power PARAMETER TEST CONDITIONS FROM POWER PINS FROM TRANSFORMER CENTER TAP UNIT 100Base-TX /W Traffic (full packet 1518B rate) Single 3.3V external supply 203 73 mW 10Base-T /W Traffic (full packet 1518B rate) Single 3.3V external supply 96 211 mW 9.5.2 Power-Down Power TEST CONDITIONS (1) FROM THE POWER SUPPLIES ROM TRANSFORMER CENTER TAP UNIT IEEE PWDN Single 3.3V external supply 12 5 mW Passive Sleep Mode Single 3.3V external supply 71 5 mW Active Sleep Mode Single 3.3V external supply 71 5 mW PARAMETER (1) 82 Measured under typical conditions. Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 9.6 9.6.1 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 AC Specifications Power Up Timing Table 9-1. Power Up Timing PARAMETER t1 TEST CONDITIONS Time from powerup to hardware-configuration pin transition to output-driver function, using internal POR (RESET_N pin tied high) MIN TYP MAX 100 270 UNIT s VDD Hardware RESET_N t1 Dual function pins Become enabled As outputs Figure 9-1. Power Up Timing NOTE It is important to choose pullup and/or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch in the proper value prior to the pin transitioning to an output driver. 9.6.2 Reset Timing Table 9-2. Reset Timing PARAMETER t1 TEST CONDITIONS XI Clock must be stable for minimum of 1ms during RESET pulse low time. RESET pulse width MIN TYP MAX 1 UNIT s VCC XI Clock t1 Hardware RESET_N T0339-01 Figure 9-2. Reset Timing Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 83 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.3 www.ti.com MII Serial Management Timing Table 9-3. MII Serial Management Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.5 25 MHz 30 ns t1 MDC Frequency t2 MDC to MDIO (Output) Delay Time t3 MDIO (Input) to MDC Hold Time 10 ns t4 MDIO (Input) to MDC Setup Time 10 ns 0 MDC t1 t2 MDIO (Output) MDC t3 t4 MDIO (Input) Valid Data T0340-01 Figure 9-3. MII Serial Management Timing 9.6.4 100Mb/s MII Transmit Timing Table 9-4. 100Mb/s MII Transmit Timing PARAMETER MIN TYP MAX 100Mbs Normal mode 16 20 24 TXD[3:0], TX_EN Data Setup to TX_CLK 100Mbs Normal mode 10 ns TXD[3:0], TX_EN Data Hold from TX_CLK 100Mbs Normal mode 0 ns t1 TX_CLK High Time t2 TX_CLK Low Time t3 t4 TEST CONDITIONS UNIT ns t2 t1 TX_CLK t3 t4 TXD[3:0] TX_EN Valid Data T0341-01 Figure 9-4. 100Mb/s MII Transmit Timing 84 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 9.6.5 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 100Mb/s MII Receive Timing Table 9-5. 100Mb/s MII Receive Timing PARAMETER (1) TEST CONDITIONS t1 RX_CLK High Time t2 RX_CLK Low Time t3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay (1) MIN TYP MAX UNIT 100Mbs Normal mode 16 20 24 ns 100Mbs Normal mode 10 30 ns RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. t1 t2 RX_CLK t3 RXD[3:0] RX_DV RX_ER Valid Data T0342-01 Figure 9-5. 100Mb/s MII Receive Timing 9.6.6 100Base-TX Transmit Packet Latency Timing Table 9-6. 100Base-TX Transmit Packet Latency Timing PARAMETER t1 (1) (2) TEST CONDITIONS MIN 100Mbs Normal mode (1) TX_CLK to PMD Output Pair Latency TYP 4.8 MAX UNIT bits (2) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the 'J' code group as output from the PMD Output Pair. 1 bit time = 10ns in 100Mbs mode. 1 bit time is equal 10 nS in 100 Mb/s mode. TX_CLK TX_EN TXD t1 PMD Output Pair IDLE (J/K) DATA T0343-01 Figure 9-6. 100Base-TX Transmit Packet Latency Timing Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 85 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.7 www.ti.com 100Base-TX Transmit Packet Deassertion Timing Table 9-7. 100Base-TX Transmit Packet Deassertion Timing PARAMETER t1 TEST CONDITIONS TX_CLK to PMD Output Pair deassertion MIN 100Mbs Normal mode TYP 4.6 MAX UNIT bits TX_CLK TX_EN TXD t1 PMD Output Pair DATA DATA (T/R) (T/R) IDLE IDLE T0344-01 Figure 9-7. 100Base-TX Transmit Packet Deassertion Timing 86 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com 9.6.8 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 100Base-TX Transmit Timing (tR/F and Jitter) Table 9-8. 100Base-TX Transmit Timing (tR/F and Jitter) PARAMETER t1 t2 (1) (2) TEST CONDITIONS MIN TYP MAX 3 4 5 ns 100Mbs tR and tF Mismatch (2) 500 ps 100Mbs PMD Output Pair Transmit Jitter 1.4 ns 100Mbs PMD Output Pair tR and tF (1) UNIT Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude. Normal Mismatch is the difference between the maximum and minimum of all rise and fall times. t1 +1 rise 90% 10% PMD Output Pair 10% 90% +1 fall t1 -1 rise t1 -1 fall t1 t2 PMD Output Pair Eye Pattern t2 T0345-01 Figure 9-8. 100Base-TX Transmit Timing (tR/F and Jitter) Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 87 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.9 www.ti.com 100Base-TX Receive Packet Latency Timing Table 9-9. 100Base-TX Receive Packet Latency Timing TEST CONDITIONS (1) PARAMETER (3) MIN TYP MAX UNIT (2) t1 Carrier Sense ON Delay 100Mbs Normal mode 14 bits t2 Receive Data Latency 100Mbs Normal mode 19 bits Receive data latency (4) 100Mb normal mode with fast RXDV detection ON 15 bits t2 (1) (2) (3) (4) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value. 1 bit time = 10 ns in 100Mbs mode Carrier Sense On Delay is determined by measuring the time from the first bit of the "J" code group to the assertion of Carrier Sense. Fast RXDV detection could be enabled by setting bit[1] of SWSCR1 (address 0x0009). PMD Input Pair IDLE (J/K) Data t1 CRS t2 RXD[3:0] RX_DV RX_ER T0346-01 Figure 9-9. 100Base-TX Receive Packet Latency Timing 9.6.10 100Base-TX Receive Packet Deassertion Timing Table 9-10. 100Base-TX Receive Packet Deassertion Timing PARAMETER t1 (1) (2) TEST CONDITIONS Carrier Sense OFF Delay (1) MIN 100Mbs Normal mode TYP 19 MAX UNIT bits (2) Carrier Sense Off Delay is determined by measuring the time from the first bit of the "T" code group to the deassertion of Carrier Sense. 1 bit time = 10 ns in 100Mbs mode PMD Input Pair DATA (T/R) IDLE t1 CRS T0347-01 Figure 9-10. 100Base-TX Receive Packet Deassertion Timing 88 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.11 10Mbs MII Transmit Timing Table 9-11. 10Mbs MII Transmit Timing PARAMETER MIN TYP MAX UNIT 10Mbs MII mode 190 200 210 ns TXD[3:0], TX_EN Data Setup to TX_CLK 10Mbs MII mode 25 ns TXD[3:0], TX_EN Data Hold from TX_CLK 10Mbs MII mode 0 ns t1 TX_CLK Low Time t2 TX_CLK High Time t3 t4 TEST CONDITIONS An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown in Figure 9-11, the MII signals are sampled on the falling edge of TX_CLK. t2 t1 TX_CLK t4 t3 TXD[3:0] TX_EN Valid Data Figure 9-11. 10Mbs MII Transmit Timing 9.6.12 10Mb/s MII Receive Timing Table 9-12. 10Mb/s MII Receive Timing PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT 160 200 240 ns t1 RX_CLK High Time t2 RX_CLK Low Time t3 RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10Mbs MII mode 100 ns RX_CLK to RXD[3:0], RX_DV Delay 10Mbs MII mode 100 ns t4 (1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. t1 t2 RX_CLK t3 t4 RXD[3:0] RX_DV Valid Data T0349-01 Figure 9-12. 10Mb/s MII Receive Timing Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 89 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9.6.13 10Base-T Transmit Timing (Start of Packet) Table 9-13. 10Base-T Transmit Timing (Start of Packet) PARAMETER t1 (1) TEST CONDITIONS Transmit Output Delay from the Falling Edge of TX_CLK MIN 10Mbs MII mode TYP MAX 5.8 UNIT (1) bits (1) 1 bit time = 100ns in 10Mb/s. TX_CLK TX_EN TXD t1 PMD Output Pair Figure 9-13. 10Base-T Transmit Timing (Start of Packet) 9.6.14 10Base-T Transmit Timing (End of Packet) Table 9-14. 10Base-T Transmit Timing (End of Packet) MIN TYP t1 End of Packet High Time (with `0' ending bit) PARAMETER TEST CONDITIONS 250 310 MAX UNIT ns t2 End of Packet High Time (with `1' ending bit) 250 310 ns TX_CLK TX_EN t1 0 PMD Output Pair PMD Output Pair 1 0 1 t2 Figure 9-14. 10Base-T Transmit Timing (End of Packet) 90 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.15 10Base-T Receive Timing (Start of Packet) Table 9-15. 10Base-T Receive Timing (Start of Packet) PARAMETER TEST CONDITIONS t1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) t2 RX_DV Latency (1) t3 Receive Data Latency (1) MIN Measurement shown from SFD TYP MAX 550 1000 UNIT ns 14 bits 14 bits 10Base-T RX_DV Latency is measured from first bit of decoded SFD on the wire to the assertion of RX_DV 1st SFD Bit Decoded 1 0 1 0 1 0 1 0 1 0 1 1 TPRD t1 CRS RX_CLK t2 RX_DV t3 RXD[3:0] 0000 Preamble SFD Data Figure 9-15. 10Base-T Receive Timing (Start of Packet) 9.6.16 10Base-T Receive Timing (End of Packet) Table 9-16. 10Base-T Receive Timing (End of Packet) PARAMETER t1 TEST CONDITIONS MIN Carrier Sense Turn Off Delay TYP MAX 1.8 1 0 1 UNIT s IDLE PMD Input Pair RX_CLK t1 CRS Figure 9-16. 10Base-T Receive Timing (End of Packet) Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 91 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9.6.17 10Mb/s Jabber Timing Table 9-17. 10Mb/s Jabber Timing PARAMETER t1 Jabber Activation Time t2 Jabber Deactivation Time TEST CONDITIONS MIN TYP MAX 100 10 Mb/s MII mode UNIT ms 500 TXEN t1 PMD Output Pair t2 COL Figure 9-17. 10Mb/s Jabber Timing 9.6.18 10Base-T Normal Link Pulse Timing Table 9-18. 10Base-T Normal Link Pulse Timing PARAMETER (1) t1 Pulse Period t2 Pulse Width (1) TEST CONDITIONS MIN 10 Mb/s MII mode TYP MAX UNIT 16 ms 100 ns Transmit timing t1 t2 Normal Link Pulse(s) T0358-01 Figure 9-18. 10Base-T Normal Link Pulse Timing 92 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.19 Auto-Negotiation Fast Link Pulse (FLP) Timing Table 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing PARAMETER TEST CONDITIONS t1 Clock Pulse to Clock Pulse Period t2 Clock Pulse to Data Pulse Period t3 Clock, Data Pulse Width t4 FLP Burst to FLP Burst Period t5 Burst Width MIN Data = 1 TYP MAX UNIT 125 s 62 s 114 ns 16 ms 2 ms t1 t2 t3 t3 Fast Link Pulse(s) Data Pulse Clock Pulse Clock Pulse t4 t5 FLP Burst FLP Burst T0359-01 Figure 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 93 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9.6.20 100Base-TX Signal Detect Timing Table 9-20. 100Base-TX Signal Detect Timing MAX UNIT t1 SD Internal Turn-on Time PARAMETER TEST CONDITIONS MIN TYP 100 s t2 Internal Turn-off Time 200 s PMD Input Pair t1 t2 SD+ Intermal T0360-01 NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant. Figure 9-20. 100Base-TX Signal Detect Timing 9.6.21 100Mbs Internal Loopback Timing Table 9-21. 100Mbs Internal Loopback Timing PARAMETER t1 TX_EN to RX_DV Loopback MIN TYP MAX 100Mbs internal loopback TEST CONDITIONS 241 242 243 100Mbs external loopback - fast RX_DV mode 201 202 203 100Mbs analog loopback 232 233 234 100Mbs PCS Input loop back 120 121 122 8 9 10 100Mbs MII loop back 94 Electrical Specifications UNIT ns Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0361-01 (1) (2) (3) (4) Due to the nature of the descrambler function, all 100Base-TX Loopback modes will cause an initial dead-time of up to 550 s during which time no data is present at the receive MII outputs. The 100Base-TX timing specified is based on device delays after the initial 550s dead-time. Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. External loopback was measured using very short external cable (~10cm). Since MII loopback introduce extreme short roundtrip delay, some hosts would use PCS Input loopback (Mainly in 100BT). Figure 9-21. 100Mbs Internal Loopback Timing Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 95 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9.6.22 10Mbs Internal Loopback Timing Table 9-22. 10Mbs Internal Loopback Timing PARAMETER t1 TEST CONDITIONS TX_EN to RX_DV Loopback MIN TYP 10Mbs internal loopback mode MAX UNIT s 1.7 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0362-01 (1) (2) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. Analog loopback was used. Looping the TX to RX at the analog input/output stage. Figure 9-22. 10Mbs Internal Loopback Timing 9.6.23 RMII Transmit Timing Table 9-23. RMII Transmit Timing PARAMETER TEST CONDITIONS MIN 50 MHz Reference Clock t1 XI Clock Period t2 TXD[1:0] and TX_EN data setup to X1 rising 1.4 t3 TXD[1:0] and TX_EN data hold to X1 rising 2.5 t4 XI Clock to PMD Output Pair Latency TYP MAX UNIT 20 ns 12 bits t1 XI t2 TXD[1:0] TX_EN t3 Valid Data t4 Symbol PMD Output Pair Figure 9-23. RMII Transmit Timing 96 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 9.6.24 RMII Receive Timing Table 9-24. RMII Receive Timing PARAMETER TEST CONDITIONS MIN XI Clock Period t2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising t3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 17.6 t4 CRS OFF delay From TR symbol on PMD Receive Pair to initial assertion of CRS_DV 26.2 t5 RXD[1:0] and RX_ER latency From symbol on Receive Pair. * Elasticity buffer set to default value (01) 29.7 t6 RX_CLK Clock Period 50 MHz "Recovered clock" while working in "RMII receive clock" mode 20 t7 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK rising While working in "RMII receive clock" mode 3.8 PMD Input Pair Idle 50 MHz Reference Clock TYP MAX t1 (J/K) 10.8 (TR) Data 20 t5 UNIT ns bits ns Data t4 XI t2 RX_DV t1 t2 t2 t6 t7 t7 t3 CRS_DV t2 RXD[1:0] RX_ER RX_CLK t7 Figure 9-24. RMII Receive Timing NOTE 1. Per the RMII Specification, output delays assume a 25pF load. 2. CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS de-assertion. 3. RX_DV is synchronous to XI. While not part of the RMII specification, this signal is provided to simplify recovery of receive data. 4. "RMII receive clock" mode is not part of the RMII specification that allows synchronization of the MAC-PHY RX interface in RMII mode. Setting register 0x000A bit [0] is required to activate this mode. Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 97 TLK110 SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 www.ti.com 9.6.25 Isolation Timing Table 9-25. Isolation Timing PARAMETER t1 TEST CONDITIONS MIN TYP MAX From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 71 UNIT ns H/W or S/W Reset t1 ISOLATE MODE NORMAL T0365-01 Figure 9-25. Isolation Timing 9.6.26 25 MHz_OUT Clock Timing Table 9-26. 25 MHz_OUT Clock Timing PARAMETER t1 t2 t3 (1) TEST CONDITIONS 25 MHz_OUT (1) propagation delay 25 MHz_OUT (1) High Time 25 MHz_OUT (1) Low Time MIN TYP Relative to XI MAX 8 MII mode 20 RMII mode 10 MII mode 20 RMII mode 10 UNIT ns ns 25 MHz_OUT characteristics are dependent upon the XI input characteristics. XI t1 t2 t3 25 MHz_OUT T0366-01 Figure 9-26. 25 MHz_OUT Timing 98 Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 TLK110 www.ti.com SLLS901A - DECEMBER 2011 - REVISED FEBRUARY 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision initial release (December 2011) to Revision A * Changed Default value of interrupt-polarity bit from 0 to 1 Page .............................................................. Electrical Specifications Copyright (c) 2011-2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK110 64 99 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLK110PT ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLK110PTR ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLK110PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK110PTR LQFP PT 48 1000 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0- 7 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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