A1359LLETR-T - ALLEGRO MICROSYSTEMS

A1359-DS, Rev. 3

MCO-0000603

FEATURES AND BENEFITS

• Dual tracking outputs: analog voltage output and pulse-

width-modulated (PWM) output

• Matched analog and PWM outputs enable user to detect

various output error conditions

• Factory-programmed offset, sensitivity, and polarity

• Sensitivity temperature coefficient (TC) and QVO/QD

temperature coefficient programmed at Allegro™ for

improved accuracy

• High-speed chopping scheme minimizes quiescent voltage

output (QVO) drift across temperature

• Temperature-stable QVO and sensitivity

• Output voltage clamps provide short-circuit diagnostic

capabilities

• Wide ambient temperature range: –40°C to 150°C

• Immune to mechanical stress

• Enhanced EMC performance for stringent automotive

applications

Factory-Programmed Dual-Output Linear-Hall Effect-Sensor IC

With Analog and Pulse-Width-Modulated Outputs

Package: 8-pin TSSOP (suffix LE)

surface mount

Functional Block Diagram

Not to scale

A1359

DESCRIPTION

New applications for linear output Hall-effect sensors, such

as displacement and angular position, require high accuracy

in conjunction with redundant outputs. The Allegro A1359

programmable, linear, Hall effect sensor IC has been designed

specifically to achieve both goals. The features associated

with this linear device make it ideal for use in automotive

and industrial applications requiring high accuracy, and

this temperature-stable device operates across an extended

temperature range: –40°C to 150°C.

The accuracy of the device is enhanced via programmability

at the Allegro factory for optimization of device sensitivity,

the quiescent voltage output (QVO: output with no magnetic

field), and quiescent duty cycle (QD) for a given application or

circuit. The A1359 also allows optimized performance across

the entire operating temperature range via programming the

temperature coefficients for both sensitivity and QVO/QD at

Allegro end-of-line test. This ratiometric Hall-effect sensor IC

provides an analog voltage, and a PWM signal with duty cycle,

that are proportional to the applied magnetic field.

Each BiCMOS monolithic circuit integrates a Hall element,

temperature-compensating circuitry to reduce the intrinsic

sensitivity drift of the Hall element, a small-signal high-

gain amplifier, a clamped low-impedance output stage and a

proprietary dynamic offset cancellation technique.

The A1359 is provided in an 8-contact surface-mount TSSOP

(suffix LE) which is lead (Pb) free, with 100% matte-tin

leadframe plating.

VCC

CBYPASS

100 nF

VSUPPLY

GND

VOUT

PWMOUT

Sensitivity, QVO, and

Temperature Compensation

Chopper

Switches

RPULLUP

Signal

Recovery

PWM

Frequency Trim

Mismatch

Compensation

PWM Carrier

Generation

Signal

Conditioning

Low-Pass

Filter

Amp

February 19, 2019

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit

Forward Supply Voltage VCC Refer to Power Derating section 6 V

Reverse Supply Voltage VRCC –0.1 V

Forward Output Voltage VOUT Refer to Power Derating section 7 V

Reverse Output Voltage VROUT –0.1 V

Forward PWM Output Voltage VPWM Refer to Power Derating section 7 V

Reverse PWM Output Voltage VRPWM –0.1 V

Output Source Current IOUT(SOURCE) VOUT to GND 2 mA

Output Sink Current IOUT(SINK) VCC to VOUT 10 mA

PWM Output Source Current IPWM(SOURCE) VPWM > –0.5 V, TA = 25°C –50 mA

PWM Output Sink Current IPWM(SINK)

Internal current limiting is intended to protect the

device from momentary short circuits and not

intended for continuous operation

25 mA

Operating Ambient Temperature TATemperature range L –40 to 150 ºC

Storage Temperature Tstg –65 to 170 ºC

Maximum Junction Temperature TJ(max) 165 ºC

SELECTION GUIDE

Part Number Factory-Programmed Output Polarity Packing*

A1359LLETR-T Forward: Output voltage increases with increasing

positive (south) applied magnetic field 4000 units / reel

A1359LLETR-RP-T Reverse: Output voltage increases with increasing

negative (north) applied magnetic field 4000 units / reel

A1359LLETR-MS-T Forward: Output voltage increases with increasing

positive (south) applied magnetic field 4000 units / reel

A1359LLETR-RP-MS-T Reverse: Output voltage increases with increasing

negative (north) applied magnetic field 4000 units / reel

*Contact Allegro for additional packing options

Pinout Diagram

PWMOUT

VCC

VOUT

GND

Terminal List Table

Number Name Function

1 PWMOUT Open-drain PWM output

2 VCC Input power supply; tie to GND with bypass capacitor

3 NC No connect, tie to either GND or VCC

4 VOUT Output signal

5 NC No connect, tie to either GND or VCC

6 NC No connect, tie to either GND or VCC

7 GND Device ground

8 NC No connect, tie to either GND or VCC

PINOUT DIAGRAM AND TERMINAL LIST TABLE

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 145 ºC/W

*Additional thermal information available on the Allegro website

20 40 60 80 100 120 140 160 180

Temperature, T

(°C)

Power Dissipation, P

(mW)

300

400

200

100

600

500

800

700

900

1000

Power Dissipation versus Ambient Temperature

θJA

= 145 ºC/W)

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Continued on the next page…

OPERATING CHARACTERISTICS: Valid over full operating temperature range, TA, CBYPASS = 0.1 µF , VCC = 5 V,

unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

ELECTRICAL CHARACTERISTICS

Supply Voltage VCC 4.5 5 5.5 V

Undervoltage Threshold2VUVLOHI TA = 25°C (device powers on) – – 3 V

VUVLOLOW TA = 25°C (device powers off) 2.5 – – V

Supply Current ICC VCC = 5 V – 10 13.5 mA

Supply Zener Clamp Voltage VZTA = 25°C, ICC = 20 mA 6 8.3 – V

Internal Bandwidth3BWiSmall signal, –3 dB – 2 – kHz

Chopping Frequency3,4 fCTA = 25°C – 400 – kHz

ANALOG OUTPUT CHARACTERISTICS

Output Referred Noise3VN

TA = 25°C, CBYPASS = 0.1 µF, Sens = 5 mV/G,

no load on VOUT – 6 – mV(p-p)

Input Referred RMS Noise Density3VNRMS

T = 25°C, CBYPASS = open, no load on VOUT,

f << BWi

– 1.9 – mG/√Hz

DC Output Resistance3ROUT – < 1 – Ω

Output Load Resistance3RLVOUT to GND 4.7 – – kΩ

Output Load Capacitance3CLVOUT to GND – – 10 nF

Analog Output Current Limit ILIMIT(ALG) RPULLUP = 0 Ω 10 – 80 mA

Output Voltage Clamp5

VCLPH

TA = 25°C, B = +350 G,

RL = 10 kΩ (VOUT to GND) 4.25 4.5 4.65 V

VCLPL

TA = 25°C, B = –350 G,

RL = 10 kΩ (VOUT to VCC) 0.4 0.5 0.7 V

Response Time3tRESPONSE_

VOUT

Impulse magnetic field of 300 G – – 500 µs

Settling Time3tSETTLEVOUT TA = 25°C, Primary Overload > 5000 G – – 750 µs

Power-On Time for Analog3tPOVOUT TA = 25°C, CL (probe) = 10 pF, on VOUT – 250 – µs

Delay to Clamp for Analog3tCLPVOUT TA = 25°C, CL = 10 nF, on VOUT – 30 – µs

PWM OUTPUT CHARACTERISTICS

PWMOUT Saturation Voltage VSAT

IPWMOUT(SINK) ≤ 20 mA, PWMOUT transistor on ––0.6 V

IPWMOUT(SINK) ≤ 10 mA, PWMOUT transistor on – – 0.5 V

PWMOUT Current Limit ILIMIT RPULLUP = 0 Ω 30 60 110 mA

PWMOUT Leakage Current ILEAK

VCC = GND, 0 V ≤ VPWMOUT ≤ 5 V,

PWMOUT transistor off – 0.1 10 µA

PWMOUT Zener Clamp Voltage VZOUT IPWMOUT(SINK) = 10 mA, TA = 25ºC 28 – – V

PWMOUT Rise Time3trTA = 25°C, RPULLUP = 2 kΩ, CL = 20 pF – 3 – µs

PWMOUT Fall Time3tfTA = 25°C, RPULLUP = 2 kΩ, CL = 20 pF – 3 – µs

Power-On Time for PWM3tPOPWM TA = 25°C, CL (probe) = 10 pF, on PWMOUT – 500 – µs

Delay to Clamp for PWM3tCLPPWM TA = 25°C, CL = 10 nF, on PWMOUT – 250 – µs

Response Time3tRESPONSE_

PWM

TA = 25°C, Impulse magnetic field of 300 G – – 1.5 ms

Settling Time3tSETTLEPWM TA = 25°C, Primary Overload > 5000 G – – 2.25 ms

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

PWM OUTPUT CHARACTERISTICS (continued)

Load Resistance3,6 RPULLUP PWMOUT to VCC 2000 – – Ω

Load Capacitance3,6 CLPWMOUT to GND – – 10 nF

Duty Cycle Jitter3JitterPWM

Measured over 1000 PWM output clock periods,

3 sigma values, Sens = 9 mV/G – ±0.18 – %D

QUIESCENT VOLTAGE OUTPUT (QVO)

Quiescent Voltage Output VOUT(Q) TA = 25°C 2.45 2.5 2.55 V

Quiescent Voltage Output

Equivalent PWM D(Q) TA = 25°C, VCC = 4.5 to 5.5 V 49 50 51 %D

PWM CARRIER FREQUENCY

Carrier Frequency fPWM TA = 25°C 3.6 4 4.4 kHz

SENSITIVITY

Sensitivity Temperature Coefficient TCSENS

Programmed at TA = 150°C, calculated relative

to Sens at 25°C 0.08 0.12 0.16 %/°C

Analog Sensitivity7Sen

A1359LLETR-T,

A1359LLETR-MS-T B = ±125 G, TA = 25°C 8.73 9.0 9.27 mV/G

A1359LLETR-RP-T,

A1359LLETR-RP-MS-T B = ±125 G, TA = 25°C –9.27 –9.0 –8.73 mV/G

ERROR COMPONENTS

PWM to Analog Output Mismatch8VOUTERR

1.75 V < VOUT < 3.25 V –57.4 – +57.4 mV

VOUT = 1.25 V, VOUT = 3.75 V –85 – +85 mV

Linearity Sensitivity Error9LinERR – ±0.5 – %

Symmetry Sensitivity Error9SymERR – ±0.5 – %

Ratiometry Quiescent Voltage

Output Error10 RatVOUT(Q)

Across supply voltage range,

(relative to VCC = 5 V) – ±0.5 – %

Ratiometry Sensitivity Error9RatSens

Across supply voltage range,

(relative to VCC = 5 V) – ±0.5 – %

Ratiometry Clamp Error10 RatVOUTCLP

TA = 25°C, across supply voltage range, (relative

to VCC = 5 V) – ±0.5 – %

Quiescent Voltage Output Drift Through

Temperature Range ∆VOUT(Q) TA =150°C –17 – +17 mV

Sensitivity Drift Due to Package

Hysteresis ∆SensPKG TA = 25°C, after temperature cycling – ±2 – %

1 1 G (gauss) = 0.1 mT (millitesla).

2 At power-up, the output is held low until VCC exceeds VUVLOHI

. When the device reaches the operational power level, the output remains valid until

VCC drops below VUVLOLO

, when the output is pulled low.

3 Determined by design and characterization, not evaluated at final test.

4 fc varies as much as approximately ±20% across the full operating ambient temperature range and process.

5 VCLPL and VCLPH scale with VCC , due to ratiometry.

6 Load capacitance and resistance directly effects the rise time of the PWM output by tr = 0.35 × 2 × π × RL × CL.

7 Room temperature sensitivity can drift, ΔSensLIFE , by an additional 3% (typical worst case) over the life of the product.

8 See Characteristic Definitions section.

9 Applicable to both analog and PWM channels. Tested at Allegro factory for only the analog channel, and determined by design and characterization

for the PWM channel.

10 Applies only to the analog channel.

OPERATING CHARACTERISTICS (continued): Valid over full operating temperature range, TA, CBYPASS = 0.1 µF , VCC = 5 V,

unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit1

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

CHARACTERISTIC DEFINITIONS

Figure 1: Denition of Analog Power-On Time, tPOVOUT Figure 2: Denition of PWM Power-On Time, tPOPWM

VCC

VCC(min)

VOUT

90% VOUT

t1= time at which power supply reaches

minimum specified operating voltage

t2=

time at which output voltage settles

within ±10% of its steady state value

under an applied magnetic field

t1t2

tPOVOUT

VCC(typ)

Time

VCC(min)

tPOPWM

First valid duty cycle

VCC

VPWMOUT

Time

B-field

PWMOUT

Propagation

Delay

1 ms

ADC BDC

ADC – DC corresponds to the A field

BDC – DC corresponds to the B field

Response

Time

0.9×

CDC

CDC – DC corresponds to the 0.9

C field

Power-On Time: When the supply is ramped to its operating

voltage, the device requires a finite time to power its internal

components before supplying a valid PWM output duty-cycle.

Power-On Time for analog output, tPOVOUT, is defined as the time

it takes for the output voltage to settle within ±10% of its steady-

state value after the power supply has reached its minimum speci-

fied operating voltage, VCC(min). (See Figure 1.)

Power-On Time is specified in a different way for the PWM out-

put than the analog output. For the PWM output, the Power-On

Time, tPOPWM, is defined as the time it takes for the duty cycle to

settle within ±10% of the target steady state value from the time

the power supply has reached the minimum specified operating

voltage, VCC(min). (See Figure 2.)

Response Time: The time interval, tRESPONSEPWM or

tRESPONSEVOUT , between: a) when the applied magnetic field

reaches 90% of its final value, and b) when the sensor IC reaches

90% of its output corresponding to the applied magnetic field

(PWM duty cycle or analog VOUT ). Figure 3 illustrates an

example with the PWM output. Response time is conceptually

the same for the analog output.

Figure 3: Denition of Response Time for PWM output

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Delay to Clamp: A large magnetic input step may cause the

clamp to overshoot its steady-state value. The delay to clamp,

tCLPVOUT

, is defined as the time it takes for the output voltage to

settle within 1% of its steady-state value after initially passing

through its steady-state voltage. This is conceptually the same for

the PWM output duty cycle settling to the steady-state value. (See

Figure 4.)

Quiescent Voltage Output: In the quiescent state (no signifi-

cant magnetic field: B = 0 G), the analog output, VOUT , is ratio-

metric to the supply voltage, VCC

, throughout the entire operating

range of VCC

. The PWM output, VPWMOUT

, by virtue of being a

% duty-cycle will remain at 50% nominal throughout the entire

VCC operating range (4.5 to 5.5 V).

Quiescent Output Drift through Temperature Range:

Due to internal component tolerances and thermal consider-

ations, the Quiescent Voltage Output, VOUT(Q) , may drift from

its nominal value across the operating ambient temperature, TA.

For purposes of specification, the Quiescent Voltage Output Drift

Through Temperature Range, ∆VOUT(Q) (mV), is defined as:

VOUT(Q)(TA) – VOUT(Q)(25°C)

∆VOUT(Q) = (1)

Sensitivity: Assuming the sensitivity of the device is posi-

tive (Positive Polarity: A1359LLETR-T, A1359LLETR-MS-T),

the presence of a south-polarity magnetic field perpendicular

to the branded surface of the package face increases the output

voltage from its quiescent value toward the supply voltage rail.

The amount of the output voltage increase is proportional to the

magnitude of the magnetic field applied. Conversely, the applica-

tion of a north-polarity field decreases the output voltage from

its quiescent value. For the case of the reverse polarity device

(A1359LLETR-RP-T, A1359LLETR-RP-MS-T), the presence

of a south-polarity magnetic field perpendicular to the branded

surface of the package face decreases the output voltage from its

quiescent value toward the ground rail. The amount of the output

voltage decrease is proportional to the magnitude of the magnetic

field applied. Conversely, the application of a north-polarity field

increases the output voltage from its quiescent value. This pro-

portionality is specified as the magnetic sensitivity, Sens (mV/G),

of the device and is defined as:

VOUT(BPOS) – VOUT(BNEG)

BPOS – BNEG

Sens = (2)

where BPOS and BNEG are two magnetic fields with opposite

polarities.

Sensitivity Temperature Coefficient: Device sensitiv-

ity changes as temperature changes, with respect to its pro-

grammed Sensitivity Temperature Coefficient, TCSENS. TCSENS

is programmed at 150°C, and calculated relative to the nominal

sensitivity programming temperature of 25°C. TCSENS (%/°C) is

defined as:

SensT2 – SensT1

SensT1 T2–T1

TCSENS =×

100%

























(3)

where T1 is the nominal Sens programming temperature of 25°C,

and T2 is the TCSENS programming temperature of 150°C. The

ideal value of Sens through the full ambient temperature range,

SensIDEAL(TA), is defined as:

SensT1× [100% +TCSENS (TA –T1)]

SensIDEAL(TA) =

(4)

Sensitivity Drift Due to Package Hysteresis: Package

stress and relaxation can cause the device sensitivity at TA = 25°C

to change during and after temperature cycling. This change in

sensitivity follows a hysteresis curve. For purposes of specifica-

tion, the Sensitivity Drift Due to Package Hysteresis, ∆SensPKG,

is defined as:

Sens(25°C)2 – Sens(25°C)1

Sens(25°C)1

∆SensPKG =×

100 (%)

(5)

Figure 4: Denition of Delay to Clamp

time (µs)

Magnetic Input Signal

t1= time at which output voltage initially

reaches steady state clamp voltage

t2= time at which output voltage settles to

within 1% of steady state clamp voltage

CLP(HIGH)

t1t2

tCLPPWM or

tCLPVOUT

VPWMOUT or VOUT

Device Output,

VPWMOUT or VOUT (V)

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

where Sens(25°C)1 is the programmed value of sensitivity

at TA = 25°C, and Sens(25°C)2 is the value of sensitivity at

TA = 25°C, after temperature cycling TA up to 150°C, down to

–40°C, and back to up 25°C.

Linearity Sensitivity Error: The A1359 is designed to provide

linear output in response to a ramping applied magnetic field.

Consider two magnetic fields, B1 and B2. Ideally, the sensitivity

of a device is the same for both fields, for a given supply voltage

and temperature. Linearity error is present when there is a differ-

ence between the sensitivities measured at B1 and B2.

Linearity Sensitivity Error is calculated separately for the positive

(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.

Linearity error (%) is measured and defined as:

SensBPOS2

SensBPOS1

SensBNEG2

SensBNEG1

1–

LinERRPOS

LinERRPOS , LinERRNEG

=×

100 (%)













1–

LinERRNEG =













LinERR max













(6)

where:

|VOUT(Bx) – VOUT(Q)|

SensBx=

(7)

and BPOSx and BNEGx are positive and negative magnetic

fields, with respect to the quiescent voltage output such that

BPOS2 > BPOS1 and BNEG2 > BNEG1.

Then:

Lin

ERR

max(

Lin

ERRPOS

, |Lin

ERRNEG

(8)

Clamping Range: The output voltage clamps, VCLPH and

VCLPL , limit the operating magnetic range of the applied field in

which the device provides a linear output. The maximum posi-

tive and negative applied magnetic fields in the operating range

can be calculated:

VCLP(HIGH) – VOUT(Q)

Sens

|BPOS(max)| =

VOUT(Q) – VCLP(LOW)

Sens

|BNEG(max)| =

(9)

Symmetry Sensitivity Error: The magnetic sensitivity of the

A1359 device is constant for any two applied magnetic fields of

equal magnitude and opposite polarities. Symmetry Sensitivity

Error, SymERR (%), is measured and defined as:

Sens

BPOS

SensBNEG

1–

SymERR =×

100 (%)













(10)

where SensBx is as defined in equation 7, and BPOS and

BNEG are positive and negative magnetic fields such that

|BPOS| = |BNEG|.

Ratiometry Error: The A1359 provides a ratiometric output.

This means that the quiescent voltage output, VOUT(Q)

, mag-

netic sensitivity, Sens, and clamp voltage, VCLPH and VCLPL, are

proportional to the supply voltage, VCC . In other words, when

the supply voltage increases or decreases by a certain percent-

age, each characteristic also increases or decreases by the same

percentage. Error is the difference between the measured change

in the supply voltage relative to 5 V, and the measured change in

each characteristic.

The ratiometric error in quiescent voltage output, RatVOUT(Q)

(%), for a given supply voltage, VCC, is defined as:

OUT(Q)(VCC)

/ V

OUT(Q)(5V)

/ 5 V

1–

Rat

ERRVOUT(Q)

=×

100 (%)













(11)

The ratiometric error in magnetic sensitivity, RatSens (%), for a

given supply voltage, VCC , is defined as:

Sens

(VCC)

/ Sens

(5V)

VCC / 5 V

1–

RatERRSens =×

100 (%)

(12)

The ratiometric error in the clamp voltages, RatVOUTCLP (%), for

a given supply voltage, VCC, is defined as:

CLP(VCC)

/ V

CLP(5V)

VCC / 5 V

1–

RatVOUTCLP =×

100 (%)

(13)

where VCLP is either VCLPH or VCLPL.

Note: Equations 11 and 13 apply to the analog channel (VOUT),

only. Recall that for the PWM output, the 0 G output is 50% from

4.5 to 5.5 V. However, as sensitivity is ratiometric with VCC for

both analog and PWM channels, equation 12 applies to both the

analog and the PWM channels.

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Duty Cycle Jitter: The duty cycle of the PWM output may

vary slightly over time despite the presence of a constant applied

magnetic field and a constant Carrier Frequency, fPWM , for the

PWM signal. This phenomenon is known as jitter, JitterPWM (%) ,

and is defined as:

JitterPWM = ± DB(max) – DB(min)

2 (14)

where DB(max) and DB(min) are the maximum and minimum

duty cycles, measured in 1000 PWM clock periods, in a constant

applied magnetic field.

Undervoltage Lockout: The A1359 features an undervolt-

age lockout function that ensures that the device will output a

valid signal when VCC is above a certain threshold, VUVLOHI

and remains valid until VCC falls below a lower threshold,

VUVLOLOW

. The undervoltage lockout feature provides a hyster-

esis of operation to eliminate indeterminate output states.

The output of the A1359 is held low (GND) until VCC exceeds

VUVLOHI . When VCC exceeds VUVLOHI

, the device powers-up

and the output provides a ratiometric output voltage proportional

to the input magnetic signal, and VCC . If VCC should drop back

down below VUVLOLOW for more than tuvlo after the device is

powered-up, the output would be pulled low. (See Figure 5.)

PWM to Analog Output Mismatch: When comparing the

PWM output to the analog output for channel mismatch, the

following equation is used to convert PWM (% D, duty cycle) to

voltage (V):

VPWMOUT = D(Q) + D(field) = VOUT(Q) × 20.0 %D / V

+ VOUT(B) × 21.0%D / V (15)

where:

D(Q) is the quiescent PWM signal with no input field (B = 0 G),

and D(field) is the PWM signal in response to the input magnetic

field. In other words, the product of PWM sensitivity (%D/G)

and input magnetic field (G). (See Figure 6.)

Figure 5: UVLO operation

VPWMOUT

or VOUT

tUVLO

VCC

VUVLOHI

VUVLOLO

time

Figure 6: Denition of PWM to Analog Output

Mismatch, VOUTERR

+VOUT (V)

+VPWMOUT (V)

Digital

Channel

Analog Channel

VOUTERR=

±85 mV

VOUTERR=

±85 mV

1.25

1.75

3.753.25

3.25

3.75

VOUTERR=

±57.4 mV

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Chopper Stabilization Technique

A1359

VOUT

GND

0.1

5 V µF

RLCL

PWMOUT

VCC

4.7 nF

RPULLUP

Optional: Recommended

for EMC robustness

Amp

Regulator

Clock/Logic

Hall Element

Tuned

Filter

Anti-aliasing

LP Filter

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small-signal voltage developed across

the Hall element. This voltage is disproportionally small relative

to the offset that can be produced at the output of the Hall sensor

IC. This makes it difficult to process the signal while maintain-

ing an accurate, reliable output over the specified operating

temperature and voltage ranges. Chopper stabilization is a unique

approach used to minimize Hall offset on the chip. Allegro

employs a technique to remove key sources of the output drift

induced by thermal and mechanical stresses. This offset reduction

technique is based on a signal modulation-demodulation process.

The undesired offset signal is separated from the magnetic field-

induced signal in the frequency domain, through modulation.

The subsequent demodulation acts as a modulation process for

the offset, causing the magnetic field-induced signal to recover

its original spectrum at base band, while the DC offset becomes

a high-frequency signal. The magnetic-sourced signal then can

pass through a low-pass filter, while the modulated DC offset

is suppressed. In addition to the removal of the thermal- and

stress-related offset, this novel technique also reduces the amount

of thermal noise in the Hall sensor while completely removing

the modulated residue resulting from the chopper operation. The

chopper stabilization technique uses a high-frequency sampling

clock. For demodulation process, a sample-and-hold technique

is used. This high-frequency operation allows a greater sampling

rate, which results in higher accuracy and faster signal-processing

capability. This approach desensitizes the chip to the effects

of thermal and mechanical stresses, and produces devices that

have extremely stable quiescent Hall output voltages and precise

recoverability after temperature cycling. This technique is made

possible through the use of a BiCMOS process, which allows the

use of low-offset, low-noise amplifiers in combination with high-

density logic integration and sample-and-hold circuits.

Figure 7: Typical Application Circuit

Figure 8: Concept of Chopper Stabilization Technique

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Package LE, 8-Pin TSSOP

1.10 MAX

0.15

0.05

0.30

0.19

0.20

0.09

8º

0º

0.60

1.00 REF

SEATING

PLANE

A1359LLETR-T A1359LLETR-RP-T

C0.10

0.65 BSC

0.25 BSC

+0.15

–0.10

3.00±0.10

4.40±0.106.40 BSC

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

For Reference Only; not for tooling use (reference MO-153 AA)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

6.10

0.65

0.45

1.70

Reference land pattern layout (reference IPC7351 SOP65P640X110-8M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias can improve

thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

1.50

2.20

Branding scale and appearance at supplier discretion

Hall element, not to scale

Branded Face

EActive Area Depth 0.36 mm REF

359

YYWW

59R

YYWW

CBranding Reference View

Top line is device designator

= Supplier emblem

Y = Last two digits of year of manufacture

W = Week of manufacture

Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC

With Analog and Pulse-Width-Modulated Outputs

A1359

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

1 June 18, 2013 Update ICC and package drawing.

2 February 26, 2016 Added A1359LLETR-MS-T and A1359LLETR-RP-MS-T part options.

3 February 19, 2019 Minor editorial updates

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.