A1359 Factory-Programmed Dual-Output Linear-Hall Effect-Sensor IC With Analog and Pulse-Width-Modulated Outputs FEATURES AND BENEFITS DESCRIPTION New applications for linear output Hall-effect sensors, such as displacement and angular position, require high accuracy in conjunction with redundant outputs. The Allegro A1359 programmable, linear, Hall effect sensor IC has been designed specifically to achieve both goals. The features associated with this linear device make it ideal for use in automotive and industrial applications requiring high accuracy, and this temperature-stable device operates across an extended temperature range: -40C to 150C. *Dual tracking outputs: analog voltage output and pulsewidth-modulated (PWM) output *Matched analog and PWM outputs enable user to detect various output error conditions *Factory-programmed offset, sensitivity, and polarity *Sensitivity temperature coefficient (TC) and QVO/QD temperature coefficient programmed at AllegroTM for improved accuracy *High-speed chopping scheme minimizes quiescent voltage output (QVO) drift across temperature *Temperature-stable QVO and sensitivity *Output voltage clamps provide short-circuit diagnostic capabilities *Wide ambient temperature range: -40C to 150C *Immune to mechanical stress *Enhanced EMC performance for stringent automotive applications The accuracy of the device is enhanced via programmability at the Allegro factory for optimization of device sensitivity, the quiescent voltage output (QVO: output with no magnetic field), and quiescent duty cycle (QD) for a given application or circuit. The A1359 also allows optimized performance across the entire operating temperature range via programming the temperature coefficients for both sensitivity and QVO/QD at Allegro end-of-line test. This ratiometric Hall-effect sensor IC provides an analog voltage, and a PWM signal with duty cycle, that are proportional to the applied magnetic field. Package: 8-pin TSSOP (suffix LE) surface mount Each BiCMOS monolithic circuit integrates a Hall element, temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal highgain amplifier, a clamped low-impedance output stage and a proprietary dynamic offset cancellation technique. The A1359 is provided in an 8-contact surface-mount TSSOP (suffix LE) which is lead (Pb) free, with 100% matte-tin leadframeplating. Not to scale Functional Block Diagram VSUPPLY VCC Chopper Switches Amp Signal Recovery Signal Conditioning Low-Pass Filter 100 nF VOUT RPULLUP Sensitivity, QVO, and Temperature Compensation CBYPASS Mismatch Compensation PWM Frequency Trim PWMOUT PWM Carrier Generation GND A1359-DS, Rev. 3 MCO-0000603 February 19, 2019 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 SELECTION GUIDE Part Number Factory-Programmed Output Polarity Forward: Output voltage increases with increasing A1359LLETR-T positive (south) applied magnetic field Reverse: Output voltage increases with increasing A1359LLETR-RP-T negative (north) applied magnetic field Forward: Output voltage increases with increasing A1359LLETR-MS-T positive (south) applied magnetic field Reverse: Output voltage increases with increasing A1359LLETR-RP-MS-T negative (north) applied magnetic field *Contact Allegro for additional packing options Packing* 4000 units /reel 4000 units /reel 4000 units /reel 4000 units /reel ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Forward Supply Voltage VCC Reverse Supply Voltage VRCC Forward Output Voltage VOUT Reverse Output Voltage VROUT Forward PWM Output Voltage VPWM Reverse PWM Output Voltage Output Source Current Output Sink Current PWM Output Source Current Rating Refer to Power Derating section Refer to Power Derating section Refer to Power Derating section VRPWM Unit 6 V -0.1 V 7 V -0.1 V 7 V -0.1 V 2 mA IOUT(SOURCE) VOUT to GND IOUT(SINK) VCC to VOUT 10 mA VPWM > -0.5V, TA = 25C -50 mA Internal current limiting is intended to protect the device from momentary short circuits and not intended for continuous operation 25 mA IPWM(SOURCE) PWM Output Sink Current Notes IPWM(SINK) Operating Ambient Temperature TA -40 to 150 C Storage Temperature Tstg -65 to 170 C TJ(max) 165 C Maximum Junction Temperature Temperature range L PINOUT DIAGRAM AND TERMINAL LIST TABLE Terminal List Table Pinout Diagram PWMOUT 1 VCC 2 Number Name 1 PWMOUT 2 VCC Function Open-drain PWM output Input power supply; tie to GND with bypass capacitor 8 NC 3 NC 7 GND 4 VOUT 5 NC No connect, tie to either GND or VCC 6 NC No connect, tie to either GND or VCC 7 GND 8 NC NC 3 6 NC VOUT 4 5 NC No connect, tie to either GND or VCC Output signal Device ground No connect, tie to either GND or VCC Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A1359 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol RJA Package Thermal Resistance Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 145 C/W *Additional thermal information available on the Allegro website Power Dissipation versus Ambient Temperature 1000 900 800 600 (R J A = 500 14 5 C /W 400 ) Power Dissipation, PD (mW) 700 300 200 100 0 20 40 60 80 100 120 140 Temperature, TA (C) 160 180 Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 OPERATING CHARACTERISTICS: Valid over full operating temperature range, TA, CBYPASS = 0.1 F, VCC = 5 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit1 ELECTRICAL CHARACTERISTICS Supply Voltage VCC Undervoltage Threshold2 4.5 5 5.5 V VUVLOHI TA = 25C (device powers on) - - 3 V VUVLOLOW TA = 25C (device powers off) 2.5 - - V - 10 13.5 mA Supply Current ICC VCC = 5 V VZ TA = 25C, ICC = 20 mA 6 8.3 - V Small signal, -3 dB - 2 - kHz fC TA = 25C - 400 - kHz VN TA = 25C, CBYPASS = 0.1 F, Sens = 5 mV/G, no load on VOUT - 6 - mV(p-p) Input Referred RMS Noise Density3 VNRMS T = 25C, CBYPASS = open, no load on VOUT, f << BWi - 1.9 - mG/Hz DC Output Resistance3 ROUT - <1 - k Supply Zener Clamp Voltage Internal Bandwidth3 BWi Chopping Frequency3,4 ANALOG OUTPUT CHARACTERISTICS Output Referred Noise3 Output Load Resistance3 Output Load Capacitance3 Analog Output Current Limit Output Voltage Clamp5 RL VOUT to GND 4.7 - - CL VOUT to GND - - 10 nF ILIMIT(ALG) RPULLUP = 0 10 - 80 mA VCLPH TA = 25C, B = +350 G, RL = 10 k (VOUT to GND) 4.25 4.5 4.65 V VCLPL TA = 25C, B = -350 G, RL = 10 k (VOUT to VCC) 0.4 0.5 0.7 V Impulse magnetic field of 300 G - - 500 s tRESPONSE_ Response Time3 VOUT TA = 25C, Primary Overload > 5000 G - - 750 s Power-On Time for Analog3 tPOVOUT TA = 25C, CL (probe) = 10 pF, on VOUT - 250 - s Delay to Clamp for Analog3 tCLPVOUT TA = 25C, CL = 10 nF, on VOUT - 30 - s Settling Time3 tSETTLEVOUT PWM OUTPUT CHARACTERISTICS IPWMOUT(SINK) 20 mA, PWMOUT transistor on - - 0.6 V IPWMOUT(SINK) 10 mA, PWMOUT transistor on - - 0.5 V ILIMIT RPULLUP = 0 30 60 110 mA PWMOUT Leakage Current ILEAK VCC = GND, 0 V VPWMOUT 5 V, PWMOUT transistor off - 0.1 10 A PWMOUT Zener Clamp Voltage VZOUT PWMOUT Saturation Voltage VSAT PWMOUT Current Limit PWMOUT Rise Time3 PWMOUT Fall Time3 Power-On Time for PWM3 Delay to Clamp for PWM3 Response Time3 Settling Time3 IPWMOUT(SINK) = 10mA, TA = 25C 28 - - V tr TA = 25C, RPULLUP = 2 k, CL = 20pF - 3 - s tf TA = 25C, RPULLUP = 2 k, CL = 20 pF - 3 - s tPOPWM TA = 25C, CL (probe) = 10 pF, on PWMOUT - 500 - s tCLPPWM TA = 25C, CL = 10 nF, on PWMOUT - 250 - s TA = 25C, Impulse magnetic field of 300 G - - 1.5 ms TA = 25C, Primary Overload > 5000 G - - 2.25 ms tRESPONSE_ PWM tSETTLEPWM Continued on the next page... Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 OPERATING CHARACTERISTICS (continued): Valid over full operating temperature range, TA, CBYPASS = 0.1 F, VCC = 5 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit1 PWM OUTPUT CHARACTERISTICS (continued) Load Resistance3,6 Load Capacitance3,6 Duty Cycle Jitter3 RPULLUP PWMOUT to VCC 2000 - - CL PWMOUT to GND - - 10 nF Measured over 1000 PWM output clock periods, 3 sigma values, Sens = 9 mV/G - 0.18 - %D 2.45 2.5 2.55 V JitterPWM QUIESCENT VOLTAGE OUTPUT (QVO) Quiescent Voltage Output VOUT(Q) Quiescent Voltage Output Equivalent PWM D(Q) TA = 25C, VCC = 4.5 to 5.5 V 49 50 51 %D fPWM TA = 25C 3.6 4 4.4 kHz Programmed at TA = 150C, calculated relative to Sens at 25C 0.08 0.12 0.16 %/C A1359LLETR-T, A1359LLETR-MS-T B = 125 G, TA = 25C 8.73 9.0 9.27 mV/G A1359LLETR-RP-T, A1359LLETR-RP-MS-T B = 125 G, TA = 25C -9.27 -9.0 -8.73 mV/G -57.4 - +57.4 mV -85 - +85 mV LinERR - 0.5 - % SymERR - 0.5 - % RatVOUT(Q) Across supply voltage range, (relative to VCC = 5 V) - 0.5 - % RatSens Across supply voltage range, (relative to VCC = 5 V) - 0.5 - % TA = 25C, across supply voltage range, (relative to VCC = 5 V) - 0.5 - % -17 - +17 mV - 2 - % TA = 25C PWM CARRIER FREQUENCY Carrier Frequency SENSITIVITY Sensitivity Temperature Coefficient Analog Sensitivity7 TCSENS Sen ERROR COMPONENTS PWM to Analog Output Mismatch8 Linearity Sensitivity Error9 Symmetry Sensitivity Error9 Ratiometry Quiescent Voltage Output Error10 Ratiometry Sensitivity Error9 Ratiometry Clamp Error10 VOUTERR RatVOUTCLP 1.75 V < VOUT < 3.25 V VOUT = 1.25 V, VOUT = 3.75 V Quiescent Voltage Output Drift Through Temperature Range VOUT(Q) TA =150C Sensitivity Drift Due to Package Hysteresis SensPKG TA = 25C, after temperature cycling 11 G (gauss) = 0.1 mT (millitesla). power-up, the output is held low until VCC exceeds VUVLOHI. When the device reaches the operational power level, the output remains valid until VCC drops below VUVLOLO, when the output is pulled low. 3 Determined by design and characterization, not evaluated at final test. 4 f varies as much as approximately 20% across the full operating ambient temperature range and process. c 5V CLPL and VCLPH scale with VCC, due to ratiometry. 6 Load capacitance and resistance directly effects the rise time of the PWM output by t = 0.35x2xxR xC . r L L 7 Room temperature sensitivity can drift, Sens LIFE, by an additional 3% (typical worst case) over the life of the product. 8 See Characteristic Definitions section. 9 Applicable to both analog and PWM channels. Tested at Allegro factory for only the analog channel, and determined by design and characterization for the PWM channel. 10 Applies only to the analog channel. 2 At Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 CHARACTERISTIC DEFINITIONS Power-On Time: When the supply is ramped to its operating voltage, the device requires a finite time to power its internal components before supplying a valid PWM output duty-cycle. Power-On Time for analog output, tPOVOUT, is defined as the time it takes for the output voltage to settle within 10% of its steadystate value after the power supply has reached its minimum specified operating voltage, VCC(min). (See Figure 1.) Power-On Time is specified in a different way for the PWM output than the analog output. For the PWM output, the Power-On Time, tPOPWM, is defined as the time it takes for the duty cycle to settle within 10% of the target steady state value from the time the power supply has reached the minimum specified operating voltage, VCC(min). (See Figure 2.) Response Time: The time interval, tRESPONSEPWM or tRESPONSEVOUT, between: a) when the applied magnetic field reaches 90% of its final value, and b) when the sensor IC reaches 90% of its output corresponding to the applied magnetic field (PWM duty cycle or analog VOUT ). Figure 3 illustrates an example with the PWM output. Response time is conceptually the same for the analog output. V VCC VCC(typ) VOUT 90% VOUT VCC VCC(min) VCC(min) t1 t2 tPOVOUT Time VPWMOUT t1= time at which power supply reaches minimum specified operating voltage First valid duty cycle t2= time at which output voltage settles within 10% of its steady state value under an applied magnetic field 0 Time tPOPWM +t Figure 1: Definition of Analog Power-On Time, tPOVOUT Figure 2: Definition of PWM Power-On Time, tPOPWM ADC - DC corresponds to the A field BDC - DC corresponds to the B field CDC - DC corresponds to the 0.9 x C field 1 ms 0.9 x C C B-field A B Time ADC BDC CDC PWMOUT Propagation Delay Response Time Figure 3: Definition of Response Time for PWM output Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 Delay to Clamp: A large magnetic input step may cause the clamp to overshoot its steady-state value. The delay to clamp, tCLPVOUT, is defined as the time it takes for the output voltage to settle within 1% of its steady-state value after initially passing through its steady-state voltage. This is conceptually the same for the PWM output duty cycle settling to the steady-state value. (See Figure 4.) Quiescent Voltage Output: In the quiescent state (no significant magnetic field: B = 0 G), the analog output, VOUT, is ratiometric to the supply voltage, VCC, throughout the entire operating range of VCC. The PWM output, VPWMOUT, by virtue of being a % duty-cycle will remain at 50% nominal throughout the entire VCC operating range (4.5 to 5.5V). Quiescent Output Drift through Temperature Range: Due to internal component tolerances and thermal considerations, the Quiescent Voltage Output, VOUT(Q), may drift from its nominal value across the operating ambient temperature, TA. For purposes of specification, the Quiescent Voltage Output Drift Through Temperature Range, VOUT(Q) (mV), is defined as: VOUT(Q) = VOUT(Q)(TA) - VOUT(Q)(25C) (1) Sensitivity: Assuming the sensitivity of the device is positive (Positive Polarity: A1359LLETR-T, A1359LLETR-MS-T), the presence of a south-polarity magnetic field perpendicular to the branded surface of the package face increases the output voltage from its quiescent value toward the supply voltage rail. Device Output, VPWMOUT or VOUT (V) VCLP(HIGH) VPWMOUT or VOUT tCLPPWM or tCLPVOUT t1 t2 t1= time at which output voltage initially reaches steady state clamp voltage t2= time at which output voltage settles to within 1% of steady state clamp voltage time (s) Figure 4: Definition of Delay to Clamp Magnetic Input Signal Magnetic Input Signal The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north-polarity field decreases the output voltage from its quiescent value. For the case of the reverse polarity device (A1359LLETR-RP-T, A1359LLETR-RP-MS-T), the presence of a south-polarity magnetic field perpendicular to the branded surface of the package face decreases the output voltage from its quiescent value toward the ground rail. The amount of the output voltage decrease is proportional to the magnitude of the magnetic field applied. Conversely, the application of a north-polarity field increases the output voltage from its quiescent value. This proportionality is specified as the magnetic sensitivity, Sens (mV/G), of the device and is defined as: VOUT(BPOS) - VOUT(BNEG) Sens = (2) BPOS - BNEG where BPOS and BNEG are two magnetic fields with opposite polarities. Sensitivity Temperature Coefficient: Device sensitivity changes as temperature changes, with respect to its programmed Sensitivity Temperature Coefficient, TCSENS. TCSENS is programmed at 150C, and calculated relative to the nominal sensitivity programming temperature of 25C. TCSENS (%/C) is defined as: 1 SensT2 - SensT1 TCSENS = 100% x SensT1 T2-T1 (3) where T1 is the nominal Sens programming temperature of 25C, and T2 is the TCSENS programming temperature of 150C. The ideal value of Sens through the full ambient temperature range, SensIDEAL(TA), is defined as: SensIDEAL(TA) = SensT1x [100% +TCSENS (TA -T1)] (4) Sensitivity Drift Due to Package Hysteresis: Package stress and relaxation can cause the device sensitivity at TA = 25C to change during and after temperature cycling. This change in sensitivity follows a hysteresis curve. For purposes of specification, the Sensitivity Drift Due to Package Hysteresis, SensPKG, is defined as: SensPKG = Sens(25C)2 - Sens(25C)1 Sens(25C)1 x 100 (%) Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com (5) 7 A1359 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs where Sens(25C)1 is the programmed value of sensitivity at TA=25C, and Sens(25C)2 is the value of sensitivity at TA=25C, after temperature cycling TA up to 150C, down to -40C, and back to up 25C. Linearity Sensitivity Error: The A1359 is designed to provide linear output in response to a ramping applied magnetic field. Consider two magnetic fields, B1 and B2. Ideally, the sensitivity of a device is the same for both fields, for a given supply voltage and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2. Linearity Sensitivity Error is calculated separately for the positive (LinERRPOS) and negative (LinERRNEG ) applied magnetic fields. Linearity error (%) is measured and defined as: where: SensBPOS2 LinERRPOS = 1- SensBPOS1 x 100 (%) SensBNEG2 LinERRNEG = 1- SensBNEG1 x 100 (%) LinERR = max LinERRPOS , LinERRNEG |VOUT(Bx) - VOUT(Q)| SensBx = Bx (6) and BPOSx and BNEGx are positive and negative magnetic fields, with respect to the quiescent voltage output such that BPOS2 > BPOS1 and BNEG2 > BNEG1. Symmetry Sensitivity Error: The magnetic sensitivity of the A1359 device is constant for any two applied magnetic fields of equal magnitude and opposite polarities. Symmetry Sensitivity Error, SymERR (%), is measured and defined as: SensBPOS x 100 (%) SymERR = 1- (10) SensBNEG where SensBx is as defined in equation 7, and BPOS and BNEG are positive and negative magnetic fields such that |BPOS|=|BNEG|. Ratiometry Error: The A1359 provides a ratiometric output. This means that the quiescent voltage output, VOUT(Q), magnetic sensitivity, Sens, and clamp voltage, VCLPH and VCLPL, are proportional to the supply voltage, VCC. In other words, when the supply voltage increases or decreases by a certain percentage, each characteristic also increases or decreases by the same percentage. Error is the difference between the measured change in the supply voltage relative to 5 V, and the measured change in each characteristic. The ratiometric error in quiescent voltage output, RatVOUT(Q) (%), for a given supply voltage, VCC, is defined as: (7) (8) Clamping Range: The output voltage clamps, VCLPH and VCLPL, limit the operating magnetic range of the applied field in which the device provides a linear output. The maximum positive and negative applied magnetic fields in the operating range can be calculated: VCLP(HIGH) - VOUT(Q) Sens VOUT(Q) - VCLP(LOW) |BNEG(max)| = Sens |BPOS(max)| = (11) The ratiometric error in magnetic sensitivity, RatSens (%), for a given supply voltage, VCC, is defined as: Then: LinERR = max( |LinERRPOS | , |LinERRNEG |) VOUT(Q)(VCC) / VOUT(Q)(5V) x 100 (%) RatERRVOUT(Q) = 1- VCC / 5 V (9) RatERRSens = 1- Sens(VCC) / Sens(5V) VCC / 5 V x 100 (%) (12) The ratiometric error in the clamp voltages, RatVOUTCLP (%), for a given supply voltage, VCC, is defined as: RatVOUTCLP = 1- VCLP(VCC) / VCLP(5V) VCC / 5 V x 100 (%) where VCLP is either VCLPH or VCLPL. (13) Note: Equations 11 and 13 apply to the analog channel (VOUT), only. Recall that for the PWM output, the 0 G output is 50% from 4.5 to 5.5 V. However, as sensitivity is ratiometric with VCC for both analog and PWM channels, equation 12 applies to both the analog and the PWM channels. Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A1359 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs Duty Cycle Jitter: The duty cycle of the PWM output may vary slightly over time despite the presence of a constant applied magnetic field and a constant Carrier Frequency, fPWM, for the PWM signal. This phenomenon is known as jitter, JitterPWM (%), and is defined as: JitterPWM = DB(max) - DB(min) 2 VUVLOHI VCC VUVLOLO tUVLO (14) where DB(max) andDB(min) are the maximum and minimum duty cycles, measured in 1000 PWM clock periods, in a constant applied magnetic field. VPWMOUT or VOUT Undervoltage Lockout: The A1359 features an undervoltage lockout function that ensures that the device will output a valid signal when VCC is above a certain threshold, VUVLOHI, and remains valid until VCC falls below a lower threshold, VUVLOLOW. The undervoltage lockout feature provides a hysteresis of operation to eliminate indeterminate output states. The output of the A1359 is held low (GND) until VCC exceeds VUVLOHI . When VCC exceeds VUVLOHI, the device powers-up and the output provides a ratiometric output voltage proportional to the input magnetic signal, and VCC. If VCC should drop back down below VUVLOLOW for more than tuvlo after the device is powered-up, the output would be pulled low. (See Figure 5.) PWM to Analog Output Mismatch: When comparing the PWM output to the analog output for channel mismatch, the following equation is used to convert PWM (% D, duty cycle) to voltage (V): VPWMOUT = D(Q) + D(field) = VOUT(Q) x 20.0 %D/V + VOUT(B) x 21.0%D/V(15) where: D(Q) is the quiescent PWM signal with no input field (B = 0 G), and D(field) is the PWM signal in response to the input magnetic field. In other words, the product of PWM sensitivity (%D/G) and input magnetic field (G). (See Figure 6.) time Figure 5: UVLO operation +VPWMOUT (V) VOUTERR= 85 mV Digital Channel 3.75 3.25 1.75 VOUTERR= 85 mV VOUTERR= 57.4 mV 1.25 1.25 1.75 3.25 3.75 +VOUT (V) Analog Channel Figure 6: Definition of PWM to Analog Output Mismatch, VOUTERR Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A1359 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs RPULLUP A1359 PWMOUT VOUT VCC 0.1 F 5V RL GND CL 4.7 nF Optional: Recommended for EMC robustness Figure 7: Typical Application Circuit Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small-signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. Allegro employs a technique to remove key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. In addition to the removal of the thermal- and stress-related offset, this novel technique also reduces the amount of thermal noise in the Hall sensor while completely removing the modulated residue resulting from the chopper operation. The chopper stabilization technique uses a high-frequency sampling clock. For demodulation process, a sample-and-hold technique is used. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with highdensity logic integration and sample-and-hold circuits. Regulator Clock/Logic Hall Element Amp Anti-aliasing Tuned LP Filter Filter Figure 8: Concept of Chopper Stabilization Technique Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs A1359 Package LE, 8-Pin TSSOP E 3.000.10 8 0.45 8 0 8 0.20 0.09 0.65 1.70 D 6.40 BSC 4.400.10 2.20 D A 1 6.10 0.60 +0.15 -0.10 1.00 REF 2 1 2 0.25 BSC 1.50 D SEATING PLANE GAUGE PLANE B PCB Layout Reference View Branded Face 0.30 0.19 0.65 BSC C 1.10 MAX 0.15 0.05 1 For Reference Only; not for tooling use (reference MO-153 AA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-8M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 59R YYWW SEATING PLANE 0.10 C 359 YYWW 8X 1 A1359LLETR-T C A1359LLETR-RP-T Branding Reference View Top line is device designator = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture Branding scale and appearance at supplier discretion D Hall element, not to scale E Active Area Depth 0.36 mm REF Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A1359 Factory-Programmed Dual-Output Linear Hall-Effect Sensor IC With Analog and Pulse-Width-Modulated Outputs Revision History Revision Revision Date Description of Revision 1 June 18, 2013 2 February 26, 2016 Update ICC and package drawing. Added A1359LLETR-MS-T and A1359LLETR-RP-MS-T part options. 3 February 19, 2019 Minor editorial updates Copyright (c)2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12