a
CMP04
Quad Low Power,
Precision Comparator
FEATURES
High Gain: 200 V/mV Typ
Single- or Dual-Supply Operation
Input Voltage Range Includes Ground
Low Power Consumption (1.5 mW/Comparator)
Low Input Bias Current: 100 nA Max
Low Input Offset Current: 10 nA Max
Low Offset Voltage: 1 mV Max
Low Output Saturation Voltage: 250 mV @ 4 mA
Logic Output Compatible with TTL, DTL, ECL, MOS,
and CMOS
Directly Replaces LM139/LM239/LM339 Comparators
GENERAL DESCRIPTION
Four precision independent comparators comprise the CMP04.
Performance highlights include a very low offset voltage, low
output saturation voltage, and high gain in a single-supply
design. The input voltage range includes ground for single-
supply operation and V– for split supplies. A low power
supply current of 2 mA, which is independent of supply voltage,
makes this the preferred comparator for precision applications
requiring minimal power consumption. Maximum logic inter-
face flexibility is offered by the open-collector TTL output.
Q3
Q2
100␮A 3.5␮A3.5␮A 100␮A
Q8
+INPUT
*
OUTPUT
Q4
Q7 *
–INPUT
Q6Q5
Q1
V+
*SUBSTRATE DIODES
Figure 1. Simplified Schematic (1/4 CMP04)
PIN CONNECTIONS
14-Lead SOIC
14
13
12
11
10
9
8
1
2
3
4
5
6
7
CMP04
14
3
2
OUT 2 OUT 3
OUT 1
V+
IN 1–
IN 1+
IN 2–
IN 2+
OUT 4
GND
IN 4+
IN 4–
IN 3+
IN 3–
TYPICAL INTERFACE
5.0
1/4
CMP04
3
12
100k⍀1/4
CD4011
Figure 2a. Driving CMOS
5.0
1/4
CMP04
3
12
10k⍀
1/4 SN7400
Figure 2b. Driving TTL
Rev. E Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
–2–
CMP04–SPECIFICATIONS
Parameter Symbol Conditions Min Typ Max Unit
Input Offset Voltage V
OS
R
S
= 0 Ω, R
L
= 5.1 kΩ, V
O
= 1.4 V
1
0.4 1 mV
Input Offset Current I
OS
I
IN
(+) – I
IN
(–), R
L
= 5.1 kΩ, V
O
= 1.4 V 2 10 nA
Input Bias Current I
B
I
IN
(+) or I
IN
(–) 25 100 nA
Voltage Gain A
V
R
L
≥ 15 kΩ, V+ = 15 V
2
80 200 V/mV
Large Signal Response Time t
r
V
IN
= TTL Logic Swing, V
REF
= 1.4 V
3
V
RL
= 5 V, R
L
= 5.1 kΩ300 ns
Small Signal Response Time t
r
V
IN
= 100 mV Step
3
, 5 mV Overdrive
V
RL
= 5 V, R
L
= 5.1 kΩ1.3 µs
Input Voltage Range CMVR Note 4 0 V+ – 1.5 V
Common-Mode Rejection Ratio CMRR Notes 2, 5 80 100 dB
Power Supply Rejection Ratio PSRR V+ = 5 V to 18 V
2
80 100 dB
Saturation Voltage V
OL
V
IN
(–) ≥ 1 V, V
IN
(+) = 0, I
SINK
≤ 4 mA 250 400 mV
Output Sink Current I
SINK
V
IN
(–) ≥ 1 V, V
IN
(+) = 0, V
O
≤ 1.5 V 6 16 mA
Output Leakage Current I
LEAK
V
IN
(+) ≥ 1 V, V
IN
(–) = 0, V
O
= 30 V 0.1 100 nA
Supply Current I+ R
L
=
∞
, All Comps V+ = 30 V 0.8 2.0 mA
NOTES
1
At output switch point, V
O
= 1.4 V, R
S
= 0 Ω with V+ from 5 V, and over the full input common-mode range (0 V to V+ – 1.5 V).
2
Guaranteed by design.
3
Sample tested.
4
The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range
is V+ – 1.5 V, but either or both inputs can go to 30 V without damage.
5
R
L
≥ 15 kΩ, V+ = 15 V, V
CM
= 1.5 V to 13.5 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(@ V+ = 5 V, T
A
= 25ⴗC, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +36 V or ±18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 36 V dc
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +36 V
Operating Temperature Range
CMP04FSZ . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature (T
J
) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Input Current (V
IN
< –3.0 V) . . . . . . . . . . . . . . . . . . . 50 mA
Output Short Circuit to GND . . . . . . . . . . . . . . . . Continuous
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Package Type ␪
JA2
␪
JC
Unit
14-Lead SOIC 120 36 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
θ
JA
is specified for worst-case mounting conditions, i.e., θ
JA
is specified for device
soldered to printed circuit board for SOIC package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the CMP04 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–3–
CMP04
CMP0 4FSZ
1
Parameter Symbol Conditions Min Typ Max Unit
Input Offset Voltage V
OS
R
S
= 0 Ω, R
L
= 5.1 kΩ12 mV
V
O
= 1.4 V
2
12 mV
Input Offset Current I
OS
I
IN
(+) – I
IN
(–) 4 20 nA
R
L
= 5.1 kΩ420nA
V
O
= 1.4 V 4 20 nA
Input Bias Current I
B
I
IN
(+) or I
IN
(–) 40 200 nA
Voltage Gain A
V
R
L
≥ 15 kΩ, V+ = 15 V
3
70 125 V/mV
Large Signal Response Time t
r
V
IN
= TTL Logic Swing 300 ns
V
REF
= 1.4 V
4
300 ns
V
RL
= 5 V, R
L
= 5.1 kΩ300 ns
Small Signal Response Time t
r
V
IN
= 100 mV Step
4
1.3 µs
5 mV Overdrive 1.3 µs
V
RL
= 5 V, R
L
= 5.1 kΩ1.3 µs
Input Voltage Range CMVR Note 5 0 V+ – 1.5 V
Common-Mode Rejection Ratio CMRR Notes 1, 3 60 100 dB
Power Supply Rejection Ratio PSRR V+ = 5 V to 18 V 80 100 dB
Saturation Voltage V
OL
V
IN
(–) ≥ 1 V, V
IN
(+) = 0, 250 700 mV
I
SINK
≤ 4 mA 250 700 mV
Output Sink Current I
SINK
V
IN
(–) ≥ 1 V, 5 16 mA
V
IN
(+) = 0, V
O
≤ 1.5 V 5 16 mA
Output Leakage Current I
LEAK
V
IN
(+) ≥ 1 V, 0.1 200 nA
V
IN
(–) = 0, V
O
= 30 V 0.1 200 nA
Supply Current I+ R
L
= ∞, All Comps 1.2 3.0 mA
V+ = 30 V 1.2 3.0 mA
NOTES
1
R
L
≥ 15 kΩ, V+ = 15 V, V
CM
= 1.5 V to 13.5 V.
2
At output switch point, V
O
= 1.4 V, R
S
= 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).
3
Guaranteed by design.
4
Sample tested.
5
The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode
voltage range is V+ – 1.5 V, but either or both inputs can go to +30 V without damage.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(@ V+ = 5 V, –40ⴗC ≤ TA ≤ +85ⴗC for CMP04FSZ, unless otherwise noted.)
3
3.6k⍀
2345617
13 12 11 10 914 8
3.6k⍀
4
2
1
CMP04
3.6k⍀
3.6k⍀
ZENER
5.8V TO 6.2V
1 WATT 470k⍀
30V
TO ADJACENT SOCKETS
–18V
+18V
–18V
100k⍀
ONE EACH
PER BOARD
+18V
MIL-STD-883, METHOD 1015, CONDITION B
Figure 3. Burn-In Circuit
REV. E
–4–
CMP04–Typical Performance Characteristics
TEMPERATURE (ⴗC)
V
OS
– OFFSET VOLTAGE (mV)
0.3
–40 0
0.2
0.1
0
–0.1
–0.2
–0.3
–20 20 40 60 80 100 120 140
–60
TPC 1. Offset Voltage vs.
Temperature
TEMPERATURE (ⴗC)
A
V
– VOLTAGE GAIN (V/mV)
160
–40 0
110
100
90
80
70
60
–20 20 40 60 80 100 120 140
–60
150
140
130
120
TPC 4. Voltage Gain vs.
Temperature
V+ – SUPPLY VOLTAGE (VDC)
IB – INPUT BIAS CURRENT (nA)
80
515
60
40
20
0
10 20 25 30 35 400
TA
= 0ⴗC
TA
= +25ⴗC/70ⴗC
TPC 2. Input Bias Current vs. V+
and Temperature
SUPPLY VOLTAGE (VDC)
1.1
515
0.9
0.3
0.1 10 20 25 30 35 400
TA
= 0ⴗC
TA
= +25ⴗC
SUPPLY CURRENT (mA)
0.5
0.7
TA
= +70ⴗC
TPC 5. Supply Current vs. Supply
Voltage
TEMPERATURE (ⴗC)
I
OS
– INPUT OFFSET CURRENT (nA)
3.0
–40 0
2.0
1.0
0
–1.0
–2.0
–3.0
–20 20 40 60 80 100 120 140
–60
TPC 3. Input Offset Current vs.
Temperature
I
O
– OUTPUT SINK CURRENT (mA)
V
OL
– SATURATION VOLTAGE (V
DC
)
10
1.0
0.1
0.01
0.001
0.1 1.0 10 1000.01
T
A
= +25ⴗC
OUT OF SATURATION
TPC 6. Output Voltage vs. Output
Current and Temperature
TIME (␮s)
6.0
5.0
–50
–100
0.5 1.0 1.5 2.00
20mV
T
A
= 25ⴗC
OUTPUT VOLTAGE
V
O
(V)
0
4.0
3.0
2.0
1.0
0
INPUT VOLTAGE
V
IN
(mV)
100mV
INPUT OVERDRIVE =
5.0mV
V
IN
5.1k⍀
V
OUT
5V
DC
TPC 7. Response Time for Various Input
Overdrives—Negative Transition
TIME (␮s)
6.0
5.0
–50
–100
0.5 1.0 1.5 2.00
20mV
TA
= 25ⴗC
OUTPUT VOLTAGE
VO (V)
0
4.0
3.0
2.0
1.0
0
INPUT VOLTAGE
VIN (mV)
5mV
INPUT OVERDRIVE =
100mV
VIN 5.1k⍀
V
OUT
5V
DC
TPC 8. Response Time for Various Input
Overdrives—Positive Transition
REV. E
CMP04
–5–
TYPICAL APPLICATIONS
V+
1/4
CMP04
6.2k⍀
VO
STROBE
INPUT
*
*OR LOGIC WITHOUT
PULLUP RESISTOR
Figure 4. Output Strobing
RS
+VREF HIGH
1/4
CMP04
1/4
CMP04
+VREF LOW
2RS
2RS
+VIN
Figure 5. Limit Comparator
10k⍀
+V
REF
1/4
CMP04
+V
IN
V
O
10M⍀
3k⍀
V+
Figure 6. Noninverting Comparator with Hysteresis
1M⍀
V+
1/4
CMP04
+VIN
VO
1M⍀
3k⍀
V+
1M⍀
Figure 7. Inverting Comparator with Hysteresis
100k⍀
V+
1/4
CMP04
VO
100k⍀
4.3k⍀
V+
100k⍀
V+
0
f = 186kHz
75pF
100k⍀
Figure 8. Square Wave Oscillator
1N914 1/4
CMP04 V
O
5.1k⍀
V+
100k⍀
V
IN1
100k⍀
V
IN2
Figure 9. Comparing Input Voltages of Opposite Polarity
REV. E
CMP04
–6–
+V
IN
1/4
CMP04
V
O
V+
V+
0
t
0
t
1
PW
1ms
0.01␮F
1M⍀
1M⍀1N914
1M⍀
1N914
100pF
V+
0
t
0
10k⍀
Figure 10. One-Shot Multivibrator
1/4
CMP04
V+
f
39k⍀
1k⍀
A
100k⍀
3k⍀
1k⍀0.375V
100k⍀
100k⍀
B
C1 = A • B • C
V+
001
Figure 11. AND Gate
+V
IN
1/4
CMP04
V
O
V+
V+
0
t
0
t
1
T
T = 0.3ms
1M⍀
100k⍀
4V
0
1S 10M⍀
100pF
1M⍀560k⍀
1/4
CMP04
10M⍀
15k⍀
240k⍀
62k⍀
100k⍀
Figure 14. One-Shot Multivibrator with Input Lockout
1/4
CMP04
V+
V+
0
t0t1t2
15k⍀
D2
1N914
80pF
R2
100k⍀
D1
1N914
R1
1M⍀
1M⍀
1M⍀
1M⍀
V+ FOR LARGE RATIOS OF R1/R2,
D1 CAN BE OMITTED.
Figure 12. Pulse Generator
1/4
CMP04
V+
f
200k⍀
1k⍀
A
100k⍀
V+
0
3k⍀
1k⍀0.075V
100k⍀
100k⍀
B
C1 = A + B + C
01
Figure 13. OR Gate
REV. E
CMP04
–7–
+VIN
V+
V+
0t0t3
INPUT GATING SIGNAL
V+
0t0t4
10k⍀
51k⍀
C1
0.001␮F
1/4
CMP04
10M⍀3.0k⍀
200k⍀
V
O3
10k⍀
V3
51k⍀
1/4
CMP04
10M⍀3.0k⍀
10k⍀
V+
V
O2
51k⍀
1/4
CMP04
10M⍀3.0k⍀
10k⍀
V+
V
O1
10k⍀
1/4
CMP04
V+
0t0t2
V+
0t0t1
15k⍀
V+
V3
V2
V1
0
V
C1
t0t4
t1t2t3
V2
V1
Figure 15. Time Delay Generator
REV. E
CMP04 Data Sheet
Rev. E | Page 8 of 8
OUTLINE DIMENSIONS
CONTROL LING D IMENSIONS ARE IN MILLI METERS ; INCH DIME NSIO NS
(IN PARENTHESES) ARE ROUNDED-OFF MI L LIMETER EQUIVALENTS FOR
REF E RENCE ON LY AND ARE NOT APPROPRIATE F OR USE I N DESIGN.
COM PLIANT TO JE DE C STANDARDS MS-012 -AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 ( 0 .0500)
BSC
SEATING
PLANE
0.25 ( 0 .0098)
0.10 ( 0 .0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 ( 0 .0500)
0.40 ( 0 .0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 16. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 T
A = 25°C, VOS Temperature Range Package Description Package Option
CMP04FSZ 1 mV −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
CMP04FSZ-REEL 1 mV −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1 Z = RoHS Compliant Part.
REVISION HISTORY
10/2018—Rev. D to Rev. E
Changed CMP04FS and CMP04F to CMP04FSZ .... Throughout
Updated Outline Dimensions .......................................................... 8
Moved Ordering Guide .................................................................... 8
Changes to Ordering Guide ............................................................. 8
3/2003—REV. C to REV. D
Renumbered TPCs and Figures ............................................. Global
Deletion of 14-Lead CERDIP and 14-Lead PDIP
Information .............................................................................. Global
Changes to Features .......................................................................... 1
Changes to Pin Connections .......................................................... 1
Changes to Absolute Maximum Ratings........................................ 2
Changes to Ordering Guide ............................................................ 2
Changes to Electrical Characteristics ............................................. 3
Removal of Dice Characteristics, Wafer Test Limits, and Typical
Electrical Characteristics Sections ................................................. 4
Changes to TPCs 2, 5, and 6 ............................................................ 4
Updated Outline Dimensions .......................................................... 8
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00266-0-10/18(E)