1
FEATURES APPLICATIONS
DE
MUX
DA[11:0]
DB[11:0]
MODE
GSET
Latch A
Latch B 12−b DAC
12−b DAC IOUTA1
IOUTA2
IOUTB1
IOUTB2
1.2 V Reference
WRTB WRTA CLKB CLKA
BIASJ_A
BIASJ_B
EXTIO
DVDD DGND AVDD AGND
SLEEP
DESCRIPTION
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
DUAL, 12-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER
Cellular Base Transceiver Station Transmit2
12-Bit Dual Transmit DAC
Channel275 MSPS Update Rate
CDMA: W-CDMA, CDMA2000, IS-95Single Supply: 3 V to 3.6 V
TDMA: GSM, IS-136, EDGE/UWC-136High SFDR: 85 dBc at 5 MHz
Medical/Test InstrumentationHigh IMD3: 78 dBc at 15.1 and 16.1 MHz
Arbitrary Waveform Generators (ARB)WCDMA ACLR: 70 dB at 30.72 MHz
Direct Digital Synthesis (DDS)Independent or Single Resistor Gain Control
Cable Modem Termination System (CMTS)Dual or Interleaved DataOn-Chip 1.2-V ReferenceLow Power: 330 mWPower-Down Mode: 15 mWPackage: 48-Pin TQFP
Figure 1.
The DAC5662 is a monolithic, dual-channel 12-bit high-speed digital-to-analog converter (DAC) with on-chipvoltage reference.
Operating with update rates of up to 275 MSPS, the DAC5662 offers exceptional dynamic performance andtight-gain and offset matching, characteristics that make it suitable in either I/Q baseband or direct IFcommunication applications.
Each DAC has a high-impedance differential current output, suitable for single-ended or differential analog-outputconfigurations. External resistors allow scaling the full-scale output current for each DAC separately or together,typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature compensated anddelivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.
The DAC5662 has two 12-bit parallel input ports with separate clocks and data latches. For flexibility, theDAC5662 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DEVICE INFORMATION
13 14 15
NC
NC
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
DA11 (MSB)
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0 (LSB) 17 18 19 20
AGND
47 46 45 44 4348 42
IOUTA1
IOUTA2
BIASJ_A
EXTIO
GSET
BIASJ_B
IOUTB2
DVDD
DB11 (MSB)
DB10
DGND
DVDD
WRTA/WRTIQ
CLKA/CLKIQ
CLKB/RESETIQ
WRTB/SELECTIQ
DGND
40 39 3841
21 22 23 24
37
NC
SLEEP
IOUTB1
MODE
AVDD
NC
Top View
48−Pin TQFP
PFB Package
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
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The DAC5662 has been specifically designed for a differential transformer coupled output with a 50- Ωdoublyterminated load. For a 20-mA full-scale output current a 4:1 impedance ratio (resulting in an output power of4 dBm) and 1:1 impedance ratio transformer (-2 dBm output power) are supported.
The DAC5662 is available in a 48-pin thin quad FlatPack (TQFP). Pin compatibility between family membersprovides 12-bit (DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5662 is pin compatible to theDAC2902 and AD9765 dual DACs. The device is characterized for operation over the industrial temperaturerange of -40 ° C to 85 ° C.
AVAILABLE OPTIONS
PACKAGED DEVICEST
A
48-TQFP
DAC5662IPFB-40 ° C to 85 ° C
DAC5662IPFBR
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 38 I Analog groundAVDD 47 I Analog supply voltageBIASJ_A 44 O Full-scale output current bias for DACABIASJ_B 41 O Full-scale output current bias for DACBCLKA/CLKIQ 18 I Clock input for DACA, CLKIQ in interleaved mode.CLKB/RESETI
19 I Clock input for DACB, RESETIQ in interleaved mode.Q
DA[11:0] 1-12 I Data port A. DA11 is MSB and DA0 is LSB. Internal pulldown.DB[11:0] 23-34 I Data port B. DB11 is MSB and DB0 is LSB. Internal pulldown.
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ABSOLUTE MAXIMUM RATINGS
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
DGND 15, 21 I Digital groundDVDD 16, 22 I Digital supply voltageEXTIO 43 I/O Internal reference output (bypass with 0.1 µF to AGND) or external reference input.GSET 42 I Gain-setting mode: H - 1 resistor, L - 2 resistors. Internal pullup.IOUTA1 46 O DACA current output. Full-scale with all bits of DA high.IOUTA2 45 O DACA complementary current output. Full-scale with all bits of DA low.IOUTB1 39 O DACB current output. Full-scale with all bits of DB high.IOUTB2 40 O DACB complementary current output. Full-scale with all bits of DB low.MODE 48 I Mode Select: H Dual Bus, L Interleaved. Internal pullup.13, 14, 35,NC - No connection36
Sleep function control input: H DAC in power-down mode, L DAC in operating mode. InternalSLEEP 37 I
pulldown.WRTA/WRTIQ 17 I Input write signal for PORT A (WRTIQ in interleaving mode).WRTB/SELEC
20 I Input write signal for PORT B (SELECTIQ in interleaving mode).TIQ
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
AVDD
(2)
-0.5 V to 4 VSupply voltage range
DVDD
(3)
-0.5 V to 4 VVoltage between AGND and DGND -0.5 V to 0.5 VVoltage between AVDD and DVDD -0.5 V to 0.5 VDA[11:0] and DB[11:0]
(3)
-0.5 V to DVDD + 0.5 VMODE, SLEEP, CLKA, CLKB, WRTA, WRTB
(3)
-0.5 V to DVDD + 0.5 VSupply voltage range
IOUTA1, IOUTA2, IOUTB1, IOUTB2
(2)
-1 V to AVDD + 0.5 VEXTIO, BIASJ_A, BIASJ_B, GSET
(2)
-0.5 V to AVDD + 0.5 VPeak input current (any input) +20 mAPeak total input current (all inputs) -30 mAOperating free-air temperature range -40 ° C to 85 ° CStorage temperature range -65 ° C to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Measured with respect to AGND.(3) Measured with respect to DGND.
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ELECTRICAL CHARACTERISTICS
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
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over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Specifications
Resolution 12 Bits
DC Accuracy
(1)
INL Integral nonlinearity -2 0.3 2 LSB1 LSB = IOUT
FS
/2
12
, T
A
= 25 ° CDNL Differential nonlinearity -2 0.2 2 LSB
Analog Output
Offset error 0.03 %FSRWith external reference ± 0.25 %FSRGain error
With internal reference 0.5 %FSRMinimum full-scale output current
(2)
2 mAMaximum full-scale output current
(2)
20 mAGain mismatch With internal reference -2 0.07 +2 %FSROutput voltage compliance range
(3)
-1 1.25 VR
O
Output resistance 300 k
C
O
Output capacitance 5 pF
Reference Output
Reference voltage 1.14 1.2 1.26 VReference output current
(4)
100 nA
Reference Input
V
EXTIO
Input voltage 0.1 1.25 VR
I
Input resistance 1 M
Small signal bandwidth 300 kHzC
I
Input capacitance 100 pF
Temperature Coefficients
ppm ofOffset drift 0
FSR/ ° Cppm ofWith external reference 50
FSR/ ° CGain drift
ppm ofWith internal reference 50
FSR/ ° CReference voltage drift 20 ppm/ ° C
(1) Measured differentially through 50 to AGND.(2) Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors andfull-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.(4) Use an external buffer amplifier with high impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, f
DATA
= 200 MSPS, f
OUT
= 1 MHz,independent gain set mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
AVDD Analog supply voltage 3 3.3 3.6 VDVDD Digital supply voltage 3 3.3 3.6 VIncluding output current through load 75 90 mAresistorI
AVDD
Supply current, analog
Sleep mode with clock 2.5 6 mASleep mode without clock 2.5 mA25 38 mAI
DVDD
Supply current, digital Sleep mode with clock 12.5 18 mASleep mode without clock < 10 µA330 390Power dissipation Sleep mode without clock 15 mWf
DATA
= 275 MSPS, f
OUT
= 20 MHz 350APSRR -0.2 0.2Power supply rejection ratio %FSR/VDPSRR -0.2 0.2T
A
Operating free-air temperature -40 85 ° C
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ELECTRICAL CHARACTERISTICS
DAC5662
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AC specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain setmode, differential 1:1 impedance ratio transformer coupled output, 50- doubly terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
f
clk
Maximum output update rate
(1)
275 MSPSt
s
Output settling time to 0.1% Mid-scale transition 20 ns(DAC)t
r
Output rise time 10% to 90% 1.4 ns(OUT)t
f
Output fall time 90% to 10% 1.5 ns(OUT)
IOUT
FS
= 20 mA 55 pA/ HzOutput noise
IOUT
FS
= 2 mA 30 pA/ Hz
AC Linearity
1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 50 81MSPS, f
OUT
= 1 MHz, IOUTFS = 0 dB1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 50 83MSPS, f
OUT
= 1 MHz, IOUTFS = -6 dB1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 50 81MSPS, f
OUT
= 1 MHz, IOUTFS = -12 dB1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 100 85MSPS, f
OUT
= 5 MHzSFDR Spurious free dynamic range dBc1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 100 78MSPS, f
OUT
= 20 MHz1st Nyquist zone, T
MIN
to T
MAX
, f
DATA
= 200
66 71MSPS, f
OUT
= 20 MHz1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 200 68MSPS, f
OUT
= 41 MHz1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 275 72MSPS, f
OUT
= 20 MHz1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 100 73MSPS, f
OUT
= 5 MHzSNR Signal-to-noise ratio dB1st Nyquist zone, T
A
= 25 ° C, f
DATA
= 200 67MSPS, f
OUT
= 20 MHzW-CDMA signal with 3.84-MHz Bandwidth,
70f
DATA
= 61.44 MSPS, IF = 15.360 MHzACLR Adjacent channel leakage ratio dBW-CDMA signal with 3.84-MHz Bandwidth,
70f
DATA
= 122.88 MSPS, IF = 30.72 MHzEach tone at -6 dBFS, T
A
= 25 ° C,f
DATA
= 200 MSPS, f
OUT
= 45.4 and 46.4 62MHzThird-order two-toneIMD3 dBcintermodulation
Each tone at -6 dBFS, T
A
= 25 ° C,f
DATA
= 100 MSPS, f
OUT
= 15.1 and 16.1 78MHz
Each tone at -12 dBFS, T
A
= 25 ° C,f
DATA
= 100 MSPS, f
OUT
= 15.6, 15.8, 16.2, 77and 16.4 MHzEach tone at -12 dBFS, T
A
= 25 ° C,IMD Four-tone intermodulation f
DATA
= 165 MSPS, f
OUT
= 68.8, 69.6, 71.2, 56 dBcand 72.0 MHzEach tone at -12 dBFS, T
A
= 25 ° C,f
DATA
= 165 MSPS, f
OUT
= 19.0, 19.1, 19.3, 74and 19.4 MHzT
A
= 25 ° C, f
DATA
= 165 MSPS,Channel isolation 97 dBcf
OUT
(CH1) = 20 MHz, f
OUT
(CH2) = 21 MHz
(1) Specified by design and bench characterization. Not production tested.
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital Input
V
IH
High-level input voltage 2 3.3 VV
IL
Low-level input voltage 0 0.8 VI
IH
High-level input current 50 µAI
IL
Low-level input current 10 µAI
IH(GSET)
High-level input current, GSET pin 7 µAI
IL(GSET)
Low-level input current, GSET pin -30 µAI
IH(MODE)
High-level input current, MODE pin -30 µAI
IL(MODE)
Low-level input current, MODE pin -80 µAC
I
Input capacitance 5 pF
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Timing - Dual Bus Mode
t
su
Input setup time 1 nst
h
Input hold time 1 nst
LPH
Input clock pulse high time 2 nst
LAT
Clock latency (WRTA/B to outputs) 4 4 clkt
PD
Propagation delay time 1.5 ns
Timing - Single Bus Interleaved Mode
t
su
Input setup time 0.5 nst
h
Input hold time 0.5 nst
LAT
Clock latency (WRTA/B to outputs) 4 4 clkt
PD
Propagation delay time 1.5 ns
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TYPICAL CHARACTERISTICS
-0.4
-0.3
-0.2
-0.1
-0.0
0.1
0.2
0.3
0.4
0 512 1024 1536 2048 2560 3072 3584 4096
Input Code
INL - Integral Nonlinearity Error - LSB
G001
-0.20
-0.15
-0.10
-0.05
-0.00
0.05
0.10
0.15
0.20
0 512 1024 1536 2048 2560 3072 3584 4096
Input Code
DNL - Differential Nonlinearity Error - LSB
G002
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
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INTEGRAL NONLINEARITY
vsINPUT CODE
Figure 2.
DIFFERENTIAL NONLINEARITY
vsINPUT CODE
Figure 3.
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60
65
70
75
80
85
90
95
100
0 4 8 12 16 20 24
fO − Output Frequency − MHz
fdata = 52 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
0 dBfS
−12 dBfS
−6 dBfS
G003
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30 35
fO − Output Frequency − MHz
fdata = 78 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
−6 dBfS
G004
0 dBfS
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30 35 40
fO − Output Frequency − MHz
fdata = 100 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
G005
0 dBfS
−6 dBfS
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30 35 40 45 50 55 60 65
fO − Output Frequency − MHz
fdata = 165 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
G006
0 dBfS
−6 dBfS
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
SPURIOUS-FREE DYNAMIC RANGE SPURIOUS-FREE DYNAMIC RANGEvs vsOUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 4. Figure 5.
SPURIOUS-FREE DYNAMIC RANGE SPURIOUS-FREE DYNAMIC RANGEvs vsOUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 6. Figure 7.
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f - Frequency - MHz
-100
-80
-60
-40
-20
0
0.0 7.8 15.6 23.4 31.2 39.0
fdata = 78 MSPS
fOUT = 15 MHz
Dual Bus Mode
Power - dBm
G007
f − Frequency − MHz
−100
−80
−60
−40
−20
0
0.0 16.5 33.0 49.5 66.0 82.5
fdata = 165 MSPS
fOUT = 30.1 MHz
Dual Bus Mode
Power − dBm
G008
fO − Output Frequency − MHz
60
65
70
75
80
85
90
95
0 5 10 15 20 25 30 35
Two-Tone IMD3 − dBc
fdata = 78 MSPS
Dual Bus Mode
G009
fO − Output Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 10 20 30 40 50
Two-Tone IMD3 − dBc
fdata = 165 MSPS
Dual Bus Mode
G010
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM SINGLE-TONE SPECTRUM
Figure 8. Figure 9.
TWO-TONE IMD3 TWO-TONE IMD3vs vsOUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 10. Figure 11.
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f − Frequency − MHz
−100
−80
−60
−40
−20
0
19.0 19.5 20.0 20.5 21.0 21.5 22.0
Power − dBm
G011
fdata = 78 MSPS
fOUT = 20.1 MHz
and 21.1 MHz
Dual Bus Mode
f − Frequency − MHz
−100
−80
−60
−40
−20
0
29.0 29.5 30.0 30.5 31.0 31.5 32.0
Power − dBm
G012
fdata = 165 MSPS
fOUT = 30.1 MHz
and 31.1 Mhz
Dual Bus Mode
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0 1 2 3 4 5 6 7 8 9 10
fdata = 122.88 MSPS
Baseband Signal
ACPR = 72 dB
Dual Bus Mode
Power − dBm
G013
f − Frequency − MHz
Power − dBm
G014
−120
−100
−80
−60
−40
−20
18 20 22 24 26 28 30 32 34 36 38 40 42 44
fdata = 122.88 MSPS
IF = 30.72 MHz
ACPR = 72 dB
Dual Bus Mode
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
TWO-TONE SPECTRUM TWO-TONE SPECTRUM
Figure 12. Figure 13.
POWER POWERvs vsFREQUENCY FREQUENCY
Figure 14. Figure 15.
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Digital Inputs and Timing
Digital Inputs
DA[11:0]
DB[11:0]
SLEEP
CLKA/B
WRTA/B
Internal
DigitalIn
DVDD
400W
100kW
DGND
GSET
MODE
Internal
DigitalIn
DVDD
400W
100kW
DGND
Input Interfaces
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
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The data input ports of the DAC5662 accept a standard positive coding with data bit D11 being the mostsignificant bit (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance willtypically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as longas the timing specifications are met. Similarly, the setup and hold times may be chosen within their specifiedlimits.
All digital inputs of the DAC5662 are CMOS compatible. Figure 16 and Figure 17 show schematics of theequivalent CMOS digital inputs of the DAC5662. The pullup and pulldown circuitry is approximately equivalent to100k . The 12-bit digital data input follows the offset positive binary coding scheme. The DAC5662 is designedto operate with a digital supply (DVDD) of 3 V to 3.6 V.
Figure 16. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
The DAC5662 features two operating modes selected by the MODE pin, as shown in Table 1 .For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its ownseparate data input bus, clock input, and data write signal (data latch-in).In single-bus interleaved mode, the data should be presented interleaved at the I-channel input bus. TheQ-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
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Dual-Bus Data Interface and Timing
Single-Bus Interleaved Data Interface and Timing
DAC5662
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................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
Table 1. Operating Modes
MODE PIN Mode pin connected to DGND Mode pin connected to DVDDBus input Single-bus interleaved mode, clock and write input equal for both Dual-bus mode, DACs operateDACs independently
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5662 consistof two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,WRTB) and clock (CLKA, CLKB) lines. The WRT lines control the channel input latches and the CLK linescontrol the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clockdomains having equal periods (but possibly different phases) are input to the DAC5662. This is defined by aminimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.This essentially implies that the rising edge of CLK must occur at the same time or before the rising edge of theWRT signal. A minimum delay of 2 ns should be maintained if the rising edge of the clock occurs after the risingedge of the write. Note that these conditions are satisfied when the clock and write inputs are connectedexternally. Note that all specifications were measured with the WRT and CLK lines connected together.
Figure 18. Dual Bus Mode Operation
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 19 shows the timing diagram. Ininterleaved mode, the I- and Q-channels share the write input (WRTIQ) and update clock (CLKIQ and internalCLKDACIQ). Multiplexing logic directs the input word at the I-channel input bus to either the I-channel input latch(SELECTIQ is high) or to the Q-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data valuein the Q-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is low,the data value in the I-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the I-channel input data rate is twice the update rate of the DAC core. As in dual-bus mode,it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch the I-and Q-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the I- andQ-DAC latches on the following falling edge of the write inputs. The DAC5662 clock input is divided by a factor oftwo before it is presented to the DAC latches.
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Valid Data
D[11:0]
tsu th
tlat tpd
tsettle
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
IOUT
or
IOUT
DAC5662
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Correct pairing of the I- and Q-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ isdivided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ andCLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respectto the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
Figure 19. Single-Bus Interleaved Mode Operation
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APPLICATION INFORMATION
Theory of Operation
DAC Transfer Function
IOUTFS +IOUT1 )IOUT2
(1)
IOUT1 +IOUTFS ǒCode
4096Ǔ
(2)
4095 - Code
I = I x
OUT2 OUTFS 4096
æ ö
÷
ç÷
ç÷
ç
è ø
(3)
IOUTFS +32 IREF +32 VREF
RSET
(4)
VOUT1 +IOUT1 RLOAD
(5)
VOUT2 +IOUT2 RLOAD
(6)
DAC5662
www.ti.com
................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
The architecture of the DAC5662 uses a current steering technique to enable fast switching and high updaterate. The core element within the monolithic DAC is an array of segmented current sources that are designed todeliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switcheseach time the DAC is updated and a corresponding output current is formed by steering all currents to eitheroutput summing node, IOUT1 and IOUT2. The complementary outputs deliver a differential output signal, whichimproves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy, improves the dynamicperformance (SFDR), and DNL. The current outputs maintain a high output impedance of greaterthan 300 k .
When GSET is high (one resistor mode), the full-scale output current for both DACs is determined by the ratio ofthe internal reference voltage (1.2 V) and an external resistor RSET connected to BIASJ_A. When GSET is low(two resistor mode), the full-scale output current for each DACs is determined by the ratio of the internalreference voltage (1.2 V) and separate external resistors RSET connected to BIASJ_A and BIASJ_B. Theresulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can rangefrom 2 mA to 20 mA, depending on the value of RSET.
The DAC5662 is split into a digital and an analog portion, each of which is powered through its own supply pin.The digital section includes edge-triggered input latches and the decoder logic, while the analog sectioncomprises the current source array with its associated switches, and the reference circuitry.
Each of the DACs in the DAC5662 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scaleoutput current, IOUTFS, is the summation of the two complementary output currents:
The individual output currents depend on the DAC code and can be expressed as:
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of thereference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltagedevelops at each output according to:
The value of the load resistance is limited by the output compliance specification of the DAC5662. To maintainspecified linearity performance, the voltage for IOUT1 and IOUT2 should not exceed the maximum allowablecompliance range.
Copyright © 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): DAC5662
VOUTDIFF +VOUT1 *VOUT2
(7)
VOUTDIFF +(2 Code *4095)
4096 IOUTFS RLOAD
(8)
Analog Outputs
AVDD
Current Source Array
IOUT1 IOUT2
S(1) S(1)C
RLOAD RLOAD
S(2) S(2)C S(N) S(N)C
Output Configurations
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
www.ti.com
The total differential output voltage is:
Figure 20. Analog Outputs
The DAC5662 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of theanalog output stage representing the differential topology is shown in Figure 20 . The output impedance of IOUT1and IOUT2 results from the parallel combination of the differential switches, along with the current sources andassociated parasitic capacitances.
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative andpositive compliance. The negative limit of 1 V is given by the breakdown voltage of the CMOS process andexceeding it compromises the reliability of the DAC5662 or even causes permanent damage. With the full-scaleoutput set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about 1V for a selected output current of IOUTFS = 2 mA. Care should be taken that the configuration of DAC5662 doesnot exceed the compliance range to avoid degradation of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the maximum full-scale output signal limited toapproximately 0.5 Vpp. This is the case for a 50- doubly terminated load and a 20-mA full-scale output current.A variety of loads can be adapted to the output of the DAC5662 by selecting a suitable transformer whilemaintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configurationin combination with a transformer will be instrumental for achieving excellent distortion performance.Common-mode errors, such as even-order harmonics or noise, can be substantially reduced. This is particularlythe case with high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select afull-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require lowpower consumption, but can tolerate a slight reduction in performance level.
The current outputs of the DAC5662 allow for a variety of configurations. As mentioned previously, utilizing theconverter s differential outputs yield the best dynamic performance. Such a differential output circuit may consistof an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for mostapplications with ac coupling, while op amps will be suitable for a dc-coupled configuration.
16 Submit Documentation Feedback Copyright © 2004 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC5662
Differential With Transformer
IOUT1 1:1
IOUT2
50
50
RLOAD
50
100 AGND
IOUT1 4:1
IOUT2
100
100
RLOAD
50
AGND
DAC5662
www.ti.com
................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
The single-ended configuration may be considered for applications requiring a unipolar output voltage.Connecting a resistor from either one of the outputs to ground converts the output current into aground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V orop-amp configuration may be considered.
Using an RF transformer provides a convenient way of converting the differential output signal into asingle-ended signal while achieving excellent dynamic performance. The appropriate transformer should becarefully selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thusimproving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitableimpedance ratio (winding ratio) the transformer can be used to provide optimum impedance matching whilecontrolling the compliance voltage for the converter outputs.
Figure 21 and Figure 22 show 50- doubly terminated transformer configurations with 1:1 and 4:1 impedanceratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enablea dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-V
PP
output for a 1:1 transformerand a 1-V
PP
output for a 4:1 transformer. In general, the 1:1 transformer configuration will have slightly betteroutput distortion, but the 4:1 transformer will have 6 dB higher output power.
Figure 21. Driving a Doubly Terminated 50- Cable Using a 1:1 Impedance Ratio Transformer
Figure 22. Driving a Doubly Terminated 50- Cable Using a 4:1 Impedance Ratio Transformer
Copyright © 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): DAC5662
Single-Ended Configuration
IOUT1
IOUT2
50 25
RLOAD
50
AGND
Reference Operation
Internal Reference
IOUTFS +32 IREF +32 VREF
RSET
(9)
External Reference
DAC5662
SLAS425B JULY 2004 REVISED MAY 2007 ................................................................................................................................................................
www.ti.com
Figure 23 shows the single-ended output configuration, where the output current I
OUT1
flows into an equivalentload resistance of 25 . Node IOUT2 should be connected to AGND or terminated with a resistor of 25 toAGND. The nominal resistor load of 25 gives a differential output swing of 1 V
PP
when applying a 20-mAfull-scale output current.
Figure 23. Driving a Doubly Terminated 50- Cable Using a Single-Ended Output
The DAC5662 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two controlamplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5662 is determined by thereference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which isdetermined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results frommultiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-k resistor value results in a full-scale output of approximately 20 mA. Resistorswith a tolerance of 1% or better should be considered. Selecting higher values, the output current can beadjusted from 20 mA down to 2 mA. Operating the DAC5662 at lower than 20-mA output currents may bedesirable for reasons of reducing the total power consumption, improving the distortion performance, orobserving the output compliance voltage limitations for a given load condition.
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The controlamplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin,which in this case functions as an input. The use of an external reference may be considered for applications thatrequire higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1- µF capacitor is recommended to be used with the internal reference, it is optional for the externalreference operation. The reference input, EXTIO, has a high input impedance (1 M ) and can easily be drivenby various sources. Note that the voltage range of the external reference should stay within the compliancerange of the reference input.
18 Submit Documentation Feedback Copyright © 2004 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC5662
Gain Setting Option
Sleep Mode
DAC5662
www.ti.com
................................................................................................................................................................ SLAS425B JULY 2004 REVISED MAY 2007
The full-scale output current on the DAC5662 can be set two ways: either for each of the two DAC channelsindependently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)must be low (i.e. connected to AGND). In this mode, two external resistors are required one RSET connectedto the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user has theflexibility to set and adjust the full-scale output current for each DAC independently, allowing for thecompensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (i.e. connected to AVDD), the DAC5662 switches into the simultaneousgain set mode. Now the full-scale output current of both DAC channels is determined by only one external RSETresistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed, however this is notrequired since this pin is not functional in this mode and the resistor has no effect on the gain equation.
The DAC5662 features a power-down function which can be used to reduce the total supply current to less than3.5 mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates thepower-down mode, while a logic low enables normal operation. When left unconnected, an internal activepulldown circuit enables the normal operation of the converter.
Copyright © 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): DAC5662
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DAC5662IPFB ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC5662IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC5662IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC5662IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5662 :
Enhanced Product: DAC5662-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC5662IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC5662IPFBR TQFP PFB 48 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-May-2009
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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