4.7 F4.7 F
DIN
CIN1 CIN2
B240A
VBAT
3.3 V
NPOR
CP2
VCP
VIN
TON
LX
ISEN–
ISEN+
VREG
CLV33
G33
V33
CP1
CPOR
ENBATS
ENBAT
ENB
V5
V5P
3.3 V
0.22 F0.22 F
0.22 FA4405
DBUCK
B240A
D1
B240A
VIN(Pin1)
D2
B240A
GND
RSENSE
300 m
1/4 W
RCL
390 m
1/4 W
RDROP
1.2
1/2 W
L1
10 H, 1.3 A
65 m MAX
3.3 V, 400 mA
(500 mA MAX)
40 °C/W
175°C MAX
1 to 4.7 F
R1
R2
1 to 2.2 F
1 to 2.2 F
5 V
Enable
100 nF
1 k100
PAD
VIGN
5 V
Protected
10 F
C
VREG
C
V33
C
V5
C
V5P
0.47 F
QV33
RTON
412 k
4.7 k
4.7 k
C
CPOR
A
A
B
B
Protection diodes D1 and D2 are required
when the V5P pin is driving a wiring harness
(or excessively long PCB trace) where
parasitic inductance will cause the voltage at
the V5P to momentarily transition above VIN
or below ground during a fault condition.
R1 and R2 should be b0.5% (used only for
5.0 V / 400 mA operation, see page 15).
Option with external LDO set to 3.3 V / 400 mA,
(Add R1 and R2 and remove RDROP to set external LDO to 5.0 V / 400 mA)
Description
The A4405 is an automotive power management IC that uses a
high frequency constant on-time 5.45 V pre-regulator to supply
two internal 5 V linear regulators and a 3.3 V linear DMOS
driver. Designed to supply CAN and microprocessor power
supplies in high temperature environments, the A4405 is ideal
for under hood applications. Efficient operation is achieved by
using a buck pre-regulator to efficiently drop the input voltage
before supplying the linear regulators; this reduces power
dissipation and increases overall regulator efficiency.
The switching regulator is capable of operating at a nominal
switching frequency of 2.2 MHz. The high switching frequency
enables the customer to select low value inductors and ceramic
capacitors while avoiding EMI in the AM frequency band.
Protection features include undervoltage lockout and thermal
shutdown. The V5P output is protected from short-to-battery
events. In case of a shorted load, all regulators feature
A4405-DS, Rev. 2
Features and Benefits
• AEC Q100 Grade 0 qualified
• Internal buck pre-regulator followed by LDO outputs
• 5.5 to 36 V VIN operating range (50 V maximum);
for start/stop, cold crank, and load dump requirements
• 2.2 MHz constant on-time buck regulator
• Valley current sensing achieves shortest buck on-times
• 50 V absolute maximum input voltage for surges
• 5.5 to 46 V input voltage range
• −40ºC to 150ºC junction temperature range
• Power-on reset (NPOR pin) with adjustable rising delay
• 5 V (V5P pin) internal low dropout tracking
linear regulator with both overcurrent foldback and
short-to-battery protection
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
Package: 20-pin TSSOP with exposed
thermal pad (suffix LP)
Typical Application Circuit
Not to scale
A4405
Continued on the next page…
Continued on the next page…
Applications:
Automotive Control Modules, such as:
• Electronic power steering (EPS)
• Transmission control (TCU)
• Antilock braking (ABS)
• Emissions control
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings1
Characteristic Symbol Notes Rating Unit
VIN Pin VIN –0.3 to 50 V
LX Pin VLX
–0.3 to 50 V
t < 250 ns –1.5 V
VCP, CP1, and CP2 Pins VVCP
, VCPx –0.3 to 60 V
ISEN– Pin VISEN––0.5 to 1 V
ISEN+ Pin VISEN+ –0.5 to 0.5 V
ENBAT Pin2VENBAT –0.3 V
ENBAT Pin Current IENBAT –50 to 50 mA
VREG Pin VVREG –0.3 to 8 V
V33 Pin VV33 –0.3 to 7 V
G33 Pin3VG33 –0.3 V
CLV33 Pin VCLV33 –0.3 to 10 V
V5P Pin VV5P –0.3 to VIN+0.5 V
V5 Pin VV5 –0.3 to 7 V
TON Pin VTON –0.3 to 50 V
NPOR and CPOR Pins VxPOR –0.3 to 7 V
ENB and ENBATS Pins VEN
, VENBATS –0.3 to 7 V
Operating Ambient Temperature TARange K –40 to 135 °C
Junction Temperature TJ(max) –40 to 150 °C
Storage Temperature Range Tstg –40 to 150 °C
1Absolute maximum ratings are limiting values that should not be exceeded under worst case operating conditions or damage may occur.
2The ENBAT pin is internally clamped to approximately 8.5 V due to an ESD protection device.
3The G33 pin is internally clamped by an ESD protection device. Clamp voltages range from 10 V (min) to 15 V (max).
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA Estimated on 4-layer PCB based on JEDEC standard 32 ºC/W
*Additional thermal information available on the Allegro website.
overcurrent protection. The A4405 also features power-on-reset
with adjustable delay for the microprocessor output.
The A4405 is supplied in a low profile (1.2 mm max) 20-pin TSSOP
package with exposed thermal pad (suffix LP). The package is lead
(Pb) free with 100% matte-tin leadframe plating
• 5 V (V5 pin) internal low dropout linear regulator with
overcurrent foldback protection
• 3.3 V (V33 pin) external linear regulator DMOS driver with a
programmable current limit (up to 500 mA) and overcurrent
foldback protection
• Logic enable input (ENB pin)
• Ignition enable input (ENBAT pin)
• Ignition status indicator (ENBATS pin)
• Buck pulse-by-pulse overcurrent protection
• Buck LX short circuit protection (latched)
• Missing asynchronous diode protection (latched)
• Switcher (VREG pin), 3.3 V (V33 pin), and charge pump
(VCP pin) undervoltage lockout protection (UVLO)
• Thermal shutdown protection (TSD)
Features and Benefits (continued) Description (continued)
Selection Guide
Part Number Packing
A4405KLPTR-T 4000 pieces per 13-in. reel
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table of Contents
Specifications 2
Functional Block Diagram 4
Pin-out Diagram and Terminal List 5
Electrical Characteristics 6
Characteristic Performance 9
Functional Description 11
Basic Operation 11
Overcurrent Protection 11
Dropout Mode 11
Soft Start 11
Buck Pulse Width ( tON ) 11
ISEN+ and ISEN– 11
Switcher Overcurrent Protection 12
LX Short Circuit Protection 12
Missing Asynchronous Diode Protection 13
Thermal Shutdown 13
Power-On Reset (NPOR) 13
V5 Regulator 14
V5P Tracking Regulator 14
3.3 V Linear Regulator 15
Charge Pump 15
ENBAT 15
ENBATS 15
ENB 15
Timing Diagrams 16
Application Information 18
Switcher On-Time and Switching Frequency 18
Low Voltage Operation 18
Inductor Selection 18
Output Capacitor 19
Input Capacitor 19
Rectification Diode 19
External MOSFET Selection 19
3.3 V Dropping Resistor (RDROP) 20
PCB Layout 21
Application Circuit Performance 23
Package Outline Drawing 26
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
+
–
+
–
+
–
3.3 V
(From V33)
3.3 V
(From V33)
VREG
V33
ENB
0.22 F0.22 F
Charge Pump
Fault
VREG UVLO
V33 UVLO
0.22 F
VIGN
B240A
DBUCK
D1
B240A
RSENSE
300 m
1/4 W
RCL
390 m
1/4 W
RDROP
1.2
1/2 W
L1
10 H, 1.3 A
65 m MAX
3.3 V, 400 mA
(500 mA MAX)
1 to 4.7 F
VREF
VREF
VREF
VREF
VREF
VREG
1 to 2.2 F
5 V
1 to 2.2 F
100 nF
4.0 VH
2.2 VL
8.5 V
100
TSD Switch
Disable
PWM Control
Soft Start
Ramp
Generator
Regulator
V33 FET
Driver
V5
Regulator
V5 Control and
V33 to V5P
Tracking Control
Short to Supply
Protection
5 V
Protected
10 F
0.47 F
RTON
412 k
4.7 k
4.7 k
Microcontroller
Reset
Microcontroller
Enable
1 k
CV33
CVREG
CCPOR
NPOR
CPOR
ENBATS
ENBAT
ENB
V5P
GND
PAD
CP2
VCP
VIN
TON
CP1
LX
ISEN–
ISEN+
VREG
CLV33
G33
V33
V5
QV33
CV5
CV5P
4.7 F4.7 F
DIN
CIN1 CIN2
B240A
VBAT
VIN(Pin1)
D2
B240A
ProtecƟon diodes D1 and D2 are required when the V5P pin is driving a wiring harness (or excessively long
PCB trace) where parasiƟc inductance will cause the voltage at the V5P to momentarily transiƟon above
VIN or below ground during a fault condiƟon.
A
A
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pin-out Diagram
PAD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VIN
GND
TON
ENBAT
ENB
ENBATS
NPOR
CPOR
V5
V5P
VCP
CP2
CP1
LX
ISEN+
ISEN–
VREG
CLV33
G33
V33
Terminal List Table
Name Number Function
CLV33 13 3.3 V current sense and limit input
CP1 18 Charge pump capacitor terminal 1
CP2 19 Charge pump capacitor terminal 2
CPOR 8 NPOR delay programming pin
ENB 5 Logic enable input from the microcontroller
ENBAT 4 Ignition enable input from the key or switch via a 1 k resistor
ENBATS 6 Open drain ignition status output
G33 12 Gate driver to the external MOSFET for 3.3 V regulation
GND 2 Ground terminal
ISEN– 15 Buck negative current sense pin, sense resistor and diode node
ISEN+ 16 Buck positive current sense pin, sense resistor and ground node
LX 17 Buck regulator switching node
NPOR 7 Active low, open-drain fault indication output
PAD – Exposed pad for enhanced thermal dissipation
TON 3 Buck regulator on-time programming pin
V33 11 3.3 V regulator output
V5 9 5 V regulator output
V5P 10 5 V tracking, protected regulator output
VCP 20 Charge pump reservoir capacitor terminal
VIN 1 Input voltage
VREG 14 Buck regulator DC output, and input to the 3.3 V external regulator
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS Valid at –40°C TJ 150°C, 5.5 V VIN 36 V; unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
General
Function Input Voltage VIN(f) Device functional, parameters not guaranteed 5.5 46 V
Operating Input Voltage VIN(op) 5.5 13.5 36 V
Supply Quiescent Current1
IQ
VIN = 13.5 V, VIGN > VIGN(H) or VENB > VENB(H),
no load on VREG –10–mA
IQ(SLEEP)
VIN = 13.5 V, VIGN < VIGN(L), VENB < VENB(L), no
load on VREG ––10A
Buck Regulator
Switcher Output VVREG
ENB = high
, VINSW(L) < VIN < 27 V,
25 mA < IVREG < 600 mA 5.25 5.45 5.60 V
ENB = high , VINSW(NOM) < VIN < 27 V,
25 mA < IVREG < 750 mA 5.30 5.45 5.60 V
ENB = high , 5.5 V < VIN < 6.5 V,
LX 100% on, 100 mA < IVREG < 600 mA 5.15 – 6.46 V
Switcher Period2
TSW(L) VINSW(L) < VIN < VINSW(NOM), RTON = 412 k– 1.6 – s
TSW(NOM) VINSW(NOM) < VIN < VINSW(H), RTON = 412 k– 450 – ns
TSW(H) VINSW(H) < VIN < 36 V, RTON = 412 k– 1.6 – s
Switcher On-Time tON
VIN = 7 V, RTON = 412 k1070 1335 1600 ns
VIN = 13.5 V, RTON = 412 k160 200 240 ns
VIN = 27 V, RTON = 412 k80 118 135 ns
VIN = 35 V, RTON = 412 k220 275 330 ns
Switcher Period VIN Threshold
VINSW(L)
VIN falling, TSW changes from TSW(L) to
100% duty cycle 5.9 6.2 6.5 V
VINSW(NOM) VIN falling, TSW changes from TSW(NOM) to TSW(L) 7.7 8.3 8.9 V
VINSW(H) VIN rising, TSW changes from TSW(NOM) to TSW(H) 28 31 34 V
Switcher Period VIN Hysteresis VINSW(HYS)
VINSW(L) and VINSW(NOM) comparators, relative to
the VIN voltage that initially caused the switcher
period to change
– 250 – mV
VINSW(H) comparator, relative to the VIN voltage
that initially caused the switcher period to
change
– 700 – mV
Buck Switch On-Resistance RDS(on)
TJ = 25°C, IDS = 0.1 A – 275 300 m
TJ = 150°C, IDS = 0.1 A – 400 470 m
Minimum On-time ton(min) VIN = 13.5 V, RTON = 49.9 k–6590ns
Minimum Off-time toff(min) VIN = 13.5 V 85 110 140 ns
ISEN Voltage Threshold VISEN VISEN+ – VISEN– 175 220 265 mV
VREG Valley Current Limit ILIM(VALLEY) RSENSE = 300 m, VIN > VINSW(L) – 733 – mA
VREG Peak Current Limit ILIM(PEAK) 2.5 5.0 – A
Continued on the next page…
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C TJ 150°C, 5.5 V VIN 36 V; unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
5 V Linear Regulators
V5 Accuracy and Load Regulation VV5 10 mA < IV5 < 215 mA, VVREG 5.25 V 4.9 5.0 5.1 V
V5P Accuracy and Load Regulation VV5P 10 mA < IV5P < 270 mA, VVREG 5.25 V 4.9 5.0 5.1 V
V5P/V33 Tracking Ratio V5Ptrack VV5P / VV33 1.507 1.515 1.523 –
V5P/V33 Tracking Accuracy ErrV5Ptrack
2.69 V < VV33 < 3.37 V, IV5P = 75 mA,
5.5 V < VIN < 27 V 0.5 – +0.5 %
Linear Regulator and FET Driver
V33 Accuracy ErrV33 10 mA < IV33 < 500 mA 3.23 3.30 3.37 V
G33 Source Current1IG33(SRC) VV33 = 3.0 V, VG33 = VG33(MAX) – 1 V 175 250 400 A
G33 Sink Current1IG33(SINK) VV33 = 3.6 V, VG33 = 6 V 0.5 3 – mA
G33 Maximum Voltage VG33(MAX) VV33 = 3.0 V 9 – 15 V
G33 Minimum Voltage VG33(MIN) VV33 = 3.6 V – 0.7 1.0 V
G33 Output Impedance2ROUT – 175 –
External FET Gate Capacitance2CISS 250 – 5200 pF
Charge Pump (VCP Pin)
Output Voltage VVCP VVCP VIN 4.1 6.6 – V
Switching Frequency fSW(CP) – 100 – kHz
Logic Enable Input (ENB Pin)
ENB Logic Input Threshold VENB(H) VENB rising – – 2.0 V
VENB(L) VENB falling 0.8 – – V
ENB Logic Input Current1IENB(IN) VENB = 3.3 V – – 100 A
ENB Pull-Down Resistance RENB –60–k
Ignition Enable Input (ENBAT and ENBATS Pins)
ENBAT and ENBATS Thresholds
VIGN(H)
VIGN rising via a 1 k series resistance,
measure VIGN when IQ occurs – – 4.0 V
VIGN(L)
VIGN falling via a 1 k series resistance,
measure VIGN when IQ(SLEEP) occurs 2.2 – – V
ENBAT Input Current1IENBAT(IN)
VIGN = 5.5 V via a 1 k series resistance – 50 100 A
VIGN = 0.8 V via a 1 k series resistance 0.5 – 5 A
ENBAT Input Resistance RENBAT – 650 – k
Ignition Status Output (ENBATS Pin)
ENBATS Output Voltage VENBATS(L) IENBATS = 4 mA – – 400 mV
ENBATS Leakage Current1IENBATS VENBATS = 3.3 V – – 1 A
ENBATS Turn-On Delay tENBATS Sleep mode to VENBATS = 3.3 V – 11 – ms
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C TJ 150°C, 5.5 V VIN 36 V; unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
NPOR Pin Output and Timing
NPOR Power-Up Delay tNPOR CPOR = 0.22 F – 20 – ms
NPOR Output Voltage VNPOR(L)
ENB = high or ENBAT = high,
VVREG < VREGNPOR(L) or VV33 < V33NPOR(L)
,
INPOR 4 mA
– – 400 mV
ENBAT = low, ENB transitioning to low,
VVREG = 5.45 V, INPOR 0.3 mA,
0.8 V < VV33 < ErrV33 , 0°C TJ 150°C
– 350 800 mV
ENBAT = low, ENB transitioning to low,
VVREG = 5.45 V, INPOR 0.3 mA,
1.0 V < VV33 < ErrV33
, 40°C TJ 150°C
– – 800 mV
NPOR Leakage Current1INPOR(LEAK) VNPOR = 3.3 V – – 1 A
CPOR Pin Characteristics
CPOR Charge Current1ICPOR(SRC) –13 – A
CPOR Threshold VCPOR(H) VCPOR rising 1.0 1.2 1.4 V
VREG Pin Soft Start Timing
Soft Start tSS –10–ms
Protection Circuitry
VREG Pin NPOR Thresholds VREGNPOR(H) VVREG rising, NPOR transitioning to high 4.80 5.00 5.20 V
VREGNPOR(L) VVREG falling, NPOR transitioning to low 4.75 4.94 5.14 V
VREG Pin NPOR Hysteresis VREG(HYS) –60–mV
V33 Regulator NPOR Thresholds V33NPOR(H) VV33 rising, NPOR transitioning to high 2.80 2.95 3.10 V
V33NPOR(L) VV33 falling, NPOR transitioning to low 2.69 2.83 2.97 V
V33 Regulator NPOR Hysteresis V33(HYS) – 125 – mV
V33 Regulator Overcurrent Threshold V33OCP VVREG – VCLV33 175 200 245 mV
V33 Regulator Current Limit IV33ILIM RCL = 620 m– 323 – mA
V33 Regulator Foldback Threshold V33IFB VV33 = 0 V, VVREG – VCLV33 35 55 75 mV
V33 Regulator Foldback
Current Limit IV33IFB RCL = 620 m–89–mA
V5P Pin Current Limit1IV5PILIM VV5P = 5 V 300 405 – mA
V5P Pin Foldback Current1IV5PIFB VV5P = 0 V 70 110 150 mA
V5 Pin Current Limit1IV5ILIM VV5 = 5 V 230 315 – mA
V5 Pin Foldback Current1IV5IFB VV5 = 0 V 84 105 163 mA
Thermal Shutdown Threshold TJTSD TJ rising 155 170 – ºC
Thermal Shutdown Hysteresis TJTSD(HYS) –20–ºC
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin.
2Determined by design and systems characterization. Not production tested.
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3.27
3.28
3.29
3.30
3.31
3.32
3.33
-40 -20 0 20 40 60 80 100 120 140
V33 Output Voltage (V)
Temperature (°C )
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
-40 -20 0 20 40 60 80 100 120 140
V5P Output Voltage (V)
Temperature (°C )
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
-40-20 0 20406080100120140
V5 Output Voltage (V)
Temperature (°C )
0
100
200
300
400
500
600
700
800
900
1,000
1,100
1,200
1,300
1,400
-40 -20 0 20 40 60 80 100 120 140
t
ON
Pulse Width (ns)
Temperature (°C )
5.40
5.41
5.42
5.43
5.44
5.45
5.46
5.47
5.48
5.49
5.50
-40 -20 0 20 40 60 80 100 120 140
VREG Output Voltage (V)
Temperature (°C )
V5 Output versus Temperature
VREG Output versus Temperature
V5P Output versus Temperature
tON versus Temperature
V33 Output versus Temperature
V
IN
= 7.5 V
V
IN
= 35 V
V
IN
= 13.5 V
V
IN
= 27 V
Characteristic Performance
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
210
205
200
195
190
185
-40 -20 0 20 40 60 80 100 120 140
V33 Over current Threshold (mV)
Temperature (
°
C)
0
50
100
150
200
250
300
-40 -20 0 20 40 60 80 100 120 140
VREG Valley Limit (mV)
Temperature (
°
C)
0
50
100
150
200
250
300
350
400
-40-20 0 20406080100120140
ENBATS
Voltage (mV)
Temperature (°C )
I
ENBATS
= 4 mA
10
11
12
13
14
15
16
-40-20 0 20406080100120140
CPOR Charging Current (uA)
Temperature (°C )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-40-20 0 20406080100120140
ENB Threshold (V)
Temperature (°C )
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
-40 -20 0 20 40 60 80 100 120 140
ENBAT Threshold (V)
Temperature (°C )
CPOR Charging Current versus Temperature
ENBAT Start / Stop Thresholds versus Temperature
ENBATS (Low) Voltage versus Temperature
ENB Start / Stop Thresholds versus Temperature
VREG Valley Current Limit versus Temperature V33 Overcurrent Threshold versus Temperature
Start
Stop
Start
Stop
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Basic Operation
The A4405 contains a fixed on-time, buck switching pre-regu-
lator with valley sensing current mode control, two integrated
5 V linear regulators, and an N-channel FET driver for a 3.3 V
linear regulator. The constant on-time (COT) converter maintains
a constant output frequency because the on-time is inversely
proportional to the supply voltage. As the input voltage decreases
the on-time is increased, which maintains a relatively constant
period. Valley mode current control allows the converter to
achieve very short on-times because current is measured during
the off-time.
With very low input voltages the buck switch maintains a 100%
duty cycle. This turns the buck switch on 100% of the time (no
switching) and allows the regulator to operate in dropout mode.
The device is enabled via logic level ENB or high voltage igni-
tion ENBAT input. When the device is enabled the converter
starts up under the control of an internal soft start routine. The
two enable inputs are logically ORed together internally so either
of the inputs can be used to enable the device.
Under light load conditions the switch enters pulse-skipping
mode to ensure regulation is maintained. In order to maintain a
wide input voltage range the switcher period is extended when
the minimum on- or off-time is reached, or when the input supply
is at either end of its range.
Overcurrent Protection
The A4405 features overcurrent protection on all regulators
including the VREG pre-regulator. The buck switch current limit
is determined by the selection of the sense resistor at the ISENx
pins. Output current is also monitored on the 5VP and 5V linear
regulators, and if shorted the outputs fold back. The external FET
driver has a current limit tap that can be used with a sense resistor
to trigger a current limit based on an external resistor and trip
voltage.
Dropout Mode
The topology of a COT timer is ideal for systems that have high
input voltages. Because current is measured during the off-time,
very short on-times can be achieved. With low input voltages
the switcher must maintain very short off-times. To prevent
the switcher from reaching its minimum off-time, the switcher
is designed to enter a 100% duty cycle mode. This causes the
switcher to stop acting as a buck switch. The voltage at VREG
then becomes the simply the supply voltage minus the drop
across the buck switch and inductor. In this mode the maximum
available current may be lower, depending on ambient tempera-
ture and supply voltage, while in dropout mode.
Soft Start
An internal ramp generator and counter allow the output voltage
to ramp-up. This limits the maximum demand on the external
power supply by controlling the inrush current required to charge
the external capacitor and any DC load at startup. Internally, the
ramp is set to 10 ms nominal.
The following conditions are required to trigger a soft start:
• ENBAT or ENB transition to high, and
• There is no thermal shutdown, and
• V33 voltage is below its UVLO threshold, and
• VREG voltage is below its UVLO threshold.
Buck Pulse Width ( tON )
A resistor from the TON input to VIN sets the on-time of the
converter for a given input voltage. When the supply voltage is
between 8.3 and 31 V, the switcher period remains constant based
on the selected value of RTON . At voltages lower than 6.5 V the
switch is in dropout mode. For reasonable input voltage ranges
the period of the converter is held constant resulting in a constant
operating frequency over the input supply range. More informa-
tion on how to choose RTON can be found in the Application
Information section.
The formula to calculate the value for the on-time resistor is:
ton = ( RTON
/ VIN
) × 6.36 × 10
–12 + 5 × 10
–9 (ns). (1)
ISEN+ and ISEN–
The sense inputs are used to sense the current in the buck, free-
wheeling diode during the off-time cycle. The value for RSENSE is
obtained by the formula:
RSENSE = 220 (mV) / IVALLEY , (2)
where IVALLEY is the lowest current measured through the induc-
tor during the off-time cycle. It is recommended that the current
sense resistor be sized so that, at peak output current, the voltage
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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at the ISEN– pin does not exceed –0.75 V during PWM opera-
tion (that is, a transient condition). Because the diode current is
measured when the inductor current is at the valley, the average
output current is greater than the IVALLEY value. The value for
IVALLEY should be:
IVALLEY = IOUT(AVG) – 0.5 × IRIPPLE + K , (3)
where:
I
OUT(AVG) is the average of the output currents of all
the regulators,
I
RIPPLE is the inductor ripple current, and
K is a design margin allowing for component tolerances.
The peak current in the switch is simply:
IPEAK = IVALLEY + IRIPPLE . (4)
Information on how to calculate the ripple current is included in
the Application Information section.
Switcher Overcurrent Protection
The converter utilizes pulse-by-pulse valley current limiting,
which is activated when the current through the sense resistor
(that is, the buck output current) is high enough to create 220 mV
between the ISEN pins. During an overload condition, the switch
is turned on for a period determined by the constant on-time
circuitry. The switch off-time is extended until the current decays
to the current limit value set by the selection of the sense resistor,
at which point the switch is allowed to turn on again. Because no
slope compensation is required in this control scheme, the current
limit is maintained at a reasonably constant level across the input
voltage range.
Figure 1 illustrates how the current is limited during an overload
condition. The current decay (period with switch off) is propor-
tional to the output voltage. As the overload is increased, the out-
put voltage tends to decrease and the switching period increases.
LX Short Circuit Protection
If the LX node is shorted to ground there will be a relatively high
peak current in the buck MOSFET within a very short time. The
A4405 protects itself by detecting the unusually high current,
turning off the buck MOSFET, and latching itself off. To avoid
false tripping, the current required to activate the peak current
protection (ILIM(PEAK), nominally 5 A) is set well above the
normal range of currents. When the peak current limit is acti-
vated the A4405 is latched off until either VIN is cycled below
its UVLO threshold or the A4405 is disabled (both ENBAT and
ENB must be brought low) and re-enabled. NPOR is not directly
activated (pulled low) by the peak current protection circuitry.
However, NPOR will certainly be in the correct state depending
on VREG and V33.
Time
Current Limit level
Inductor current, operating at maximum load
Inductor current, operating a soft overload
Current Limit level
Current Current
Constant On-Time
Constant Period
Extended Period
Maximum load
Overload
Time
Constant On-Time
Figure 1. Current limiting during overload conditions
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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Missing Asynchronous Diode Protection
In most high voltage asynchronous buck regulators, if the asyn-
chronous diode is missing or damaged the LX pin will transition
to a very high negative voltage when the upper MOSFET turns
off, resulting in damage to the regulator. The A4405 includes pro-
tection circuitry to detect when the asynchronous diode is missing
or damaged. If the LX pin becomes more negative than 1.2 V at
25°C for more than 157 ns, the A4405 will latch itself in the off
state to prevent damage. After a missing diode fault occurs, the
latch must be reset by either cycling VIN or ENBAT or ENB. See
figure 2 for the missing diode voltage threshold and time filtering
versus temperature.
Thermal Shutdown
If the A4405 junction temperature becomes too high, a thermal
shutdown circuit disables the VREG output, thus protecting the
A4405 from damage. When a thermal shutdown occurs, the buck
regulator stops switching and the VREG voltage will decay.
When VVREG crosses its UVLO threshold, the NPOR signal is
pulled low. Thermal shutdown is not a latched condition so, when
the junction temperature cools to an acceptable level, the A4405
will automatically restart.
Power-On Reset (NPOR)
The NPOR output is an open drain pin that can be used to signal
a reset event to a DSP or microcontroller. The NPOR function
actively monitors ENBAT, ENB, V33, and VREG. During power-
up, NPOR is held low for a programmable amount of time, tNPOR,
after both VREG and V33 transition above their upper UVLO
thresholds. The rising edge delay allows time for the regulators to
be within specification when the DSP or microcontroller begins
processing. The amount of the rising edge delay is determined by
the value of the external capacitor from the CPOR pin to ground.
The rising delay can be calculated from the following formula:
tNPOR = 92.3 × 103 × CCPOR (seconds). (5)
Any of the following conditions will force NPOR to transition to
low immediately (within a few microseconds):
• V33 voltage falls below its UVLO threshold, or
• VREG voltage falls below its UVLO threshold, or
• ENBAT and ENB are both low, or
• Charge pump voltage is too low. or
• Internal IC regulation (VRAIL) is too low.
If thermal shutdown occurs, PWM switching will terminate,
VVREG and/or VV33 will decay below the UVLO threshold, and
NPOR will transition to low. Thus, a thermal shutdown event
indirectly causes NPOR to transition to low.
When the A4405 is disabled (either both ENB and ENBAT are
low, or VIN is removed) the NPOR output is held low until the
voltage from the 3.3 V regulator (VV33) falls below 1.0 V. This
assumes maximum initial current (4 mA) in the NPOR open drain
DMOS. The NPOR voltages would be somewhat lower for lower
values of INPOR
. See figure 3.
ENB, ENBAT
V
V33
I
NPOR
V
NPOR
3.3 V
1.0 V
0.3 mA
800 mV
4mA
350 mV (typ)
400 mV
Figure 3. NPOR and V33 characteristics when the A4405 is disabled
Figure 2. Missing diode protection versus device junction temperature
120
130
140
150
160
170
180
190
200
210
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
-50 -25 0 25 50 75 100 125 150
Time Filterin
g
(ns)
NegaƟve Voltage Threshold (V)
JuncƟon Temperature (°C)
Time Filtering
Voltage Threshold
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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V5 Regulator
The 5 V linear regulator is provided to supply local circuitry. This
regulator can deliver 300 mA (typ), 215 mA (min). When a direct
short is applied to this regulator the output the current folds back
to 0 V at approximately 100 mA (typ) (figure 4).
V5P Tracking Regulator
The 5VP linear tracking regulator is provided to supply remote
circuitry such as off-board sensors. The V5P pin is monitored and
if a short to ground or a short to battery occurs the V5P output is
disabled and/or disconnected and the other outputs (VREG, V5,
and V33) remain active until the short is removed. The regulator
can deliver 375 mA (typ), 270 mA (min). When a direct short is
applied to this regulator the output the current folds back to 0 V
at approximately 112 mA (typ) (figure 5).
The V5P regulator is designed to track the V33 output during
power-up and when the device is completing a soft start ramp.
The V5P regulator tracks the 3.3 V output to within ±0.5% under
normal steady state operating conditions. If the V33 regulator is
decreasing, the V5P regulator accurately tracks the V33 output
down to the point at which a V33 undervoltage fault (2.825 V
nominally: 2.95 V – 125 mV) results in the NPOR output
going active.
The figures 6 and 7 show A4405 operation when the V5P pin
is shorted to ground and VIN (battery). In both cases, the V5P
output is disabled and/or disconnected while the other outputs
(VREG, V5, and V33) remain active.
Figure 6. V5P is shorted to ground in 5 s (DV5P is populated); shows
VVREG (ch1, 2 V/div.), VV33 (ch2, 1 V/div.), VV5 (ch3, 2 V/div.), VV5P (ch4,
2 V /div.), t = 10 s/div.
t
VV33
VV5
VV5P
VVREG
C1
C3
C4
C2
Figure 7. V5P is shorted to a 25 V battery; shows VVREG (ch1, 2 V/div.),
VV33 (ch2, 2 V/div.), VIN pin (ch3, 5 V/div.), VV5P (ch4, 5 V /div.),
t = 10 s/div.
6
5
4
3
2
1
0
50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Output Voltage (V)
Output Current (mA)
Typical
MinimumMinimum
Maximum
6
5
4
3
2
1
0
50 100 150 200 250 300 350
Output Voltage (V)
Output Current (mA)
400 450 500
Typical
Minimum
Minimum
Maximum
Figure 4. Foldback current limit of the 5V regulator Figure 5. Foldback current limit of the 5VP regulator
t
VV33
VREG
VV5P
5 V
25 V
30 V
VIN pin
Ringing due to parasitics from a long wire
V5P is clamped to a safe level above VIN
by D2 (see application schematic)
All
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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3.3 V Linear Regulator
An additional 3.3V linear regulator can be implemented using
an external MOSFET. In the event the 3.3V regulator output is
shorted to ground, the A4405 protects the external MOSFET
by folding back when the programmed current limit, ICL , is
exceeded. The current limit is determined by the voltage devel-
oped across the external sense resistor, RCL
, shown in the Typical
Application Circuit schematic. The 3.3V current limit can be
calculated using the following formula:
ICL = VCLV33 / RCL , (6)
where VCLV33 is as documented in the Electrical Characteris-
tics table, nominally 200 mV. Typically RCL will be a fairly low
value so it will not dissipate significant power, 1/4 W should be
adequate, but the tolerance should be 1% or less.
When ICL is exceeded, the maximum load current through the
external MOSFET is typically folded back to 48% of ICL as
shown in figure 8.
Some applications require 5.0 V instead of 3.3 V. The external
LDO controller will produce 5.0 V if a resistor divider is inserted
between the controller output (that is, the source of the external
MOSFET) and the V33 pin, as shown on page 1 of this datasheet.
In this case, the 1.2 Ω/0.5 W power dropping resistor in series
with the drain of the external MOSFET must be removed from
the design.
Allegro recommends using resistors with ≤0.5% tolerance for two
reasons: (1) the 5.0 V output will have the best accuracy, and (2)
to maintain a low tracking error between the V5P and the 5.0 V
output. A comparison of two sets of resistor values at 0.1% and
0.5% tolerance are shown in the following table.
R1 and R2 Values
and Tolerances
5V Output Range (V) V5P/V5
Tracking
Accuracy (%)
Min. Typ. Max.
100 and 196
±0.1% 4.887 4.999 5.112 ±0.6
100 and 196
±0.5% 4.874 4.999 5.125 ±0.9
1.02 k and 2.18 k
±0.1% 4.867 5.002 5.141 –1.1, +1.2
1.02 k and 2.18 k
±0.5% 4.855 5.002 5.154 –1.4, +1.5
Charge Pump
The charge pump is used to generate a supply above VIN
.
A 0.22 μF ceramic monolithic capacitor should be connected
between VCP and VIN to act as a reservoir to run the DMOS
switch. The VCP voltage is internally monitored to ensure that
the charge pump is disabled in the case of a fault condition.
A 0.22 μF ceramic monolithic capacitor should be connected
between CP1 and CP2.
ENBAT
This is a level-triggered enable input, use for enabling the device
based on a high voltage ignition or battery switch (via a 1 kΩ
resistor). The ENBAT comparator thresholds are VIGN(L) =
2.2 V(min)and VIGN(H) = 4.0 V (max). ENBAT is used only as a
momentary switch to enable or wake up the A4405. After ENBAT
is removed, ENB must be high to keep the A4405 enabled. The
ENB and ENBAT signals are logically ORed together internally
so either one may wake up the A4405 and both must be low to
disable the A4405. Only one of the two inputs must be pulled
high in order to enable the part. If there is no requirement for an
ignition switch, then ENBAT can be pulled low, which makes
ENB a single reset control.
If an external resistor and capacitor are used to form a low-pass
filter to the ENBAT pin, then a 100 Ω resistor must be used to
prevent the external capacitor from discharging into and damag-
ing the ENBAT pin. See the Typical Application Circuit sche-
matic for connection of these 3 components.
ENBATS
When a logic high is sensed on the ENBAT input, the ENBATS
output will go high, signaling to the user that the ignition input
is high. When a logic low is sensed on the ENBAT input, then
ENBATS will also transition to low. The ENBATS input logic
levels are identical to the ENBAT input logic levels.
ENB
This pin can be used as an enable input from either a DSP or from
a microcontroller. This input has an internal pull-down resistor so
it may be left unconnected if not used.
3.5
3.0
2.5
2.0
1.5
1.0
05
0
50 10 20 30 40 50 60 12090 100 1108070
Output Voltage (V)
Percentage of Normal Current Seng (%)
Typical
Minimum
Maximum
Figure 8. Foldback current limit of the V33 regulator
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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Timing Diagrams
Typical power-up and power-down by ENBAT and ENB with VIN = 13.5 V; ENBATS is assumed to be connected to V33 via a pull-up resistor
VIN
NPOR
CPOR
ENBATS
ENBAT
ENB
V5
V5P
3V3
Internal
V
RAIL
or VCP
VREG
V
H
=4.0V
V
L
=2.2V
10 ms
20 ms
1. 2 V
13.5 V
V
H
=5.00V
V
H
=2.95V
Clamped at 8.5V via 1k
V
L
=4.94V
V
L
=2.83V
V
H
=2V
V
L
=0.8V
Internal
UVLO
1.0 V
0.8 V
MAX
Internal
UVLO
VREG > 5.00 V and
V33 > 2.95 V
ENB < 0.8V or
VREG < 4.94V or
V33 < 2.83V or
VCP low or
Internal VRAIL low
NPOR is open-drain, pulled up to V33
Decay rates of VREG, V5, V5P,
and V33 depend on output
capacitances and loading
ENBATS is open-drain, pulled up to V33
V5, V5P, and V33 ramp
at approximately the
same rate as VREG
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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VIN
NPOR
CPOR
ENBATS
ENBAT
ENB
V5
V5P
3V3
Internal
V
RAIL
or VCP
VREG 10 ms
20 ms
1. 2 V
13.5V
V
H
=5.00V
V
H
=2.95V
V
L
=4.94V
V
L
=2.83V
6.5 V
Internal
UVLO
5.2 V 5.5 V 4.9 V
V
ENBAT
= 0V
ENBATS is not connected
100 % Duty
Cycle
Internal regulators
collapse
0.8 V
MAX
1.0 V
Internal
UVLO
V
ENB
2V prior to
V
IN
ramping up
VREG > 5.00 V and
V33 > 2.95 V
ENB < 0.8V or
VREG < 4.94V or
V33 < 2.83V
VCP low or
Internal V
RAIL
low
V5P tracks V33 until
V
V33NPOR(L)
or V
IN
< 5.5 V
V5, V5P, and V33 ramp
at approximately the
same rate as VREG
NPOR is open-drain, pulled up to V33
Decay rates of VREG, V5,
V5P, and V33 depend on
output capacitances and
loading
Typical power-up and power-down via VIN with ENB always logic high; ENBAT and ENBATS are not used
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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Application Information
Switcher On-Time and Switching Frequency
In order for the switcher to maintain regulation, the energy that is
transferred to the inductor during the on-time must be transferred
to the capacitor during the off-time. Because of this relation-
ship, the load current and IR drops, as well as input and output
voltages, affect the on-time of the converter. The formula that
governs switcher on-time is shown below:
=
tON VIN –
RDS(on)
×
IPEAK
+
Vf
TSW
×
{VVREG
+
[(RL
+
RSENSE)
×
IPEAK]
+
Vf }.
(7)
where Vf is the forward voltage on the diode DBUCK in the Typi-
cal Application Circuit schematic.
The effects of the voltage drop on the inductor and trace resis-
tance will affect the switching frequency. However, the frequency
variation due to these factors is small and is covered in the varia-
tion of the switcher period, which is ±25% of the target. Remov-
ing these current dependant terms simplifies the formula:
=
tON VIN –
RDS(on)
×
IPEAK
+
Vf
(1/ fSW)
×
(VVREG
+
RSENSE
×
IPEAK
)
+
Vf.
(8)
Be sure to use the worst-case sense voltage and forward voltage
of the diode DBUCK , including any effects due to temperature.
For an example: assume a 1 A converter with a supply voltage of
13.5 V. The output voltage is 5.45 V, Vf is 0.45 V, RSENSE × IPEAK
is 0.20 V, RDS(ON) × IPEAK is 0.15 V, and the required frequency
is 2.2 MHz. Substituting into equation 8, we can solve for tON:
tON = 1 / 2.2 (MHz) ×
[(5.45+0.20+0.45) / (13.5 – 0.15 + 0.45)]
= 201 (ns) .
The formulas above describe how tON changes based on input
and load conditions. Because load changes are minimal and the
output voltage is fixed, the only factor that will affect the on-time
is the input voltage. The converter is able to maintain a constant
period over a varying supply voltage because the on-time changes
based on the input voltage. The current into the TON terminal is
derived from a resistor tied to VIN, which sets the on-time pro-
portional to the supply voltage. Selecting the resistor value based
on the tON calculated above is done using the following formula:
RTON = [VIN × ( tON − 5 (ns) )] / 6.36 × 10
–12 . (9)
After the resistor is selected and a suitable tON is found, it must
be demonstrated that tON does not, under worst-case condi-
tions, exceed the minimum on-time or minimum off-time of
the converter. The minimum on-time occurs at maximum input
voltage and minimum load. The maximum off-time occurs at
minimum supply voltage and maximum load. For supply voltages
below 8.3 V and above 6.5 V, refer to the Low Voltage Opera-
tion section.
Low Voltage Operation
The converter can run at very low input voltages; with a 5.25 V
output the minimum input supply can be as low as 5.5 V. When
operating at high frequencies the on-time of the converter must
be very short because the available period is short. At high input
voltages the converter should not violate the minimum on-time,
tON(min), while at low input voltages the converter should not
violate the minimum off-time, tOFF(min). Rather than limit
the supply voltage range, the converter solves this problem by
automatically increasing the period. With the period extended
the converter will not violate the minimum on-time or off-time
specifications. If the input voltage is between 8.3 and 31 V, the
converter maintains a constant period. When calculating worst
case on-times and off-times, make sure to use the highest switch-
ing frequency if the supply voltage is in that range.
When operating at voltages below 8.3 V, additional care must
be taken when selecting the inductor and diode. At low voltages
the maximum current may be limited due to the IR drops in the
current path. When selecting external components for low volt-
age operation, the IR drops must be considered for determining
on-time, so the complete equation (formula 8) should be used to
make sure the converter does not violate the timing specification.
Inductor Selection
Choosing the right inductor is critical to the correct operation of
the switcher. The converter is capable of running at frequencies
above 2 MHz, this makes it possible to use small inductor values,
which reduces cost and board area.
The inductor value is what determines the ripple current. It is
important to size the inductor so that under worst-case condi-
tions ITRIP equals IAV G , minus half of the ripple current, plus a
reasonable margin. If the ripple current is too large, the converter
will activate the current limit function. Typically peak-to-peak
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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ripple current should be limited to a range of 20% to 25% of the
maximum average load current.
Worst-case ripple current occurs at maximum supply voltage.
After calculating the duty cycle for this condition, the ripple cur-
rent can be calculated:
=
DVIN(max)–
RDS(on)
×
IPEAK
+
Vf
VVREG
+
(
RSENSE
×
IPEAK )
+
Vf.
(10)
Using the duty cycle, a ripple current can be calculated using the
formula below:
=
L×
D ×
IRIPPLE
VIN –
VVREG fSW(min)
1,
(11)
where IRIPPLE is 25% of the maximum load current, and fSW(min)
is the minimum switching frequency, nominal frequency minus
25%. For the example used above, a 1 A converter with a supply
voltage of 13.5 V was the design objective. The supply voltage
can vary by ±10%. The output voltage is 5.45 V, Vf is 0.5 V,
VSENSE is 0.20 V and the required frequency is 2.2 MHz. The
duty cycle is calculated to be 36.45%. The worst-case frequency
is 1.76 MHz, 2.2 MHz minus 20%. Using these numbers in
formula 11 shows that the minimum inductance for this converter
is 9.6 μH.
Output Capacitor
The converter is designed to operate with a low value ceramic
output capacitor on VREG (CVREG
). When choosing a ceramic
capacitor make sure the rated voltage is at least 3 times the
maximum output voltage of the converter. This is because the
capacitance of a ceramic decreases as it operates closer to the
capacitor rated voltage. It is recommended that the VREG output
be decoupled with a 10 μF X7R ceramic capacitor. Greater
capacitance may be required on the output if load surges dramati-
cally influence the output voltage.
Output ripple is determined by the output capacitance and the
effects of ESR and ESL can be ignored assuming recommended
layout techniques are followed. The output voltage ripple is
approximated by:
VRIPPLE = IRIPPLE / (8 × fSW × CVREG
) (12)
Input Capacitor
The value of the input capacitance affects the amount of cur-
rent ripple on the input. This current ripple is usually the source
of supply-side EMI. The amount of interference will depend on
the impedance from the input capacitor and the bulk capacitance
located on the supply bus. Placing a 0.1 μF ceramic capacitor
very close to the input supply pin will help reduce EMI effects.
The small capacitor will help reduce high frequency transient cur-
rents on the supply line. If further filtering is needed it is recom-
mended that two ceramic capacitors be used in parallel to further
reduce emissions.
Rectification Diode
The diode conducts the current during the off cycle. A Schottky
diode is required to minimize the forward drop and switching
losses. In order to size the diode correctly it is necessary to find
the average diode conduction current using the formula below :
Idiode(avg) = I load × (1 – D(min
)) (13)
where D(min) is the minimum duty cycle, defined as:
D(min
) = (VVREG + Vf ) / (VIN + Vf ) (14)
where VIN is the maximum input voltage and Vf is the maximum
forward voltage of the diode.
The average power dissipation in the diode is:
PDdiode(avg) = Iavg × D(min
) × Vf (15)
The power dissipation in the sense resistor must also be consid-
ered using I2R and the minimum duty cycle.
External MOSFET Selection
To choose an external MOSFET for the 3.3 V linear regulator
consider the maximum of: drain-to-source voltage (VDS), contin-
uous drain current (ID
), threshold voltage (VGSTH), on-resistance
(RDS(on)), and thermal resistance (RJC
).
The buck switcher pre-regulates the voltage to the external
MOSFET, so even under worst case conditions, the MOSFET
will not have to support more than 7 V from drain to source. Also,
the 3.3 V current limit will usually be set from 200 to 500 mA
using the external current setting resistor, RCL . Numerous
MOSFETs are available with VDS ratings of at least 20 V that
can support much more than 1 A. These two goals should not be
difficult to achieve.
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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The A4405 gate drive circuitry is guaranteed to pull the G33
voltage down to 1 V, maximum. Therefore, Allegro recommends
using a MOSFET with a VGS threshold (VGSTH) higher than 1 V.
Do not use a MOSFET that will conduct significant current when
VGS is at 1 V and the system is at the highest expected ambient
temperature.
One of the more critical specifications is the MOSFET on-
resistance, RDS(on) . If the on-resistance is too high, then the 3.3 V
regulator will not be able to maintain 3.3 V at the maximum
required load current, ILIM(V33) . Calculate the typical RDS(on) (at
25°C) using the following formula:
RDS(on)25°C < 0.6 × 1.56 (V) / (ILIM(V33) – RDROP) (16)
where ILIM(V33) is the maximum required 3.3 V output current,
and RDROP is the value of the resistor connected from the CLV33
pin to the drain of the MOSFET.
The multiplier of 0.6 in the following formula allows a 66%
increase in RDS(on) when the MOSFET is very hot:
<
RDS(on)25°C 0.6 ×
–
RDROP
ILIM(V33)
1.56 (V) .
(17)
where ILIM(V33) is the maximum required 3.3 V output current.
The necessity and value of RDROP is closely related to the thermal
resistance (RJC) of the MOSFET. For a medium size MOSFET
(such as an SOT-223) including RDROP in the PCB layout is
highly recommended. For a large size MOSFET with a very
low thermal resistance (such as a DPAK) RDROP is probably not
necessary.
MOSFET thermal resistance is a function of die size, package
size, and cost. So, choosing RDROP and RJC together should
result in optimal performance, minimal component sizes, and
lowest system cost. Determining the value and power dissipated
by the series dropping resistor and MOSFET thermal resistance
are addressed in detail in the 3.3 V Dropping Resistor section.
3.3 V Dropping Resistor (RDROP)
In the Typical Application Circuit schematic, there are two resis-
tors, RCL and RDROP , from the output of the buck regulator to
the drain of the external MOSFET. RCL must always be pres-
ent because it sets the 3.3 V regulator current limit threshold.
However, RDROP , if used, prevents the external MOSFET from
dissipating too much power during certain conditions. In particu-
lar, when the battery voltage is extremely low (VBAT ≤ 6.5 V) and
the buck regulator transitions to dropout mode (100% duty cycle)
then VVREG will be approximately 1 V higher than normal. In this
situation, without RDROP , the MOSFET could dissipate too much
power.
The value of RDROP depends on the maximum PCB temperature,
the maximum current load on the 3.3 V regulator, ILIM(V33) , the
maximum allowable junction temperature of the MOSFET, and
the thermal resistance of the MOSFET. As the thermal resistance
of the MOSFET decreases, the required value of RDROP will also
decrease. If the MOSFET is relatively large and has a very low
thermal resistance, then RDROP is not required (0 Ω).
Figure 9 shows recommended values of RDROP versus MOSFET
thermal resistance at various 3.3 V regulator maximum current
settings ( ILIM(V33) ). This graph assumes a PCB temperature of
135°C, a maximum MOSFET junction temperature of 145°C,
VBAT of 6.5 V, and 3.23 V from the linear regulator. This graph
takes into account the voltage drop across the 3.3 V current limit
resistor, RCL .
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
10 15 20 25 30 35 40 45 50 55 60
R
DROP
(Ω)
MOSFET Thermal Resistance (°C/W)
140 mA
230 mA
320 mA
410 mA
500 mA
Figure 9. Value of RDROP versus MOSFET thermal resistance at various
V33 regulator maximum current settings, ILIM(V33)
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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After a value for RDROP is determined, the designer should calcu-
late its maximum power dissipation (I2 × R) and select an appro-
priate component, allowing adequate design margin. Assuming
the RDROP value was chosen referencing figure 9, then figure 10
can be used to determine the power dissipated by RDROP versus
MOSFET thermal resistance at various 3.3V regulator current
settings. The exact value of RDROP is not critical, so a component
with 1% or 5% tolerance could be used.
PCB Layout
The board layout will have a large impact on the performance of
the device. It is important to isolate high current ground returns
to minimize ground bounce that could produce reference errors in
the device. The method used to isolate power ground from noise
sensitive circuitry is to use a star ground. This approach ensures
that the high current components such as the input capacitor, out-
put capacitor, and diode have very low impedance paths to each
other. Figure 11 illustrates the technique.
The ground connections from each of the components should be
very close to each other and be connected on the same surface as
the components. Internal ground planes should not be used for
the star ground connection, because vias add impedance to the
current path.
In order to further reduce noise effects on the PCB, noise sensi-
tive traces should not be connected to internal ground planes.
The feedback network from the switcher output should have an
independent ground trace that goes directly to the exposed pad
underneath the device. The exposed pad should be connected
to internal ground plans and any exposed copper used for heat
dissipation. If the ground connections from the device are also
connected directly to the exposed pad, the ground reference from
the feedback network will be less susceptible to noise injection or
ground bounce.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
10 15 20 25 30 35 40 45 50 55 60
P
RDROP
(W)
MOSFET Thermal Resistance (°C/W)
140 mA
230 mA
320 mA
410 mA
500 mA
Figure 10. RDROP Dissipation versus MOSFET thermal resistance at
various V33 regulator maximum current settings, IV33ILIM
Figure 11. Illustration of star ground connection
Star Ground
LX
Q1
A4405
DBUCK Current path
(off-cycle)
Current path (on-cycle)
RSENSE
L1
VIN
CIN
RLOAD
CVREG
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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To reduce radiated emissions from the high frequency switching
nodes, it is important to have an internal ground plane directly
under the LX node. The plane should not be broken directly
under the node because the lowest impedance path back to the
star ground would then be directly under the signal trace. If
another trace does break the return path, the energy will have to
find another path, which is through radiated emissions.
For accurate current sensing, the current sense pins, ISEN+ and
ISEN–, and the internal differential amplifier comprise a dif-
ferential signal receiver, and a balanced pair of traces should be
routed from the pins of the buck current sense resistor, RSENSE ,
as shown in figure 12 (upper panel). The ISEN+ pin and the sense
resistor ground should not be separated by simply using local via
connections to the ground plane (figure 12 lower panel). Incorrect
routing of the ISEN+ pin would likely add an offset error to the
buck current sense signal.
LX
ISEN–
ISEN+
A4405
Differential
Amplifier DBUCK
(Asynchronous)
RSENSE
L1
+
–
LX
ISEN–
ISEN+
Ground plane
A4405
Differential
Amplifier DBUCK
(Asynchronous)
RSENSE
L1
+
–
Figure 12. Comparison of routing paths for the traces between the A4405
ISEN+ and ISEN– traces and the sense resistor, RSENSE
Correct routing of ISEN+ and ISEN– traces
(direct on same plane)
Incorrect routing of ISEN+ and ISEN– traces
(using vias to a ground plane)
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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Allegro MicroSystems, LLC
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Application Circuit Performance
(Refer to Typical Application Circuit diagram.)
Frequency (kHz)
Phase (°)
Gain (dB)
103
10010110–1
60
48
36
24
12
0
-12
-24
-36
-48
-60
200
160
120
80
40
0
-40
-80
-120
-160
-200
Gain 215 mA
Gain 0.8 A
Gain Margin 12 dB
Phase 215 mA
Phase Margin 215 mA (55°)
Phase Margin 0.8 A (59°)
Phase 0.8 A
Gain 0 dB
(215 mA: at 106 kHz
0.8 mA: at 104 kHz)
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80
VOUT Percentage Drop (%)
VOUT Percentage Drop (%)
Output Current, IOUT (A)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.000 0.050 0.100 0.150 0.200 0.250 0.300
Output Current, I
OUT
(A)
V5
V5P
V33
50
55
60
65
70
75
80
85
90
95
100
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80
Efficiency (%)
Output Current, I
OUT
(A)
Buck Regulator Bode Plots
At ILOAD = 215 mA and 0.8 A
Efficiency (%)
Output Current, I
OUT
(A)
-
-
-
Output Current, I
OUT
(A)
Buck Regulator (VREG) Efficiency
Buck Regulator (VREG) Load Regulation Linear Regulator Load Regulation
V
IN
= 8 V
V
IN
= 12 V
V
IN
= 16 V
V
IN
= 8 V
V
IN
=
12
V
V
IN
= 16 V
Bill of Materials for Critical Components
This design is capable of full load, 135°C ambient, and 5.5 VBAT indefinitely with an adequate thermal solution
Component Description Package Manufacturer Part Number
QV33 MOSFET, 40 V, 90 A, 4.3 m, TJ 175°C DPAK Infineon IPD90N04S3-04
RSENSE Resistor, 0.300 , 1/4 W, 1% 1206
RCL Resistor, 0.390 , 1/4 W, 1% 1206
RDROP Resistor, 1.2 total, 1/2 W, 1% 1210
CIN1
, CIN2 Capacitor, Ceramic, 4.7 F, 50 V, 10%, X7R 1210 Murata GCM32ER71H475KA55L
CVREG Capacitor, Ceramic, 10 F, 16 V, 10%, X7R 1206 Kemet C1206C106K4RACTU
CV33, CV5, CV5P Capacitor, Ceramic, 2.2 F, 16 V, 10%, X7R 1206 Murata GRM31MR71C225KA35L
DBUCK , DIN, DV5P Diode, Schottky, 2 A, 40 V SMA Diodes, Inc. B240A-13-F
L1 Inductor, 10 H, 64 m, 2.39 Asat
, 165°C 7.6 x 7.6 mm Cooper/Bussman DRA73-100-R
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
24
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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Startup at VIN = 13.5 V; shows VVREG (ch1, 2 V/div.), VV33 (ch2, 2 V/div.),
NPOR (ch3, 2 V /div.), t = 5 ms/div.
t
VV33
NPOR
VVREG
C1
C3
C2
PWM at VBAT = 12 V with a VREG 0.8 A load; shows VVREG (ch1,
5 V/div.), VLX (ch2, 5 V/div.), IL (ch3, 500 mA/div.), t = 500 ns/div.
t
VREG
VLX
IL
C1
C3
C2
Startup at VIN = 13.5 V; shows VVREG (ch1, 2 V/div.), VV5 (ch2, 2 V/div.),
VV5P (ch3, 2 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.
C1
C3
C4
C2
t
VV5
VV5P
NPOR
VVREG
Startup at VIN = 6.5 V; shows VVREG (ch1, 2 V/div.), VV5 (ch2, 2 V/div.),
VV5P (ch3, 2 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.
C1
C3
C4
C2
t
VV5
VV5P
NPOR
VVREG
Startup at VIN = 6.5 V; shows VVREG (ch1, 2 V/div.), VV33 (ch2, 2 V/div.),
NPOR (ch3, 2 V /div.), t = 5 ms/div.
t
VV33
NPOR
VVREG
C1
C3
C2
PWM at VBAT = 12 V with a VREG 25 mA load; shows VVREG (ch1,
5 V/div.), VLX (ch2, 5 V/div.), IL (ch3, 100 mA/div.), t = 2 s/div.
t
VVREG
IL
C1
C3
C2
VLX
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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VV33 Transient Response: 125 mA to 250 mA; shows VV33 (ch1,
50 mV/div.), IV33 (ch2, 100 mA/div.), t = 50 s/div.
t
VV33
IV33
C1
C2
VV5 Transient Response: 100 mA to 200 mA; shows VV5 (ch1,
50 mV/div.), IV5 (ch2, 100 mA/div.), t = 50 s/div.
C1
C2
t
VV5
IV5
VREG Short Circuit Operation, VIN = 12 V; shows VVREG (ch1, 2 V/div.),
IL (ch2, 500 mA/div.), t = 5 s/div.
C1
C2 t
IL
VVREG
VV5P Transient Response: 125 mA to 250 mA; shows VV5P (ch1,
50 mV/div.), IV5P (ch2, 100 mA/div.), t = 50 s/div.
t
VV5P
IV5P
C1
C2
VREG Normal and Overloaded Operation, VIN = 12 V; shows IL (ch1,
250 mA/div.), VVREG (ch2, 2 V/div.)
t
ILIL
VVREG
VVREG
Before Overcurrent After Overcurrent
C1
C2
C1
C2
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
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Allegro MicroSystems, LLC
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1.508.853.5000; www.allegromicro.com
Package LP, 20-Pin TSSOP
with Exposed Thermal Pad
A
1.20 MAX
0.15
0.00
0.30
0.19
0.20
0.09
8º
0º
0.60 ±0.15
1.00 REF
C
SEATING
PLANE
C0.10
20X
0.65 BSC
0.25 BSC
21
20
6.50±0.10
4.40±0.103.00 3.00
4.20
4.20
6.40±0.20
GAUGE PLANE
SEATING PLANE
ATerminal #1 mark area
For Reference Only; not for tooling use (reference MO-153 ACT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
0.45
1.70
20
21
PCB Layout Reference View
B
6.10
0.65
CExposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
SOP65P640X110-21M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
C
Constant On-T ime Buck Regulator
W ith One External and Two Internal Linear Regulators
A4405
27
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Rev. 2 February 11, 2013 Update typical application and asynchronous
diode description
Copyright ©2012-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
