CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
2-V to 6-V VCC Operation
D
Wide Operating Temperature Range of
–55°C to 125°C
D
3-State Outputs Directly Drive Bus Lines
D
Balanced Propagation Delays and
Transition Times
D
Bus Driver Outputs Drive Up To 15 LS-TTL
Loads
D
Significant Power Reduction Compared to
LS-TTL Logic ICs
description/ordering information
The ’HC573 devices are octal transparent D-type
latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – E Tube CD74HC573E CD74HC573E
55°Cto125°C
SOIC M
Tube CD74HC573M
HC573M
–
55°C
to
125°C
SOIC
–
M
Tape and reel CD74HC573M96
HC573M
CDIP – F Tube CD54HC573F3A CD54HC573F3A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CD54HC573 ...F PACKAGE
CD74HC573 ...E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D Q
L H H H
LHL L
LLX Q
0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
219
LE
1D
C1
1D 1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output drain current per output, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output source or sink current per output, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): E package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
TA = 25°CTA = –55°C
TO 125°CTA = –40°C
TO 85°CUNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 2 6 2 6 2 6 V
VCC = 2 V 1.5 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 3.15 V
VCC = 6 V 4.2 4.2 4.2
VCC = 2 V 0.5 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 1.35 V
VCC = 6 V 1.8 1.8 1.8
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
VCC = 2 V 1000 1000 1000
ttInput transition (rise and fall) time VCC = 4.5 V 500 500 500 ns
VCC = 6 V 400 400 400
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
TA = 25°CTA = –55°C
TO 125°CTA = –40°C
TO 85°CUNIT
CC
MIN MAX MIN MAX MIN MAX
2 V 1.9 1.9 1.9
IOH = –20 µA4.5 V 4.4 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.9 5.9 V
IOH = –6 mA 4.5 V 3.98 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.2 5.34
2 V 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.1 0.1 0.1 V
IOL = 6 mA 4.5 V 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±1±1µA
IOZ VO = VCC or 0 6 V ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci10 10 10 pF
Co20 20 20 pF
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
CC
TA = 25°CTA = –55°C
TO 125°CTA = –40°C
TO 85°CUNIT
CC
MIN MAX MIN MAX MIN MAX
2 V 80 120 100
twPulse duration, LE high 4.5 V 16 24 20 ns
6 V 14 20 17
↓
2 V 50 75 65
tsu Setup time, data before LE
↓
4.5 V 10 15 13 ns
6 V 9 13 11
↓
2 V 40 60 50
thHold time, data after LE
↓
4.5 V 8 12 10 ns
6 V 7 10 9
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
V
CC
TA = 25°CTA = –55°C
TO 125°CTA = –40°C
TO 85°CUNIT
(INPUT)
(OUTPUT)
CAPACITANCE
CC
MIN MAX MIN MAX MIN MAX
2 V 175 265 220
D Q CL = 50 pF 4.5 V 35 53 44
td
6 V 30 45 37
ns
t
pd 2 V 175 265 220
ns
LE Q CL = 50 pF 4.5 V 35 53 44
6 V 30 45 37
2 V 150 225 190
ten OE Q CL = 50 pF 4.5 V 30 45 38 ns
6 V 26 38 33
2 V 150 225 190
tdis OE Q CL = 50 pF 4.5 V 30 45 38 ns
6 V 26 38 33
2 V 60 90 75
ttQ CL = 50 pF 4.5 V 12 18 15 ns
6 V 10 15 13
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
Cpd Power dissipation capacitance 51 pF
CD54HC573, CD74HC573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Test
Point
From Output
Under TestCL
(see Note A)
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
RL = 1 kΩ
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC 10%
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVER Y TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC573F ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD54HC573F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
CD74HC573E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC573EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC573M ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC573M96 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC573M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC573MG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC573M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC573M96 SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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