DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT4094
8-stage shift-and-store bus register
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP0to QP7). The parallel outputs
may be connected directly to common bus lines.
Data is shifted on the positive-going clock (CP) transitions.
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS1and QS2) are available for
cascading a number of “4094” devices. Data is available at
QS1on the positive-going clock edges to allow high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS2on
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC = 5 V
CP to QS115 19 ns
CP to QS213 18 ns
CP to QPn20 21 ns
STR to QPn18 19 ns
fmax maximum clock frequency 95 86 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 83 92 pF
December 1990 3
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 STR strobe input
2 D serial input
3 CP clock input
4, 5, 6, 7,14, 13, 12, 11 QP0to QP7parallel outputs
8 GND ground (0 V)
9, 10 QS1,QS
2serial outputs
15 OE output enable input
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 5
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
NC= no change
= LOW-to-HIGH CP transition
= HIGH-to-LOW CP transition
Q’6= the information in the seventh register stage is transferred to the 8th register stage and QSnoutput at the
positive clock edge
INPUTS PARALLEL OUTPUTS SERIAL
OUTPUTS
CP OE STR D QP0QPnQS1QS2
L
L
H
H
H
H
X
X
L
H
H
H
X
X
X
L
H
H
Z
Z
NC
L
H
NC
Z
Z
NC
QPn - 1
QPn - 1
NC
Q’6
NC
Q’6
Q’6
Q’6
NC
NC
QP7
NC
NC
NC
QP7
Fig.6 Timing diagram.
December 1990 6
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to QS1
50
18
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
CP to QS2
44
16
13
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
CP to QPn
63
23
18
195
39
33
245
49
42
295
59
50
ns 2.0
4.5
6.0
Fig.7
tPHL/ tPLH propagation delay
STR to QPn
58
21
17
180
36
31
225
45
38
270
54
46
ns 2.0
4.5
6.0
Fig.8
tPZH/ tPZL 3-state output enable time
OE to QPn
55
20
16
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.9
tPHZ/ tPLZ 3-state output disable
time OE to QPn
41
15
12
125
25
21
155
31
26
190
38
32
ns 2.0
4.5
6.0
Fig.9
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5 Fig.7
tWclock pulse width
HIGH or LOW 80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tWstrobe pulse width
HIGH 80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
tsu set-up time
D to CP 50
10
9
14
5
4
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.10
tsu set-up time
CP to STR 100
20
17
28
10
8
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.8
December 1990 7
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
thhold time
D to CP 3
3
3
6
2
2
3
3
3
3
3
3
ns 2.0
4.5
6.0
Fig.10
thhold time
CP to STR 0
0
0
14
5
4
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.8
fmax maximum clock pulse
frequency 6.0
30
35
28
87
103
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
December 1990 8
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
OE, CP
D
STR
1.50
0.40
1.00
December 1990 9
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to QS1
23 39 49 59 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
CP to QS2
21 36 45 54 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
CP to QPn
25 43 54 65 ns 4.5 Fig.7
tPHL/ tPLH propagation delay
STR to QPn
22 39 49 59 ns 4.5 Fig.8
tPZH/ tPZL 3-state output enable time
OE to QPn
20 35 44 53 ns 4.5 Fig.9
tPHZ/ tPLZ 3-state output disable time
OE to QPn
21 35 44 53 ns 4.5 Fig.9
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7
tWclock pulse width
HIGH or LOW 16 7 20 24 ns 4.5 Fig.7
tWstrobe pulse width
HIGH 16 5 20 24 ns 4.5 Fig.8
tsu set-up time
D to CP 10 4 13 15 ns 4.5 Fig.10
tsu set-up time
CP to STR 20 9 25 30 ns 4.5 Fig.8
thhold time
D to CP 4 0 4 4 ns 4.5 Fig.10
thhold time
CP to STR 04 0 0 ns 4.5 Fig.8
fmax maximum clock pulse
frequency 30 80 24 20 MHz 4.5 Fig.7
December 1990 10
Philips Semiconductors Product specification
8-stage shift-and-store bus register 74HC/HCT4094
AC WAVEFORMS
Fig.7 Waveforms showing the clock (CP) to
output (QPn,QS
1
,QS
2
) propagation
delays, the clock pulse width and the
maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the strobe (STR) to
output (QPn) propagation delays and the
strobe pulse width and the clock set-up and
hold times for the strobe input.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the 3-state enable and
disable times for input OE.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.10 Waveforms showing the data set-up and
hold times for the data input (D).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.