TLC542IDWG4 - Texas Instruments

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUAR Y 1989 – REVISED JUNE 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-Bit Resolution A/D Converter

Microprocessor Peripheral or Stand-Alone

Operation

On-Chip 12-Channel Analog Multiplexer

Built-In Self-Test Mode

Software-Controllable Sample and Hold

Total Unadjusted Error ... ±0.5 LSB Max

Direct Replacement for Motorola

MC145041

Onboard System Clock

End-of-Conversion (EOC) Output

Pinout and Control Signals Compatible

With the TLC1542/3 10-Bit A/D Converters

CMOS Technology

PARAMETER VALUE

Channel Acquisition/Sample Time 16 µs

Conversion T ime (Max) 20 µs

Samples per Second (Max) 25 × 103

Power Dissipation (Max) 10 mW

description

The TLC542 is a CMOS converter built around an

8-bit switched-capacitor successive-approximation

analog-to-digital converter . The device is designed

for serial interface to a microprocessor or peripheral

via a 3-state output with three inputs [including I/O

CLOCK, CS (chip select), and ADDRESS INPUT].

The TLC542 allows high-speed data transfers and

sample rates of up to 40,000 samples per second. In addition to the high-speed converter and versatile control

logic, an on-chip 12-channel analog multiplexer can sample any one of 1 1 inputs or an internal self-test voltage,

and the sample and hold is started under microprocessor control. At the end of conversion, the end-of-

conversion (EOC) output pin goes high to indicate that conversion is complete.

The converter incorporated in the TLC542 features differential high-impedance reference inputs that facilitate

ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noises. A switched-

capacitor design allows low-error (±0.5 LSB) conversion in 20 µs over the full operating temperature range.

The TLC542C is characterized for operation from 0°C to 70°C and the TLC542I is characterized for operation

from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

TACHIP CARRIER

(FN) PLASTIC DIP

(N) SMALL OUTLINE

(DW)

0°C to 70°C — TLC542CN TLC542CDW

–40°C to 85°C TLC542IFN TLC542IN TLC542IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

INPUT A0

INPUT A1

INPUT A2

INPUT A3

INPUT A4

INPUT A5

INPUT A6

INPUT A7

INPUT A8

GND

VCC

EOC

I/O CLOCK

ADDRESS INPUT

DATA OUT

REF+

REF–

INPUT A10

INPUT A9

DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

I/O CLOCK

ADDRESS INP

DATA OUT

REF+

INPUT A3

INPUT A4

INPUT A5

INPUT A6

INPUT A7

FN PACKAGE

(TOP VIEW)

INPUT A2

INPUT A1

INPUT A0

INPUT A10

REF– V

EOC

INPUT A8

GND

INPUT A9 CC

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

12-Channel

Analog

Multiplexer

Sample and

Hold 8-Bit

Analog-to-Digital

Converter

(Switched-Capacitors)

Self-Test

Reference

Output

Data

8-to-1 Data

Selector and

Driver

Control Logic

and I/O

Counters

Input Address

REF+ REF–

DATA

OUT

Analog

Inputs

I/O CLOCK

EOC

Input

Multiplexer

ADDRESS

INPUT

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

Ci = 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

INPUT

A0–A10 INPUT

A0–A10

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating sequence

MSB LSB Don’t Care Don’t Care

MSB LSB

tc(1)

(see Note A)

Hi-Z

State

Hi-Z State

Access

Cycle C

Access

Cycle B

Previous Conversion Data A Conversion Data B

MSB LSB MSB LSB

(see Note B)

B7 B6 B5 B4 B3 B2 B1 B0A7 A6 A5 A4 A3 A2 A1 A0

B3 B2 B1 B0 C3 C2 C1 C0

1 2345678 1 2345678

I/O

CLOCK

ADDRESS

INPUT

DATA

OUT

EOC

12 Internal System Clocks ≤12 µs

tsu(CS)

tsu(A) tacq t(acq)

td(I/O–EOC) td(EOC–DATA)

tc(2)

See Note B

Don’t Care

NOTES: A. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge

of the internal system clock after CS↓before responding to control input signals. The CS setup time is given by the tsu(CS)

specifications. Therefore, no attempt should be made to clock-in an address until the minimum chip select setup time has elapsed.

B. The output becomes 3-state on CS going high or on the negative edge of the eighth I/O clock.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO –0.3 V to VCC+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current range (any input), Ip-p) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs), IP ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: TLC542C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC542l –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, TC: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions, VCC = 4.75 to 5.5 V

MIN NOM MAX UNIT

Supply voltage, VCC 4.75 5 5.5 V

Positive reference voltage, V ref+ (see Note 2) Vref–VCC VCC + 0.1 V

Negative reference voltage, V ref– (see Note 2) –0.1 0 Vref+ V

Differential reference voltage, Vref+ – Vref– (see Note 2) 1 VCC VCC + 0.2 V

Analog input voltage (see Note 3) 0 VCC V

High-level control input voltage, VIH 2 V

Low-level control input voltage, VIL 0.8 V

Setup time, address bits at data input before I/O CLOCK↑, tsu(A) 400 ns

Hold time, address bits after I/O CLOCK↑, th(A) 0 ns

Hold time, CS low after 8th I/O CLOCK↑, th(CS) 0 ns

Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 4) 3.8 µs

Input/output clock frequency, f(clock I/O) 0 1.1 MHz

Input/output clock high, tw(H I/O) 404 ns

Input/output clock low, tw(L I/O) 404 ns

I/O CLOCK transition time tt(see Note 3)

fclock(I/O) ≤525 kHz 100

I/O

CLOCK

transition

time

(see

Note

fclock(I/O) > 525 kHz 40

erating free air tem

erature TA

TLC542C 0 70

°C

Operating

free

air

temperature

ATLC542I –40 85

°C

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (11111111), while input voltages less than that applied

to REF– convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF–. Also, the total

unadjusted error may increase as this differential reference voltage falls below 4.75 V.

3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity

of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of

the internal system clock after CS ↓before responding to control input signals. The CS setup time is given by the tsu(CS)

specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.

electrical characteristics over recommended operating temperature range, VCC = V ref+ = 4.75 V to

5.5 V, f(clock I/O) = 1.1 MHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VOH High-level output voltage (DATA OUT) VCC = 4.75 V, IOH = –360 µA 2.4 V

VOL Low-level output voltage VCC = 4.75 V, IOL = 1.6 mA 0.4 V

Off state (high im

edance state) out

ut current

VO = VCC, CS at VCC 10

µA

Off

state

(high

impedance

state)

output

current

VO = 0, CS at VCC –10 µ

IIH High-level input current VI = VCC 0.005 2 µA

IIL Low-level input current VI = 0 –0.005 –2.5 µA

ICC Operating supply current CS at 0 V 1.2 2 mA

Selected channel leakage current

Selected channel at VCC and

unselected channel at 0 V 0.4

µA

Selected

channel

leakage

current

Selected channel at 0 V and

unselected channel at VCC –0.4 µ

Iref Maximum static analog reference current into REF+ Vref+ = VCC, Vref– = GND 10 µA

ut ca

acitance

Analog inputs 7 55 p

Input

capacitance

Control inputs 5 15

†All typical values are at TA = 25°C.

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range,

VCC = Vref+ = 4.75 to 5.5 V, f(clock I/O) = 1 MHZ

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

ELLinearity error (see Note 5) ±0.5 LSB

EZS Zero-scale error (see Note 6) See Note 2 ±0.5 LSB

EFS Full-scale error (see Note 6) See Note 2 ±0.5 LSB

Total unadjusted error (see Note 7) ±0.5 LSB

Self-test output code Input A11 address = 1011,

See Note 8 01111101

(126) 128 10000011

(130)

tc(1) Conversion time See operating sequence 20 µs

tc(2) Total access and conversion cycle time See operating sequence 40 µs

t(acq) Channel acquisition time (sample cycle) See operating sequence 16 µs

t(v) T ime output data remains valid after I/O CLK↓See Figure 5 10 ns

td(IO-DATA) Delay time, I/O CLK↓to data output valid See Figure 5 400 ns

td(IO-EOC) Delay time, 8th I/O CLK↓to EOC↓See Figure 6 500 ns

td(EOC-DATA) Delay time, EOC↑ to data out (MSB) See Figure 7 400 ns

tPZH, tPZL Delay time, CS↓ to data out (MSB) See Figure 2 3.4 µs

tPHZ, tPLZ Delay time, CS↑ to data out (MSB) See Figure 2 150 ns

tr(EOC) Rise time See Figure 7 100 ns

tf(EOC) Fall time See Figure 6 100 ns

tr(bus) Data bus rise time See Figure 5 300 ns

tf(bus) Data bus fall time See Figure 5 300 ns

†All typical values are at TA = 25°C.

NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied

to REF– convert to all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF–. Also, the total

unadjusted error may increase as this differential reference voltage falls below 4.75 V.

5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference

between 11111111 and the converted output for full-scale input voltage.

7. Total unadjusted error is the sum of linearity , zero-scale, and full-scale errors.

8. Both the input address and the output codes are expressed in positive logic. The A1 1 analog input signal is internally generated and

is used for test purposes.

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT FOR

tPZL AND tPLZ

LOAD CIRCUIT FOR

tPZH AND tPHZ

3 kΩ

VCC

LOAD CIRCUIT FOR

td, tr, AND tf

(see Note A)

Test

Point

3 kΩ

1.4 V

Output

Under Test

Output

Under Test Output

Under Test

(see Note A) CL

(see Note A)

Test

Point Test

Point

NOTE A: CL = 50 pF

Figure 1. Load Circuits

DATA OUT 2.4 V

0.4 V

90%

10%

tPZH, tPZL tPHZ, tPLZ

0.8 V

2 V

Figure 2. CS to Data Output Timing

th(A)

0.8 V

2 V

I/O

CLOCK

Address

Valid

tsu(A)

Figure 3. Address Timing

8th

Clock

CS 0.8 V

2 V

th(CS)

tsu(CS)

0.8 V

I/O CLOCK

Figure 4. Figure 4. CS to I/O CLOCK Timing

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

0.4 V

2.4 V 0.4 V

2.4 V

2 V 0.8 V

I/O CLOCK

DATA OUT

tr(I/O)

0.8 V

2 V

tr(bus), tf(bus)

td(I/O-DATA)

t(v)

f(clock I/O)

tf(I/O)

0.8 V

Figure 5. Data Output Timing

8th

Clock 0.8 V

2.4 V 0.4 V

tf(EOC)

td(I/O-EOC)

I/O CLOCK

EOC

Figure 6. EOC Timing

0.4 V

2.4 V

EOC

td(EOC-DATA)

Valid MSB

DATA OUT

0.4 V 2.4 V

tr(EOC)

Figure 7. Data Output to EOC Timing

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 8, the time required to charge the analog input capacitance from 0 to VS

within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

VC = VS 1–e–tc/RtCi

( ) (1

)

where Rt = Rs + ri

The final voltage to 1/2 LSB is given by

(2)VC (1/2 LSB) = VS – (VS/512)

Equating equation 1 to equation 2 and solving for time tc gives

VS –(VS/512) = VS 1–e

( ) (3

)

–tc/RtCi

and tc (1/2 LSB) = Rt × Ci × ln(512) (4

)

Therefore, with the values given the time for the analog input signal to settle is

(5)

tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(512)

This time must be less than the converter sample time shown in the timing diagrams.

Rsri

VSVC

50 pF MAX

1 kΩ MAX

Driving Source†TLC542

VI= Input Voltage at INPUT A0–A10

VS= External Driving Source Voltage

Rs= Source Resistance

ri= Input Resistance

Ci= Input Capacitance

†Driving source requirements:

•Noise and distortion for the source must be equivalent to the

resolution of the converter.

•Rs must be real at the input frequency.

Figure 8. Equivalent Input Circuit Including the Driving Source

TLC542C, TLC542I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The TLC542 is a complete data acquisition system on a single chip. The device includes such functions as analog

multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. Three control inputs

(I/O CLOCK, CS (chip select), and ADDRESS INPUT) are included for flexibility and access speed. These control

inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or

microcomputer. With judicious interface timing, the TLC542 can complete a conversion in 20 µs, while complete

input-conversion-output cycles can be repeated every 40 µs. Furthermore, this fast conversion can be executed on

any of 11 inputs or its built-in self-test and in any order desired by the controlling processor.

When CS is high, the DATA OUT terminal is in a 3-state condition, and the ADDRESS INPUT and I/O CLOCK

terminals are disabled. When additional TLC542 devices are used, this feature allows each of these terminals, with

the exception of the CS terminal, to share a control logic point with their counterpart terminals on additional A/D

devices. Thus, this feature minimizes the control logic terminals required when using multiple A/D devices.

The control sequence is designed to minimize the time and effort required to initiate conversion and obtain the

conversion result. A normal control sequence is as follows:

1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two

rising edges and then a falling edge of the internal system clock before recognizing the low CS transition.

The MSB of the result of the previous conversion automatically appears on the DATA OUT terminal.

2. On the first four rising edges of the I/O CLOCK, a new positive-logic multiplexer address is shifted in, with

the MSB of this address shifted first. The negative edges of these four I/O CLOCK pulses shift out the

second, third, fourth, and fifth most significant bits of the result of the previous conversion. The on-chip

sample and hold begins sampling the newly addressed analog input after the fourth falling edge of the I/O

CLOCK. The sampling operation basically involves charging the internal capacitors to the level of the analog

input voltage.

3. Three clock cycles are applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion

bits are shifted out on the negative edges of these clock cycles.

4. The final eighth clock cycle is applied to the I/O CLOCK terminal. The falling edge of this clock cycle initiates

a 12-system clock (≈12 µs) additional sampling period while the output is in the high-impedance state.

Conversion is then performed during the next 20 µs. After this final I/O CLOCK cycle, CS must go high or

the I/O CLOCK must remain low for at least 20 µs to allow for the conversion function.

CS can be kept low during periods of multiple conversion. If CS is taken high, it must remain high until the end of

conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion process.

A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through

4 before the 20-µs conversion time has elapsed. Such action yields the conversion result of the previous conversion

and not the ongoing conversion.

The end-of-conversion (EOC) output goes low on the negative edge of the eighth I/O CLOCK. The subsequent

low-to-high transition of EOC indicates the A/D conversion is complete and the conversion is ready for transfer.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC542CDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542CDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542CN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC542CNE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC542IDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542IDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC542IFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC542IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC542IFNR ACTIVE PLCC FN 20 1000 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC542IFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC542IN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC542INE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 25-May-2009

Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 25-May-2009

Addendum-Page 2

IMPORTANT NOTICE
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