DCT OR DCU PACKAGE
(TOP VIEW)
18
GND
27
VREF1
3 6
SCL1
45
SDA1
EN
VREF2
SCL2
SDA2
DQE PACKAGE
(TOP VIEW)
EN
SCL2
SDA2
SCL1
SDA1
1
2
3
4
8
7
6
5
GND
VREF1 VREF2
45
3 6
27
18
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
YZT PACKAGE
(BOTTOM VIEW)
D1
C1
B1
A1
D2
C2
B2
A2
PCA9306
www.ti.com
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus
VOLTAGE-LEVEL TRANSLATOR
Check for Samples: PCA9306
1FEATURES
• 2-Bit Bidirectional Translator for SDA and SCL • Latch-Up Performance Exceeds 100 mA Per
Lines in Mixed-Mode I2C Applications JESD 78, Class II
• I2C and SMBus Compatible • ESD Protection Exceeds JESD 22
• Less Than 1.5-ns Maximum Propagation Delay – 2000-V Human-Body Model (A114-A)
to Accommodate Standard-Mode and – 200-V Machine Model (A115-A)
Fast-Mode I2C Devices and Multiple Masters – 1000-V Charged-Device Model (C101)
• Allows Voltage-Level Translator Between
– 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V,
or 5-V VREF2
– 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
– 2.5-V VREF1 and 3.3-V or 5-V VREF2
– 3.3-V VREF1 and 5-V VREF2
• Provides Bidirectional Voltage Translation
With No Direction Pin
• Low 3.5-ΩON-State Connection Between Input
and Output Ports Provides Less Signal
Distortion
• Open-Drain I2C I/O Ports (SCL1, SDA1, SCL2,
and SDA2)
• 5-V Tolerant I2C I/O Ports to Support
Mixed-Mode Signal Operation
• High-Impedance SCL1, SDA1, SCL2, and SDA2
Pins for EN = Low
• Lock-Up-Free Operation for Isolation When
EN = Low
• Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
DESCRIPTION/ORDERING INFORMATION
This dual bidirectional I2C and SMBus voltage-level translator, with an enable (EN) input, is operational from
1.2-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.
The PCA9306 allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin.
The low ON-state resistance (ron) of the switch allows connections to be made with minimal propagation delay.
When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2
I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and
a high-impedance state exists between ports.
In I2C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the
PCA9306 enables the system designer to isolate two halves of a bus; thus, more I2C devices or longer trace
length can be accommodated.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9306
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
www.ti.com
The PCA9306 also can be used to run two buses, one at 400-kHz operating frequency and the other at 100-kHz
operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated
when the 400-kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum
system operating frequency may be less than 400 kHz because of the delays added by the repeater.
As with the standard I2C system, pullup resistors are required to provide the logic high levels on the translator's
bus. The PCA9306 has a standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with standard-mode and fast-mode I2C devices, in addition to SMBus devices. Standard-mode I2C devices
only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.
Under certain conditions, high termination currents can be used.
When the SDA1 or SDA2 port is low, the clamp is in the ON state, and a low resistance connection exists
between the SDA1 and SDA2 ports. Assuming the higher voltage is on the SDA2 port when the SDA2 port is
high, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is high, the SDA2
port is pulled to the drain pullup supply voltage (VDPU) by the pullup resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user, without the need for directional
control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel.
All channels have the same electrical characteristics, and there is minimal deviation from one output to another in
voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the
fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower-voltage devices
and at the same time protects less ESD-resistant devices.t
ORDERING INFORMATION(1)
TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
Reel of 3000 PCA9306DCTR
SSOP – DCT 7BD_ _ _
Reel of 250 PCA9306DCTT
uQFN – DQE Reel of 5000 PCA9306DQER 7F
–40°C to 85°C uCSP – YZT Reel of 3000 PCA9306YZTR _ _ _7FS
Reel of 3000 PCA9306DCUR
VSSOP – DCU 7BD_
Reel of 250 PCA9306DCUT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCT/DQE/YZT/DCU: The actual top-side marking has three additional characters that designate the year, month, and wafer
fab/assembly site.
TERMINAL FUNCTIONS
TERMINAL
NO. DESCRIPTION
NAME DCT, DCU, YZT
DQE
GND 1 A1 Ground, 0 V
VREF1 2 B1 Low-voltage-side reference supply voltage for SCL1 and SDA1
SCL1 3 C1 Serial clock, low-voltage side
SDA1 4 D1 Serial data, low-voltage side
SDA2 5 D2 Serial data, high-voltage side
SCL2 6 C2 Serial clock, high-voltage side
VREF2 7 B2 High-voltage-side reference supply voltage for SCL2 and SDA2
EN 8 A2 Switch enable input
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Product Folder Link(s): PCA9306
SCL2
SDA2
SCL1
SDA1
VREF1
GND
VREF2
8
7
6
5
1
2
3
4
SW
SW
EN
PCA9306
www.ti.com
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
FUNCTION TABLE
LOGIC DIAGRAM (POSITIVE LOGIC) INPUT TRANSLATOR FUNCTION
EN(1)
H SCL1 = SCL2, SDA1 = SDA2
L Disconnect
(1) The SCL switch conducts if EN is ≥1 V higher than SCL1 or
SCL2. The same is true of SDA.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): PCA9306
PCA9306
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VREF1 DC reference voltage range –0.5 7 V
VREF2 DC reference bias voltage range –0.5 7 V
VIInput voltage range(2) –0.5 7 V
VI/O Input/output voltage range(2) –0.5 7 V
Continuous channel current 128 mA
IIK Input clamp current VI< 0 –50 mA
DCT package 220
DCU package 227
qJA Package thermal impedance(3) °C/W
DQE package 260
YZT package 102
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and input/output negative voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VI/O Input/output voltage SCL1, SDA1, SCL2, SDA2 0 5 V
VREF1 Reference voltage 0 5 V
VREF2 Reference voltage 0 5 V
EN Enable input voltage 0 5 V
IPASS Pass switch current 64 mA
TAOperating free-air temperature –40 85 °C
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II= –18 mA, EN = 0 V –1.2 V
IIH Input leakage current VI= 5 V, EN = 0 V 5 mA
Ci(EN) Input capacitance VI= 3 V or 0 11 pF
Cio(off) Off capacitance SCLn, SDAn VO= 3 V or 0, EN = 0 V 4 6 pF
Cio(on) On capacitance SCLn, SDAn VO= 3 V or 0, EN = 3 V 10.5 12.5 pF
EN = 4.5 V 3.5 5.5
EN = 3 V 4.7 7
VI= 0, IO= 64 mA EN = 2.3 V 6.3 9.5
ron (2) On-state resistance SCLn, SDAn EN = 1.5 V 25.5 32 Ω
EN = 4.5 V 1 6 15
VI= 2.4 V, IO= 15 mA EN = 3 V 20 60 140
VI= 1.7 V, IO= 15 mA EN = 2.3 V 20 60 140
(1) All typical values are at TA= 25°C.
(2) Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals, at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
4Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9306
PCA9306
www.ti.com
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
AC PERFORMANCE (TRANSLATING DOWN) (3)
Switching Characteristics
over recommended operating free-air temperature range, EN = 3.3 V, VIH = 3.3 V, VIL = 0, VM= 1.15 V (unless otherwise
noted) (see Figure 1)CL= 50 pF CL= 30 pF CL= 15 pF
FROM TO
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
tPLH 0 0.8 0 0.6 0 0.3
SCL2 or SDA2 SCL1 or SDA1 ns
tPHL 0 1.2 0 1 0 0.5
(3) Translating down–the high voltage side driving toward the lower voltage side
Switching Characteristics
over recommended operating free-air temperature range, EN = 2.5 V, VIH = 3.3 V, VIL = 0, VM= 0.75 V (unless otherwise
noted) (see Figure 1)CL= 50 pF CL= 30 pF CL= 15 pF
FROM TO
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
tPLH 0 1 0 0.7 0 0.4
SCL2 or SDA2 SCL1 or SDA1 ns
tPHL 0 1.3 0 1 0 0.6
AC PERFORMANCE (TRANSLATING UP) (1)
Switching Characteristics
over recommended operating free-air temperature range, EN = 3.3 V, VIH = 2.3 V, VIL = 0, VT= 3.3 V, VM= 1.15 V, RL= 300
Ω(unless otherwise noted) (see Figure 1)CL= 50 pF CL= 30 pF CL= 15 pF
FROM TO
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
tPLH 0 0.9 0 0.6 0 0.4
SCL1 or SDA1 SCL2 or SDA2 ns
tPHL 0 1.4 0 1.1 0 0.7
(1) Translating up–the lower voltage side driving toward the higher voltage side
Switching Characteristics
over recommended operating free-air temperature range, EN = 2.5 V, VIH = 1.5 V, VIL = 0, VT= 2.5 V, VM= 0.75 V, RL= 300
Ω, (unless otherwise noted) (see Figure 1)CL= 50 pF CL= 30 pF CL= 15 pF
FROM TO
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
tPLH 0 1 0 0.6 0 0.4
SCL1 or SDA1 SCL2 or SDA2 ns
tPHL 0 1.3 0 1.3 0 0.8
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): PCA9306
NOTES: A. CLincludes probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ ≤ ≤10 MHz, Z = 50 t 2 ns, t
O r f
Ω, 2ns.
C. The outputs are measured one at a time, with one transition per measurement.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
TRANSLATING UP
TRANSLATING DOWN
RLTranslating up
Translating down
S1
S2
USAGE SWITCH
VMVM
3.3 V
VIL
Input
VMVM
5 V
VOL
Output
VMVM
5 V
VIL
Input
VMVM
2 V
VOL
Output
VT
S1
S2
Open
PCA9306
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit for Outputs
6Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9306
1
2
3
45
6
7
8
SW
SW
V = 1.8 V
REF1
V = 3.3 V
DPU
I C Bus
Master
2
I C Bus
Device
2
VREF1 VREF2
EN
VCC VCC
PCA9306
GND GND GND
SDA
SDA1 SDA2
200 kΩ
SCL1
SCL SCL
SDA
SCL2
RPU RPU
RPU RPU
PCA9306
www.ti.com
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
APPLICATION INFORMATION
General Applications of I2C
In I2C applications, the bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the
PCA9306 enables the system designer to isolate two halves of a bus; thus, more I2C devices or longer trace
length can be accommodated.
The PCA9306 also can be used to run two buses, one at 400-kHz operating frequency and the other at 100-kHz
operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated
when the 400-kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum
system operating frequency may be less than 400 kHz because of the delays added by the repeater.
As with the standard I2C system, pullup resistors are required to provide the logic high levels on the translator's
bus. The PCA9306 has a standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with standard-mode and fast-mode I2C devices, in addition to SMBus devices. Standard-mode I2C devices
only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.
Under certain conditions, high termination currents can be used.
Figure 2. Typical Application Circuit (Switch Always Enabled)
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): PCA9306
SDA1
VREF1 = 1.8 V
VDPU = 3.3 V
I2C Bus
Master
PCA9306
I2C Bus
Device
1
2
3
45
6
7
8
SCL1 SCL2
SDA2
VREF1 VREF2
EN
RPU RPU
200 kΩ
VCC
SDA
SCL SW
SW
SCL
SDA
VCC
RPU RPU
GND GND GND
3.3-V Enable Signal
Off
On
PCA9306
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
www.ti.com
Figure 3. Typical Application Circuit (Switch Enable Control)
Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to VREF2 and both pins pulled to high-side VDPU through a pullup resistor
(typically 200 kΩ). This allows VREF2 to regulate the EN input. A filter capacitor on VREF2 is recommended. The
I2C bus master output can be totem pole or open drain (pullup resistors may be required) and the I2C bus device
output can be totem pole or open drain (pullup resistors are required to pull the SCL2 and SDA2 outputs to
VDPU). However, if either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and
be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. If both
outputs are open drain, no direction control is needed.
The reference supply voltage (VREF1) is connected to the processor core power-supply voltage.
Application Operating Conditions
see Figure 2
MIN TYP(1) MAX UNIT
VREF2 Reference voltage VREF1 + 0.6 2.1 5 V
EN Enable input voltage VREF1 + 0.6 2.1 5 V
VREF1 Reference voltage 0 1.5 4.4 V
IPASS Pass switch current 14 mA
IREF Reference-transistor current 5 mA
TAOperating free-air temperature –40 85 °C
(1) All typical values are at TA= 25°C.
8Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9306
RPU +VDPU *0.35 V
0.015 A
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0.1 110 100 1000
Gain (dB)
Frequency (MHz)
PCA9306
www.ti.com
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
Sizing Pullup Resistor
The pullup resistor value needs to limit the current through the pass transistor, when it is in the on state, to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15
mA, the pullup resistor value is calculated as:
The following table summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA.
The resistor value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage
of the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on
both sides of the PCA9306 device at 0.175 V, although the 15 mA applies only to current flowing through the
PCA9306 device.
PULLUP RESISTOR VALUES (1) (2)
PULLUP RESISTOR VALUE (Ω)
15 mA 10 mA 3 mA
VDPU NOMINAL +10%(3) NOMINAL +10%(3) NOMINAL +10%(3)
5 V 310 341 465 512 1550 1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V 77 85 115 127 383 422
1.2 V 57 63 85 94 283 312
(1) Calculated for VOL = 0.35 V
(2) Assumes output driver VOL = 0.175 V at stated current
(3) +10% to compensate for VDD range and resistor tolerance
PCA9306 Bandwidth
The maximum frequency of the PCA9306 is dependent on the application. The device can operate at speeds of
> 100MHz given the correct conditions. The maximum frequency is dependent upon the loading of the
application. The PCA9306 behaves like a standard switch where the bandwidth of the device is dictated by the
on resistance and on capacitance of the device.
Figure 4 shows a bandwidth measurement of the PCA9306 using a two-port network analyzer.
Figure 4. Bandwidth
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): PCA9306
PCA9306
SCPS113J –OCTOBER 2004–REVISED OCTOBER 2010
www.ti.com
The 3-dB point of the PCA9306 is ≈600 MHz. However, this measurement is an analog type of measurement.
For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. As a rule of
thumb, the frequency bandwidth should be at least five times the maximum digital clock rate. This component of
the signal is very important in determining the overall shape of the digital signal. In the case of the PCA9306,
digital clock frequency of >100 MHz can be achieved.
The PCA9306 does not provide any drive capability like the PCA9515 or PCA9517 series of devices. Therefore
higher frequency applications will require higher drive strength from the host side. No pullup resistor is needed on
the host side (3.3 V) if the PCA9306 is being driven by standard CMOS totem pole output driver. Ideally, it is best
to minimize the trace length from the PCA9306 on the sink side (1.8 V) to minimize signal degradation.
You can then use a simple formula to compute the maximum "practical" frequency component. Or the "knee"
frequency (fknee). All fast edges have an infinite spectrum of frequency components. However, there is an
inflection (or "knee") in the frequency spectrum of fast edges where frequency components higher than fknee are
insignificant in determining the shape of the signal.
To calculate fknee:
fknee= 0.5/RT (10–80%)
fknee = 0.4/RT (20–80%)
For signals with rise time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by
the rise time of the signal. For signals with rise time characteristics based on 20- to 80-percent thresholds, which
is very common in many of today's device specifications, fknee is equal to 0.4 divided by the rise time of the
signal.
Some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the PCA9306 close to the I2C output of the processor
• The trace length should be less than half the time of flight to reduce ringing and line reflections or non
monotonic behavior in the switching region
• To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected
10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9306
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9306DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCTT ACTIVE SM8 DCT 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCTTE4 ACTIVE SM8 DCT 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCTTG4 ACTIVE SM8 DCT 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCUR ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
PCA9306DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCUT ACTIVE US8 DCU 8 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
PCA9306DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DCUTG4 ACTIVE US8 DCU 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306DQER ACTIVE X2SON DQE 8 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9306YZTR ACTIVE DSBGA YZT 8 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF PCA9306 :
•Automotive: PCA9306-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9306DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
PCA9306DQER X2SON DQE 8 5000 180.0 8.4 1.47 1.73 0.65 4.0 8.0 Q1
PCA9306YZTR DSBGA YZT 8 3000 180.0 8.4 1.02 2.02 0.75 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9306DCUR US8 DCU 8 3000 202.0 201.0 28.0
PCA9306DQER X2SON DQE 8 5000 202.0 201.0 28.0
PCA9306YZTR DSBGA YZT 8 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
0,60
0,20
0,25
0°– 8°
0,15 NOM
Gage Plane
4188781/C 09/02
4,25
5
0,30
0,15
2,90 3,75
2,70
8
4
3,15
2,75
1
0,10
0,00
1,30 MAX
Seating Plane
0,10
M
0,13
0,65
PIN 1
INDEX AREA
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
D: Max =
E: Max =
1.918 mm, Min =
0.918 mm, Min =
1.858 mm
0.858 mm
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