11 fo 1 egaP 00.3.veR 0030JE1300SD90R
Mar 12, 2013
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The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
teehS ataD
NE5550979A
Silicon Power LDMOS FET
FEATURES
•High Output Power : Pout = 39.5 dBm TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 25 dBm)
•High power added efficiency : ηadd = 66% TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 25 dBm)
•High Linear gain : GL = 22 dB TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 10 dBm)
•High ESD tolerance : ESD tolerance > 8 kV (IEC61000-4-2, Contact discharge)
•Suitable for VHF to UHF-BAND Class-AB power amplifier.
APPLICATIONS
•150 MHz Band Radio System
•460 MHz Band Radio System
•900 MHz Band Radio System
ORDERING INFORMATION
Part Number Order Number Package Marking Supplying Form
NE5550979A NE5550979A-A 79A
(Pb Free)
W6 •12 mm wide embossed taping
•Gate pin faces the perforation side of the tape
NE5550979A-T1 NE5550979A-T1-A •12 mm wide embossed taping
•Gate pin faces the perforation side of the tape
•Qty 1 kpcs/reel
NE5550979A-T1A NE5550979A-T1A-A •12 mm wide embossed taping
•Gate pin faces the perforation side of the tape
•Qty 5 kpcs/reel
Remark To order evaluation samples, please contact your nearby sales office.
Part number for sample order: NE5550979A-A
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified)
Operation in excess of any one of these parameters may result in permanent damage.
Parameter Symbol Ratings Unit
Drain to Source Voltage VDS 30 V
Gate to Source Voltage VGS 6.0 V
I tnerruC niarD DS 3.0 A
Total Power Dissipation Note Ptot 25 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg −55 to +150 °C
Note: Value at TC = 25°C
CAUTION
Observe precautions when handling because these devices are sensitive to electrostatic discharge.
R09DS0031EJ0300
Rev.3.00
Mar 12, 2013
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 2 of 11
Mar 12, 2013
RECOMMENDED OPERATING RANGE (TA = 25°C)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Drain to Source Voltage VDS − 7.5 9.0 V
Gate to Source Voltage VGS 1.65 2.20 2.85 V
Drain Current IDS − 1.7 − A
Input Power Pin f = 460 MHz, VDS = 7.5 V − 25 30 dBm
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
DC Characteristics
Gate to Source Leakage Current IGSS V
GS = 6.0 V − − 100 nA
Drain to Source Leakage Current
(Zero Gate Voltage Drain Current)
IDSS V
DS = 25 V − − 10 μA
Gate Threshold Voltage Vth V
DS = 7.5 V, IDS = 1.0 mA 1.15 1.65 2.25 V
Drain to Source Breakdown Voltage BVDSS I
DS = 10 μA 25 37 − V
Transconductance Gm V
DS = 7.5 V, IDS = 700±100 mA 1.8 2.2 2.9 S
Thermal Resistance Rth Channel to Case − 5.0 − °C/W
RF Characteristics
Output Power Pout f = 460 MHz, VDS = 7.5 V, 38.5 39.5 − dBm
Drain Current IDS P
in = 25 dBm, − 1.70 − A
Power Drain Efficiency
η
d I
Dset = 200 mA (RF OFF) − 68 − %
Power Added Efficiency
η
add − 66 − %
Linear Gain GL Note 1 − 22.0 − dB
Output Power Pout f = 157 MHz, VDS = 7.5 V, − 39.6 − dBm
Drain Current IDS P
in = 23 dBm, − 1.60 − A
Power Drain Efficiency
η
d I
Dset = 200 mA (RF OFF) − 75 − %
Power Added Efficiency
η
add − 73 − %
Linear Gain GL Note 2 − 25.0 − dB
Output Power Pout f = 900 MHz, VDS = 7.5 V, − 38.6 − dBm
Drain Current IDS P
in = 27 dBm, − 1.76 − A
Power Drain Efficiency
η
d I
Dset = 200 mA (RF OFF) − 55 − %
Power Added Efficiency
η
add − 52 − %
Linear Gain GL Note 1 − 16.0 − dB
Note 1 : Pin = 10 dBm
Note 2 : Pin = 5 dBm
Remark DC performance is 100% testing. RF performance is testing several samples per wafer.
Wafer rejection criteria for standard devices is 1 reject for several samples.
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 3 of 11
Mar 12, 2013
TEST CIRCUIT SCHEMATIC FOR 460 MHz
C20
C10
IN OUT
C22
C11 C12 C21
C1
V
DS
C1 L1R1
V
GS
FET
NE5550979A (WS)
50 Ω50 Ω
COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS
Symbol Value Type Maker
C1 1
μ
F GRM31CR72A105KA01B Murata
C10 100 pF GRM1882C1H101JA01 Murata
C11 24 pF ATC100A240JW American Technical
Ceramics
C12 2.4 pF ATC100A2R4BW American Technical
Ceramics
C20 27 pF ATC100A270JW American Technical
Ceramics
C21 1.8 pF ATC100A1R8BW American Technical
Ceramics
C22 100 pF ATC100A101JW American Technical
Ceramics
R1 4.7 kΩ 1/10 W Chip Resistor SSM
SSM_RG1608PB472
L1 123 nH
φ
0.5 mm,
φ
D = 3 mm, 10 Turns Ohesangyou
PCB − R1766, t = 0.4 mm,
ε
r = 4.5, size = 30 × 48 mm Panasonic
SMA Connecter − WAKA 01K0790-20 WAKA
COMPONENT LAYOUT OF TEST CIRCUIT FOR 460 MHz
C11
C10
C12
C1
R1
L1
C1
C20 C21
C22
VGS GND VDS
C11
C10
C12
C1
R1
L1
C1
C20 C21
C22
VGS GND VDS
<R>
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 4 of 11
Mar 12, 2013
TYPICAL CHARACTERISTICS 1 (TA = 25°C)
R: f = 460MHz, VDS = 3.6/4.5/6/7.5/8.4/9 V, IDset = 200 mA, Pin = 0 to 32 dBm
IM: f1 = 460MHz, f2 = 461 MHz, VDS = 3.6/4.5/6/7.5/8.4/9 V, IDset = 200mA, Pout (2 tone) = 12 to 38 dBm
add
- 3.6 V
add
- 6.0 V
add
- 4.5 V
add
- 9 V
add
- 7.5 V
3rd/5th Order Intermodulation Distortion IM
3
/IM
5
(dBc)
2 Tones Output Power P
out
(2 tone) (dBm)
IM
3
/IM
5
vs. 2 TONES OUTPUT POWER
2nd Harmonics 2f
0
(dBc)
3rd Harmonics 3f
0
(dBc)
Output Power P
out
(dBm)
2f
0
, 3f
0
vs. OUTPUT POWER
P
out
- 3.6 V
P
out
- 4.5 V
P
out
- 6.0 V
P
out
- 7.5 V
P
out
- 9 V
I
DS
- 3.6 V
I
DS
- 6.0 V
I
DS
- 4.5 V
I
DS
- 9 V
I
DS
- 7.5 V
Output Power P
out
(dBm)
Drain Current I
DS
(A)
Input Power P
in
(dBm)
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
0 0.0
50 5.0
45 4.5
40 4.0
35 3.5
30 3.0
25 2.5
20 2.0
15 1.5
10 1.0
5 0.5
3530201510–505 25
Power Gain G
P
(dB)
Power Added Efficiency
add
(%)
η
Input Power P
in
(dBm)
POWER GAIN, POWER ADDED
EFFICIENCY vs. INPUT POWER
G
p
- 3.6 V
G
p
- 4.5 V
G
p
- 6 V
G
p
- 7.5 V
G
p
- 9 V
00
40 80
35 70
30 60
25 50
20 40
15 30
10 20
510
3530201510–505 25
2f
0
- 3.6 V
2f
0
- 4.5 V
2f
0
- 6.0 V
2f
0
- 7.5 V
3f
0
- 3.6 V
3f
0
- 4.5 V
3f
0
- 7.5 V
3f
0
- 6.0 V
3f
0
- 9 V
2f
0
- 9 V
–70
0
–10
–20
–30
–40
–50
–60
4535302510 15 20 40
IM
3
- 3.6 V
IM
3
- 4.5 V
IM
3
- 6 V
IM
3
- 7.5 V
IM
5
- 3.6 V
IM
5
- 4.5 V
IM
5
- 7.5 V
IM
5
- 6.0 V
IM
5
- 9 V
IM
3
- 9 V
–70
0
–10
–20
–30
–40
–50
–60
4035302510 15 20
η
η
η
η
η
Remark The graphs indicate nominal characteristics.
A Business Partner of Renesas Electronics Corporation.
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 5 of 11
Mar 12, 2013
TEST CIRCUIT SCHEMATIC FOR 157 MHz
C10
IN OUT
C24
C11 C12 C21 C22 C23
C20
C1
V
DS
C1 L1
L11 L20
R1
V
GS
FET
NE5550979A
50 Ω50 Ω
COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS
Symbol Value Type Maker
C1 1
μ
F GRM31CR72A105KA01B Murata
C10 100 pF GRM1882C1H101JA01 Murata
C11 4.7 pF ATC100A4R7CT American Technical
Ceramics
C12 39 pF ATC100A390JT American Technical
Ceramics
C20 2.0 pF ATC100A2R0CT American Technical
Ceramics
C21 22 pF ATC100A220JT American Technical
Ceramics
C22 68 pF ATC100A680JT American Technical
Ceramics
C23 12 pF ATC100A120JT American Technical
Ceramics
C24 100 pF ATC100A101JT American Technical
Ceramics
R1 4.7 kΩ 1/10 W Chip Resistor SSM
SSM_RG1608PB472
L1 123 nH
φ
0.5 mm,
φ
D = 3 mm, 10 Turns Ohesangyou
L11 27 nH LLQ2012-F27N TOKO
L20 35 nH
φ
0.5 mm,
φ
D = 2.4 mm, 5 Turns Ohesangyou
PCB − R1766, t = 0.4 mm,
ε
r = 4.5, size = 30 × 48 mm Panasonic
SMA Connecter − WAKA 01K0790-20 WAKA
<R>
<R>
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 6 of 11
Mar 12, 2013
COMPONENT LAYOUT OF TEST CIRCUIT FOR 157 MHz
TYPICAL CHARACTERISTICS 2 (TA = 25°C)
R: f = 157 MHz, VDS = 3.6/4.5/6/7.5/9 V, IDset = 200 mA, Pin = 0 to 27 dBm
add - 3.6 V
add - 6 V
add - 4.5 V
add - 9 V
add - 7.5 V
Pout - 3.6 V
Pout - 4.5 V
Pout - 6.0 V
Pout - 7.5 V
Pout - 9 V
Output Power Pout (dBm)
Drain Current IDS (A)
Input Power Pin (dBm)
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
0 0.0
45 4.5
40 4.0
35 3.5
30 3.0
25 2.5
20 2.0
15 1.5
10 1.0
5 0.5
30201510–505 25
Power Gain GP (dB)
Power Added Efficiency add (%)
η
Input Power Pin (dBm)
POWER GAIN, POWER ADDED
EFFICIENCY vs. INPUT POWER
Gp - 3.6 V
Gp - 4.5 V
Gp - 6 V
Gp - 7.5 V
Gp - 9 V
00
40 80
35 70
30 60
25 50
20 40
15 30
10 20
510
IDS - 3.6 V
IDS - 6 V
IDS - 4.5 V
IDS - 9 V
IDS - 7.5 V
30201510–505 25
η
η
η
η
η
C23
C11
C10
C12
C1
R1
L1
C1
C20
C22
L11
C21 L20
C24
VGS VDSGND
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 7 of 11
Mar 12, 2013
TEST CIRCUIT SCHEMATIC FOR 900 MHz
C10
IN OUT
C23
C11 C21 C22
C20
C1
VDS
C1 L1R1
VGS
FET
NE5550979A
50 Ω50 Ω
COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS
Symbol Value Type Maker
C1 1
μ
F GRM31CR72A105KA01B Murata
C10 100 pF GRM1882C1H101JA01 Murata
C11 15 pF ATC100A150JW American Technical
Ceramics
C20 3.3 pF ATC100A3R3BW American Technical
Ceramics
C21 3.3 pF ATC100A3R3BW American Technical
Ceramics
C22 12 pF ATC100A120JT American Technical
Ceramics
C23 100 pF ATC100A101JT American Technical
Ceramics
R1 4.7 kΩ 1/10 W Chip Resistor SSM
SSM_RG1608PB472
L1 123 nH
φ
0.5 mm,
φ
D = 3 mm, 10 Turns Ohesangyou
PCB − R1766, t = 0.4 mm,
ε
r = 4.5, size = 30 × 48 mm Panasonic
SMA Connecter − WAKA 01K0790-20 WAKA
<R>
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 8 of 11
Mar 12, 2013
COMPONENT LAYOUT OF TEST CIRCUIT FOR 900 MHz
TYPICAL CHARACTERISTICS 3 (TA = 25°C)
RF: f = 900 MHz VDS = 3.6/4.5/6/7.5/9 V, IDset = 200 mA, Pin = 0 to 32 dBm
add
- 6.0 V
add
- 4.5 V
add
- 7.5 V
add
- 9 V
add
- 3.6 V
P
out
- 3.6 V
P
out
- 4.5 V
P
out
- 6.0 V
P
out
- 7.5 V
P
out
- 9 V
I
DS
- 3.6 V
I
DS
- 6.0 V
I
DS
- 4.5 V
I
DS
- 9 V
I
DS
- 7.5 V
Output Power P
out
(dBm)
Drain Current I
DS
(A)
Input Power P
in
(dBm)
OUTPUT POWER, DRAIN CURRENT
vs. INPUT POWER
0 0.0
50 5.0
45 4.5
40 4.0
35 3.5
30 3.0
25 2.5
20 2.0
15 1.5
10 1.0
5 0.5
3530201510–505 25
Power Gain G
P
(dB)
Power Added Efficiency
add
(%)
η
Input Power P
in
(dBm)
POWER GAIN, POWER ADDED
EFFICIENCY vs. INPUT POWER
G
p
- 3.6 V
G
p
- 4.5 V
G
p
- 6 V
G
p
- 7.5 V
G
p
- 9 V
00
40 80
35 70
30 60
25 50
20 40
15 30
10 20
510
3530201510–505 25
η
η
η
η
η
Remark The graphs indicate nominal characteristics.
C11
C10
C1
R1
L1
C1
C20
C22
VGS VDS
C21
C23
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 9 of 11
Mar 12, 2013
S-PARAMETERS
S-parameters and noise parameters are provided on our web site in a form (S2P) that enables direct import of the
parameters to microwave circuit simulators without the need for keyboard inputs.
Click here to download S-parameters.
[Products] → [RF Devices] → [Device Parameters]
URL http://www.renesas.com/products/microwave/
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 10 of 11
Mar 12, 2013
PACKAGE DIMENSIONS
79A (UNIT: mm)
0.9±0.2
0.2±0.1
0.4±0.15
5.7 MAX.
5.7 MAX.
0.6±0.15
0.8±0.15
4.4 MAX.
4.2 MAX.
Source
Gate Drain
(Bottom View)
3.6±0.2
1.5±0.2
1.2 MAX.
0.8 MAX.
1.0 MAX.
Source
Gate Drain
W 6
21001
79A PACKAGE RECOMMENDED P.C.B. LAYOUT (UNIT: mm)
1.7
4.0
0.5
1.0
5.9
1.2
Gate
Source
Drain
0.5
6.1
0.5 Through Hole: 0.2 × 33
φ
Stop up the hole with a rosin o
r
something to avoid solder flow
.
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NE5550979A
R09DS0031EJ0300 Rev.3.00 Page 11 of 11
Mar 12, 2013
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For soldering methods and
conditions other than those recommended below, contact your nearby sales office.
Soldering Method Soldering Conditions Condition Symbol
Infrared Reflow Peak temperature (package surface temperature) : 260°C or below
Time at peak temperature : 10 seconds or less
Time at temperature of 220°C or higher : 60 seconds or less
Preheating time at 120 to 180°C : 120±30 seconds
Maximum number of reflow processes : 3 times
Maximum chlorine content of rosin flux (% mass) : 0.2% (Wt.) or below
IR260
Wave Soldering Peak temperature (molten solder temperature) : 260°C or below
Time at peak temperature : 10 seconds or less
Preheating temperature (package surface temperature)
: 120°C or below
Maximum number of flow processes : 1 time
Maximum chlorine content of rosin flux (% mass) : 0.2% (Wt.) or below
WS260
Partial Heating Peak temperature (terminal temperature) : 350°C or below
Soldering time (per side of device) : 3 seconds or less
Maximum chlorine content of rosin flux (% mass) : 0.2% (Wt.) or below
HS350
CAUTION
Do not use different soldering methods together (except for partial heating).
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All trademarks and registered trademarks are the property of their respective owners.
C - 1
Revision History NE5550979A Data Sheet
Description
Rev. Date Page Summary
1.00 Nov 25, 2011 − First edition issued
2.00 Jul 04, 2012 p.1 Modification of ORDERING INFORMATION
p.5 Addition of TEST CIRCUIT SCHEMATIC FOR 157 MHz
p.6 Addition of COMPONENT LAYOUT OF TEST CIRCUIT FOR 157 MHz
p.7 Addition of TEST CIRCUIT SCHEMATIC FOR 900 MHz
p.8 Addition of COMPONENT LAYOUT OF TEST CIRCUIT FOR 900 MHz
p.9 Modification of S-PARAMETERS
3.00 Mar 12, 2013 P3 Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING
ELECTRICAL CHARACTERISTICS
P5 Modification of TEST CIRCUIT SCHEMATIC FOR 157 MHz
Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING
ELECTRICAL CHARACTERISTICS
P7
Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING
ELECTRICAL CHARACTERISTICS
DISCONTINUED
NOTICE
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and
application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. California
Eastern Laboratories and Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits,
software, or information.
2. California Eastern Laboratories has used reasonable care in preparing the information included in this document, but California Eastern Laboratories does
not warrant that such information is error free. California Eastern Laboratories and Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3. California Eastern Laboratories and Renesas Electronics do not assume any liability for infringement of patents, copyrights, or other intellectual property
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respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product
characteristics. California Eastern Laboratories shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products
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the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation
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NOTE 1: “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
NOTE 2: “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
NOTE 3: Products and product information are subject to change without notice.
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For a complete list of sales ofces, representatives and distributors,
Please visit our website: www.cel.com/contactus
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Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
CEL:
NE5550979A-EV04-A NE5550979A-T1-A NE5550979A-A NE5550979A-EV09-A