DOCUMENT NUMBER 9S12B128DGV1/D MC9S12B128 Device User Guide V01.04 Covers also MC9S12B64P Original Release Date: 22 Nov 2002 Revised: 05 May 2003 Semiconductor Products Sector Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2001 1 DOCUMENT NUMBER 9S12B128DGV1/D Revision History Version Revision Effective Number Date Date Author Description of Changes V01.00 20 NOV 2002 20 NOV 2002 Initial version based on MC9S12DGJ64-1.10 Version. V01.01 27 JAN 2003 01 FEB 2003 updated Table 0-1; added submodule configuration in Section 6 & Section 11. Updated memory map $0118-$011B V01.02 24 FEB 2003 24 FEB 2003 updated Table 0-1; updated section 2.2.28; Updated memory map $0101. V01.03 18MAR 2003 18 MAR 2003 added the IIC to the document; added for B64P more details in the preface and the according "Memory Map out of Reset" V01.04 05MAY 2003 05 MAY 2003 updated bus frequency in Table A-4; updated numbers in A.3.1.2 and A.3.1.3 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c)Motorola, Inc., 2001 2 Device User Guide -- 9S12B128DGV1/D V01.04 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Section 2 Signal Description 2.1 System Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.1.1 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.2 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.2.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.2.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.4 VREGEN -- Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.5 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . .51 2.2.7 PAD[15:0] / AN[15:0] -- Port AD Input Pins ATD . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.2.8 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .52 2.2.9 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.10 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2.11 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.12 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.13 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2.14 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.15 PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.16 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.17 PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.18 PH7 / KWH7 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.19 PH6 / KWH6 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.20 PH5 / KWH5 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.21 PH4 / KWH4 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.22 PH3 / KWH3 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.2.23 PH2 / KWH2 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.24 PH1 / KWH1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.25 PH0 / KWH0 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.26 PJ7 / KWJ7 / SCL -- Port J I/O Pins 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.27 PJ6 / KWJ6 / SDA -- Port J I/O Pins 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.28 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.29 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.30 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.2.31 PM7 -- Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.32 PM6 -- Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.33 PM5 / SCK0 -- Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.34 PM4 / MOSI0 -- Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.35 PM3 / SS0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.36 PM2 / MISO0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.37 PM1 / TXCAN0 -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.38 PM0 / RXCAN0 -- Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.39 PP7 / KWP7 / PWM7 -- Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.2.40 PP6 / KWP6 / PWM6 -- Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.41 PP5 / KWP5 / PWM5 -- Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.42 PP4 / KWP4 / PWM4 -- Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.43 PP3 / KWP3 / PWM3 -- Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.44 PP2 / KWP2 / PWM2 -- Port P I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.45 PP1 / KWP1 / PWM1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.46 PP0 / KWP0 / PWM0 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.47 PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.48 PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2.49 PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.50 PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.51 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.52 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.53 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.54 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.2.55 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4 Device User Guide -- 9S12B128DGV1/D V01.04 2.3.1 2.3.2 59 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 VDDX, VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . .59 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator VDD1, VDD2, VSS1, VSS2 -- Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .60 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .60 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .60 VREGEN -- On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Section 3 System Clock Description Section 4 Modes of Operation 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Section 5 Resets and Interrupts 5.1 5.2 5.2.1 5.3 5.3.1 5.3.2 5.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Section 6 HCS12 Core Block Description 6.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Section 7 Voltage Regulator (VREG3V3) Block Description 5 Device User Guide -- 9S12B128DGV1/D V01.04 Section 8 Clock and Reset Generator (CRG) Block Description 8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Section 9 Oscillator (OSC) Block Description 9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Section 10 Standard Timer (TIM) Block Description Section 11 Analog to Digital Converter (ATD) Block Description Section 12 Inter-IC Bus (IIC) Block Description Section 13 Serial Communications Interface (SCI) Block Description Section 14 Serial Peripheral Interface (SPI) Block Description Section 15 Flash EEPROM 128K1 Block Description Section 16 EEPROM 1K Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Pulse Width Modulator (PWM) Block Description Section 20 Port Integration Module (PIM) Block Description Section 21 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 6 Device User Guide -- 9S12B128DGV1/D V01.04 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.2.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.2.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.2.3 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 A.2.4 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.4 VREG_3V3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.4.2 Chip Power-up and Voltage Drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.4.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Appendix B Package Information B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 7 Device User Guide -- 9S12B128DGV1/D V01.04 8 Device User Guide -- 9S12B128DGV1/D V01.04 List of Figures Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure 21-1 Figure 21-2 Figure 21-3 Figure 21-4 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure B-1 Figure B-2 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 MC9S12B128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 MC9S12B128 Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 MC9S12B64P Memory Map out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Pin Assignments in 112-pin LQFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . .47 Pin Assignments in 80-pin QFP for MC9S12B128 . . . . . . . . . . . . . . . . . . . . . . .48 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Recommended PCB Layout 112LQFP Colpitts Oscillator. . . . . . . . . . . . . . . . . .73 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .74 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .75 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .76 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 VREG_3V3 - Chip Power-up and Voltage Drops (not scaled). . . . . . . . . . . . . 100 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 120 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 121 9 Device User Guide -- 9S12B128DGV1/D V01.04 10 Device User Guide -- 9S12B128DGV1/D V01.04 List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 $0000 - $000F MEBI map 1 of 3 (Core User Guide) ........................................................28 $0010 - $0014 MMC map 1 of 4 (Core User Guide) ........................................................28 $0015 - $0016 INT map 1 of 2 (Core User Guide) ...........................................................29 $0017 - $0017 MMC map 2 of 4 (Core User Guide) ........................................................29 $0018 - $0018 Reserved ..................................................................................................29 $0019 - $0019 VREG3V3 (Voltage Regulator) ................................................................29 $001A - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................29 $001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4) ...................29 $001E - $001E MEBI map 2 of 3 (Core User Guide) ........................................................29 $001F - $001F INT map 2 of 2 (Core User Guide) ...........................................................30 $0020 - $0027 Reserved ..................................................................................................30 $0028 - $002F BKP (Core User Guide) ...........................................................................30 $0030 - $0031 MMC map 4 of 4 (Core User Guide) ........................................................30 $0032 - $0033 MEBI map 3 of 3 (Core User Guide) ........................................................30 $0034 - $003F CRG (Clock and Reset Generator) ..........................................................31 $0040 - $006F TIM (Timer 16 Bit 8 Channels) .................................................................31 $0070 - $007F Reserved .................................................................................................33 $0080 - $00AF ATD (Analog to Digital Converter 10 Bit 16 Channel) ..............................33 $00B0 - $00C7 Reserved .................................................................................................35 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................35 $00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................35 $00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................36 $00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................36 $00E8 - $00FF Reserved ..................................................................................................37 $0100 - $010F Flash Control Register (fts128k1) ............................................................37 $0110 - $011B EEPROM Control Register (eets1k) ........................................................38 $011C - $013F Reserved ..................................................................................................38 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................38 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout . . . . . . . . . . .39 $0180 - $01FF Reserved ..................................................................................................40 11 Device User Guide -- 9S12B128DGV1/D V01.04 $0200 - $0227 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................40 $0228 - $023F Reserved ..................................................................................................42 $0240 - $027F PIM (Port Integration Module) ..................................................................42 $0280 - $03FF Reserved ..................................................................................................44 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 2-2 MC9S12B128 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .59 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 6-1 Configuration of HCS12 Core on MC9S12B128 . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 21-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table A-7 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Table A-8 Supply Current Characteristics at 25MHz Bus Frequency. . . . . . . . . . . . . . . . . . .87 Table A-9 Supply Current Characteristics at 16MHz Bus Frequency. . . . . . . . . . . . . . . . . . .88 Table A-10 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table A-11 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Table A-12 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Table A-13 ATD Conversion Performance In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Table A-14 ATD Conversion Performance In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Table A-15 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table A-16 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Table A-17 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Table A-18 VREG_3V3 - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table A-19 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Table A-20 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Table A-21 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Table A-22 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-23 Table A-24 Table A-25 Table A-26 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Expanded Bus Timing Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . .117 13 Device User Guide -- 9S12B128DGV1/D V01.04 14 Device User Guide -- 9S12B128DGV1/D V01.04 Derivative Differences and Document References The Device User Guide provides information about the particular system made up of the MC9S12B128. Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about using the HCS12 D family as a development platform for the HCS12B family refer also to engineering bulletin EB388. Table 0-1 Derivative Differences Generic device MC9S12B128 MC9S12B64P Packages 112LQFP, 80QFP 112LQFP, 80QFP Mask Set L80R L80R Temp Options M, V, C M, V, C Package Codes PV, FU PV, FU Bus Speed Options 25MHz, 16MHz 25MHz, 16MHz Note An errata exists contact Sales office An errata exists contact Sales office MC9S12 B128 (P) C FU 25 Speed Package Option Temperature Option Preliminary Option Device Title Controller Family Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Package Options FU = 80QFP PV = 112LQFP Speed Options 25 = 25MHz bus 16 = 16MHz bus Figure 0-1 Order Partnumber Example The following items should be considered when using a derivative. * Preliminary Option - Preliminary B64 using B128 die The B128 is tested only for B64 functionality. For the preliminary B64 the upper 2K Bytes RAM of the B128 are reserved and should not be used. Also the pages $38-$3B of Flash are reserved and should not be used. * Pins not available in 80 pin QFP package 15 Device User Guide -- 9S12B128DGV1/D V01.04 - Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing a $FF to the pull enable register (PERH at Base+$0264). - Port J[1:0] Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Therefore care must be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at Base+$026C. - Port K Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. Therefor care must be taken not to clear this bit. - Port M[7:6] PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. - Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. - Port S[7:4] PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs. - PAD[15:8] (ATD channels) Out of reset the ATD channels to PAD[15:8] are disabled preventing current flows in the pins. Do not modify the ATD registers for these channels! Document References The Device User Guide provides information about the MC9S12B128 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide. Table 0-2 Document References Versi on Document Order Number HCS12 V1.5 Core User Guide 1.5 HCS12COREUG Clock and Reset Generator (CRG) Block User Guide V04 S12CRGV4/D Oscillator (OSC) Block User Guide V02 S12OSCV2/D Input Capture/Output Compare Timer (TIM_16B8C) Block User Guide V01 S12TIM16B8CV1/D Analog to Digital Converter10 Bit 16 Channel (ATD_10B16C) Block User Guide V03 S12ATD10B16CV3/D User Guide 16 Device User Guide -- 9S12B128DGV1/D V01.04 User Guide Versi on Document Order Number Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D Serial Peripheral Interface (SPI) Block User Guide V03 S12SPIV3/D Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D 128K Byte Flash (FTS128K1) Block User Guide V01 S12FTS128K1V1/D 1K Byte EEPROM (EETS1K) Block User Guide V01 S12EETS1KV1/D Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D Voltage Regulator (VREG3V3) Block User Guide V02 S12VREG3V3V2/D Port Integration Module (PIM_9B128) Block User Guide V01 S12PIM9B128V1/D 17 Device User Guide -- 9S12B128DGV1/D V01.04 18 Device User Guide -- 9S12B128DGV1/D V01.04 Section 1 Introduction 1.1 Overview The MC9S12B128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 128K bytes of Flash EEPROM, 4K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), serial peripheral interface (SPI), an input capture/output compare timer (TIM), 16- channel, 10-bit analog-to-digital converter (ADC), an 8-channel pulse-width modulator (PWM), one CAN 2.0 A, B software compatible module (MSCAN12) and an Inter-IC Bus. The MC9S12B128 has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with Wake-Up capability from STOP or WAIT mode. 1.2 Features * HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing * * - MEBI (Multiplexed External Bus Interface) - MMC (Module Mapping Control) - INT (Interrupt control) - BKP (Breakpoints) - BDM (Background Debug Mode) CRG - Low current Colpitts or - Pierce oscillator, - PLL, - COP watchdog, - Real time interrupt, - Clock monitor 8-bit and 4-bit ports with interrupt functionality 19 Device User Guide -- 9S12B128DGV1/D V01.04 * * * * * 20 - Digital filtering - Programmable rising or falling edge trigger Memory - 128K Flash EEPROM - 1K byte EEPROM - 4K byte RAM Analog-to-Digital Converter - 16-channels for 112 Pin Package, 8 channels for 80 Pin package options - 10-bit resolution - External conversion trigger capability 1M bit per second, CAN 2.0 A, B software compatible module - Five receive and three transmit buffers - Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit - Four separate interrupt channels for Rx, Tx, error and wake-up - Low-pass filter wake-up function - Loop-back for self test operation Input Capture/Output Compare Timer (TIM) - 16-bit Counter with 7-bit Prescaler - 8 programmable input capture or output compare channels - 16-bit Pulse Accumulators - Simple PWM Mode - Modulo Reset of Timer Counter - External Event Counting - Gated Time Accumulation 8 PWM channels - Programmable period and duty cycle - 8-bit 8-channel or 16-bit 4-channel - Separate control for each pulse width and duty cycle - Center-aligned or left-aligned outputs - Programmable clock select logic with a wide range of frequencies - Fast emergency shutdown input - Usable as interrupt inputs Device User Guide -- 9S12B128DGV1/D V01.04 * * * * Serial interfaces - Two asynchronous Serial Communications Interfaces (SCI) - Synchronous Serial Peripheral Interface (SPI) Inter-IC Bus (IIC) - Compatible with I2C Bus standard - Multi-master operation - Software programmable for one of 256 different serial clock frequencies Internal 2.5V Regulator - Supports an input voltage range from 2.97V to 5.5V - Low power mode capability - Includes low voltage reset (LVR) circuitry - Includes low voltage interrupt (LVI) circuitry 112-Pin LQFP or 80 QFP package - I/O lines with 5V input and drive capability - 5V A/D converter inputs - Operation at 32 MHz equivalent to 16 MHz Bus Speed; Option 50MHz equivalent to 25MHz Bus Speed - Development support - Single-wire background debugTM mode (BDM) - On-chip hardware breakpoints 1.3 Modes of Operation User modes * * Normal and Emulation Operating Modes - Normal Single-Chip Mode - Normal Expanded Wide Mode - Normal Expanded Narrow Mode - Emulation Expanded Wide Mode - Emulation Expanded Narrow Mode Special Operating Modes - Special Single-Chip Mode with active Background Debug Mode - Special Test Mode (Motorola use only) 21 Device User Guide -- 9S12B128DGV1/D V01.04 - Special Peripheral Mode (Motorola use only) Low power modes * Stop Mode * Pseudo Stop Mode * Wait Mode 22 Device User Guide -- 9S12B128DGV1/D V01.04 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12B128 device. 23 Device User Guide -- 9S12B128DGV1/D V01.04 Figure 1-1 MC9S12B128 Block Diagram VRH ATD Multiplexed Address/Data Bus PWM DDRA DDRB PTA PTB PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RXD TXD RXD TXD SCI0 Internal Logic 2.5V VDD1,2 VSS1,2 PLL 2.5V VDDPLL VSSPLL PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 I/O Driver 5V VDDA VSSA Voltage Regulator 5V & I/O VDDR VSSR 24 KWJ0 KWJ1 VDDX VSSX A/D Converter 5V & Voltage Regulator Reference IIC Pin Interrupt Logic DDRK AD PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 RxCAN TxCAN DDRM Multiplexed Narrow Bus CAN0 MISO MOSI SCK SS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Multiplexed Wide Bus DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0 SCI1 SPI0 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 PTT TEST DDRT Input Capture Output Compare Timer IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PTP XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS DDRP Periodic Interrupt COP Watchdog Clock Monitor Breakpoints PK0 PK1 PK2 PK3 PK4 PK5 PK7 PTS PTE PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Clock and Reset Generation Module DDRS PLL PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS PPAGE PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 SDA SCL KWJ6 KWJ7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 PTJ XFC VDDPLL VSSPLL EXTAL XTAL RESET CPU12 DDRJ Single-wire Background Debug Module DDRE BKGD Voltage Regulator AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PJ0 PJ1 PJ6 PJ7 PH0 PH1 PH2 PTH VDDR VSSR VREGEN VDD1,2 VSS1,2 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 AD AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 1K Byte EEPROM PTM 4K Byte RAM VRH VRL VDDA VSSA PTK VRL VDDA VSSA DDRH 128K Byte Flash EEPROM PH3 PH4 PH5 PH6 PH7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 ECS Device User Guide -- 9S12B128DGV1/D V01.04 1.5 System Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12B128 after reset. The 1K EEPROM is mapped twice in a 2K address space. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space, and the 1K $0400 - $07FF is hidden by the RAM. Table 1-1 Device Memory Map Address $0000 - $0017 Module CORE (Ports A, B, E, Modes, Inits, Test) Size (Bytes) 24 $0018 Reserved 1 $0019 Voltage Regulator (VREG) 1 $001A - $001B Device ID register (PARTID) 2 $001C - $001F CORE (MEMSIZ, IRQ, HPRIO) 4 $0020 - $0027 8 Reserved $0028 - $002F CORE (Background Debug Mode) 8 $0030 - $0033 CORE (PPAGE, Port K) 4 $0034 - $003F Clock and Reset Generator (PLL, RTI, COP) 12 $0040 - $006F Standard Timer Module16-bit 8-channels (TIM) 48 $0070 - $007F Reserved 16 $0080 - $00AF Analog to Digital Converter 10-bit 16 channels (ATD) 48 $00B0 - $00C7 Reserved $00C8 - $00CF Serial Communications Interface 0 (SCI0) 24 8 $00D0 - $00D7 Serial Communications Interface 1 (SCI1) 8 $00D8 - $00DF Serial Peripheral Interface (SPI0) 8 $00E0 - $00E7 Inter IC Bus (IIC) 8 $00E8 - $00FF Reserved 24 $0100- $010F Flash Control Register 16 $0110 - $011B EEPROM Control Register 12 $011C - $013F Reserved 36 $0140 - $017F Motorola Scalable Can (CAN0) 64 $0180 - $01FF Reserved $0200 - $0227 PWM (Pulse Width Modulator 8 Bit 8 Channel) 40 $0228 - $023F Reserved 24 $0240 - $027F Port Integration Module (PIM) 64 128 $0280 - $03FF Reserved $0000 - $07FF EEPROM array 1k Array mapped twice in the address space 384 2048 $0000 - $0FFF RAM array 4096 $0000 - $3FFF Fixed Flash EEPROM array 16384 $4000 - $7FFF Fixed Flash EEPROM array incl. 0.5K, 1K, 2K or 4K Protected Sector at start 16384 $8000 - $BFFF Flash EEPROM Page Window (eight 16k windows) 16384 Fixed Flash EEPROM array $C000 - $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF 16384 25 Device User Guide -- 9S12B128DGV1/D V01.04 Figure 1-2 MC9S12B128 Memory Map out of Reset $0000 $0000 $0400 $03FF $0800 $1000 REGISTERS (Mappable to any 2K Boundary within the first 32K) $0000 1K Bytes EEPROM $07FF (Mappable to any 2K Boundary; 1K mapped two times in the 2K address space) $0000 4K Bytes RAM (Mappable to any 4K Boundary) EXTERN EXTERN $0FFF $0000 16K Fixed Flash Page $3D = 61 $3FFF (This is dependant on the state of the ROMHM bit) $0000-$0FFF hidden $4000 16K Fixed Flash Page $3E = 62 $4000 (This is dependant on the state of the ROMHM bit) $7FFF $8000 $8000 16K Page Window 8 x 16K Flash EEPROM pages EXTERN $BFFF $C000 $C000 16K Fixed Flash Page $3F = 63 $FFFF $FF00 BDM (if active) $FF00 VECTORS VECTORS VECTORS EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP $FFFF 26 $FFFF Device User Guide -- 9S12B128DGV1/D V01.04 Figure 1-3 MC9S12B64P Memory Map out of Reset $0000 $0000 $0400 $03FF $0800 $1000 EXTERN EXTERN REGISTERS (Mappable to any 2K Boundary within the first 32K) $0000 1K Bytes EEPROM $07FF (Mappable to any 2K Boundary; 1K mapped two times in the 2K address space) $0000 4K Bytes RAM $0FFF $0000 (Mappable to any 4K Boundary) upper 2K of RAM are reserved 16K Fixed Flash Page $3D = 61 $3FFF (This is dependant on the state of the ROMHM bit) $0000-$0FFF hidden $4000 16K Fixed Flash Page $3E = 62 $4000 (This is dependant on the state of the ROMHM bit) $7FFF $8000 $8000 EXTERN $BFFF 16K Page Window 8 x 16K Flash EEPROM pages pages $38-$3B of Flash EEPROM are reserved $C000 $C000 16K Fixed Flash Page $3F = 63 $FFFF $FF00 BDM (if active) $FF00 VECTORS VECTORS VECTORS EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP $FFFF $FFFF 27 Device User Guide -- 9S12B128DGV1/D V01.04 1.5.1 Detailed Register Map $0000 - $000F Address Name $0000 PORTA $0001 PORTB $0002 DDRA $0003 DDRB $0004 Reserved $0005 Reserved $0006 Reserved $0007 Reserved $0008 PORTE $0009 DDRE $000A PEAR $000B MODE $000C PUCR $000D RDRIV $000E EBICTL $000F Reserved $0010 - $0014 Address 28 Name $0010 INITRM $0011 INITRG $0012 INITEE $0013 MISC $0014 Reserved MEBI map 1 of 3 (Core User Guide) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 Bit 1 Bit 0 6 5 4 3 Bit 2 0 0 PIPOE NECLK LSTRE RDWE 0 0 EMK EME PUPBE PUPAE RDPB RDPA 0 MODB MODA 0 0 0 0 0 0 0 0 0 IVIS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 PUPEE RDPE ESTR MMC map 1 of 4 (Core User Guide) Bit 7 Read: RAM15 Write: Read: 0 Write: Read: EE15 Write: Read: 0 Write: Read: 0 Write: Bit 6 Bit 5 Bit 4 Bit 3 RAM14 RAM13 RAM12 RAM11 REG14 REG13 REG12 REG11 EE14 EE13 EE12 EE11 0 0 0 0 0 0 RAMHAL 0 EEON EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0 Device User Guide -- 9S12B128DGV1/D V01.04 $0015 - $0016 Address INT map 1 of 2 (Core User Guide) Name $0015 ITCR $0016 ITEST Read: Write: Read: Write: $0017 - $0017 Address $0017 Read: Write: $0018 - $0018 Address $0018 Read: Write: $0019 - $0019 Address $0019 Read: Write: $001A - $001B Address PARTIDH $001B PARTIDL Read: Write: Read: Write: $001C - $001D Address Name $001C MEMSIZ0 $001D MEMSIZ1 $001E Bit 1 Bit 0 WRINT ADR3 ADR2 ADR1 ADR0 INT8 INT6 INT4 INT2 INT0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 0 Bit 6 0 Bit 3 0 Bit 2 LVDS Bit 1 Bit 0 LVIE LVIF Bit 5 0 Bit 4 0 Bit 7 ID15 Bit 6 ID14 Bit 5 ID13 Bit 4 ID12 Bit 3 ID11 Bit 2 ID10 Bit 1 ID9 Bit 0 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0 MEBI map 2 of 3 (Core User Guide) Name INTCR INTA Bit 2 MMC map 3 of 4 (Core and Device User Guide, Table 1-4) $001E - $001E Address INTC Bit 3 Miscellaneous Peripherals (Device User Guide, Table 1-3) Name $001A INTE Bit 4 VREG3V3 (Voltage Regulator) Name VREGCTRL Bit 5 0 Reserved Name Reserved Bit 6 0 MMC map 2 of 4 (Core User Guide) Name Reserved Bit 7 0 Read: Write: Bit 7 Bit 6 IRQE IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 29 Device User Guide -- 9S12B128DGV1/D V01.04 $001F - $001F Address $001F INT map 2 of 2 (Core User Guide) Name HPRIO Read: Write: $0020 - $0027 Address $0020 $0027 Read: Write: $0028 - $002F Address Name $0028 BKPCT0 $0029 BKPCT1 $002A BKP0X $002B BKP0H $002C BKP0L $002D BKP1X $002E BKP1H $002F BKP1L PPAGE $0031 Reserved Read: Write: Read: Write: 30 PORTK $0033 DDRK Bit 2 Bit 1 PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 0 Bit 6 0 Bit 0 0 Bit 7 0 Bit 6 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 MEBI map 3 of 3 (Core User Guide) Name $0032 Bit 3 MMC map 4 of 4 (Core User Guide) $0032 - $0033 Address Bit 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Name $0030 Bit 5 BKP (Core User Guide) $0030 - $0031 Address Bit 6 Reserved Name Reserved Bit 7 Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Device User Guide -- 9S12B128DGV1/D V01.04 $0034 - $003F Address Name $0034 SYNR $0035 REFDV $0036 CTFLG test only $0037 CRGFLG $0038 CRGINT $0039 CLKSEL $003A PLLCTL $003B RTICTL $003C COPCTL $003D $003E $003F FORBYP test only CTCTL test only ARMCOP $0040 - $006F Address Name $0040 TIOS $0041 CFORC $0042 OC7M $0043 OC7D $0044 TCNT (hi) $0045 TCNT (lo) $0046 TSCR1 $0047 TTOV $0048 TCTL1 $0049 TCTL2 CRG (Clock and Reset Generator) Bit 7 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 7 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 0 0 PORF LVRF LOCKIF 0 0 PSTP LOCKIE SYSWAI ROAWAI REFDV3 REFDV2 REFDV1 REFDV0 0 0 LOCK TRACK 0 0 PLLWAI CWAI RTIWAI COPWAI PRE PCE SCME RTR2 RTR1 RTR0 CR2 CR1 CR0 0 0 SCMIF SCMIE 0 SCM 0 PLLON AUTO ACQ RTR6 RTR5 RTR4 RTR3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 RSBCK TIM (Timer 16 Bit 8 Channels) Bit 7 Read: IOS7 Write: 0 Read: Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Bit 7 Read: Write: Read: TEN Write: Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 FOC6 0 FOC5 0 FOC4 0 FOC3 0 FOC2 0 FOC1 0 FOC0 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 TSWAI TSFRZ TFFCA 0 0 0 0 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 OL7 OM6 OL6 OM5 OL5 OM4 OL4 OL3 OM2 OL2 OM1 OL1 OM0 OL0 31 Device User Guide -- 9S12B128DGV1/D V01.04 32 Address Name $004A TCTL3 $004B TCTL4 $004C TIE $004D TSCR2 $004E TFLG1 $004F TFLG2 $0050 TC0 (hi) $0051 TC0 (lo) $0052 TC1 (hi) $0053 TC1 (lo) $0054 TC2 (hi) $0055 TC2 (lo) $0056 TC3 (hi) $0057 TC3 (lo) $0058 TC4 (hi) $0059 TC4 (lo) $005A TC5 (hi) $005B TC5 (lo) $005C TC6 (hi) $005D TC6 (lo) $005E TC7 (hi) $005F TC7 (lo) $0060 PACTL $0061 PAFLG Bit 7 Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: 0 Read: Write: Read: 0 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A C6I C5I C4I C3I C2I C1I C0I 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 PAOVF PAIF Device User Guide -- 9S12B128DGV1/D V01.04 Address Name $0062 PACNT (hi) $0063 PACNT (lo) $0064$006F Reserved Read: Write: Read: Write: Read: Write: $0070 - $007F $0070 - $007F Reserved $0080 - $00AF Address Name $0080 ATDCTL0 $0081 ATDCTL1 $0082 ATDCTL2 $0083 ATDCTL3 $0084 ATDCTL4 $0085 ATDCTL5 $0086 ATDSTAT0 $0087 Reserved $0088 ATDTEST0 $0089 ATDTEST1 $008A ATDSTAT2 $008B ATDSTAT1 $008C ATDDIEN0 $008D ATDDIEN1 $008E PORTAD0 $008F PORTAD1 $0090 ATDDR0H $0091 ATDDR0L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Read: Write: 0 ATD (Analog to Digital Converter 10 Bit 16 Channel) Bit 7 Read: 0 Write: Read: ETRIGSEL Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF15 Write: Read: CCF7 Write: Read: IEN15 Write: Read: IEN7 Write: Read: PTAD15 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 WRAP3 WRAP2 WRAP1 WRAP0 0 0 0 ETRIGC H3 ETRIGC H2 ETRIGC H1 ETRIG ASCIE ETRIGC H0 ASCIF AFFC AWAI S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 DSGN SCAN MULT CD CC CB CA ETORF FIFOR CC3 CC2 CC1 CC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 14 13 12 11 10 9 Bit8 Bit6 0 0 0 0 0 0 0 ETRIGLE ETRIGP SC 33 Device User Guide -- 9S12B128DGV1/D V01.04 $0080 - $00AF Address 34 ATD (Analog to Digital Converter 10 Bit 16 Channel) Name $0092 ATDDR1H $0093 ATDDR1L $0094 ATDDR2H $0095 ATDDR2L $0096 ATDDR3H $0097 ATDDR3L $0098 ATDDR4H $0099 ATDDR4L $009A ATDDR5H $009B ATDDR5L $009C ATDDR6H $009D ATDDR6L $009E ATDDR7H $009F ATDDR7L $00A0 ATDDR8H $00A1 ATDDR8L $00A2 ATDDR9H $00A3 ATDDR9L $00A4 ATDDR10H $00A5 ATDDR10L $00A6 ATDDR11H $00A7 ATDDR11L $00A8 ATDDR12H $00A9 ATDDR12L $00AA ATDDR13H Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit15 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit 0 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Device User Guide -- 9S12B128DGV1/D V01.04 $0080 - $00AF Address ATD (Analog to Digital Converter 10 Bit 16 Channel) Name $00AB ATDDR13L $00AC ATDDR14H $00AD ATDDR14L $00AE ATDDR15H $00AF ATDDR15L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $00B0 - $00C7 $00B0 - $00C7 Reserved $00C8 - $00CF Address Name $00C8 SCI0BDH $00C9 SCI0BDL $00CA SCI0CR1 $00CB SCI0CR2 $00CC SCI0SR1 $00CD SCI0SR2 $00CE SCI0DRH $00CF SCI0DRL $00D0 - $00D7 Address Name $00D0 SCI1BDH $00D1 SCI1BDL $00D2 SCI1CR1 $00D3 SCI1CR2 Bit 7 Bit7 Bit 6 Bit6 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Read: Write: 0 0 SCI0 (Asynchronous Serial Interface) Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 RSRC M WAKE ILT PE PT RIE ILIE TE RE RWU SBK RDRF IDLE OR NF FE PF 0 0 0 BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF SCI1 (Asynchronous Serial Interface) Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Bit 5 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 RSRC M WAKE ILT PE PT RIE ILIE TE RE RWU SBK 35 Device User Guide -- 9S12B128DGV1/D V01.04 $00D0 - $00D7 Address SCI1 (Asynchronous Serial Interface) Name $00D4 SCI1SR1 $00D5 SCI1SR2 $00D6 SCI1DRH $00D7 SCI1DRL Read: Write: Read: Write: Read: Write: Read: Write: $00D8 - $00DF Address SPI0CR1 $00D9 SPI0CR2 $00DA SPI0BR $00DB SPI0SR $00DC Reserved $00DD SPI0DR $00DE Reserved $00DF Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $00E0 - $00E7 Address 36 IBAD $00E1 IBFD $00E2 IBCR $00E3 IBSR $00E4 IBDR Bit 5 RDRF Bit 4 IDLE Bit 3 OR 0 0 0 0 0 0 0 R5 T5 R4 T4 R8 R7 T7 T8 R6 T6 Bit 2 NF Bit 1 FE Bit 0 PF BRK13 TXDIR 0 0 0 0 R3 T3 R2 T2 R1 T1 R0 T0 RAF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 Bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0 0 0 MODFEN BIDIROE 0 0 IIC (Inter IC Bus) Name $00E0 Bit 6 TC SPI0 (Serial Peripheral Interface) Name $00D8 Bit 7 TDRE Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBEN IBIE MS/SL TX/RX TXAK 0 TCF IAAS IBB 0 0 RSTA SRW D7 D6 D5 D3 D2 IBAL D4 IBIF D1 IBC0 IBSWAI RXAK D0 Device User Guide -- 9S12B128DGV1/D V01.04 $00E0 - $00E7 Address IIC (Inter IC Bus) Name $00E5 Reserved $00E6 Reserved $00E7 Reserved Read: Write: Read: Write: Read: Write: $00E8 - $00FF Address $00E8 $00FF $0100 - $010F Address Name $0100 FCLKDIV $0101 FSEC $0102 Reserved $0103 FCNFG $0104 FPROT $0105 FSTAT $0106 FCMD $0107 Reserved $0108 FADDRHI $0109 FADDRLO $010A FDATAHI $010B FDATALO $010C $010F Reserved Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 3 Bit 2 Bit 1 Bit 0 FDIV3 FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 0 0 0 0 0 0 0 0 FPHS0 FPLDIS FPLS1 FPLS0 0 0 Reserved Name Reserved Bit 7 0 Read: Write: Bit 7 0 Flash Control Register (fts128k1) Bit 7 Bit 6 Bit 5 Bit 4 Read: FDIVLD PRDIV8 FDIV5 FDIV4 Write: Read: KEYEN1 KEYEN0 NV5 NV4 Write: Read: 0 0 0 0 Write: Read: 0 CBEIE CCIE KEYACC Write: Read: FPOPEN NV6 FPHDIS FPHS1 Write: Read: CCIF CBEIF PVIOL ACCERR Write: Read: 0 0 CMDB6 CMDB5 Write: Read: 0 0 0 0 Write: Read: Bit 15 Bit 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: Bit 15 14 13 12 Write: Read: Bit 7 6 5 4 Write: Read: 0 0 0 0 Write: 0 0 BLANK CMDB2 0 CMDB0 0 0 0 0 11 10 9 Bit 8 3 2 1 Bit 0 11 10 9 Bit 8 3 2 1 Bit 0 0 0 0 0 37 Device User Guide -- 9S12B128DGV1/D V01.04 $0110 - $011B Address Name $0110 ECLKDIV $0111 Reserved $0112 Reserved $0113 ECNFG $0114 EPROT $0115 ESTAT $0116 ECMD $0117 Reserved $0118 EADDRHI $0119 EADDRLO $011A EDATAHI $011B EDATALO EEPROM Control Register (eets1k) Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: NV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit7 6 Write: Read: Bit15 14 Write: Read: Bit7 6 Write: $011C - $013F Address $011C $013F $0140 - $017F Address 38 Name $0140 CAN0CTL0 $0141 CAN0CTL1 $0142 CAN0BTR0 $0143 CAN0BTR1 $0144 CAN0RFLG $0145 CAN0RIER $0146 CAN0TFLG Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NV5 NV4 EPDIS EP2 EP1 EP0 PVIOL ACCERR 0 BLANK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 Bit0 13 12 11 10 9 Bit8 5 4 3 2 1 Bit0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 CMDB5 CMDB2 0 CMDB0 0 Bit8 Reserved Name Reserved Bit 5 Read: Write: Bit 7 0 Bit 6 0 CAN0 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Write: Read: 0 SLPAK INITAK CANE CLKSRC LOOPB LISTEN WUPM Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 Write: Device User Guide -- 9S12B128DGV1/D V01.04 $0140 - $017F Address Name $0147 CAN0TIER $0148 CAN0TARQ $0149 CAN0TAAK $014A CAN0TBSEL $014B CAN0IDAC $014C Reserved $014D Reserved $014E CAN0RXERR $014F CAN0TXERR $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F CAN0IDAR0 CAN0IDAR3 CAN0IDMR0 CAN0IDMR3 CAN0IDAR4 CAN0IDAR7 CAN0IDMR4 CAN0IDMR7 CAN0RXFG CAN0TXFG CAN0 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Read: 0 0 0 0 0 TXEIE2 TXEIE1 Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 Write: Read: 0 0 0 0 0 TX2 TX1 Write: Read: 0 0 0 IDHIT2 IDHIT1 IDAM1 IDAM0 Write: Read: 0 0 0 0 0 0 0 Write: Read: 0 0 0 0 0 0 0 Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-2 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-2 Write: Bit 0 TXEIE0 ABTRQ0 ABTAK0 TX0 IDHIT0 0 0 RXERR0 TXERR0 AC0 AM0 AC0 AM0 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address $0164$016B Name Extended ID Standard ID CAN0RIDR0 Extended ID Standard ID CAN0RIDR1 Extended ID Standard ID CAN0RIDR2 Extended ID Standard ID CAN0RIDR3 CAN0RDSR0 CAN0RDSR7 $016C CAN0RDLR $0160 $0161 $0162 $0163 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: Write: Bit 7 ID28 ID10 Bit 6 ID27 ID9 Bit 5 ID26 ID8 Bit 4 ID25 ID7 Bit 3 ID24 ID6 Bit 2 ID23 ID5 Bit 1 ID22 ID4 Bit 0 ID21 ID3 ID20 ID2 ID19 ID1 ID18 ID0 SRR=1 RTR IDE=1 IDE=0 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 39 Device User Guide -- 9S12B128DGV1/D V01.04 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name $016D Reserved $016E CAN0RTSRH $016F CAN0RTSRL $0170 $0171 $0172 $0173 Extended ID CAN0TIDR0 Standard ID Extended ID CAN0TIDR1 Standard ID Extended ID CAN0TIDR2 Standard ID Extended ID CAN0TIDR3 Standard ID $0174$017B CAN0TDSR0 CAN0TDSR7 $017C CAN0TDLR $017D CAN0TTBPR $017E CAN0TTSRH $017F CAN0TTSRL Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $0180 - $01FF Address $0180 $01FF $0200 - $0227 40 Address Name $0200 PWME $0201 PWMPOL $0202 PWMCLK Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 ID2 ID1 ID0 RTR IDE=0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Reserved Name Reserved Bit 7 Read: Write: Bit 7 0 Bit 6 0 PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: PWME7 Write: Read: PPOL7 Write: Read: PCLK7 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 Device User Guide -- 9S12B128DGV1/D V01.04 $0200 - $0227 Address $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $020F $0210 $0211 $0212 $0213 $0214 $0215 $0216 $0217 $0218 $0219 $021A $021B Name PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: 0 PWMPRCLK Write: Read: PWMCAE CAE7 Write: Read: PWMCTL CON67 Write: Read: 0 PWMTST Test Only Write: 0 PWMPRSC Read: Test Only Write: Read: PWMSCLA Bit 7 Write: Read: PWMSCLB Bit 7 Write: 0 PWMSCNTA Read: Test Only Write: 0 PWMSCNTB Read: Test Only Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Read: Bit 7 PWMCNT3 Write: 0 Read: Bit 7 PWMCNT4 Write: 0 Read: Bit 7 PWMCNT5 Write: 0 Read: Bit 7 PWMCNT6 Write: 0 Read: Bit 7 PWMCNT7 Write: 0 Read: PWMPER0 Bit 7 Write: Read: PWMPER1 Bit 7 Write: Read: PWMPER2 Bit 7 Write: Read: PWMPER3 Bit 7 Write: Read: PWMPER4 Bit 7 Write: Read: PWMPER5 Bit 7 Write: Read: PWMPER6 Bit 7 Write: Read: PWMPER7 Bit 7 Write: Bit 6 Bit 5 Bit 4 PCKB2 PCKB1 PCKB0 CAE6 CAE5 CAE4 CON45 CON23 0 Bit 3 0 Bit 2 Bit 1 Bit 0 PCKA2 PCKA1 PCKA0 CAE3 CAE2 CAE1 CAE0 CON01 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 41 Device User Guide -- 9S12B128DGV1/D V01.04 $0200 - $0227 Address Name $021C PWMDTY0 $021D PWMDTY1 $021E PWMDTY2 $021F PWMDTY3 $0220 PWMDTY4 $0221 PWMDTY5 $0222 PWMDTY6 $0223 PWMDTY7 $0224 PWMSDN $0225$0227 Reserved PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: $0228 - $023F Address $0228 $023F $0240 - $027F Address 42 Name $0240 PTT $0241 PTIT $0242 DDRT $0243 RDRT $0244 PERT $0245 PPST $0246 Reserved $0247 Reserved $0248 PTS Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 0 PWM7IN PWMIE 0 PWMRSTRT PWMLVL PWM7INL PWM7ENA 0 0 0 0 0 0 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Reserved Name Reserved Bit 6 Read: Write: Bit 7 0 PIM (Port Integration Module) Bit 7 Read: PTT7 Write: Read: PTIT7 Write: Read: DDRT7 Write: Read: RDRT7 Write: Read: PERT7 Write: Read: PPST7 Write: Read: 0 Write: Read: 0 Write: Read: PTS7 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Device User Guide -- 9S12B128DGV1/D V01.04 $0240 - $027F Address PIM (Port Integration Module) Name $0249 PTIS $024A DDRS $024B RDRS $024C PERS $024D PPSS $024E WOMS $024F Reserved $0250 PTM $0251 PTIM $0252 DDRM $0253 RDRM $0254 PERM $0255 PPSM $0256 WOMM $0257 MODRR $0258 PTP $0259 PTIP $025A DDRP $025B RDRP $025C PERP $025D PPSP $025E PIEP $025F PIFP $0260 PTH $0261 PTIH Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 PTIS7 Bit 6 PTIS6 Bit 5 PTIS5 Bit 4 PTIS4 Bit 3 PTIS3 Bit 2 PTIS2 Bit 1 PTIS1 Bit 0 PTIS0 DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 0 0 0 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 MODRR4 43 Device User Guide -- 9S12B128DGV1/D V01.04 $0240 - $027F Address PIM (Port Integration Module) Name $0262 DDRH $0263 RDRH $0264 PERH $0265 PPSH $0266 PIEH $0267 PIFH $0268 PTJ $0269 PTIJ $026A DDRJ $026B RDRJ $026C PERJ $026D PPSJ $026E PIEJ $026F PIFJ $0270 $027F Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $0280 - $03FF Address $0280 $03FF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 PTJ7 PTJ6 0 0 0 0 PTJ1 PTJ0 PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0 DDRJ7 DDRJ7 0 0 0 0 DDRJ1 DDRJ0 RDRJ7 RDRJ6 0 0 0 0 RDRJ1 RDRJ0 PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 PPSJ7 PPSJ6 0 0 0 0 PPSJ1 PPSJ0 PIEJ7 PIEJ6 0 0 0 0 PIEJ1 PIEJ0 PIFJ7 PIFJ6 0 0 0 0 PIFJ1 PIFJ0 0 0 0 0 0 0 0 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Reserved Name Reserved Bit 7 Read: Write: Bit 7 0 1.6 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID number. 44 Device User Guide -- 9S12B128DGV1/D V01.04 Table 1-3 Assigned Part ID Numbers Device Mask Set Number MC9S12B128 0L80R Part ID1 $2100 NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to section Module Mapping and Control (MMC) of HCS12 Core User Guide for further details. Table 1-4 Memory size registers Register name MEMSIZ0 MEMSIZ1 Value $11 $C0 45 Device User Guide -- 9S12B128DGV1/D V01.04 Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device. 46 Device User Guide -- 9S12B128DGV1/D V01.04 2.1 System Pinout The MC9S12B128 is available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments. MC9S12B128 112LQFP 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP4/KWP4/PWM4 PP5/KPW5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 PM6 PM7 VSSA VRL Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12B128 Signals shown in Bold are not available on the 80 Pin Package 47 Device User Guide -- 9S12B128DGV1/D V01.04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12B128 80 QFP ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM0/RxCAN0 PM1/TxCAN0 PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6/SDA PJ7/KWJ7/SCL VREGEN PS3/TxD1 PX2/RxD1 PS1/TxD0 PS0/RxD0 VSSA VRL Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12B128 48 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Device User Guide -- 9S12B128DGV1/D V01.04 2.1.1 Signal Properties Summary Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. Table 2-1 Signal Properties Pin Name Pin Name Powered Function Function by 3 4 Pin Name Function1 Pin Name Function2 EXTAL -- -- -- XTAL -- -- -- Internal Pull Resistor CTRL Description Reset State VDDPLL Oscillator Pins RESET -- -- -- VDDR TEST -- -- -- N.A. VREGEN -- -- -- VDDX XFC -- -- -- VDDPLL BKGD TAGHI MODC -- VDDR PAD[15:8] AN[15:8] -- -- PAD[07:00] AN[07:00] -- -- PA[7:0] ADDR[15:8]/ DATA[15:8] -- -- PB[7:0] ADDR[7:0]/ DATA[7:0] -- -- PUCR/ PUPBE PE7 NOACC XCLKS -- PUCR/ PUPEE PE6 IPIPE1 MODB -- PE5 IPIPE0 MODA -- PE4 ECLK -- -- PE3 LSTRB TAGLO -- PE2 R/W -- -- PE1 IRQ -- -- Port E Input, Maskable Interrupt PE0 XIRQ -- -- Port E Input, Non Maskable Interrupt VDDA None None External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Always Up None PUCR/ PUPAE Up None Background Debug, Tag High, Mode Input Port AD Inputs, Analog Inputs AN[15:8] of ATD Port AD Inputs, Analog Inputs AN[7:0] of ATD Port A I/O, Multiplexed Address/Data Disabled Port B I/O, Multiplexed Address/Data Up While RESET pin is low: Down Port E I/O, Access, Clock Select Port E I/O, Pipe Status, Mode Input Port E I/O, Pipe Status, Mode Input Port E I/O, Bus Clock Output Port E I/O, Byte Strobe, Tag Low VDDR PUCR/ PUPEE Up Port E I/O, R/W in expanded modes PH7 KWH7 -- -- Port H I/O, Interrupt PH6 KWH6 -- -- Port H I/O, Interrupt PH5 KWH5 -- -- PH4 KWH4 -- -- PH3 KWH3 -- -- PH2 KWH2 -- -- Port H I/O, Interrupt PERH/ PPSH Disabled Port H I/O, Interrupt Port H I/O, Interrupt Port H I/O, Interrupt PH1 KWH1 -- -- Port H I/O, Interrupt PH0 KWH0 -- -- Port H I/O, Interrupt PJ7 KWJ7 SCL -- PJ6 KWJ6 SDA -- PJ[1:0] KWJ[1:0] -- -- Port J I/O, Interrupt,SCL of IIC, VDDX PERJ/ PPSJ Up Port J I/O, Interrupt,SDA of IIC, Port J I/O, Interrupts 49 Device User Guide -- 9S12B128DGV1/D V01.04 Pin Name Pin Name Powered Function Function by 3 4 Pin Name Function1 Pin Name Function2 PK7 ECS ROMCTL -- PK[5:0] XADDR[19:14] -- -- Internal Pull Resistor CTRL Reset State PUCR/ PUPKE Up Description Port K I/O, Emulation Chip Select, ROM On Enable Port K I/O, Extended Addresses PM7 -- -- -- Port M I/O PM6 -- -- -- Port M I/O PM5 -- SCK -- Port M I/O, SCK of SPI0 PM4 -- MOSI -- PM3 -- SS0 -- PM2 -- MISO0 -- Port M I/O, MOSI of SPI0 PERM/ PPSM Port M I/O, SS of SPI0 Port M I/O, MISO of SPI0 PM1 TXCAN0 -- -- Port M I/O, TX of CAN0 PM0 RXCAN0 -- -- Port M I/O, RX of CAN0 PP7 KWP7 PWM7 -- Disabled Port P I/O, Interrupt, Channel 7 of PWM PP6 KWP6 PWM6 -- PP5 KWP5 PWM5 -- PP4 KWP4 PWM4 -- PP3 KWP3 PWM3 -- Port P I/O, Interrupt, PWM Channel 3 PP2 KWP2 PWM2 -- Port P I/O, Interrupt, PWM Channel 2 PP1 KWP1 PWM1 -- Port P I/O, Interrupt, PWM Channel 1 PP0 KWP0 PWM0 -- Port P I/O, Interrupt, PWM Channel 0 PS7 SS0 -- -- Port S I/O, SS of SPI0 PS6 SCK0 -- -- Port S I/O, SCK of SPI0 PS5 MOSI0 -- -- Port S I/O, MOSI of SPI0 PS4 MISO0 -- -- PS3 TXD1 -- -- PS2 RXD1 -- -- Port S I/O, RXD of SCI1 PS1 TXD0 -- -- Port S I/O, TXD of SCI0 PS0 RXD0 -- -- PT[7:0] IOC[7:0] -- Port P I/O, Interrupt, PWM Channel 6 VDDX -- Port P I/O, Interrupt, PWM Channel 5 PERP/ PPSP PERS/ PPSS Port P I/O, Interrupt, PWM Channel 4 Up Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI0 PERT/ PPST Disabled Port T I/O, Timer channels 2.2 Detailed Signal Descriptions 2.2.1 EXTAL, XTAL -- Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 50 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.2 RESET -- External Reset Pin An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. 2.2.3 TEST -- Test Pin This input only pin is reserved for test. NOTE: The TEST pin must be tied to VSS in all applications. 2.2.4 VREGEN -- Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator. 2.2.5 XFC -- PLL Loop Filter Pin PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. XFC R0 MCU CP CS VDDPLL VDDPLL Figure 2-3 PLL Loop Filter Connections 2.2.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device. 2.2.7 PAD[15:0] / AN[15:0] -- Port AD Input Pins ATD PAD15 - PAD0 are general purpose input pins and analog inputs AN[15:0] of the analog to digital converter ATD. 51 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.8 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.2.9 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.2.10 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL. EXTAL CDC * MCU C1 Crystal or ceramic resonator XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. Figure 2-4 Colpitts Oscillator Connections (PE7=1) 52 Device User Guide -- 9S12B128DGV1/D V01.04 EXTAL C3 MCU XTAL Crystal or ceramic resonator RB RS* C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer's data. Figure 2-5 Pierce Oscillator Connections (PE7=0) EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) MCU XTAL not connected Figure 2-6 External Clock Connections (PE7=0) 2.2.11 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. 2.2.12 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. 2.2.13 PE4 / ECLK -- Port E I/O Pin 4 PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference. 53 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.14 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue. 2.2.15 PE2 / R/W -- Port E I/O Pin 2 PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus. 2.2.16 PE1 / IRQ -- Port E Input Pin 1 PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. 2.2.17 PE0 / XIRQ -- Port E Input Pin 0 PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. 2.2.18 PH7 / KWH7 -- Port H I/O Pin 7 PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.19 PH6 / KWH6 -- Port H I/O Pin 6 PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.20 PH5 / KWH5 -- Port H I/O Pin 5 PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.21 PH4 / KWH4 -- Port H I/O Pin 2 PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.22 PH3 / KWH3 -- Port H I/O Pin 3 PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 54 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.23 PH2 / KWH2 -- Port H I/O Pin 2 PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.24 PH1 / KWH1 -- Port H I/O Pin 1 PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.25 PH0 / KWH0 -- Port H I/O Pin 0 PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.26 PJ7 / KWJ7 / SCL -- Port J I/O Pins 7 PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module. 2.2.27 PJ6 / KWJ6 / SDA -- Port J I/O Pins 6 PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC module. 2.2.28 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.2.29 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). While configurating MCU expanded modes this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. For a complete list of modes refer to 4.2 Chip Configuration Summary. 2.2.30 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus. 55 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.31 PM7 -- Port M I/O Pin 7 PM7 is a general purpose input or output pin. 2.2.32 PM6 -- Port M I/O Pin 6 PM6 is a general purpose input or output pin. 2.2.33 PM5 / SCK0 -- Port M I/O Pin 5 PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). 2.2.34 PM4 / MOSI0 -- Port M I/O Pin 4 PM4 is a general purpose input or output pin. It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). 2.2.35 PM3 / SS0 -- Port M I/O Pin 3 PM3 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2.2.36 PM2 / MISO0 -- Port M I/O Pin 2 PM2 is a general purpose input or output pin. It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0). 2.2.37 PM1 / TXCAN0 -- Port M I/O Pin 1 PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). 2.2.38 PM0 / RXCAN0 -- Port M I/O Pin 0 PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). 2.2.39 PP7 / KWP7 / PWM7 -- Port P I/O Pin 7 PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. 56 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.40 PP6 / KWP6 / PWM6 -- Port P I/O Pin 6 PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. 2.2.41 PP5 / KWP5 / PWM5 -- Port P I/O Pin 5 PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. 2.2.42 PP4 / KWP4 / PWM4 -- Port P I/O Pin 4 PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. 2.2.43 PP3 / KWP3 / PWM3 -- Port P I/O Pin 3 PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. 2.2.44 PP2 / KWP2 / PWM2 -- Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. 2.2.45 PP1 / KWP1 / PWM1 -- Port P I/O Pin 1 PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. 2.2.46 PP0 / KWP0 / PWM0 -- Port P I/O Pin 0 PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. 2.2.47 PS7 / SS0 -- Port S I/O Pin 7 PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2.2.48 PS6 / SCK0 -- Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). 57 Device User Guide -- 9S12B128DGV1/D V01.04 2.2.49 PS5 / MOSI0 -- Port S I/O Pin 5 PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0). 2.2.50 PS4 / MISO0 -- Port S I/O Pin 4 PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0). 2.2.51 PS3 / TXD1 -- Port S I/O Pin 3 PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1). 2.2.52 PS2 / RXD1 -- Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). 2.2.53 PS1 / TXD0 -- Port S I/O Pin 1 PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0). 2.2.54 PS0 / RXD0 -- Port S I/O Pin 0 PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0). 2.2.55 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Timer (TIM). 2.3 Power Supply Pins MC9S12B128 power and ground pins are described below. NOTE: 58 All VSS pins must be connected together in the application. Device User Guide -- 9S12B128DGV1/D V01.04 Table 2-2 MC9S12B128 Power and Ground Connection Summary Pin Number 112-pin QFP Nominal Voltage VDD1, 2 13, 65 2.5V VSS1, 2 14, 66 0V VDDR 41 5.0V VSSR 40 0V VDDX 107 5.0V VSSX 106 0V VDDA 83 5.0V VSSA 86 0V VRL 85 0V VRH 84 5.0V VDDPLL 43 2.5V VSSPLL 45 0V VREGEN 97 5.0V Mnemonic Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable 2.3.1 VDDX, VSSX -- Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDX and VSSX are the supplies for Ports J, K, M, P, T and S. 2.3.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDR and VSSR are the supplies for Ports A, B, E and H. 59 Device User Guide -- 9S12B128DGV1/D V01.04 2.3.3 VDD1, VDD2, VSS1, VSS2 -- Core Power Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors. 2.3.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the two analog to digital converters. It also provides the reference for the internal voltage regulator. This allows the supply voltage to ATD0/ATD1 and the reference voltage to be bypassed independently. 2.3.5 VRH, VRL -- ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 2.3.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator. NOTE: No load allowed except for bypass capacitors. 2.3.7 VREGEN -- On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. 60 Device User Guide -- 9S12B128DGV1/D V01.04 Section 3 System Clock Description The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. BDM S12_CORE core clock Flash RAM EEPROM TIM EXTAL ATD CRG bus clock PWM SCI0, SCI1 oscillator clock XTAL SPI0 CAN0 PIM IIC Figure 3-1 Clock Connections 61 Device User Guide -- 9S12B128DGV1/D V01.04 Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12B128. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device. 4.2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection BKGD = MODC PE6 = MODB PE5 = MODA PK7 = ROMCTL ROMON Bit 0 0 0 X 1 0 0 1 0 1 1 0 0 1 0 X 0 0 1 1 0 X 1 0 0 1 1 X 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed For further explanation on the modes refer to the Core User Guide. Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 1 62 Description Colpitts Oscillator selected Device User Guide -- 9S12B128DGV1/D V01.04 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 0 Description Pierce Oscillator/external clock selected Table 4-3 Voltage Regulator VREGEN VREGEN Description 1 Internal Voltage Regulator enabled 0 Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * Protection of the contents of FLASH, * Protection of the contents of EEPROM, * Operation in single-chip mode, * Operation from external memory with internal FLASH and EEPROM disabled. The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM. 4.3.1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration. 4.3.2 Operation of the Secured Microcontroller 4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 63 Device User Guide -- 9S12B128DGV1/D V01.04 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. 4.3.3 Unsecuring the Microcontroller In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 Low Power Modes The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG). 4.4.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts. 4.4.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter. 4.4.3 Wait This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks. 64 Device User Guide -- 9S12B128DGV1/D V01.04 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. 65 Device User Guide -- 9S12B128DGV1/D V01.04 Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations Interrupt Source CCR Mask Local Enable HPRIO Value to Elevate $FFFE, $FFFF External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) None None - $FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) - $FFFA, $FFFB COP failure reset None COP rate select - $FFF8, $FFF9 Unimplemented instruction trap None None - $FFF6, $FFF7 SWI None None - $FFF4, $FFF5 XIRQ X-Bit None - Vector Address $FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2 $FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0 $FFEE, $FFEF Standard Timer channel 0 I-Bit TIE (C0I) $EE $FFEC, $FFED Standard Timer channel 1 I-Bit TIE (C1I) $EC $FFEA, $FFEB Standard Timer channel 2 I-Bit TIE (C2I) $EA $FFE8, $FFE9 Standard Timer channel 3 I-Bit TIE (C3I) $E8 $FFE6, $FFE7 Standard Timer channel 4 I-Bit TIE (C4I) $E6 $FFE4, $FFE5 Standard Timer channel 5 I-Bit TIE (C5I) $E4 $FFE2, $FFE3 Standard Timer channel 6 I-Bit TIE (C6I) $E2 $FFE0, $FFE1 Standard Timer channel 7 I-Bit TIE (C7I) $E0 $FFDE, $FFDF Standard Timer overflow I-Bit TMSK2 (TOI) $DE $FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC $FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA $FFD8, $FFD9 SPI0 I-Bit SPICR1 (SPIE, SPTIE) $D8 $FFD6, $FFD7 SCI0 I-Bit SCICR2 (TIE, TCIE, RIE, ILIE) $D6 $FFD4, $FFD5 SCI1 I-Bit SCICR2 (TIE, TCIE, RIE, ILIE) $D4 $FFD2, $FFD3 ATD I-Bit ATDCTL2 (ASCIE) $D2 $FFD0, $FFD1 Reserved I-Bit Reserved $D0 I-Bit PIEJ (PIEJ7, PIEJ6, PIEJ1, PIEJ0) $CE $FFCE, $FFCF 66 Port J Device User Guide -- 9S12B128DGV1/D V01.04 $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 Port H Reserved I-Bit PIEH (PIEH7-0) I-Bit Reserved I-Bit $CC $CA $C8 $FFC6, $FFC7 CRG PLL lock I-Bit CRGINT (LOCKIE) $FFC4, $FFC5 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4 $FFC2, $FFC3 Reserved I-Bit Reserved $C2 $FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $FFBE, $FFBF $FFBC, $FFBD $FFBA, $FFBB Reserved I-Bit Reserved I-Bit $C6 $C0 $BE $BC EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA $FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8 $FFB6, $FFB7 CAN0 wake-up I-Bit CANRIER (WUPIE) $B6 $FFB4, $FFB5 CAN0 errors I-Bit CANRIER (CSCIE, OVRIE) $B4 $FFB2, $FFB3 CAN0 receive I-Bit CANRIER (RXFIE) $B2 $FFB0, $FFB1 CAN0 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $B0 $FFAE, $FFAF I-Bit $AE $FFAC, $FFAD I-Bit $AC $FFAA, $FFAB I-Bit $AA $FFA8, $FFA9 I-Bit $A8 $FFA6, $FFA7 I-Bit $A6 $FFA4, $FFA5 I-Bit $A4 $FFA2, $FFA3 I-Bit $A2 $FFA0, $FFA1 $FF9E, $FF9F Reserved I-Bit I-Bit Reserved $A0 $9E $FF9C, $FF9D I-Bit $9C $FF9A, $FF9B I-Bit $9A $FF98, $FF99 I-Bit $98 $FF96, $FF97 I-Bit $96 $FF94, $FF95 I-Bit $94 $FF92, $FF93 I-Bit $92 $FF90, $FF91 I-Bit $FF8E, $FF8F Port P $FF8C, $FF8D $FF8A, $FF8B $FF80 to $FF89 $90 I-Bit PIEP (PIEP7-0) $8E PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C VREG LVI I-Bit CTRL0 (LVIE) $8A Reserved 5.3 Resets When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. For details on the different kind of resets refer to the HCS12 Core User Guide, CRG and VREG_3V3 Block User Guides. 67 Device User Guide -- 9S12B128DGV1/D V01.04 5.3.1 I/O pins Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins. 5.3.2 Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. 5.4 Interrupts For details on the different kind of interrupts refer to the HCS12 Core User Guide and according module Block User Guides. 68 Device User Guide -- 9S12B128DGV1/D V01.04 Section 6 HCS12 Core Block Description Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM). Table 6-1 shows the HCS12 configuration for MC9S12B128. Table 6-1 Configuration of HCS12 Core on MC9S12B128 Name PUCR_RESET NUM_INT INITEE_RST Description PUCR reset state Interrupt Request Bus Width INITEE reset state INITEE_WOK INITEE Write anytime in normal mode PPAGE_SMOD_ONLY PPAGE Write only in special mode MC9S12B128 Configuration $90 56 $01 INITEE register is writeable once in normal modes PPAGE register is writable in allmodes, reset state of the PPAGE register is $00 6.1 Device-specific information When the BDM section of S12 Core User Guide refers to alternate clock this is equivalent to oscillator clock. Section 7 Voltage Regulator (VREG3V3) Block Description Consult the VREG3V3 Block User Guide for information about the dual output linear voltage regulator. VREGEN is accessible externally. Section 8 Clock and Reset Generator (CRG) Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module. 8.1 Device-specific information The Low Voltage Reset feature of the CRG is available on this device. Section 9 Oscillator (OSC) Block Description 69 Device User Guide -- 9S12B128DGV1/D V01.04 Consult the OSC Block User Guide for information about the Oscillator module. 9.1 Device-specific information The XCLKS input signal is active low (see 2.2.10 PE7 / NOACC / XCLKS -- Port E I/O Pin 7). Section 10 Standard Timer (TIM) Block Description Consult the TIM_16B8C Block User Guide for information about the Standard Timer module. When the TIM_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode. Section 11 Analog to Digital Converter (ATD) Block Description Consult the ATD_10B16C Block User Guide for information about the Analog to Digital Converter module. When the ATD_10B16C Block User Guide refers to freeze mode this is equivalent to active BDM mode. The ETRIG pin option is not available. Section 12 Inter-IC Bus (IIC) Block Description Consult the IIC Block User Guide for information about the Inter-IC Bus module. Section 13 Serial Communications Interface (SCI) Block Description There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12B128 device. Consult the SCI Block User Guide for information about each Serial Communications Interface module. Section 14 Serial Peripheral Interface (SPI) Block Description Consult the SPI Block User Guide for information about the Serial Peripheral Interface module. Section 15 Flash EEPROM 128K1 Block Description 70 Device User Guide -- 9S12B128DGV1/D V01.04 Consult the FTS128K1 Block User Guide for information about the flash module. Section 16 EEPROM 1K Block Description Consult the EETS1K Block User Guide for information about the EEPROM module. Section 17 RAM Block Description This module supports single-cycle misaligned word accesses. Section 18 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. Section 19 Pulse Width Modulator (PWM) Block Description Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module. When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode. Section 20 Port Integration Module (PIM) Block Description Consult the PIM_9B128 Block User Guide for information about the Port Integration Module. 71 Device User Guide -- 9S12B128DGV1/D V01.04 Section 21 Printed Circuit Board Layout Proposals Table 21-1 Suggested External Component Values Component Purpose Type Value C1 VDD1 filter cap ceramic X7R 100 .. 220nF C2 VDD2 filter cap ceramic X7R 100 .. 220nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R/tantalum >=100nF C5 VDDPLL filter cap ceramic X7R 100nF C6 VDDX filter cap X7R/tantalum >=100nF C7 OSC load cap C8 OSC load cap C9 / CS PLL loop filter cap C10 / CP PLL loop filter cap C11 / CDC DC cutoff cap Colpitts mode only, if recommended by quartz manufacturer R1 PLL loop filter res See PLL specification chapter R2 / RB OSC res R3 / RS OSC res Q1 Quartz See PLL specification chapter See PLL specification chapter Pierce mode only The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins(C1 - C6). * Central point of the ground star should be the VSSR pin. * Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. * VSSPLL must be directly connected to VSSR. * Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. * Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. * Central power input should be fed in at the VDDA/VSSA pins. 72 Device User Guide -- 9S12B128DGV1/D V01.04 Figure 21-1 Recommended PCB Layout 112LQFP Colpitts Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 C7 C8 C10 C9 R1 C11 C5 VDDR Q1 VSSPLL VDDPLL 73 Device User Guide -- 9S12B128DGV1/D V01.04 Figure 21-2 Recommended PCB Layout for 80QFP Colpitts Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSR C4 C5 VDDR C7 C8 C11 Q1 C10 C9 R1 74 VSSPLL VDDPLL Device User Guide -- 9S12B128DGV1/D V01.04 Figure 21-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR VSSPLL C4 R3 C5 VDDR R2 Q1 C7 C8 C10 C9 VDDPLL R1 75 Device User Guide -- 9S12B128DGV1/D V01.04 Figure 21-4 Recommended PCB Layout for 80QFP Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 VDD2 VSSPLL VSSR C4 R3 C5 VDDR R2 Q1 VDDPLL C7 76 C8 C10 C9 R1 VSSPLL Device User Guide -- 9S12B128DGV1/D V01.04 Appendix A Electrical Characteristics A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. NOTE: The part is specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the part is not tested in production test in the intermediate range. This supplement contains the most accurate electrical information for the MC9S12B128 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE: This classification is shown in the column labeled "C" in the parameter tables where appropriate. P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. 77 Device User Guide -- 9S12B128DGV1/D V01.04 A.1.2 Power Supply The MC9S12B128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the internal voltage regulator. The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. 78 Device User Guide -- 9S12B128DGV1/D V01.04 A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator. A.1.4 Current Injection Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). 79 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-1 Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit 1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.5 V 2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V 3 PLL Supply Voltage 2 VDDPLL -0.3 3.0 V 4 Voltage difference VDDX to VDDR and VDDA VDDX -0.3 0.3 V 5 Voltage difference VSSX to VSSR and VSSA VSSX -0.3 0.3 V 6 Digital I/O Input Voltage VIN -0.3 6.5 V 7 Analog Reference VRH, VRL -0.3 6.5 V 8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V 9 TEST input VTEST -0.3 10.0 V 10 Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 ID -25 +25 mA 11 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 I DL -25 +25 mA 12 Instantaneous Maximum Current Single pin limit for TEST 5 IDT -0.25 0 mA 15 Storage Temperature Range T - 65 155 C stg NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions Model 80 Description Symbol Value Unit Device User Guide -- 9S12B128DGV1/D V01.04 Table A-2 ESD and Latch-up Test Conditions Human Body Machine Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative - 3 3 Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V Latch-up Table A-3 ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 T Human Body Model (HBM) VHBM 2000 - V 2 T Machine Model (MM) VMM 200 - V 3 T Charge Device Model (CDM) VCDM 500 - V 4 Latch-up Current at TA = 125C T positive negative ILAT +100 -100 - mA 5 Latch-up Current at TA = 27C T positive negative ILAT +200 -200 - mA A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions Rating Symbol Min Typ Max Unit I/O, Regulator and Analog Supply Voltage VDD5 2.97 5 5.5 V Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V 81 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-4 Operating Conditions PLL Supply Voltage 1 VDDPLL 2.35 2.5 2.75 V Voltage Difference VDDX to VDDR and VDDA VDDX -0.1 0 0.1 V Voltage Difference VSSX to VSSR and VSSA VSSX -0.1 0 0.1 V Oscillator fosc 0.5 - 16 MHz Bus Frequency fbus 0.252 - 253 MHz T J -40 - 100 C TA -40 27 85 C Operating Junction Temperature Range TJ -40 - 120 C Operating Ambient Temperature Range 4 TA -40 27 105 C Operating Junction Temperature Range TJ -40 - 140 C Operating Ambient Temperature Range 4 TA -40 27 125 C MC9S12B128C Operating Junction Temperature Range Operating Ambient Temperature Range 4 MC9S12B128V MC9S12B128M NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. This applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. See bus speed option at Table 0-1 Derivative Differences 4. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO 82 Device User Guide -- 9S12B128DGV1/D V01.04 P INT = Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ------------ ;for outputs driven low I OL respectively V DD5 - V OH R DSON = ------------------------------------ ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. 83 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-5 Thermal Package Characteristics1 Num C Rating Symbol Min Typ Max Unit 1 T Thermal Resistance LQFP112, single sided PCB2 JA - - 54 o 2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 JA - - 41 o 3 T Junction to Board LQFP112 JB - - 31 oC/W 4 T Junction to Case LQFP112 JC - - 11 o 5 T Junction to Package Top LQFP112 JT - - 2 o 6 T Thermal Resistance QFP 80, single sided PCB JA - - 51 oC/W 7 T JA - - 41 oC/W 8 T Junction to Board QFP80 JB - - 27 oC/W 9 T Junction to Case QFP80 JC - - 14 oC/W 10 T Junction to Package Top QFP80 JT - - 3 oC/W Thermal Resistance QFP 80, double sided PCB with 2 internal planes C/W C/W C/W C/W NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-3 3. PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. 84 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-6 5V I/O Characteristics Conditions are 4.5< VDDX <5.5V Termperature from -40C to +140C, unless otherwise noted Num C Rating Symbol 1 P Input High Voltage V 2 P Input Low Voltage V 3 C Input Hysteresis 4 Input Leakage Current (pins in high impedance input P mode) V =V or VSS5 in DD5 5 Output High Voltage (pins in output mode) P Partial Drive IOH = -2mA Full Drive IOH = -10mA V 6 Output Low Voltage (pins in output mode) P Partial Drive IOL = +2mA Full Drive IOL = +10mA 7 IH IL V Min Typ Max Unit 0.65*VDD5 - VDD5 + 0.3 V VSS5 - 0.3 - 0.35*VDD5 V 250 HYS mV -1 - 1 A VDD5 - 0.8 - - V V OL - - 0.8 V Internal Pull Up Device Current, P tested at V Max. IPUL - - -130 A Internal Pull Up Device Current, C tested at V Min. IPUH -10 - - A Internal Pull Down Device Current, P tested at V Min. IPDH - - 130 A Internal Pull Down Device Current, C tested at V Max. IPDL 10 - - A 11 D Input Capacitance Cin 7 - pF 12 Injection current1 T Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP - 2.5 25 mA 13 P Port H, J, P Interrupt Input Pulse filtered2 tpign 3 s 14 P Port H, J, P Interrupt Input Pulse passed2 tpval IL 8 IH 9 IH 10 IL Iin OH -2.5 -25 10 s NOTES: 1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. 85 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-7 3.3V I/O Characteristics Conditions are VDDX=3.3V +/-10% Termperature from -40C to +140C, unless otherwise noted Num C Rating Symbol 1 P Input High Voltage V 2 P Input Low Voltage V 3 C Input Hysteresis 4 Input Leakage Current (pins in high impedance input P mode) V =V or VSS5 in DD5 5 Output High Voltage (pins in output mode) P Partial Drive IOH = -0.75mA Full Drive IOH = -4.5mA V 6 Output Low Voltage (pins in output mode) P Partial Drive IOL = +0.9mA Full Drive IOL = +5.5mA 7 IH IL V Min Typ Max Unit 0.65*VDD5 - VDD5 + 0.3 V VSS5 - 0.3 - 0.35*VDD5 V 250 HYS mV -1 - 1 A VDD5 - 0.4 - - V V OL - - 0.4 V Internal Pull Up Device Current, P tested at V Max. IPUL - - -60 A Internal Pull Up Device Current, C tested at V Min. IPUH -6 - - A Internal Pull Down Device Current, P tested at V Min. IPDH - - 60 A Internal Pull Down Device Current, C tested at V Max. IPDL 6 - - A 11 D Input Capacitance Cin 7 - pF 12 Injection current1 T Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP - 2.5 25 mA 13 P Port H, J, P Interrupt Input Pulse filtered2 tpign 3 s 14 P Port H, J, P Interrupt Input Pulse passed2 tpval IL 8 IH 9 IH 10 IL Iin OH -2.5 -25 10 s NOTES: 1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. 86 Device User Guide -- 9S12B128DGV1/D V01.04 A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz or 16Mhz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-8 Supply Current Characteristics at 25MHz Bus Frequency Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Run supply currents Single Chip, Internal regulator enabled IDD5 55 IDDW 35 7 1 P 2 P P All modules enabled, PLL on only RTI enabled 1 C P C C P C P C P Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C C C C C C C C Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Min Typ Max Unit mA Wait Supply current 3 4 IDDPS IDDPS 370 400 450 550 600 650 800 850 1200 mA 500 1600 A 2100 5000 570 600 650 750 850 1200 1500 A Stop Current 2 5 C P C C P C P C P -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C IDDS 12 25 100 130 160 200 350 400 600 100 1200 A 1700 5000 87 Device User Guide -- 9S12B128DGV1/D V01.04 NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed Table A-9 Supply Current Characteristics at 16MHz Bus Frequency Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Run supply currents Single Chip, Internal regulator enabled IDD5 55 IDDW 35 7 1 P 2 P P All modules enabled, PLL on only RTI enabled 1 C P C C P C P C P Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C C C C C C C C Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Min Typ Max Unit mA Wait Supply current 3 4 IDDPS IDDPS 370 400 450 550 600 650 800 850 1200 mA 500 1600 A 2100 5000 570 600 650 750 850 1200 1500 A Stop Current 2 5 C P C C P C P C P -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed 88 IDDS 12 25 100 130 160 200 350 400 600 100 1200 1700 5000 A Device User Guide -- 9S12B128DGV1/D V01.04 A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test. A.2.1 ATD Operating Characteristics In 5V Range The Table A-10 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-10 ATD Operating Characteristics In 5V Range Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10% Num C Rating Symbol Min VRL VRH VSSA VDDA/2 Typ Max Unit VDDA/2 VDDA V V 5.25 V Reference Potential 1 D Low High 2 C Differential Reference Voltage1 VRH-VRL 4.75 3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz 14 7 28 14 Cycles s 12 6 26 13 Cycles s 5.00 ATD 10-Bit Conversion Period Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 4 D 5 D 6 D Recovery Time (VDDA=5.0 Volts) tREC 20 s 7 P Reference Supply current IREF 0.750 mA ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK NCONV8 TCONV8 NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.75V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.2 ATD Operating Characteristics In 3.3V Range The Table A-11 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive 89 Device User Guide -- 9S12B128DGV1/D V01.04 beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-11 ATD Operating Characteristics In 3.3V Range Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10% Num C Rating Symbol Min VRL VRH VSSA VDDA/2 Typ Max Unit VDDA/2 VDDA V V 3.6 V Reference Potential 1 D Low High 2 C Differential Reference Voltage1 VRH-VRL 3.0 3 D ATD Clock Frequency fATDCLK 0.5 2.0 MHz 4 D 14 7 28 14 Cycles s 5 D 12 6 26 13 Cycles s 6 D Recovery Time (VDDA=3.3 Volts) tREC 20 s 7 P Reference Supply current IREF 0.500 mA 3.3 ATD 10-Bit Conversion Period Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK NCONV8 TCONV8 NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 3.0V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.3 Factors influencing accuracy Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.3.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.3.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). 90 Device User Guide -- 9S12B128DGV1/D V01.04 A.2.3.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-12 ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit RS - - 1 K 10 22 pF 2.5 mA 1 C Max input Source Resistance 2 Total Input Capacitance T Non Sampling Sampling 3 C Disruptive Analog Input Current INA 4 C Coupling Ratio positive current injection Kp 10-4 A/A 5 C Coupling Ratio negative current injection Kn 10-2 A/A CINN CINS -2.5 91 Device User Guide -- 9S12B128DGV1/D V01.04 A.2.4 ATD accuracy A.2.4.1 5V Range Table A-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-13 ATD Conversion Performance In 5V Range Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Supply Voltage 5V-10% <= VDDA <=5V+10% Num C Rating Symbol Min 1 P 10-Bit Resolution LSB 2 P 10-Bit Differential Nonlinearity DNL -1 3 P 10-Bit Integral Nonlinearity INL -2.5 4 P 10-Bit Absolute Error1 AE -3 5 P 8-Bit Resolution LSB 6 P 8-Bit Differential Nonlinearity DNL -0.5 7 P 8-Bit Integral Nonlinearity INL -1.0 8 P 8-Bit Absolute Error1 AE -1.5 Typ 5 Unit mV 1 Counts 1.5 2.5 Counts 2.0 3 Counts 20 mV 0.5 Counts 0.5 1.0 Counts 1.0 1.5 Counts NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. 92 Max Device User Guide -- 9S12B128DGV1/D V01.04 A.2.4.2 3.3V Range Table A-14 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-14 ATD Conversion Performance In 3.3V Range Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV fATDCLK = 2.0MHz Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10% Num C Rating Symbol Min 1 P 10-Bit Resolution LSB 2 P 10-Bit Differential Nonlinearity DNL -1.5 3 P 10-Bit Integral Nonlinearity INL -3.5 4 P 10-Bit Absolute Error1 AE -5 5 P 8-Bit Resolution LSB 6 P 8-Bit Differential Nonlinearity DNL -0.5 7 P 8-Bit Integral Nonlinearity INL -1.5 8 P 8-Bit Absolute Error1 AE -2.0 Typ Max 3.25 Unit mV 1.5 Counts 1.5 3.5 Counts 2.5 5 Counts 13 mV 0.5 Counts 1.0 1.5 Counts 1.5 2.0 Counts NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. A.2.4.3 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. Vi - Vi - 1 DNL ( i ) = ------------------------ - 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = i=1 Vn - V0 DNL ( i ) = -------------------- - n 1LSB 93 Device User Guide -- 9S12B128DGV1/D V01.04 DNL 10-Bit Absolute Error Boundary LSB Vi-1 Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F4 8-Bit Resolution 10-Bit Resolution $3F5 $FD $3F3 9 Ideal Transfer Curve 8 2 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-1 ATD Accuracy Definitions NOTE: 94 Figure A-1 shows only definitions, for specification values refer to Table A-13. Device User Guide -- 9S12B128DGV1/D V01.04 A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-15 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz. A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus A.3.1.2 Row Programming This applies only to the Flash where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus The time to program a whole row is: t brpgm = t swpgm + 63 t bwpgm Row programming is more than 2 times faster than single word programming. 95 Device User Guide -- 9S12B128DGV1/D V01.04 A.3.1.3 Sector Erase Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes: 1 t era 4000 --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: 1 t mass 20000 --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check location t cyc + 10 t cyc Table A-15 NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 50 1 MHz 1 D External Oscillator Clock fNVMOSC 0.5 2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 3 D Operating Frequency fNVMOP 150 200 kHz 4 P Single Word Programming Time tswpgm 46 2 74.5 3 s 5 D Flash Burst Programming consecutive word 4 tbwpgm 20.4 2 31 3 s 6 D Flash Burst Programming Time for 32 Words 4 tbrpgm 678.4 2 1035.5 3 s 7 P Sector Erase Time tera 20 5 26.7 3 ms 8 P Mass Erase Time tmass 100 5 133 3 ms 9 D Blank Check Time Flash per block tcheck 11 6 32778 7 tcyc 10 D Blank Check Time EEPROM per block tcheck 11 6 20587 tcyc MHz NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 96 Device User Guide -- 9S12B128DGV1/D V01.04 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Burst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. Table A-16 NVM Reliability Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit Data Retention at an average junction temperature of TJavg = 70C tNVMRET 15 Years nFLPE 10,000 Cycles 1 C 2 C Flash number of Program/Erase cycles 3 C EEPROM number of Program/Erase cycles (-40C TJ 0C) nEEPE 10,000 Cycles 4 C EEPROM number of Program/Erase cycles (0C < TJ 140C) nEEPE 100,000 Cycles 97 Device User Guide -- 9S12B128DGV1/D V01.04 98 Device User Guide -- 9S12B128DGV1/D V01.04 A.4 VREG_3V3 A.4.1 Operating Conditions Table A-17 VREG_3V3 - Operating Conditions Conditions are shown in Table A-4 unless otherwise noted Num C Symbol Min Typical Max Unit 1 P Input Voltages VVDDR,A 2.97 -- 5.5 V 2 P Regulator Current Reduced Power Mode Shutdown Mode IREG -- -- 20 12 50 40 A A P Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode VDD 2.35 1.6 -- 2.5 2.5 --1 2.75 2.75 -- V V V 4 P Output Voltage PLL Full Performance Mode Reduced Power Mode2 Reduced Power Mode3 Shutdown Mode 2.35 2.0 1.6 -- 2.5 2.5 2.5 --4 2.75 2.75 2.75 -- V V V 7 P Low Voltage Interrupt5 Assert Level Deassert Level VLVIA VLVID 4.1 4.25 4.37 4.52 4.66 4.77 V V 8 P Low Voltage Reset6 Assert Level VLVRA 2.25 -- -- V 9 C Power-on Reset7 Assert Level Deassert Level VPORA VPORD 0.97 -- -- -- -- 2.05 V V 3 Characteristic VDDPLL NOTES: 1. High Impedance Output 2. Current IDDPLL = 1mA (Colpitts Oscillator) 3. Current IDDPLL = 3mA (Pierce Oscillator) 4. High Impedance Output 5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 6. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-2) 7. Monitors VDD. Active in all modes. A.4.2 Chip Power-up and Voltage Drops VREG_3V3 sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-2. 99 Device User Guide -- 9S12B128DGV1/D V01.04 Figure A-2 VREG_3V3 - Chip Power-up and Voltage Drops (not scaled) V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR A.4.3 Output Loads A.4.3.1 Resistive Loads On-chip voltage regulator VREG_3V3 intended to supply the internal logic and oscillator circuits allows no external DC loads. A.4.3.2 Capacitive Loads The capacitive loads are specified in Table A-18. Ceramic capacitors with X7R dielectricum are required. 100 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-18 VREG_3V3 - Capacitive Loads Num Characteristic 1 VDD external capacitive load 3 VDDPLL external capacitive load Symbol Min Typical Max Unit CDDext 200 440 12000 nF CDDPLLext 90 220 5000 nF 101 Device User Guide -- 9S12B128DGV1/D V01.04 102 Device User Guide -- 9S12B128DGV1/D V01.04 A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-19 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide. Table A-19 Startup Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 D Reset input pulse width, minimum input time 2 D Startup from Reset 3 D Interrupt pulse width, IRQ edge-sensitive mode 4 D Wait recovery startup time Symbol Min PWRSTL 2 nRST 192 PWIRQ 20 tWRS Typ Max Unit tosc 196 nosc ns 14 tcyc A.5.1.1 POR The release level VPORD (see Table A-17) and the assert level VPORA (see Table A-17) are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 LVR The assert level VLVRA (see Table A-17) is derived from the VDD Supply. After releasing the LVR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.3 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.4 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. 103 Device User Guide -- 9S12B128DGV1/D V01.04 A.5.1.5 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. A.5.1.6 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. A.5.2 Oscillator The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset.By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-20 Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1a C Crystal oscillator range (Colpitts) fOSC 0.5 16 MHz 1b C Crystal oscillator range (Pierce) 1 fOSC 0.5 40 MHz 2 P Startup Current iOSC 100 3 C Oscillator start-up time (Colpitts) tUPOSC 4 D Clock Quality check time-out tCQOUT 0.45 5 P Clock Monitor Failure Assert Frequency fCMFA 50 6 P External square wave input frequency 4 fEXT 0.5 7 D External square wave pulse width low tEXTL 9.5 ns 8 D External square wave pulse width high tEXTH 9.5 ns 9 D External square wave rise time tEXTR 1 ns 10 D External square wave fall time tEXTF 1 ns 11 D Input Capacitance (EXTAL, XTAL pins) 12 C DC Operating Bias in Colpitts Configuration on EXTAL Pin 82 100 1003 ms 2.5 s 200 KHz 50 MHz CIN 7 pF VDCBIAS 1.1 V NOTES: 1. Depending on the crystal a damping series resistor might be necessary 104 A Device User Guide -- 9S12B128DGV1/D V01.04 2. fosc = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. XCLKS =0 during reset A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL R Phase Cs fosc 1 refdv+1 fref fcmp XFC Pin VCO K KV fvco Detector Loop Divider 1 synr+1 1 2 Figure A-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-21. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: KV = K1 e ( f 1 - f vco ) ----------------------K 1 1V = - 100 e ( 60 - 50 ) ------------------------ 100 = -90.48MHz/V The phase detector relationship is given by: 105 Device User Guide -- 9S12B128DGV1/D V01.04 K = - i ch K V = 316.7Hz/ ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. 2 f ref f ref 1 f C < ------------------------------------------ ------ f C < -------------- ;( = 0.9 ) 4 10 2 10 + 1 + fC < 25kHz And finally the frequency relationship is defined as f VCO n = ------------- = 2 ( synr + 1 ) f ref = 50 With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz: 2 n fC R = ----------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K The capacitance Cs can now be calculated as: 2 0.516 2 C s = ---------------------- --------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R The capacitance Cp should be chosen in the range of: C s 20 C p C s 10 Cp = 470pF A.5.3.2 Jitter Information The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. 106 Device User Guide -- 9S12B128DGV1/D V01.04 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t min ( N ) t max ( N ) J ( N ) = max 1 - --------------------- , 1 - --------------------- N t nom N t nom For N < 100, the following equation is a good fit for the maximum jitter: j1 J ( N ) = -------- + j 2 N J(N) 1 5 10 20 N Figure A-5 Maximum bus clock jitter approximation 107 Device User Guide -- 9S12B128DGV1/D V01.04 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Table A-21 PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency fSCM 1 5.5 MHz 2 D VCO locking range fVCO 8 50 MHz 3 D |trk| 3 4 %1 4 D Lock Detection |Lock| 0 1.5 %(1) 5 D Un-Lock Detection |unl| 0.5 2.5 %(1) 6 D |unt| 6 8 %(1) 7 C PLLON Total Stabilization delay (Auto Mode) 2 tstab 0.5 ms 8 D PLLON Acquisition mode stabilization delay (2) tacq 0.3 ms 9 D PLLON Tracking mode stabilization delay (2) tal 0.2 ms 10 D Fitting parameter VCO loop gain K1 -100 MHz/V 11 D Fitting parameter VCO loop frequency f1 60 MHz 12 D Charge pump current acquisition mode | ich | 38.5 A 13 D Charge pump current tracking mode | ich | 3.5 A 14 C Jitter fit parameter 1(2) j1 1.1 % 15 C Jitter fit parameter 2(2) j2 0.13 % Lock Detector transition from Acquisition to Tracking mode Lock Detector transition from Tracking to Acquisition mode NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K. 108 Device User Guide -- 9S12B128DGV1/D V01.04 A.6 MSCAN Table A-22 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol 1 P MSCAN Wake-up dominant pulse filtered tWUP 2 P MSCAN Wake-up dominant pulse pass tWUP Min 5 Typ Max Unit 2 s s 109 Device User Guide -- 9S12B128DGV1/D V01.04 110 Device User Guide -- 9S12B128DGV1/D V01.04 A.7 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-23 the measurement conditions are listed. Table A-23 Measurement Conditions Description Value Unit full drive mode -- 50 pF (20% / 80%) VDDX V Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted. SS1 (OUTPUT) 2 1 SCK (CPOL = 0) (OUTPUT) 13 12 13 3 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 10 MOSI (OUTPUT) 12 4 BIT 6 . . . 1 LSB IN 9 MSB OUT2 BIT 6 . . . 1 11 LSB OUT 1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6 SPI Master Timing (CPHA=0) In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted. 111 Device User Guide -- 9S12B128DGV1/D V01.04 SS1 (OUTPUT) 1 2 12 13 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 LSB IN 11 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-7 SPI Master Timing (CPHA=1) In Table A-24 the timing characteristics for master mode are listed. Table A-24 SPI Master Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck 1/2048 -- 1/2 fbus 1 SCK Period tsck 2 -- 2048 tbus 2 Enable Lead Time tlead -- 1/2 -- tsck 3 Enable Lag Time tlag -- 1/2 -- tsck 4 Clock (SCK) High or Low Time twsck -- 1/2 -- tsck 5 Data Setup Time (Inputs) tsu 8 -- -- ns 6 Data Hold Time (Inputs) thi 8 -- -- ns 9 Data Valid after SCK Edge tvsck -- -- 30 ns 10 Data Valid after SS fall (CPHA=0) tvss -- -- 15 ns 11 Data Hold Time (Outputs) tho 20 -- -- ns 12 Rise and Fall Time Inputs trfi -- -- 8 ns Rise and Fall Time Outputs trfo -- -- 8 ns 13 112 Device User Guide -- 9S12B128DGV1/D V01.04 A.7.2 Slave Mode In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted. SS (INPUT) 1 12 13 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 10 8 7 MISO (OUTPUT) 9 see note SLAVE MSB 5 MOSI (INPUT) BIT 6 . . . 1 11 11 SLAVE LSB OUT SEE NOTE 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure A-8 SPI Slave Timing (CPHA=0) In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted. 113 Device User Guide -- 9S12B128DGV1/D V01.04 SS (INPUT) 3 1 2 12 13 12 13 SCK (CPOL = 0) (INPUT) 4 4 SCK (CPOL = 1) (INPUT) see note SLAVE 7 MSB OUT 5 MOSI (INPUT) 8 11 9 MISO (OUTPUT) BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure A-9 SPI Slave Timing (CPHA=1) In Table A-25 the timing characteristics for slave mode are listed. Table A-25 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck DC -- 1/4 fbus 1 SCK Period tsck 4 -- tbus 2 Enable Lead Time tlead 4 -- -- tbus 3 Enable Lag Time tlag 4 -- -- tbus 4 Clock (SCK) High or Low Time twsck 4 -- -- tbus 5 Data Setup Time (Inputs) tsu 8 -- -- ns 6 Data Hold Time (Inputs) thi 8 -- -- ns Slave Access Time (time to data active) ta -- -- 20 ns Slave MISO Disable Time tdis -- -- 22 7 8 ns 1 ns 9 Data Valid after SCK Edge tvsck -- -- 30 + tbus 10 Data Valid after SS fall tvss -- -- 30 + tbus 1 ns 11 Data Hold Time (Outputs) tho 20 -- -- ns 12 Rise and Fall Time Inputs trfi -- -- 8 ns 13 Rise and Fall Time Outputs trfo -- -- 8 ns NOTES: 1. tbus added due to internal synchronization delay 114 Device User Guide -- 9S12B128DGV1/D V01.04 A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on Table A-26 in 5V range. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. A.8.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. 115 Device User Guide -- 9S12B128DGV1/D V01.04 1, 2 3 4 ECLK PE4 5 9 Addr/Data (read) PA, PB 6 data 16 15 7 data 8 14 13 data addr 17 11 data addr 12 Addr/Data (write) PA, PB 10 19 18 Non-Multiplexed Addresses PK5:0 20 21 22 23 ECS PK7 24 25 26 27 28 29 30 31 32 33 34 R/W PE2 LSTRB PE3 NOACC PE7 35 36 IPIPO0 IPIPO1, PE6,5 Figure A-10 General External Bus Timing 116 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-26 Expanded Bus Timing Characteristics In 5V Range Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF. Supply Voltage 5V-10% <= VDDX <=5V+10% Num C Rating Symbol Min Typ Max Unit fo 0 25.0 MHz tcyc 40 ns 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low PWEL 19 ns 4 D Pulse width, E high1 PWEH 19 ns 5 D Address delay time tAD 6 D Address valid time to E rise (PWEL-tAD) tAV 11 ns 7 D Muxed address hold time tMAH 2 ns 8 D Address hold to data valid tAHDS 7 ns 9 D Data hold to address tDHA 2 ns 10 D Read data setup time tDSR 13 ns 11 D Read data hold time tDHR 0 ns 12 D Write data delay time tDDW 13 D Write data hold time tDHW 2 ns 14 D Write data setup time1 (PWEH-tDDW) tDSW 12 ns 15 D Address access time1 (tcyc-tAD-tDSR) tACCA 19 ns 16 D E high access time1 (PWEH-tDSR) tACCE 6 ns 17 D Chip select delay time tCSD 18 D Chip select access time1 (tcyc-tCSD-tDSR) tACCS 11 ns 19 D Chip select hold time tCSH 2 ns 20 D Chip select negated time tCSN 8 ns 21 D Read/write delay time tRWD 22 D Read/write valid time to E rise (PWEL-tRWD) tRWV 14 ns 23 D Read/write hold time tRWH 2 ns 24 D Low strobe delay time tLSD 25 D Low strobe valid time to E rise (PWEL-tLSD) tLSV 14 ns 26 D Low strobe hold time tLSH 2 ns 27 D NOACC strobe delay time tNOD 28 D NOACC valid time to E rise (PWEL-tNOD) tNOV 14 ns 29 D NOACC hold time tNOH 2 ns 30 D IPIPO[1:0] delay time tP0D 2 8 7 16 7 7 7 7 ns ns ns ns ns ns ns 117 Device User Guide -- 9S12B128DGV1/D V01.04 Table A-26 Expanded Bus Timing Characteristics In 5V Range Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF. Supply Voltage 5V-10% <= VDDX <=5V+10% Num C Rating Symbol Min 31 D IPIPO[1:0] valid time to E rise (PWEL-tP0D) tP0V 11 32 D IPIPO[1:0] delay time1 (PWEH-tP1V) tP1D 2 33 D IPIPO[1:0] valid time to E fall tP1V 11 Typ NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches. 118 Max Unit ns 25 ns ns Device User Guide -- 9S12B128DGV1/D V01.04 Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12B128 packages. 119 Device User Guide -- 9S12B128DGV1/D V01.04 B.2 112-pin LQFP package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 57 29 F D 56 0.13 N T L-M N SECTION J1-J1 S1 A S C2 VIEW AB 2 0.050 0.10 T 112X SEATING PLANE 3 T R R2 R 0.25 R1 GAGE PLANE (K) C1 E (Y) (Z) VIEW AB M 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3 MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13 Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) 120 BASE METAL ROTATED 90 COUNTERCLOCKWISE A1 C AA J V1 Device User Guide -- 9S12B128DGV1/D V01.04 B.3 80-pin QFP package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B) 121 Device User Guide -- 9S12B128DGV1/D V01.04 122 Device User Guide -- 9S12B128DGV1/D V01.04 Device User Guide End Sheet 123 Device User Guide -- 9S12B128DGV1/D V01.04 FINAL PAGE OF 124 PAGES 124