Ultra Low Power, 64 /3 2 kB , 10- Bi t A DC
MCU with Integrated 240–960 MHz EZRadioPRO® Transceiver
Si106x/108x
Rev. 1.0 2/13 Copyright © 2013 by Silicon Laborator ie s Si106x/108x
Ultra-low power 8051 µC Core
-25 MHz, single-cycle 8051 compatible CPU
-25 MIPS peak throughput with 25 MHz clock
-Industry's lowest active and sleep currents
-160 µA/MHz: active mode
-10 nA sleep with brownout detectors disabled
-50 nA sleep with brownout detectors enabled
-600 nA sleep with internal RTC
-2 µs wake-up time
-On-chip debug
Memory
-Up to 64 kB of flash and 4 kB of RAM
Peripherals
-10-bit analog-to-digital converter
-Temperature sensor
-Dual comparators
-11 general purpose I/O
-UART, SPI, I2C
-Four general purpose 16-bit counter/timers
-Precision internal oscillators
-24.5 MHz with ±2% accuracy
-Low power 20 MHz internal oscillator
-External oscillator: crystal, RC, C, CMOS clock
-RTC: 32.768 kHz crystal or self-oscillate
Transceiver Features (Si1060)
-Data rate up to 1 Mbps
-142–1050 MHz frequency range
-On-chip crystal tuning
-–126 dBm receive sensitivity @ 500 bps, GFSK
-Modulation: OOK, (G)FSK, and 4(G)FSK
-Up to +20 dBm output power
-Low power consumption
-10/13 mA RX
-18 mA TX at +10 dBm
-30 nA shutdown, 50 nA standby
-Fast wake and hop times
-Excellent selectivity performance
-60 dB adjacent channel
-73 dB blocking at 1 MHz
-Antenna diversity and T/R switch control
-Highly configurable packet handler
-TX and RX 64 byte FIFOs
-Auto frequency control (AFC)
-Automatic gain control (AGC)
-IEEE 802.15.4g compliant
System
-Supply voltage: 1.8 to 3.6 V
-0.9–3.6 V operation with built-in dc-dc converter
-Brownout detectors cover sleep and active modes
-Low battery detector
-Low BOM count
-5x6 36-pin QFN package
Applications
-Home automation
-Home security
-Remote control
-Garage door openers
-Remote keyless Entry
-Home health care
-Smart metering
-Building Lighting control
-Building HVAC control
-Fire and Security monitoring
-Security and Access control
-Telemetry
CIP-51 8051
Controller Core
Flash
Program Memory
SRAM
SFR
Bus
P0.2/XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
RST/C2CK
Wake
P0.3/XTAL2
Low Power
20 MHz
Oscillator
SmaRTClock
Oscillator
XTAL3
XTAL4
CRC
Engine
RXp
RXn
TX
XIN
XOUT
Analog Peripherals
Comparators
+
-
10-bit
300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
VREF
GND
CP0, CP0A
+
-
CP1, CP1A
RF XCVR
OSC
PA
LNA
AGC
Mixer
PGA
ADC
Port I/O
Config
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
Transceiver Control Interface
SPI 0
11 ANALOG &
DIGITAL I/O
GPIO
LDO
POR VDD
Modem
FIFO
Packet
Handler
Digital
Logic
4
DC/DC
Converter
Analog
Power
VREG Digital
Power
VDD/DC+
GND/DC-
VBAT
GND
2 Rev. 1.0
Rev. 1.0 3
Si106x/108x
Table of Contents
1. System Overview..................................................................................................... 15
1.1. Typical Connection Diagram ............................................................................. 17
1.2. CIP-51™ Microcontroller Core .......................................................................... 18
1.3. Port Input/Output ............................................................................................... 19
1.4. Serial Ports........................................................................................................ 20
1.5. Programmable Counter Array............................................................................ 20
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode............................................................................................... 21
1.7. Comparators...................................................................................................... 22
2. Si106x/108x Ordering Information.......................................................................... 24
3. Pinout and Package Definitions............................................................................. 25
4. Electrical Characteristics........................................................................................ 42
4.1. Absolute Maximum Specifications..................................................................... 42
4.2. MCU Electrical Characteristics.......................................................................... 43
4.3. Radio Electrical Characteristics......................................................................... 67
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode ....................................................................................................... 78
5.1. Output Code Formatting.................................................................................... 78
5.2. Modes of Operation........................................................................................... 80
5.3. 8-Bit Mode ......................................................................................................... 85
5.4. Programmable Window Detector....................................................................... 92
5.5. ADC0 Analog Multiplexer .................................................................................. 95
5.6. Temperature Sensor.......................................................................................... 97
5.7. Voltage and Ground Reference Options ......................................................... 100
5.8. External Voltage References........................................................................... 101
5.9. Internal Voltage References............................................................................ 101
5.10. Analog Ground Reference............................................................................. 101
5.11. Temperature Sensor Enable ......................................................................... 101
5.12. Voltage Reference Electrical Specifications.................................................. 102
6. Comparators........................................................................................................... 103
6.1. Comparator Inputs........................................................................................... 103
6.2. Comparator Outputs........................................................................................ 104
6.3. Comparator Response Time ........................................................................... 105
6.4. Comparator Hysteresis.................................................................................... 105
6.5. Comparator Register Descriptions .................................................................. 106
6.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 110
7. CIP-51 Microcontroller........................................................................................... 113
7.1. Performance.................................................................................................... 113
7.2. Programming and Debugging Support............................................................ 114
7.3. Instruction Set.................................................................................................. 114
7.4. CIP-51 Register Descriptions .......................................................................... 119
8. Memory Organization............................................................................................ 122
8.1. Program Memory............................................................................................. 124
Si106x/108x
4 Rev. 1.0
8.2. Data Memory................................................................................................... 125
9. On-Chip XRAM....................................................................................................... 127
9.1. Accessing XRAM............................................................................................. 127
9.2. Special Function Registers.............................................................................. 128
10. Special Function Registers................................................................................. 129
10.1. SFR Paging ................................................................................................... 130
11. Interrupt Handler.................................................................................................. 137
11.1. Enabling Interrupt Sources............................................................................ 137
11.2. MCU Interrupt Sources and Vectors.............................................................. 137
11.3. Interrupt Priorities .......................................................................................... 138
11.4. Interrupt Latency............................................................................................ 138
11.5. Interrupt Register Descriptions...................................................................... 140
11.6. External Interrupts INT0 and INT1................................................................. 147
12. Flash Memory....................................................................................................... 149
12.1. Programming the Flash Memory ................................................................... 149
12.2. Non-Volatile Data Storage............................................................................. 151
12.3. Security Options ............................................................................................ 151
12.4. Determining the Device Part Number at Run Time ....................................... 154
12.5. Flash Write and Erase Guidelines................................................................. 154
12.6. Minimizing Flash Read Current ..................................................................... 156
13. Power Management............................................................................................. 160
13.1. Normal Mode................................................................................................. 161
13.2. Idle Mode....................................................................................................... 162
13.3. Stop Mode ..................................................................................................... 162
13.4. Suspend Mode .............................................................................................. 163
13.5. Sleep Mode ................................................................................................... 163
13.6. Configuring Wakeup Sources........................................................................ 164
13.7. Determining the Event that Caused the Last Wakeup................................... 164
13.8. Power Management Specifications ............................................................... 166
14. Cyclic Redundancy Check Unit (CRC0)............................................................. 167
14.1. 16-bit CRC Algorithm..................................................................................... 167
14.2. 32-bit CRC Algorithm..................................................................................... 169
14.3. Preparing for a CRC Calculation ................................................................... 170
14.4. Performing a CRC Calculation ...................................................................... 170
14.5. Accessing the CRC0 Result .......................................................................... 170
14.6. CRC0 Bit Reverse Feature............................................................................ 174
15. On-Chip DC-DC Converter (DC0)........................................................................ 175
15.1. Startup Behavior............................................................................................ 176
15.2. High Power Applications................................................................................ 177
15.3. Pulse Skipping Mode..................................................................................... 177
15.4. Enabling the DC-DC Converter ..................................................................... 177
15.5. Minimizing Power Supply Noise .................................................................... 179
15.6. Selecting the Optimum Switch Size............................................................... 179
15.7. DC-DC Converter Clocking Options .............................................................. 179
15.8. DC-DC Converter Behavior in Sleep Mode................................................... 180
Rev. 1.0 5
Si106x/108x
15.9. DC-DC Converter Register Descriptions....................................................... 181
15.10. DC-DC Converter Specifications ................................................................. 183
16. Voltage Regulator (VREG0)................................................................................. 184
16.1. Voltage Regulator Electrical Specifications................................................... 184
17. Reset Sources...................................................................................................... 185
17.1. MCU Power-On (VBAT Supply Monitor) Reset ............................................. 186
17.2. Power-Fail (VDD_MCU Supply Monitor) Reset............................................. 187
17.3. External Reset............................................................................................... 189
17.4. Missing Clock Detector Reset ....................................................................... 189
17.5. Comparator0 Reset ....................................................................................... 190
17.6. PCA Watchdog Timer Reset ......................................................................... 190
17.7. Flash Error Reset .......................................................................................... 190
17.8. SmaRTClock (Real Time Clock) Reset ......................................................... 190
17.9. Software Reset.............................................................................................. 190
18. Clocking Sources................................................................................................. 192
18.1. Programmable Precision Internal Oscillator .................................................. 193
18.2. Low Power Internal Oscillator........................................................................ 193
18.3. External Oscillator Drive Circuit..................................................................... 193
18.4. Special Function Registers for Selecting and Configuring the System Clock 197
19. SmaRTClock (Real Time Clock).......................................................................... 200
19.1. SmaRTClock Interface .................................................................................. 200
19.2. SmaRTClock Clocking Sources .................................................................... 207
19.3. SmaRTClock Timer and Alarm Function ....................................................... 211
20. Si106x/108xPort Input/Output............................................................................. 217
20.1. Port I/O Modes of Operation.......................................................................... 218
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 219
20.3. Priority Crossbar Decoder ............................................................................. 221
20.4. Port Match ..................................................................................................... 226
20.5. Special Function Registers for Accessing and Configuring Port I/O ............. 229
21. Controller Interface.............................................................................................. 238
21.1. Serial Interface (SPI1) ................................................................................... 238
21.2. Fast Response Registers (Si1060/61/62/63 and Si1080/81/82/83) .............. 241
21.3. Operating Modes and Timing ........................................................................ 241
21.4. Application Programming Interface (API) ...................................................... 246
21.5. GPIO .......................................................................................................... 247
22. Radio 142–1050 MHz Transceiver Functional Description .............................. 248
23. Modulation and Hardware Configuration Options............................................ 249
23.1. Modulation Types .......................................................................................... 249
23.2. Hardware Configuration Options ................................................................... 249
23.3. Preamble Length ........................................................................................... 250
24. Internal Functional Blocks.................................................................................. 252
24.1. RX Chain ....................................................................................................... 252
24.2. RX Modem..................................................................................................... 253
24.3. Synthesizer.................................................................................................... 255
24.4. Transmitter (TX) ............................................................................................ 258
Si106x/108x
6 Rev. 1.0
24.5. Crystal Oscillator ........................................................................................... 261
25. Data Handling and Packet Handler .................................................................... 262
25.1. RX and TX FIFOs.......................................................................................... 262
25.2. Packet Handler.............................................................................................. 262
26. RX Modem Configuration.................................................................................... 263
27. Auxiliary Blocks................................................................................................... 263
27.1. Wake-Up Timer and 32 kHz Clock Source.................................................... 263
27.2. Low Duty Cycle Mode (Auto RX Wake-Up)................................................... 265
27.3. Antenna Diversity (Si1060–Si1063, Si1080-Si1083)..................................... 266
28. SMBus................................................................................................................... 267
28.1. Supporting Documents.................................................................................. 268
28.2. SMBus Configuration..................................................................................... 268
28.3. SMBus Operation .......................................................................................... 268
28.4. Using the SMBus........................................................................................... 270
28.5. SMBus Transfer Modes................................................................................. 282
28.6. SMBus Status Decoding................................................................................ 285
29. UART0................................................................................................................... 290
29.1. Enhanced Baud Rate Generation.................................................................. 291
29.2. Operational Modes ........................................................................................ 292
29.3. Multiprocessor Communications ................................................................... 293
30. Enhanced Serial Peripheral Interface (SPI0)..................................................... 298
30.1. Signal Descriptions........................................................................................ 299
30.2. SPI0 Master Mode Operation........................................................................ 299
30.3. SPI0 Slave Mode Operation.......................................................................... 301
30.4. SPI0 Interrupt Sources .................................................................................. 302
30.5. Serial Clock Phase and Polarity .................................................................... 303
30.6. SPI Special Function Registers..................................................................... 304
31. Timers................................................................................................................... 311
31.1. Timer 0 and Timer 1 ...................................................................................... 313
31.2. Timer 2 .......................................................................................................... 321
31.3. Timer 3 .......................................................................................................... 327
32. Si106x/108xSi106x/108x Programmable Counter Array................................... 333
32.1. PCA Counter/Timer ....................................................................................... 334
32.2. PCA0 Interrupt Sources................................................................................. 335
32.3. Capture/Compare Modules ........................................................................... 336
32.4. Watchdog Timer Mode .................................................................................. 344
32.5. Register Descriptions for PCA0..................................................................... 346
33. Device Specific Behavior.................................................................................... 352
33.1. Device Identification ...................................................................................... 352
34. C2 Interface .......................................................................................................... 353
34.1. C2 Interface Registers................................................................................... 353
34.2. C2 Pin Sharing .............................................................................................. 356
Document Change List.............................................................................................. 357
Contact Information................................................................................................... 358
Rev. 1.0 7
Si106x/108x
List of Figures
Figure 1.1. Si106x/Si108x Block Diagram ............................................................... 16
Figure 1.2. Si106x/108x RX/TX Direct-Tie Application Example ............................. 17
Figure 1.3. Si106x/108x Antenna Diversity Application Example ............................ 17
Figure 1.4. Port I/O Functional Block Diagram ........................................................ 19
Figure 1.5. PCA Block Diagram ............................................................................... 20
Figure 1.6. ADC0 Functional Block Diagram ........................................................... 21
Figure 1.7. ADC0 Multiplexer Block Diagram .......................................................... 22
Figure 1.8. Comparator 0 Functional Block Diagram .............................................. 23
Figure 1.9. Comparator 1 Functional Block Diagram .............................................. 23
Figure 3.1. Si1060/1, Si1080/1-A-GM Pinout Diagram (Top View) ......................... 34
Figure 3.2. Si1062/3, Si1082/3-A-GM Pinout Diagram (Top View) ......................... 35
Figure 3.3. Si1064/5, Si1084/5-A-GM Pinout Diagram (Top View) ......................... 36
Figure 3.4. QFN-36 Package Drawing .................................................................... 37
Figure 3.5. QFN-36 PCB Land Pattern Dimensions ................................................ 39
Figure 3.6. QFN-36 PCB Stencil and Via Placement .............................................. 41
Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 46
Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 47
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V ... 48
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 49
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 50
Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 51
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 53
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 54
Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 55
Figure 4.10. Typical VOL Curves, 0.9–1.8 V ........................................................... 56
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 81
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 83
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 84
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 94
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 94
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95
Figure 5.8. Temperature Sensor Transfer Function ................................................ 97
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 98
Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100
Figure 6.1. Comparator 0 Functional Block Diagram ............................................ 103
Figure 6.2. Comparator 1 Functional Block Diagram ............................................ 104
Figure 6.3. Comparator Hysteresis Plot ................................................................ 105
Figure 6.4. CPn Multiplexer Block Diagram ........................................................... 110
Figure 7.1. CIP-51 Block Diagram ......................................................................... 113
Figure 8.1. Si106x Memory Map ........................................................................... 122
Figure 8.2. Si108x Memory Map ........................................................................... 123
Figure 8.3. Si106x Flash Program Memory Map ................................................... 124
Si106x/108x
8 Rev. 1.0
Figure 8.4. Si108x Flash Program Memory Map ................................................... 124
Figure 12.1. Si106x Flash Program Memory Map ................................................. 151
Figure 12.2. Si108x Flash Program Memory Map ................................................. 152
Figure 13.1. Si106x/108x Power Distribution ........................................................ 161
Figure 14.1. CRC0 Block Diagram ........................................................................ 167
Figure 14.2. Bit Reverse Register ......................................................................... 174
Figure 15.1. DC-DC Converter Block Diagram ...................................................... 175
Figure 15.2. DC-DC Converter Configuration Options .......................................... 178
Figure 17.1. Reset Sources ................................................................................... 185
Figure 17.2. Power-Fail Reset Timing Diagram .................................................... 186
Figure 17.3. Power-Fail Reset Timing Diagram .................................................... 187
Figure 18.1. Clocking Sources Block Diagram ...................................................... 192
Figure 18.2. 25 MHz External Crystal Example ..................................................... 194
Figure 19.1. SmaRTClock Block Diagram ............................................................. 200
Figure 19.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 209
Figure 20.1. Port I/O Functional Block Diagram .................................................... 217
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 218
Figure 20.3. Crossbar Priority Decoder with No Pins Skipped .............................. 222
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 223
Figure 21.1. SPI Write Command .......................................................................... 239
Figure 21.2. SPI Read Command—Check CTS Value ......................................... 239
Figure 21.3. SPI Read Command—Clock Out Read Data .................................... 240
Figure 21.4. State Machine Diagram ..................................................................... 241
Figure 21.5. POR Timing Diagram ........................................................................ 243
Figure 21.6. Start_TX Commands and Timing ...................................................... 245
Figure 24.1. RX Architecture vs. Data Rate .......................................................... 253
Figure 24.2. +20 dBm TX Power vs. PA_PWR_LVL ............................................. 259
Figure 24.3. +20 dBm TX Power vs. VDD ............................................................. 260
Figure 24.4. +20 dBm TX Power vs. Temp ........................................................... 260
Figure 24.5. Capacitor Bank Frequency Offset Characteristics ............................ 261
Figure 25.1. TX and RX FIFOs .............................................................................. 262
Figure 25.2. Packet Handler Structure .................................................................. 262
Figure 27.1. RX and TX LDC Sequences .............................................................. 265
Figure 27.2. Low Duty Cycle Mode for RX ............................................................ 265
Figure 28.1. SMBus Block Diagram ...................................................................... 267
Figure 28.2. Typical SMBus Configuration ............................................................ 268
Figure 28.3. SMBus Transaction ........................................................................... 269
Figure 28.4. Typical SMBus SCL Generation ........................................................ 271
Figure 28.5. Typical Master Write Sequence ........................................................ 282
Figure 28.6. Typical Master Read Sequence ........................................................ 283
Figure 28.7. Typical Slave Write Sequence .......................................................... 284
Figure 28.8. Typical Slave Read Sequence .......................................................... 285
Figure 29.1. UART0 Block Diagram ...................................................................... 290
Figure 29.2. UART0 Baud Rate Logic ................................................................... 291
Figure 29.3. UART Interconnect Diagram ............................................................. 292
Rev. 1.0 9
Si106x/108x
Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 292
Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 293
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 294
Figure 30.1. SPI Block Diagram ............................................................................ 298
Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 300
Figure 30.3. 3-Wire Single Master and Slave Mode Connection Diagram ............ 300
Figure 30.4. 4-Wire Single Master and Slave Mode Connection Diagram ............ 301
Figure 30.5. Master Mode Data/Clock Timing ....................................................... 303
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 304
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 304
Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 308
Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 308
Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 309
Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 309
Figure 31.1. T0 Mode 0 Block Diagram ................................................................. 314
Figure 31.2. T0 Mode 2 Block Diagram ................................................................. 315
Figure 31.3. T0 Mode 3 Block Diagram ................................................................. 316
Figure 31.4. Timer 2 16-Bit Mode Block Diagram ................................................. 321
Figure 31.5. Timer 2 8-Bit Mode Block Diagram ................................................... 322
Figure 31.6. Timer 2 Capture Mode Block Diagram .............................................. 323
Figure 31.7. Timer 3 16-Bit Mode Block Diagram ................................................. 327
Figure 31.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 328
Figure 31.9. Timer 3 Capture Mode Block Diagram .............................................. 329
Figure 32.1. PCA Block Diagram ........................................................................... 333
Figure 32.2. PCA Counter/Timer Block Diagram ................................................... 334
Figure 32.3. PCA Interrupt Block Diagram ............................................................ 335
Figure 32.4. PCA Capture Mode Diagram ............................................................. 337
Figure 32.5. PCA Software Timer Mode Diagram ................................................. 338
Figure 32.6. PCA High-Speed Output Mode Diagram ........................................... 339
Figure 32.7. PCA Frequency Output Mode ........................................................... 340
Figure 32.8. PCA 8-Bit PWM Mode Diagram ........................................................ 341
Figure 32.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 342
Figure 32.10. PCA 16-Bit PWM Mode ................................................................... 343
Figure 32.11. PCA Module 5 with Watchdog Timer Enabled ................................ 344
Figure 33.1. Si106x Revision Information .............................................................. 352
Figure 34.1. Typical C2 Pin Sharing ...................................................................... 356
Rev. 1.0 10
Si106x/108x
List of Tables
Table 2.1. Orderable Part Number .......................................................................... 24
Table 3.1. Si1060/Si1061/Si1080/Si1081 Pin Definitions ........................................ 25
Table 3.2. Si1062/Si1063/Si1082/Si1083 Pin Definitions ........................................ 28
Table 3.3. Si1064/Si1065/Si1084/Si1085 Pin Definitions ........................................ 31
Table 3.4. QFN-36 Package Dimensions ................................................................ 38
Table 3.5. QFN-36 PCB Land Pattern Dimensions ................................................. 40
Table 4.1. Absolute Maximum Ratings .................................................................... 42
Table 4.2. Global Electrical Characteristics ............................................................. 43
Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 52
Table 4.4. Reset Electrical Characteristics .............................................................. 57
Table 4.5. Power Management Electrical Specifications ......................................... 58
Table 4.6. Flash Electrical Characteristics .............................................................. 58
Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 59
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 59
Table 4.9. ADC0 Electrical Characteristics .............................................................. 60
Table 4.10. Temperature Sensor Electrical Characteristics .................................... 61
Table 4.11. Voltage Reference Electrical Characteristics ....................................... 62
Table 4.12. Comparator Electrical Characteristics .................................................. 63
Table 4.13. DC-DC Converter (DC0) Electrical Characteristics .............................. 65
Table 4.14. VREG0 Electrical Characteristics ......................................................... 66
Table 4.15. DC Characteristics ................................................................................ 67
Table 4.16. Synthesizer AC Electrical Characteristics ............................................ 68
Table 4.17. Receiver AC Electrical Characteristics ................................................. 69
Table 4.18. Transmitter AC Electrical Characteristics ............................................ 73
Table 4.19. Auxiliary Block Specifications ............................................................... 75
Table 4.20. Digital IO Specifications (GPIO_x, nIRQ) ............................................. 75
Table 4.21. Absolute Maximum Ratings (Radio) ..................................................... 77
Table 4.22. Thermal Properties ............................................................................... 77
Table 7.1. CIP-51 Instruction Set Summary .......................................................... 115
Table 10.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 129
Table 10.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 130
Table 10.3. Special Function Registers ................................................................. 131
Table 10.4. Select Registers with Varying Function .............................................. 135
Table 11.1. Interrupt Summary .............................................................................. 139
Table 12.1. Flash Security Summary .................................................................... 152
Table 13.1. Power Modes ...................................................................................... 160
Table 14.1. Example 16-bit CRC Outputs ............................................................. 168
Table 14.2. Example 32-bit CRC Outputs ............................................................. 170
Table 15.1. IPeak Inductor Current Limit Settings ................................................. 176
Table 18.1. Recommended XFCN Settings for Crystal Mode ............................... 194
Table 18.2. Recommended XFCN Settings for RC and C modes ......................... 195
Table 19.1. SmaRTClock Internal Registers ......................................................... 201
Table 19.2. SmaRTClock Load Capacitance Settings .......................................... 208
Si106x/108x
11 Rev. 1.0
Table 19.3. SmaRTClock Bias Settings ................................................................ 210
Table 20.1. Port I/O Assignment for Analog Functions ......................................... 220
Table 20.2. Port I/O Assignment for Digital Functions ........................................... 220
Table 20.3. Port I/O Assignment for External Digital Event Capture Functions .... 221
Table 21.1. Internal Connection for Radio and MCU ............................................. 238
Table 21.2. Serial Interface Timing Parameters .................................................... 238
Table 21.3. Operating State Response Time and Current Consumption
Si1060/61/62/63, Si1080/81/82/83 ..................................................... 242
Table 21.4. Operating State Response Time and Current Consumption
(Si1064/65, Si1084/85) ....................................................................... 242
Table 21.5. POR Timing ........................................................................................ 243
Table 21.6. GPIOs ................................................................................................. 247
Table 23.1. Recommended Preamble Length ....................................................... 251
Table 24.1. Output Divider (Outdiv) Values for the Si1060–Si1063, Si1080-1083 256
Table 24.2. Output Divider (Outdiv) for the Si1064/Si1065/Si1084/Si1085 ........... 256
Table 27.1. WUT Specific Commands and Properties .......................................... 264
Table 28.1. SMBus Clock Source Selection .......................................................... 271
Table 28.2. Minimum SDA Setup and Hold Times ................................................ 272
Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 276
Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 277
Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 286
Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 288
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 297
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 297
Table 30.1. SPI Slave Timing Parameters ............................................................ 310
Table 31.1. Timer 0 Running Modes ..................................................................... 313
Table 32.1. PCA Timebase Input Options ............................................................. 334
Table 32.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare
Modules .............................................................................................. 336
Table 32.3. Watchdog Timer Timeout Intervals1 ................................................... 345
Rev. 1.0 12
Si106x/108x
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 86
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 87
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 88
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 89
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 90
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 91
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 91
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 92
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 92
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 93
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 93
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 96
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 99
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 99
SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 102
SFR Definition 6.1. CPT0CN: Comparator 0 Control .................................................. 106
SFR Definition 6.2. CPT0MD: Comparator 0 Mode Selection .................................... 107
SFR Definition 6.3. CPT1CN: Comparator 1 Control .................................................. 108
SFR Definition 6.4. CPT1MD: Comparator 1 Mode Selection .................................... 109
SFR Definition 6.5. CPT0MX: Comparator0 Input Channel Select ............................. 111
SFR Definition 6.6. CPT1MX: Comparator1 Input Channel Select ............................. 112
SFR Definition 7.1. DPL: Data Pointer Low Byte ........................................................ 119
SFR Definition 7.2. DPH: Data Pointer High Byte ....................................................... 119
SFR Definition 7.3. SP: Stack Pointer ......................................................................... 120
SFR Definition 7.4. ACC: Accumulator ....................................................................... 120
SFR Definition 7.5. B: B Register ................................................................................ 120
SFR Definition 7.6. PSW: Program Status Word ........................................................ 121
SFR Definition 9.1. EMI0CN: External Memory Interface Control .............................. 128
SFR Definition 10.1. SFRPage: SFR Page ................................................................. 131
SFR Definition 11.1. IE: Interrupt Enable .................................................................... 141
SFR Definition 11.2. IP: Interrupt Priority .................................................................... 142
SFR Definition 11.3. EIE1: Extended Interrupt Enable 1 ............................................ 143
SFR Definition 11.4. EIP1: Extended Interrupt Priority 1 ............................................ 144
SFR Definition 11.5. EIE2: Extended Interrupt Enable 2 ............................................ 145
SFR Definition 11.6. EIP2: Extended Interrupt Priority 2 ............................................ 146
SFR Definition 11.7. IT01CF: INT0/INT1 Configuration .............................................. 148
SFR Definition 12.1. PSCTL: Program Store R/W Control ......................................... 157
SFR Definition 12.2. FLKEY: Flash Lock and Key ...................................................... 158
SFR Definition 12.3. FLSCL: Flash Scale ................................................................... 159
SFR Definition 12.4. FLWR: Flash Write Only ............................................................ 159
SFR Definition 13.1. PMU0CF: Power Management Unit Configuration ..................... 165
SFR Definition 13.2. PCON: Power Management Control Register ........................... 166
SFR Definition 14.1. CRC0CN: CRC0 Control ........................................................... 171
SFR Definition 14.2. CRC0IN: CRC0 Data Input ........................................................ 172
Si106x/108x
13 Rev. 1.0
SFR Definition 14.3. CRC0DAT: CRC0 Data Output .................................................. 172
SFR Definition 14.4. CRC0AUTO: CRC0 Automatic Control ...................................... 173
SFR Definition 14.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 173
SFR Definition 14.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 174
SFR Definition 15.1. DC0CN: DC-DC Converter Control ........................................... 181
SFR Definition 15.2. DC0CF: DC-DC Converter Configuration .................................. 182
SFR Definition 16.1. REG0CN: Voltage Regulator Control ........................................ 184
SFR Definition 17.1. VDM0CN: VDD_MCU Supply Monitor Control .......................... 189
SFR Definition 17.2. RSTSRC: Reset Source ............................................................ 191
SFR Definition 18.1. CLKSEL: Clock Select ............................................................... 197
SFR Definition 18.2. OSCICN: Internal Oscillator Control .......................................... 198
SFR Definition 18.3. OSCICL: Internal Oscillator Calibration ..................................... 198
SFR Definition 18.4. OSCXCN: External Oscillator Control ........................................ 199
SFR Definition 19.1. RTC0KEY: SmaRTClock Lock and Key .................................... 204
SFR Definition 19.2. RTC0ADR: SmaRTClock Address ............................................ 205
SFR Definition 19.3. RTC0DAT: SmaRTClock Data .................................................. 206
Internal Register Definition 19.4. RTC0CN: SmaRTClock Control . . . . . . . . . . . . . . . 213
Internal Register Definition 19.5. RTC0XCN: SmaRTClock Oscillator Control . . . . . . 214
Internal Register Definition 19.6. RTC0XCF: SmaRTClock Oscillator Configuration . 215
Internal Register Definition 19.7. RTC0PIN: SmaRTClock Pin Configuration . . . . . . 215
Internal Register Definition 19.8. CAPTUREn: SmaRTClock Timer Capture . . . . . . . 216
Internal Register Definition 19.9. ALARMn: SmaRTClock Alarm Programmed Value 216
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0 .......................................... 224
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1 .......................................... 225
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2 .......................................... 226
SFR Definition 20.4. P0MASK: Port0 Mask Register .................................................. 227
SFR Definition 20.5. P0MAT: Port0 Match Register ................................................... 227
SFR Definition 20.6. P1MASK: Port1 Mask Register .................................................. 228
SFR Definition 20.7. P1MAT: Port1 Match Register ................................................... 228
SFR Definition 20.8. P0: Port0 .................................................................................... 230
SFR Definition 20.9. P0SKIP: Port0 Skip .................................................................... 230
SFR Definition 20.10. P0MDIN: Port0 Input Mode ...................................................... 231
SFR Definition 20.11. P0MDOUT: Port0 Output Mode ............................................... 231
SFR Definition 20.12. P0DRV: Port0 Drive Strength .................................................. 232
SFR Definition 20.13. P1: Port1 .................................................................................. 233
SFR Definition 20.14. P1SKIP: Port1 Skip .................................................................. 233
SFR Definition 20.15. P1MDIN: Port1 Input Mode ...................................................... 234
SFR Definition 20.16. P1MDOUT: Port1 Output Mode ............................................... 234
SFR Definition 20.17. P1DRV: Port1 Drive Strength .................................................. 235
SFR Definition 20.18. P2: Port2 .................................................................................. 235
SFR Definition 20.19. P2SKIP: Port2 Skip .................................................................. 236
SFR Definition 20.20. P2MDIN: Port2 Input Mode ...................................................... 236
SFR Definition 20.21. P2MDOUT: Port2 Output Mode ............................................... 237
SFR Definition 20.22. P2DRV: Port2 Drive Strength .................................................. 237
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration ...................................... 273
Rev. 1.0 14
Si106x/108x
SFR Definition 28.2. SMB0CN: SMBus Control .......................................................... 275
SFR Definition 28.3. SMB0ADR: SMBus Slave Address ............................................ 278
SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask .................................. 278
SFR Definition 28.5. SMB0DAT: SMBus Data ............................................................ 281
SFR Definition 29.1. SCON0: Serial Port 0 Control .................................................... 295
SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 296
SFR Definition 30.7. SPI0CFG: SPI0 Configuration ................................................... 305
SFR Definition 30.8. SPI0CN: SPI0 Control ............................................................... 306
SFR Definition 30.9. SPI0CKR: SPI0 Clock Rate ....................................................... 307
SFR Definition 30.10. SPI0DAT: SPI0 Data ............................................................... 307
SFR Definition 31.1. CKCON: Clock Control .............................................................. 312
SFR Definition 31.2. TCON: Timer Control ................................................................. 317
SFR Definition 31.3. TMOD: Timer Mode ................................................................... 318
SFR Definition 31.4. TL0: Timer 0 Low Byte ............................................................... 319
SFR Definition 31.5. TL1: Timer 1 Low Byte ............................................................... 319
SFR Definition 31.6. TH0: Timer 0 High Byte ............................................................. 320
SFR Definition 31.7. TH1: Timer 1 High Byte ............................................................. 320
SFR Definition 31.8. TMR2CN: Timer 2 Control ......................................................... 324
SFR Definition 31.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 325
SFR Definition 31.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 325
SFR Definition 31.11. TMR2L: Timer 2 Low Byte ....................................................... 326
SFR Definition 31.12. TMR2H Timer 2 High Byte ....................................................... 326
SFR Definition 31.13. TMR3CN: Timer 3 Control ....................................................... 330
SFR Definition 31.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 331
SFR Definition 31.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 331
SFR Definition 31.16. TMR3L: Timer 3 Low Byte ....................................................... 332
SFR Definition 31.17. TMR3H Timer 3 High Byte ....................................................... 332
SFR Definition 32.1. PCA0CN: PCA Control .............................................................. 346
SFR Definition 32.2. PCA0MD: PCA Mode ................................................................ 347
SFR Definition 32.3. PCA0PWM: PCA PWM Configuration ....................................... 348
SFR Definition 32.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 349
SFR Definition 32.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 350
SFR Definition 32.6. PCA0H: PCA Counter/Timer High Byte ..................................... 350
SFR Definition 32.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 351
SFR Definition 32.8. PCA0CPHn: PCA Capture Module High Byte ........................... 351
C2 Register Definition 34.1. C2ADD: C2 Address ...................................................... 353
C2 Register Definition 34.2. DEVICEID: C2 Device ID ............................................... 354
C2 Register Definition 34.3. REVID: C2 Revision ID .................................................. 354
C2 Register Definition 34.4. FPCTL: C2 Flash Programming Control ........................ 355
C2 Register Definition 34.5. FPDAT: C2 Flash Programming Data ............................ 355
Rev. 1.0 15
Si106x/108x
1. System Overview
Silicon Laboratories’ Si106x Wireless MCUs combine high-performance wireless connectivity and ultra-low
power microcontroller processing into a small 5x6 mm form factor. Support for major frequency bands in
the 142 to 1050 MHz range is provided including an integrated advanced packet handling engine and the
ability to realize a link budget of up to 146 dB. The devices have been optimized to minimize energy con-
sumption for battery-backed applications by minimizing TX, RX, active, and sleep mode current as well as
supporting fast wake-up times. The Si106x and Si108x Wireless MCUs are pin-compatible and can scale
from 8 to 64 kB of flash and provides a robust set of analog and digital peripherals including an ADC, dual
comparators, timers, and GPIO. All devices are designed to be compliant with the 802.15.4g smart meter-
ing standard and support worldwide regulatory standards including FCC, ETSI, and ARIB. Refer to
Table 2.1 for specific product feature selection and part ordering numbers.
With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the Si106x devices are
truly standalone system-on-a-chip solutions. The flash memory can be reprogrammed even in-circuit, pro-
viding non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has
complete control of all peripherals, and may individually shut down any or all peripherals for power sav-
ings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, and run and halt commands. All analog and digital peripherals are fully functional while debug-
ging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging
without occupying package pins.
Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C).
Select devices will work down to 0.9 V with the dc-dc boost converter, supporting operation on a single
alkaline cell battery. The Port I/O and RST pins are tolerant of input signals up to 5 V. The Si106x devices
are available in a 36-pin QFN package (lead-free and RoHS compliant). See Table 2.1 for ordering infor-
mation. See Figure 1.1 for the block diagram.
The transceiver's extremely low receive sensitivity (–126 dBm) coupled with industry leading +20 dBm out-
put power ensures extended range and improved link performance. Built-in antenna diversity and support
for frequency hopping can be used to further extend range and enhance performance. The advanced radio
supports major frequency bands in the 119 to 1050 MHz range. The Si106x family includes optimal phase
noise, blocking, and selectivity performance for narrow band and licensed band applications such as FCC
Part90 and 169 MHz wireless Mbus. The 60 dB adjacent channel selectivity with 12.5 kHz channel spacing
ensures robust receive operation in harsh RF conditions, which is particularly important for narrow band
operation.
The Si106x offers exceptional output power of up to +20 dBm with outstanding TX efficiency. The high out-
put power and sensitivity results in an industry-leading link budget of 146 dB allowing extended ranges and
highly robust communication links. The active mode TX current consumption of 18 mA at +10 dBm and RX
current of 10 mA coupled with extremely low standby current and fast wake times ensure extended battery
life in the most demanding applications. The Si106x wireless MCUs can achieve up to +27 dBm output
power with built-in ramping control of a low-cost external FET. The devices are highly flexible and can be
configured via Silicon Labs’ graphical configuration tools.
Si106x/108x
16 Rev. 1.0
Figure 1.1. Si106x/Si108x Block Diagram
CIP-51 8051
Controller Core
ISP Flash
Program Memory
SRAM
SFR
Bus
XRAM
VDD
P0.2/XTAL1
SYSCLK
System Clock
Configuration
External
Oscillator
Circuit
Precision
24.5 MHz
Oscillator
Debug /
Programming
Hardware
Power On
Reset/PMU
Reset
C2D
RST/C2CK
Wake
P0.3/XTAL2
Low Power
20 MHz
Oscillator
SmaRTClock
Oscillator
XTAL3
XTAL4
GND
VREG
CRC
Engine
RXp
RXn
TX
XIN
XOUT
Analog Peripherals
Comparators
+
-
10-bit
300ksps
ADC
A
M
U
X
Temp
Sensor
External
VREF
Internal
VREF VDD
VREF
GND
CP0, CP0A
+
-
CP1, CP1A
RF XCVR
OSC
PA
LNA
AGC
Mixer
PGA
ADC
Port I/O
Config
Digital Peripherals
UART
Timers 0,
1, 2, 3
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
Transceiver Control Interface
SPI 0
11 ANALOG &
DIGITAL I/O
GPIO
LDO
POR VDD
Modem
FIFO
Packet
Handler
Digital
Logic
4
Rev. 1.0 17
Si106x/108x
1.1. Typical Connection Diagram
The application shown in Figure 1.2 is designed for a system with a TX/RX direct-tie configuration without
the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie
reference design is available from Silicon Laboratories applications support.
For applications seeking improved performance in the presence of multipath fading, antenna diversity can
be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the
system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range
increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applica-
tions support.
Figure 1.2. Si106x/108x RX/TX Direct-Tie Application Example
Figure 1.3. Si106x/108x Antenna Diversity Application Example
Si106x/108x
18 Rev. 1.0
1.2. CIP-51™ Microcontroller Core
1.2.1. Fully 8051 Compatible
The Si106x/108x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used
to develop software. The CIP-51 core offers all the peripherals included with a standard 8052.
1.2.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.2.3. Additional Features
The Si106x/108x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous
analog and digital peripherals to interrupt the controller. An interrupt driven system requires less interven-
tion by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when
building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a watchdog timer, a Missing Clock Detector, SmaRT-
Clock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an exter-
nal reset pin, and an illegal flash access protection circuit. Each reset source except for the POR, Reset
Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in
software after a power-on reset during MCU initialization.
The internal oscillator factory is calibrated to 24.5 MHz and is accurate to ±2% over the full temperature
and supply range. The internal oscillator period can also be adjusted by user firmware. An additional
20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator
drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock
source to generate the system clock. If desired, the system clock source may be switched between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 7 3 1 2 1
Rev. 1.0 19
Si106x/108x
1.3. Port Input/Output
Digital and analog resources are available through 11 I/O pins. Four additional GPIO pins are available
through the radio peripheral. Port pins are organized as three byte-wide ports. Port pins P0.0–P0.6 and
P1.4–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal
digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog
resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section
“33. Device Specific Behavior” on page 352 for more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins and is limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “20.3. Priority Crossbar Decoder” on
page 221 for more information on the crossbar.
All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog func-
tions can operate up to the VDD_MCU supply voltage. See Section “20.1. Port I/O Modes of Operation” on
page 218 for more information on Port I/O operating modes and the electrical specifications chapter for
detailed electrical specifications.
Figure 1.4. Port I/O Functional Block Diagram
XBR0, XBR1,
XBR2, PnSKIP
Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.6
8
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
7
PCA
4
CP0
CP1
Outputs
SPI0
SPI1
4
P1
I/O
Cells
P1.4
P1.5
8
(Port Latches)
P0 (P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
P2
I/O
Cell
P2 (P2.0-P2.7)
8
8
PnMDOUT,
PnMDIN Registers
No analog functionality
available on P2.7
P1.6
P2.7
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, AGND)
Note: P0.7, P1.0, P1.1, P1.2 and P1.3 are internally connected to the
radio peripheral. P1.7 and P2.0 – P2.6 are not internally or externally
connected.
External Interrupts
EX0 and EX1
Si106x/108x
20 Rev. 1.0
1.4. Serial Ports
The Si106x/108x family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate
configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware
and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There is
also a dedicated radio serial interface (SPI1) to allow communication with the radio peripheral.
1.5. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or
the external oscillator clock source divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Addi-
tionally, Capture/Compare Module 5 offers watchdog timer capabilities. Following a system reset, Module 5
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Figure 1.5. PCA Block Diagram
Capture/ Compare
Module 1
Capture/ Compare
Module 0
Capture/ Compare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16 -Bit Counter/Timer
PCA
CLOCK
MUX
/
Capture/ Compare
Module 4
Capture/ Compare
Module 3
Capture/ Compare
Module 5 / WDT
CEX4
CEX5
CEX3
8
/
/12
0
SYSCLK
SYSCLK 4
Timer Overflow
ECI
SYSCLK
External Clock
Rev. 1.0 21
Si106x/108x
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
Si106x/108x devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power
Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in
a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automati-
cally average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional
CPU intervention.
The ADC can sample the voltage at any of the MCU GPIO pins (with the exception of P2.7) and has an on-
chip attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
Figure 1.6. ADC0 Functional Block Diagram
ADC0CF
AMP0GN
AD0TM
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100 CNVSTR Input
Window
Compare
Logic
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN+
From
AMUX0
Burst Mode Logic
ADC0TK
ADC0PWR
16-Bit Accumulator
Si106x/108x
22 Rev. 1.0
Figure 1.7. ADC0 Multiplexer Block Diagram
1.7. Comparators
Si106x/108x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0),
which is shown in Figure 1.8, and Comparator 1 (CPT1), which is shown in Figure 1.9. The two compara-
tors operate identically but may differ in their ability to be used as reset or wake-up sources. See Section
“17. Reset Sources” on page 185 and Section “13. Power Management” on page 160 for details on reset
sources and low power mode wake-up sources, respectively.
The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches. See Application Note “AN338: Capacitive Touch Sense
Solution” for details on Capacitive Touch Switch sensing.
ADC0
Temp
Sensor
AMUX
ADC0MX
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
AIN+
P0.0
P2.6*
*P1.0 – P1.4 are not
available as device pins
Digital Supply
VDD_MCU
Programmable
Attenuator
Gain = 0. 5 or 1
Rev. 1.0 23
Si106x/108x
Figure 1.8. Comparator 0 Functional Block Diagram
Figure 1.9. Comparator 1 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
Px.x
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0 CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge
CP0
Falling-edge
CP0
Interrupt
Px.x
Px.x
Px.x
CP0 -
(ASYNCHRONOUS)
Analog Input Multiplexer
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
Px.x
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0 CPT0MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge
CP1
Falling-edge
CP1
Interrupt
Px.x
Px.x
Px.x
CP1 -
(ASYNCHRONOUS)
Analog Input Multiplexer
24 Rev. 1.0
2. Si106x/108x Ordering Information
Table 2.1. Orderable Part Number
Orderable Part
Number Radio Flash RAM DC-DC
Boost Frequency Max
Output
Power
Max Data
Rate Sensitivity Advanced
Features*
142-175 MHz
283-350 MHz
425-525 MHz
850-960 MHz
960-1050 MHz
Max 40Kbps,
GFSK
Si1060-A-GM EZRadioPro 64 KB 4 KB No +20 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1062-A-GM EZRadioPro 64 KB 4 KB Yes +13 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1064-A-GM EZRadio 64 KB 4 KB Yes +13 dBm 500 kbps -116 dBm -108 dBm No
Si1061-A-GM EZRadioPro 32 KB 4 KB No +20 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1063-A-GM EZRadioPro 32 KB 4 KB Yes +13 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1065-A-GM EZRadio 32 KB 4 KB Yes +13 dBm 500 kbps -116 dBm -108 dBm No
Si1080-A-GM EZRadioPro 16 KB 768 bytes No +20 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1082-A-GM EZRadioPro 16 KB 768 bytes Yes +13 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1084-A-GM EZRadio 16 KB 768 bytes Yes +13 dBm 500 kbps -116 dBm -108 dBm No
Si1081-A-GM EZRadioPro 8 KB 768 bytes No +20 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1083-A-GM EZRadioPro 8 KB 768 bytes Yes +13 dBm 1 Mbps -126 dBm -110 dBm Yes
Si1085-A-GM EZRadio 8 KB 768 bytes Yes +13 dBm 500 kbps -116 dBm -108 dBm No
*Note: Advanced features include antenna diversity, narrowband support and autonomous low-duty cycle support.
Rev. 1.0 25
Si106x/108x
3. Pinout and Package Definitions
Table 3.1. Si1060/Si1061/Si1080/Si1081 Pin Definitions
Pin Designation Description
1P2.7/C2D Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route
signals to this pin and it cannot be configured as an analog input. See Port
I/O section for a complete
description. Bi-directional data signal for the C2 Debug Interface.
2XTAL4 SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
3XTAL3 SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
4P1.6 Port 1.6. See Port I/O section for a complete description.
5P1.5 Port 1.5. See Port I/O section for a complete description.
6P1.4 Port 1.4. See Port I/O section for a complete description.
7XOUT Crystal Oscillator Output.
Connect to an external 25 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
8XIN Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal, or connect to an external
source.
9GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
10 GPIO2 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
11 GPIO3 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
12 RXP EZRadioPRO peripheral differential RF input pins of the LNA. See applica-
tion schematic for example matching network.
13 RXN EZRadioPRO peripheral differential RF input pins of the LNA. See applica-
tion schematic for example matching network.
14 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
15 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
Si106x/108x
26 Rev. 1.0
16 TX EZRadioPRO peripheral transmit RF output pin. The PA output is an open-
drain connection so the L-C match must supply 1.8 to 3.6 VDC to this pin.
17 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
18 VDD_RF Power Supply Voltage for the analog portion of the EZRadioPRO periph-
eral. Must be 1.8 to 3.6 V.
19 TXRAMP Programmable Bias Output with Ramp Capability for external FET PA.
20 VDD_RF Power Supply Voltage for the analog portion of the EZRadioPRO periph-
eral. Must be 1.8 to 3.6 V.
21 GPIO0 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
22 GPIO1 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
23 IRQ EZRadioPRO peripheral interrupt status pin. Will be set low to indicate a
pending EZRadioPRO interrupt event. See the EZRadioPRO Control Logic
Registers for more details. This pin is an open-drain output with a 220 k
internal pullup resistor. An external pull-up resistor is recommended.
24 P0.6/CNVSTR Port 0.6. See Port I/O section for a complete description.
External Convert Start Input for ADC0. See ADC0 section for a complete
description.
25 P0.5/RX Port 0.5. See Port I/O section for a complete description.
UART RX Pin. See Port I/O section.
26 P0.4/TX Port 0.4. See Port I/O section for a complete description.
UART TX Pin. See Port I/O section.
27 P0.3/XTAL2 Port 0.3. See Port I/O Section for a complete description.
External Clock Output. This pin is the excitation driver for an external crystal
or resonator.
External Clock Input. This pin is the external clock input in external CMOS
clock mode.
External Clock Input. This pin is the external clock input in capacitor or RC
oscillator configurations.
See Oscillator section for complete details.
28 P0.2/XTAL1 Port 0.2. See Port I/O Section for a complete description.
External Clock Input. This pin is the external oscillator return for a crystal or
resonator. See Oscillator section.
Table 3.1. Si1060/Si1061/Si1080/Si1081 Pin Definitions (Continued)
Pin Designation Description
Rev. 1.0 27
Si106x/108x
29 P0.1/AGND Port 0.1. See Port I/O Section for a complete description.
Optional Analog ground. See VREF chapter.
30 P0.0/VREF Port 0.0. See Port I/O section for a complete description.
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors are recom-
mended. See Voltage Reference section.
31 GND_MCU Required ground for the entire MCU except for the EZRadioPRO peripheral
32 NC No Connect
33 VDD_MCU Power Supply Voltage for the entire MCU except for the EZRadioPRO
peripheral. Must be 1.8 to 3.6 V. This supply voltage is not required in low
power sleep mode. This voltage must always be > VBAT.
34 NC No Connect
35 NC No Connect
36 RST/C2CK Device Reset. Open-drain output of internal POR or VDD monitor. An exter-
nal source can initiate a system reset by driving this pin low for at least 15
μs. A 1–5 k pullup to VDD_MCU is recommended. See Reset Sources sec-
tion for a complete description.
Clock signal for the C2 Debug Interface.
Table 3.1. Si1060/Si1061/Si1080/Si1081 Pin Definitions (Continued)
Pin Designation Description
Si106x/108x
28 Rev. 1.0
Table 3.2. Si1062/Si1063/Si1082/Si1083 Pin Definitions
Pin Designation Description
1P2.7/C2D Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route sig-
nals to this pin and it cannot be configured as an analog input. See Port I/O
section for a complete
description. Bi-directional data signal for the C2 Debug Interface.
2XTAL4 SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
3XTAL3 SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
4P1.6 Port 1.6. See Port I/O section for a complete description.
5P1.5 Port 1.5. See Port I/O section for a complete description.
6P1.4 Port 1.4. See Port I/O section for a complete description.
7XOUT Crystal Oscillator Output.
Connect to an external 25 to 32 MHz crystal or leave floating when driving
with an external source on XIN.
8XIN Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal or connect to an external source.
9GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
10 GPIO2 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
11 GPIO3 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer,
TRSW, AntDiversity control, etc. See the EZRadioPRO GPIO Configuration
Registers for more information.
12 RXP EZRadioPRO peripheral differential RF input pins of the LNA. See application
schematic for example matching network.
13 RXN EZRadioPRO peripheral differential RF input pins of the LNA. See application
schematic for example matching network.
14 TX EZRadioPRO peripheral transmit RF output pin. The PA output is an open-
drain connection so the L-C match must supply 1.8 to 3.6 VDC to this pin.
15 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
16 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
17 GND_RF Required ground for the digital and analog portions of the EZRadioPRO
peripheral.
Rev. 1.0 29
Si106x/108x
18 VDD_RF Power Supply Voltage for the analog portion of the EZRadioPRO peripheral.
Must be 1.8 to 3.6 V.
19 TXRAMP Programmable Bias Output with Ramp Capability for External FET PA.
20 VDD_RF Power Supply Voltage for the analog portion of the EZRadioPRO peripheral.
Must be 1.8 to 3.6 V.
21 GPIO0 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW,
AntDiversity control, etc. See the EZRadioPRO GPIO Configuration Regis-
ters for more information.
22 GPIO1 General Purpose I/O controlled by the EZRadioPRO peripheral.
May be configured through the EZRadioPRO registers to perform various
functions including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW,
AntDiversity control, etc. See the EZRadioPRO GPIO Configuration Regis-
ters for more information.
23 IRQ EZRadioPRO peripheral interrupt status pin. Will be set low to indicate a
pending EZRadioPRO interrupt event. See the EZRadioPRO Control Logic
Registers for more details. This pin is an open-drain output with a 220 k inter-
nal pullup resistor. An external pull-up resistor is recommended.
24 P0.6/CNVSTR Port 0.6. See Port I/O section for a complete description.
External Convert Start Input for ADC0. See ADC0 section for a complete
description.
25 P0.5/RX Port 0.5. See Port I/O section for a complete description.
UART RX Pin. See Port I/O section.
26 P0.4/TX Port 0.4. See Port I/O section for a complete description.
UART TX Pin. See Port I/O section.
27 P0.3/XTAL2 Port 0.3. See Port I/O Section for a complete description.
External Clock Output. This pin is the excitation driver for an external crystal
or resonator.
External Clock Input. This pin is the external clock input in external CMOS
clock mode.
External Clock Input. This pin is the external clock input in capacitor or RC
oscillator configurations.
See Oscillator section for complete details.
28 P0.2/XTAL1 Port 0.2. See Port I/O Section for a complete description.
External Clock Input. This pin is the external oscillator return for a crystal or
resonator. See Oscillator section.
29 P0.1/AGND Port 0.1. See Port I/O Section for a complete description.
Optional Analog ground. See VREF chapter.
Table 3.2. Si1062/Si1063/Si1082/Si1083 Pin Definitions (Continued)
Pin Designation Description
Si106x/108x
30 Rev. 1.0
30 P0.0/VREF Port 0.0. See Port I/O section for a complete description.
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors are recom-
mended. See Voltage Reference section.
31 GND_MCU/DC- DC-DC converter return current path. In single-cell battery mode, this pin is
typically not connected to ground.
In dual-cell battery mode, this pin must be connected directly to ground.
32 GND_MCU/
VBAT–
Required ground for the entire MCU except for the EZRadioPRO
peripheral.
33 VDD_MCU/DC+ Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is not
required in low power sleep mode. This voltage must always be > VBAT.
Positive output of the dc-dc converter. In single-cell battery mode, a 1 μF
ceramic capacitor is required between DC+ and DC–. This pin can supply
power to external devices when operating in single-cell battery mode.
34 DCEN DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to
VBAT through a 0.68 μH inductor.
In dual-cell battery mode, this pin must be connected directly to ground.
35 VBAT+ Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and
1.8 to 3.6 V in dual-cell battery mode.
36 RST/C2CK Device Reset. Open-drain output of internal POR or VDD monitor. An exter-
nal source can initiate a system reset by driving this pin low for at least 15 μs.
A 1–5 k pullup to VDD_MCU is recommended. See Reset Sources section for
a complete description.
Clock signal for the C2 Debug Interface.
Table 3.2. Si1062/Si1063/Si1082/Si1083 Pin Definitions (Continued)
Pin Designation Description
Rev. 1.0 31
Si106x/108x
Table 3.3. Si1064/Si1065/Si1084/Si1085 Pin Definitions
Pin Designation Description
1P2.7/C2D Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route signals
to this pin and it cannot be configured as an analog input. See Port I/O section for
a complete
description. Bi-directional data signal for the C2 Debug Interface.
2XTAL4 SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
3XTAL3 SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
4P1.6 Port 1.6. See Port I/O section for a complete description.
5P1.5 Port 1.5. See Port I/O section for a complete description.
6P1.4 Port 1.4. See Port I/O section for a complete description.
7XOUT Crystal Oscillator Output.
8XIN Crystal Oscillator Input.
No bias required, but if used should be set to 0.7V. Also used for external TCXO
input.
9GND_RF Required ground for the digital and analog portions of the EZRadio peripheral.
10 GPIO2 General Purpose I/O controlled by the EZRadio peripheral.
May be configured through the EZRadio registers to perform various functions
including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW, AntDiversity
control, etc. See the EZRadio GPIO Configuration Registers for more information.
11 GPIO3 General Purpose I/O controlled by the EZRadio peripheral.
May be configured through the EZRadio registers to perform various functions
including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW, AntDiversity
control, etc. See the EZRadio GPIO Configuration Registers for more information.
12 RXP EZRadio peripheral differential RF input pins of the LNA. See application sche-
matic for example matching network.
13 RXN EZRadio peripheral differential RF input pins of the LNA. See application sche-
matic for example matching network.
14 TX EZRadio peripheral transmit RF output pin. The PA output is an open-drain con-
nection so the L-C match must supply 1.8 to 3.6 VDC to this pin.
15 GND_RF Required ground for the digital and analog portions of the EZRadio peripheral.
16 GND_RF Required ground for the digital and analog portions of the EZRadio peripheral.
17 GND_RF Required ground for the digital and analog portions of the EZRadio peripheral.
18 VDD_RF Power Supply Voltage for the analog portion of the EZRadio peripheral. Must be
1.8 to 3.6 V.
19 NC No Connect
20 VDD_RF Power Supply Voltage for the analog portion of the EZRadio peripheral. Must be
1.8 to 3.6 V.
Si106x/108x
32 Rev. 1.0
21 GPIO0 General Purpose I/O controlled by the EZRadio peripheral.
May be configured through the EZRadio registers to perform various functions
including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW, AntDiversity
control, etc. See the EZRadio GPIO Configuration Registers for more information.
22 GPIO1 General Purpose I/O controlled by the EZRadio peripheral.
May be configured through the EZRadio registers to perform various functions
including: Clock Output, FIFO status, POR, Wake-Up Timer, TRSW, AntDiversity
control, etc. See the EZRadio GPIO Configuration Registers for more information.
23 IRQ EZRadio peripheral interrupt status pin. Will be set low to indicate a pending
EZRadio interrupt event. See the EZRadio Control Logic Registers for more
details. This pin is an open-drain output with a 220 k internal pullup
resistor. An external pull-up resistor is recommended.
24 P0.6/
CNVSTR
Port 0.6. See Port I/O section for a complete description.
External Convert Start Input for ADC0. See ADC0 section for a complete descrip-
tion.
25 P0.5/RX Port 0.5. See Port I/O section for a complete description.
UART RX Pin. See Port I/O section.
26 P0.4/TX Port 0.4. See Port I/O section for a complete description.
UART TX Pin. See Port I/O section.
27 P0.3/XTAL2 Port 0.3. See Port I/O Section for a complete description.
External Clock Output. This pin is the excitation driver for an external crystal or
resonator.
External Clock Input. This pin is the external clock input in external CMOS clock
mode.
External Clock Input. This pin is the external clock input in capacitor or RC oscilla-
tor configurations.
See Oscillator section for complete details.
28 P0.2/XTAL1 Port 0.2. See Port I/O Section for a complete description.
External Clock Input. This pin is the external oscillator return for a crystal or reso-
nator. See Oscillator section.
29 P0.1/AGND Port 0.1. See Port I/O Section for a complete description.
Optional Analog ground. See VREF chapter.
30 P0.0/VREF Port 0.0. See Port I/O section for a complete description.
External VREF Input.
Internal VREF Output. External VREF decoupling capacitors are recommended.
See Voltage Reference section.
31 GND_MCU/
DC–
DC-DC converter return current path. In single-cell battery mode, this pin is typi-
cally not connected to ground.
In dual-cell battery mode, this pin must be connected directly to ground.
32 GND_MCU/
VBAT–
Required ground for the entire MCU except for the EZRadio peripheral.
Table 3.3. Si1064/Si1065/Si1084/Si1085 Pin Definitions (Continued)
Pin Designation Description
Rev. 1.0 33
Si106x/108x
33 VDD_MCU/
DC+
Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is not required in
low power sleep mode. This voltage must always be > VBAT.
Positive output of the dc-dc converter. In single-cell battery mode, a 1 μF ceramic
capacitor is required between DC+ and DC–. This pin can supply power to exter-
nal devices when operating in single-cell battery mode.
34 DCEN DC-DC Enable Pin. In single-cell battery mode, this pin must be connected to
VBAT through a 0.68 μH inductor.
In dual-cell battery mode, this pin must be connected directly to ground.
35 VBAT+ Battery Supply Voltage. Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to
3.6 V in dual-cell battery mode.
36 RST/C2CK Device Reset. Open-drain output of internal POR or VDD monitor. An external
source can initiate a system reset by driving this pin low for at least 15 μs. A 1–5 k
pullup to VDD_MCU is recommended. See Reset Sources section for a complete
description.
Clock signal for the C2 Debug Interface.
Table 3.3. Si1064/Si1065/Si1084/Si1085 Pin Definitions (Continued)
Pin Designation Description
Rev. 1.0 34
Si106x/108x
Figure 3.1. Si1060/1, Si1080/1-A-GM Pinout Diagram (Top View)
3017
36
35
34
33
32
31
11
12
13
14
15
16
2918
Si1060/Si1061
Si1080/Si1081
(Top View)
GPIO3
RXP
RXN
GND_RF
GND_RF
TX
GND_RF
VDD_RF
RST/C2CK
NC
NC
VDD_MCU
NC
GND_MCU
P0.0/VREF
P0.1/AGND
GND_RF
8
1
2
3
4
5
6
7
10
9
P2.7/C2D
XTAL4
XTAL3
P1.6
P1.5
P1.4
XOUT
XIN
GND_RF
GPIO2
21
28
27
26
25
24
23
22
19
20
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
IRQ
GPIO1
GPIO0
VDD_RF
TXRAMP
Si106x/108x
35 Rev. 1.0
Figure 3.2. Si1062/3, Si1082/3-A-GM Pinout Diagram (Top View)
3017
36
35
34
33
32
31
11
12
13
14
15
16
2918
Si1062/Si1063
Si1082/Si1083
(Top View)
GPIO3
RXP
RXN
TX
GND_RF
GND_RF
GND_RF
VDD_RF
RST/C2CK
VBAT+
DCEN
VDD_MCU/DC+
GND_MCU/VBAT-
GND_MCU/DC-
P0.0/VREF
P0.1/AGND
GND_RF
8
1
2
3
4
5
6
7
10
9
P2.7/C2D
XTAL4
XTAL3
P1.6
P1.5
P1.4
XOUT
XIN
GND_RF
GPIO2
21
28
27
26
25
24
23
22
19
20
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
IRQ
GPIO1
GPIO0
VDD_RF
TXRAMP
Rev. 1.0 36
Si106x/108x
Figure 3.3. Si1064/5, Si1084/5-A-GM Pinout Diagram (Top View)
3017
36
35
34
33
32
31
11
12
13
14
15
16
2918
Si1064/Si1065
Si1084/Si1085
(Top View)
GPIO3
RXP
RXN
TX
GND_RF
GND_RF
GND_RF
VDD_RF
RST/C2CK
VBAT+
DCEN
VDD_MCU/DC+
GND_MCU/VBAT-
GND_MCU/DC-
P0.0/VREF
P0.1/AGND
GND_RF
8
1
2
3
4
5
6
7
10
9
P2.7/C2D
XTAL4
XTAL3
P1.6
P1.5
P1.4
XOUT
XIN
GND_RF
GPIO2
21
28
27
26
25
24
23
22
19
20
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
IRQ
GPIO1
GPIO0
VDD_RF
NC
Si106x/108x
37 Rev. 1.0
Figure 3.4. QFN-36 Package Drawing
Rev. 1.0 38
Si106x/108x
Table 3.4. QFN-36 Package Dimensions
Dimension Min Nom Max
A0.70 0.75 0.80
A1 0.00 0.02 0.05
b0.20 0.25 0.30
D5.00 BSC
D2 3.55 3.60 3.65
e0.50 BSC
E6.00 BSC
E2 4.05 4.10 4.15
L0.30 0.40 0.50
aaa — — 0.10
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation
VHJD.
Si106x/108x
39 Rev. 1.0
Figure 3.5. QFN-36 PCB Land Pattern Dimensions
Rev. 1.0 40
Si106x/108x
Table 3.5. QFN-36 PCB Land Pattern Dimensions
Dimension mm
C1 4.90
C2 5.90
E0.50
X1 0.30
Y1 0.85
X2 3.65
Y2 4.15
Notes:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A 2x2 array of 1.550 mm x 1.300 mm square openings on 1.05 mm pitch should be used for
the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Si106x/108x
41 Rev. 1.0
Figure 3.6. QFN-36 PCB Stencil and Via Placement
Center pad paste detail:
1.550
1.300
R 0.250
1.506
Ø0.250
1.506
1.7561.756
Rev. 1.0 42
Si106x/108x
4. Electrical Characteristics
In sections 4.1 and 4.2, “VDD” refers to the VDD_MCU supply voltage on Si1060/1, Si1080/1 devices and
to the VDD_MCU/DC+ supply voltage on Si1062/3/4/5, Si1082/3/4/5 devices. The ADC, Comparator, and
Port I/O specifications in these two sections do not apply to the radio peripheral.
In section 4.3, “VDD” refers to the VDD_RF Supply Voltage. All specifications in these sections pertain to
the radio peripheral.
4.1. Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Parameter Test Condition Min Typ Max Unit
Storage Temperature –65 — 150 °C
Voltage on any Px.x I/O Pin or
RST with Respect to GND
VDD > 2.2 V
VDD < 2.2 V
–0.3
–0.3
—
—
5.8
VDD + 3.6
V
Voltage on VBAT with respect to
GND
One-Cell Mode
Two-Cell Mode
–0.3
–0.3
—
—
2.0
4.0
V
Voltage on VDD_MCU or
VDD_MCU/DC+ with respect to
GND
–0.3 — 4.0 V
Maximum Total Current through
VBAT, DCEN, VDD_MCU/DC+ or
GND
——500mA
Maximum Output Current Sunk
by RST or any Px.x Pin
——100mA
Maximum Total Current through
all Px.x Pins
——200mA
DC-DC Converter Output Power — — 110 mW
ESD (Human Body Model) All pins except TX, RXp,
and RXn
—— 2 kV
TX, RXp, and RXn — — 1 kV
ESD (Machine Model) All pins except TX, RXp,
and RXn
——150 V
TX, RXp, and RXn — — 45 V
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Si106x/108x
43 Rev. 1.0
4.2. MCU Electrical Characteristics
Table 4.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Test Condition Min Typ Max Unit
Battery Supply Voltage (VBAT) One-Cell Mode
Two-Cell Mode
0.9
1.8
1.2
2.4
1.8
3.6
V
Supply Voltage
(VDD_MCU/DC+)
One-Cell Mode
Two-Cell Mode
1.8
1.8
1.9
2.4
3.6
3.6
V
Minimum RAM Data
Retention Voltage1
VDD (not in Sleep Mode)
VBAT (in Sleep Mode)
—
—
1.4
0.3
—
0.5
V
SYSCLK (System Clock)20 — 25 MHz
TSYSH (SYSCLK High Time) 18 — — ns
TSYSL (SYSCLK Low Time) 18 — — ns
Specified Operating
Temperature Range
–40 —+85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from flash )
IDD 3, 4, 5, 6, 7, 8 VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current)
—4.1 5.0 mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—3.5 —mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO cur-
rent)
—
—
295
365
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz
(includes SmaRTClock oscillator cur-
rent)
—90 —µA
IDD Frequency Sensitivity3, 5, 6,
7. 8 VDD = 1.8–3.6 V, T = 25 °C,
F < 10 MHz (flash oneshot active, see
12.6)
—226 —µA/MHz
VDD = 1.8–3.6 V, T = 25 °C,
F > 10 MHz (flash oneshot bypassed,
see 12.6)
—120 —µA/MHz
Rev. 1.0 44
Si106x/108x
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from flash)
IDD4, 6,7,8VDD = 1.8–3.6 V, F = 24.5 MHz
(includes precision oscillator current)
—2.5 3.0 mA
VDD = 1.8–3.6 V, F = 20 MHz
(includes low power oscillator current)
—1.8 —mA
VDD = 1.8 V, F = 1 MHz
VDD = 3.6 V, F = 1 MHz
(includes external oscillator/GPIO cur-
rent)
—
—
165
235
—
—
µA
µA
VDD = 1.8–3.6 V, F = 32.768 kHz
(includes SmaRTClock oscillator
current)
—84 —µA
IDD Frequency Sensitivity1,6,8 VDD = 1.8–3.6 V, T = 25 °C—95 —µA/MHz
Digital Supply Current—Suspend and Sleep Mode
Digital Supply Current6,7,8
(Suspend Mode)
VDD = 1.8–3.6 V, two-cell mode —77 —µA
Digital Supply Current8
(Sleep Mode, SmaRTClock
running)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes SmaRTClock oscillator and
brownout detector)
—
—
—
—
—
—
0.61
0.76
0.87
1.32
1.62
1.93
—
—
—
—
—
—
µA
Digital Supply Current8
(Sleep Mode)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes brownout detector)
—
—
—
—
—
—
0.06
0.09
0.14
0.77
0.92
1.23
—
—
—
—
—
—
µA
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Test Condition Min Typ Max Unit
Si106x/108x
45 Rev. 1.0
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained
with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration
requires 3 CPU clock cycles, and the flash memory is read on each cycle. The supply current will vary slightly
based on the physical location of the sjmp instruction and the number of flash address lines that toggle as a
result. In the worst case, current can increase by up to 30% if the sjmp loop straddles a 128-byte flash
address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences
will have few transitions across the 128-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <10 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to
estimate IDD for >10 MHz, the estimate should be the current at 25 MHz minus the difference in current
indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 4.1 mA –
(25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA.
6. The Supply Voltage is the voltage at the VDD_MCU pin, typically 1.8 to 3.6 V (default = 1.9 V).
Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz –
5 MHz) x 0.095 mA/MHz = 0.6 mA.
7. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can
be estimated using the following equation:
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
8. The radio peripheral is placed in Shutdown mode.
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter Test Condition Min Typ Max Unit
VBAT Current (one-cell mode) Supply Voltage Supply Current (two-cell mode)
DC-DC Converter Efficiency VBAT Voltage
-----------------------------------------------------------------------------------------------------------------------------------
=
Rev. 1.0 46
Si106x/108x
Figure 4.1. Active Mode Current (External CMOS Clock)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
012345678910111213141516171819202122232425
Frequency (MHz)
Supply Current (uA)
F < 10 MHz
Oneshot Enabled
F > 10 MHz
Oneshot Bypassed
< 170 µA/MH
z
200 µA/MHz
240 µA/MHz
300 µA/MHz
215 µA/MHz
250 µA/MHz
Si106x/108x
47 Rev. 1.0
Figure 4.2. Idle Mode Current (External CMOS Clock)
Supply Current vs. Frequency
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Supply Current (uA)
Rev. 1.0 48
Si106x/108x
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V
Load Current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
6:6(/ 6:6(/
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ
LQGXFWRUZLWKDORZHU(65
Si106x/108x
49 Rev. 1.0
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V)
Load current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
6:6(/ 6:6(/
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV
3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\
FKRRVLQJDQLQGXFWRUZLWKDORZHU(65
Rev. 1.0 50
Si106x/108x
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V)
Load current (mA)
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV
Si106x/108x
51 Rev. 1.0
Figure 4.6. Typical One-Cell Suspend Mode Current
9%$79
9%$7&XUUHQWX$
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 9/RDG&XUUHQW X$
Rev. 1.0 52
Si106x/108x
Table 4.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Test Condition Min Typ Max Unit
Output High Voltage High Drive Strength, PnDRV.n = 1
IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
Low Drive Strength, PnDRV.n = 0
IOH = –1 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –3 mA, Port I/O push-pull
VDD – 0.7
VDD – 0.1
VDD – 0.7
VDD – 0.1
—
—
—
See Chart
—
—
See Chart
—
—
—
—
—
V
Output Low Voltage High Drive Strength, PnDRV.n = 1
IOL = 8.5 mA
IOL = 10 µA
IOL = 25 mA
Low Drive Strength, PnDRV.n = 0
IOL = 1.4 mA
IOL = 10 µA
IOL = 4 mA
—
—
—
—
—
—
—
—
See Chart
—
—
See Chart
0.6
0.1
—
0.6
0.1
—
V
Input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 — — V
VDD = 0.9 to 2.0 V 0.7 x VDD — — V
Input Low Voltage VDD = 2.0 to 3.6 V — — 0.6 V
VDD = 0.9 to 2.0 V — — 0.3 x VDD V
Input Leakage
Current
Weal Pullup Off
Weak Pullup On, VIN = 0 V, VDD = 1.8 V
Weak Pullup On, Vin = 0 V, VDD = 3.6 V
—
—
—
—
4
20
1
—
35
µA
Si106x/108x
53 Rev. 1.0
Figure 4.7. Typical VOH Curves, 1.8–3.6 V
Typical VOH (High Drive Mode)
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
0 5 10 15 20 25 30 35 40 45 50
Load Current (mA)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
Typical VOH (Low Drive Mode)
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
3.6
0123456789101112131415
Load Current (mA)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
Rev. 1.0 54
Si106x/108x
Figure 4.8. Typical VOH Curves, 0.9–1.8 V
Typical VOH (High Drive Mode)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0123456789101112
Load Current (mA)
Voltage
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
Typical VOH (Low Drive Mode)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0123
Load Current (mA)
Voltage
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
Si106x/108x
55 Rev. 1.0
Figure 4.9. Typical VOL Curves, 1.8–3.6 V
Typical VOL (High Drive Mode)
0
0.3
0.6
0.9
1.2
1.5
1.8
-80 -70 -60 -50 -40 -30 -20 -10 0
Load Current (mA)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
Typical VOL (Low Drive Mode)
0
0.3
0.6
0.9
1.2
1.5
1.8
-10-9-8-7-6-5-4-3-2-1 0
Load Current (mA)
Voltage
VDD = 3.6V
VDD = 3.0V
VDD = 2.4V
VDD = 1.8V
Rev. 1.0 56
Si106x/108x
Figure 4.10. Typical VOL Curves, 0.9–1.8 V
Typical VOL (High Drive Mode)
0
0.1
0.2
0.3
0.4
0.5
-5 -4 -3 -2 -1 0
Load Current (mA)
Voltage
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
Typical VOL (Low Drive Mode)
0
0.1
0.2
0.3
0.4
0.5
-3 -2 -1 0
Load Current (mA)
Voltage
VDD = 1.8V
VDD = 1.5V
VDD = 1.2V
VDD = 0.9V
Si106x/108x
57 Rev. 1.0
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
RST Output Low Voltage IOL = 1.4 mA, — — 0.6 V
RST Input High Voltage VDD = 2.0 to 3.6 V VDD – 0.6 — — V
VDD = 0.9 to 2.0 V 0.7 x VDD — — V
RST Input Low Voltage VDD = 2.0 to 3.6 V — — 0.6 V
VDD = 0.9 to 2.0 V — — 0.3 x VDD V
RST Input Pullup Current RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
—
—
4
20
—
35
µA
VDD_MCU Monitor
Threshold (VRST)
Early Warning
Reset Trigger
(all power modes except Sleep)
1.8
1.7
1.85
1.75
1.9
1.8
V
VDD Ramp Time for Power
On
One-cell Mode: VBAT Ramp 0–0.9 V
Two-cell Mode: VBAT Ramp 0–1.8 V
— — 3 ms
VDD Monitor Threshold
(VPOR)
Initial Power-On (VDD Rising)
Brownout Condition (VDD Falling)
Recovery from Brownout (VDD Rising)
—
0.7
—
0.75
0.8
0.95
—
0.9
—
V
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100 650 1000 µs
Minimum System Clock w/
Missing Clock Detector
Enabled
System clock frequency which triggers
a missing clock detector timeout
— 7 10 kHz
Reset Time Delay Delay between release of any reset
source and code
execution at location 0x0000
—10 —µs
Minimum RST Low Time to
Generate a System Reset
15 — — µs
VDD Monitor Turn-on Time —300 —ns
VDD Monitor Supply
Current
— 7 — µA
Rev. 1.0 58
Si106x/108x
Table 4.5. Power Management Electrical Specifications
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Idle Mode Wake-up Time 2 — 3 SYSCLKs
Suspend Mode Wake-up Time Low power oscillator —400 — ns
Precision oscillator —1.3 —µs
Sleep Mode Wake-up Time Two-cell mode — 2 — µs
One-cell mode —10 —µs
Table 4.6. Flash Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Flash Size Si1060, Si1062, Si1064 65536 — — bytes
Si1061, Si1063, Si1065 32768 — — bytes
Si1080, Si1082, Si1084 16384 — — bytes
Si1081, Si1083, Si1085 8192 — — bytes
Scratchpad Size Si1060-Si1065 1024 —1024 bytes
Si1080-Si1085 512 —512 bytes
Endurance 1k 30k —Erase/Write
Cycles
Erase Cycle Time 28 32 36 ms
Write Cycle Time 57 64 71 µs
Notes:
1. 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved.
2. 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved.
Si106x/108x
59 Rev. 1.0
Table 4.7. Internal Precision Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Test Condition Min Typ Max Unit
Oscillator Frequency 24 24.5 25 MHz
Oscillator Supply Current
(from VDD)
25 °C; includes bias current
of 90–100 µA —300*— µA
*Note: Does not include clock divider or clock tree supply current.
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics
VDD = 1.8 to 3.6 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Test Condition Min Typ Max Unit
Oscillator Frequency 18 20 22 MHz
Oscillator Supply Current
(from VDD)
25 °C
No separate bias current
required.
— 100* — µA
*Note: Does not include clock divider or clock tree supply current.
Rev. 1.0 60
Si106x/108x
Table 4.9. ADC0 Electrical Characteristics
VDD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
DC Accuracy
Resolution 10 bits
Integral Nonlinearity —±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic —±0.5 ±1 LSB
Offset Error —±<1 ±2 LSB
Full Scale Error —±1 ±2.5 LSB
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 300 ksps)
Signal-to-Noise Plus Distortion 54 58 —dB
Signal-to-Distortion —73 —dB
Spurious-Free Dynamic Range —75 —dB
Conversion Rate
SAR Conversion Clock — — 7.33 MHz
Conversion Time in SAR Clocks 10-bit Mode
8-bit Mode
13
11
—
—
—
—
clocks
Track/Hold Acquisition Time 1.5 — — us
Throughput Rate — — 300 ksps
Analog Inputs
ADC Input Voltage Range Single Ended (AIN+ – GND) 0 — VREF V
Absolute Pin Voltage with respect
to GND
Single Ended 0 — VDD V
Sampling Capacitance 1x Gain
0.5x Gain
—30
28
—pF
Input Multiplexer Impedance — 5 — k
Power Specifications
Power Supply Current
(VDD supplied to ADC0)
Conversion Mode (300 ksps)
Tracking Mode (0 ksps)
—
—
800
680
—
—
µA
Power Supply Rejection Internal High Speed VREF
External VREF
—
—
67
74
—
—
dB
Si106x/108x
61 Rev. 1.0
Table 4.10. Temperature Sensor Electrical Characteristics
VDD = 1.8 to 3.6V V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Linearity —±1 —°C
Slope —3.40 —mV/°C
Slope Error1—40 —µV/°C
Offset Temp = 25 °C —1025 —mV
Offset Error1Temp = 25 °C —18 —mV
Temperature Sensor Settling
Time2Initial Voltage=0 V
Initial Voltage=3.6 V
— — 3.0
6.5
µs
Supply Current —35 —µA
Notes:
1. Represents one standard deviation from the mean.
2. The temperature sensor settling time is guaranteed by characterization. The temperature sensor settling time,
resulting from an ADC mux change or enabling of the temperature sensor, varies with the voltage of the
previously sampled channel and can be up to 6.5 µs if the previously sampled channel voltage was greater
than 3 V. To minimize the temperature sensor settling time, the ADC mux can be momentarily set to ground
before being set to the temperature sensor output. This ensures that the temperature sensor output will settle
in 3 µs or less.
Rev. 1.0 62
Si106x/108x
Table 4.11. Voltage Reference Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Internal High-Speed Reference (REFSL[1:0] = 11)
Output Voltage –40 to +85 °C,
VDD = 1.8–3.6 V
1.60 1.65 1.70 V
VREF Turn-on Time* — — 1.7 µs
Supply Current —200 —µA
Internal Precision Reference (REFSL[1:0] = 00, REFOE = 1)
Output Voltage –40 to +85 °C,
VDD = 1.8–3.6 V
1.645 1.680 1.715 V
VREF Short-Circuit Current —3.5 —mA
Load Regulation Load = 0 to 200 µA to AGND —400 —µV/µA
VREF Turn-on Time 1 4.7 µF tantalum, 0.1 µF ceramic
bypass, settling to 0.5 LSB
—15 —ms
VREF Turn-on Time 2 0.1 µF ceramic bypass, settling to
0.5 LSB
—300 —µs
VREF Turn-on Time 3 no bypass cap, settling to 0.5 LSB —25 —µs
Supply Current —15 —µA
External Referenc e (REFSL[1:0] = 00, REFOE = 0)
Input Voltage Range 0 — VDD V
Input Current Sample Rate = 300 ksps; VREF =
3.0 V
—5.25 —µA
*Note: Guaranteed by characterization.
Si106x/108x
63 Rev. 1.0
Table 4.12. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter Test Condition Min Typ Max Unit
Response Time:
Mode 0, VDD = 2.4 V, VCM* = 1.2 V
CP0+ – CP0– = 100 mV —130 —ns
CP0+ – CP0– = –100 mV —200 —ns
Response Time:
Mode 1, VDD = 2.4 V, VCM* = 1.2 V
CP0+ – CP0– = 100 mV —210 —ns
CP0+ – CP0– = –100 mV —410 —ns
Response Time:
Mode 2, VDD = 2.4 V, VCM* = 1.2 V
CP0+ – CP0– = 100 mV —420 —ns
CP0+ – CP0– = –100 mV —1200 —ns
Response Time:
Mode 3, VDD = 2.4 V, VCM* = 1.2 V
CP0+ – CP0– = 100 mV —1750 —ns
CP0+ – CP0– = –100 mV —6200 —ns
Common-Mode Rejection Ratio —1.5 4mV/V
Inverting or Non-Inverting Input
Voltage Range
–0.25 — VDD + 0.25 V
Input Capacitance —12 —pF
Input Bias Current — 1 — nA
Input Offset Voltage –7 —+7 mV
Power Supply
Power Supply Rejection —0.1 —mV/V
Power-up Time VDD = 3.6 V — 0.6 —µs
VDD = 3.0 V — 1.0 —µs
VDD = 2.4 V — 1.8 —µs
VDD = 1.8 V — 10 —µs
Supply Current at DC Mode 0 —23 —µA
Mode 1 —8.8 —µA
Mode 2 —2.6 —µA
Mode 3 —0.4 —µA
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 1.0 64
Si106x/108x
Hysteresis
Mode 0
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —8.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) —17 —mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —34 —mV
Mode 1
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —6.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) —13 —mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —26 —mV
Mode 2
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 1 mV
Hysteresis 2 (CPnHYP/N1–0 = 01) 2 5 10 mV
Hysteresis 3 (CPnHYP/N1–0 = 10) 510 20 mV
Hysteresis 4 (CPnHYP/N1–0 = 11) 12 20 30 mV
Mode 3
Hysteresis 1 (CPnHYP/N1–0 = 00) — 0 — mV
Hysteresis 2 (CPnHYP/N1–0 = 01) —4.5 —mV
Hysteresis 3 (CPnHYP/N1–0 = 10) — 9 — mV
Hysteresis 4 (CPnHYP/N1–0 = 11) —17 —mV
Table 4.12. Comparator Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted.
Parameter Test Condition Min Typ Max Unit
Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Si106x/108x
65 Rev. 1.0
Table 4.13. DC-DC Converter (DC0) Electrical Characteristics
VBAT = 0.9 to 1.8 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Input Voltage Range 0.9 —1.8 V
Input Inductor Value 500 680 900 nH
Input Inductor Current Rat-
ing
250 — — mA
Inductor DC Resistance — — 0.5
Input Capacitor Value
Source Impedance < 2
—
—
4.7
1.0
—
—
µF
Output Voltage Range Target Output = 1.8 V 1.73 1.80 1.87 V
Target Output = 1.9 V 1.83 1.90 1.97 V
Target Output = 2.0 V 1.93 2.00 2.07 V
Target Output = 2.1 V 2.03 2.10 2.17 V
Target Output = 2.1 V 2.30 2.40 2.50 V
Target Output = 2.7 V 2.60 2.70 2.80 V
Target Output = 3.0 V 2.90 3.00 3.10 V
Target Output = 3.3 V 3.18 3.30 3.42 V
Output Load Regulation Target Output = 2.0 V, 1 to 30 mA —±0.3 — %
Target Output = 3.0 V, 1 to 20 mA —±1 — %
Output Current
(based on output power
spec)
Target Output = 1.8 V — — 36 mA
Target Output = 1.9 V — — 34 mA
Target Output = 2.0 V — — 32 mA
Target Output = 2.1 V — — 30 mA
Target Output = 2.4 V — — 27 mA
Target Output = 2.7 V — — 24 mA
Target Output = 3.0 V — — 21 mA
Target Output = 3.3 V — — 19 mA
Output Power — — 65 mW
Bias Current from VBAT supply
from VDD/DC+ supply
—
—
80
100
—
—
µA
Clocking Frequency 1.6 2.4 3.2 MHz
Maximum DC Load Current
During Startup
— — 1 mA
Capacitance Connected to
Output
0.8 1.0 2.0 µF
Rev. 1.0 66
Si106x/108x
Table 4.14. VREG0 Electrical Characteristics
VDD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Test Condition Min Typ Max Unit
Input Voltage Range 1.8 — 3.6 V
Bias Current Normal, Idle, Suspend, or Stop Mode —20 —µA
Rev. 1.0 67
Si106x/108x
4.3. Radio Electrical Characteristics
Table 4.15. DC Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage
Range
VDD 1.8 3.3 3.6 V
Power Saving
Modes
IShutdown RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
—30 —nA
IStandby Register values maintained and RC
oscillator/WUT OFF
—50 —nA
ISleepRC RC Oscillator/WUT ON and all register values
maintained, and all other blocks OFF
—900 —nA
IReady Crystal Oscillator and Main Digital Regulator
ON,
all other blocks OFF
—1.8 —mA
TUNE Mode
Current
ITune_RX RX Tune, High Performance Mode —7.2 —mA
ITune_TX TX Tune, High Performance Mode — 8 — mA
RX Mode Current IRXH High Performance Mode —13.7 —mA
IRXL Low Power Mode —10.7 —mA
TX Mode Current
(Si1060/61,
Si1080/81)
ITX_+20 +20 dBm output power, switched-current
match, 915 MHz, 3.3 V
—85 —mA
+20 dBm output power, switched-current match,
460 MHz, 3.3 V
—75 —mA
+20 dBm output power, square-wave match,
169 MHz, 3.3 V
—70 —mA
TX Mode Current
(Si1062/63/64/65,
Si1082/83/84/85)
ITX_+13 +13 dBm output power, switched-current match,
868 MHz, 3.3 V
—29 —mA
ITX_+10 +10 dBm output power, Class-E match,
868 MHz, 3.3 V
—18 —mA
Si106x/108x
68 Rev. 1.0
Table 4.16. Synthesizer AC Electrical Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Synthesizer Frequency
Range (Si1060/61/62/63,
Si1080/81/82/83)
FSYN 850 —1050 MHz
420 —525 MHz
284 —350 MHz
142 —175 MHz
Synthesizer Frequency
Range (Si1064/65,
Si1084/85)
FSYN 850 —960 MHz
425 —525 MHz
283 —350 MHz
Synthesizer Frequency
Resolution*
(Si1060/61/62/63,
Si1080/81/82/83)
FRES-960 850–1050 MHz —28.6 —Hz
FRES-525 420–525 MHz —14.3 —Hz
FRES-350 283–350 MHz —9.5 —Hz
FRES-175 142–175 MHz —4.7 —Hz
Synthesizer Frequency
Resolution (Si1064/65,
Si1084/85)
FRES-960 850–960 MHz —114.4 —Hz
FRES-525 425-525 MHz —57.2 —Hz
FRES-350 283–350 MHz —38.1 —Hz
Synthesizer Settling Time tLOCK Measured from exiting Ready
mode with XOSC running to any
frequency.
Including VCO Calibration.
—50 —µs
Phase Noise L(fM)F = 10 kHz, 460 MHz,
High-Performance Mode
—–106 —dBc/Hz
F = 100 kHz, 460 MHz,
High-Performance Mode
—–110 —dBc/Hz
F = 1 MHz, 460 MHz,
High-Performance Mode
—–123 —dBc/Hz
F = 10 MHz, 460 MHz,
High-Performance Mode
—–130 —dBc/Hz
*Note: Default API setting for modulation deviation resolution is double the typical value specified.
Rev. 1.0 69
Si106x/108x
Table 4.17. Receiver AC Electrical Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
RX Frequency
Range
(Si1060/61/62/63,
Si1080/81/82/83)
FRX 850 —1050 MHz
420 —525 MHz
284 —350 MHz
142 —175 MHz
RX Frequency
Range (Si1064/65,
Si1084/85)
FRX 850 —960 MHz
425 —525 MHz
283 —350 MHz
RX Sensitivity
(Si1060/61/62/63,
Si1080/81/82/83)
PRX_0.5 (BER < 0.1%)
(500 bps, GFSK, BT = 0.5,
f = 250Hz)
—–126 —dBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)
—–110 —dBm
PRX_100 (BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)
—–106 —dBm
PRX_125 (BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
Df = ±62.5 kHz)*
—–105 —dBm
PRX_500 (BER < 0.1%)
(500 kbps, GFSK, BT = 0.5,
f = 250 kHz)
—–97 —dBm
PRX_9.6 (PER 1%)
(9.6 kbps, 4GFSK, BT = 0.5,
f = kHz)*
—–110 —dBm
PRX_1M (PER 1%)
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)*
—–88 —dBm
Notes:
1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and
BER tested in the 450–470 MHz band.
2. Guaranteed by design.
Si106x/108x
70 Rev. 1.0
RX Sensitivity
(Si1060/61/62/63,
Si1080/81/82/83)
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz
BW, OOK, PN15 data)
—–110 —dBm
(BER < 0.1%, 40 kbps, 350 kHz
BW, OOK, PN15 data)
—–104 —dBm
(BER < 0.1%, 120 kbps, 350 kHz
BW, OOK, PN15 data)
—–99 —dBm
RX Sensitivity
(Si1064/65, Si1084/85)
PRX_2
PRX_2 (BER < 0.1%)
(2.4 kbps, GFSK, BT = 0.5,
f = 30 kHz, 114 kHz Rx BW)
—–116 —dBm
PRX_40 (BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)Note1
—–108 —dBm
PRX_128 (BER < 0.1%)
(128 kbps, GFSK, BT = 0.5,
f = 70 kHz, 305 kHz Rx BW)
—–103 —dBm
PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz
BW, OOK, PN15 data)
—–108 —dBm
(BER < 0.1%, 40 kbps, 350 kHz
BW, OOK, PN15 data)
—–102 —dBm
(BER < 0.1%, 120 kbps, 350 kHz
BW, OOK, PN15 data)
—–97 —dBm
RX Channel
Bandwidth
(Si1060/61/62/63,
Si1080/81/82/83)2
BW 1.1 —850 kHz
RX Channel
Bandwidth (Si1064/65,
Si1084/85)2
BW 40 —850 kHz
BER Variation vs
Power Level2
PRX_RES Up to +5 dBm Input Level —00.1 Ppm
RSSI Resolution1RESRSSI —±0.5 —dB
Table 4.17. Receiver AC Electrical Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and
BER tested in the 450–470 MHz band.
2. Guaranteed by design.
Rev. 1.0 71
Si106x/108x
1-Ch Offset
Selectivity, 169 MHz
Si1060/61/62/63,
Si1080/81/82/83
C/I1-CH Desired Ref Signal 3 dB above
sensitivity, BER < 0.1%. Interferer
is CW, and desired is modulated
with 2.4 kbps
F = 1.2 kHz GFSK with
BT = 0.5, RX channel
BW = 4.8 kHz,
channel spacing = 12.5 kHz
—–60 —dB
1-Ch Offset
Selectivity, 450 MHz
Si1060/61/62/63,
Si1080/81/82/83
C/I1-CH —–58 —dB
1-Ch Offset
Selectivity,
868/915 MHz
Si1060/61/62/63,
SI1080/81/82/83
C/I1-CH —–53 —dB
1-Ch Offset
Selectivity
Si1064/65, Si1084/85
C/I1-CH Desired Ref Signal 3 dB above
sensitivity, BER < 0.1%. Interferer
is CW, and desired is modulated
with 1.2 kbps
F = 5.2 kHz GFSK with
BT = 0.5, RX channel
BW = 58 kHz,
channel spacing = 100 kHz
—–56 —dB
2-Ch Offset
Selectivity
C/I1-CH —–59 —dB
Blocking 1 MHz Offset
Si1064/65, Si1084/85
1MBLOCK Desired Ref Signal 3 dB above
sensitivity, BER < 0.1%. Interferer
is CW, and desired is modulated
with 1.2 kbps
F = 5.2 kHz GFSK with
BT = 0.5, RX channel
BW = 58 kHz,
—–61 —dB
Blocking 8 MHz Offset
Si1064/65, Si1084/85
8MBLOCK —–79 —dB
Blocking 1 MHz Offset
Si1060/61/62/63,
Si1080/81/82/83
1MBLOCK Desired Ref Signal 3 dB above
sensitivity, BER = 0.1%. Interferer
is CW, and desired is modulated
with 2.4 kbps,
F = 1.2 kHz GFSK with
BT = 0.5,
RX channel BW = 4.8 kHz
—–75 —dB
Blocking 8 MHz Offset
Si1060/61/62/63,
Si1080/81/82/83
8MBLOCK —–84 —dB
Table 4.17. Receiver AC Electrical Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and
BER tested in the 450–470 MHz band.
2. Guaranteed by design.
Si106x/108x
72 Rev. 1.0
Image Rejection
Si1060/61/62/63,
Si1080/81/82/83
ImREJ No image rejection calibration.
Rejection at the image frequency.
IF = 468 kHz
—35 —dB
With image rejection calibration.
Rejection at the image frequency.
IF = 468 kHz
—55 —dB
Image Rejection
(Si1064/65,
Si1084/85)
ImREJ Rejection at the image
frequency IF = 468 kHz
—35 —dB
Spurious
(Si1064/65,
Si1084/85)
POB_RX1 Measured at RX pins —–54 —dBm
Table 4.17. Receiver AC Electrical Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and
BER tested in the 450–470 MHz band.
2. Guaranteed by design.
Rev. 1.0 73
Si106x/108x
Table 4.18. Transmitter AC Electrical Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
TX Frequency
Range
(Si1060/61/62/63,
Si1080/81/82/83)
FTX 850 —1050 MHz
420 —525 MHz
284 —350 MHz
142 —175 MHz
TX Frequency
Range Si1064/65,
Si1084/85
FTX 850 —960 MHz
425 —525 MHz
283 —350 MHz
(G)FSK Data Rate1,2
Si1060/61/62/63,
Si1080/81/82/83
DRFSK 0.1 —500 kbps
4(G)FSK Data Rate1,2
Si1060/61/62/63,
Si1080/81/82/83
DR4FSK 0.2 —1000 kbps
OOK Data Rate1,2
Si1060/61/62/63,
Si1084/85
DROOK 0.1 —120 kbps
(G)FSK Data Rate1,2
Si1064/65, Si1084/85 DRFSK 1 — 500 kbps
OOK Data Rate1,2
Si1064/65, Si1084/85 DROOK 0.5 —120 kbps
Modulation Deviation
Range
Si1060/61/62/63,
Si1080/81/82/83
f960 850–1050 MHz —1.5 —MHz
f525 420–525 MHz —750 —kHz
f350 283–350 MHz —500 —kHz
f175 142–175 MHz —250 —kHz
Modulation Deviation
Range1
Si1064/65, Si1084/85
f960 850–960 MHz —500 kHz
f525 425-525 MHz —500 kHz
f350 283-350 MHz —500 kHz
Modulation Deviation
Resolution
Si1060/61/62/63,
Si1080/81/82/83
FRES-960 850–1050 MHz —28.6 —Hz
FRES-525 420–525 MHz —14.3 —Hz
FRES-350 283–350 MHz —9.5 —Hz
FRES-175 142–175 MHz —4.7 —Hz
Notes:
1. Guaranteed by characterization.
2. Output power is dependent on matching components and board layout.
Si106x/108x
74 Rev. 1.0
Modulation Deviation
Resolution
Si1064/65, Si1084/85
FRES-960 850–960 MHz —114.4 —Hz
FRES-525 425-525 MHz —57.2 —Hz
FRES-350 283-350 MHz —38.1 —Hz
Output Power Range1, 2
(Si1060/61, Si1080/81) PTX –20 —+20 dBm
Output Power Range1, 2
(Si1062/63/64/65,
Si1082/83/84/85)
PTX60 –40 —+13 dBm
TX RF Output Steps PRF_OUT
Using switched current match
within 6 dB of max power —0.1 —dB
TX RF Output Level
Variation vs. Temperature PRF_TEMP –40 to +85 C— 1 — dB
TX RF Output Level
Variation vs. Frequency PRF_FREQ
Measured across
902–928 MHz —0.5 —dB
Transmit Modulation
Filtering B*T Gaussian Filtering Bandwidth
Time Product —0.5 —
Table 4.18. Transmitter AC Electrical Characteristics (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Guaranteed by characterization.
2. Output power is dependent on matching components and board layout.
Rev. 1.0 75
Si106x/108x
Table 4.19. Auxiliary Block Specifications
Parameter Symbol Test Condition Min Typ Max Unit
XTAL Range*XTALRange 25 —32 MHz
30 MHz XTAL Start-Up Time t30M Using XTAL and board
layout in reference
design. Start-up time
will vary with XTAL type
and board layout.
—250 —µs
30 MHz XTAL Cap
Resolution
30MRES —70 —fF
POR Reset Time tPOR — — 5 ms
*Note: XTAL Range tested in production using an external clock source (similar to using a TCXO).
Table 4.20. Digital IO Specifications (GPIO_x, nIRQ)
Parameter Symbol Test Condition Min Typ Max Unit
Rise Time1,2 TRISE 0.1 x VDD to 0.9 x VDD,
CL = 10 pF,
DRV<1:0> = LL
—2.3 —ns
Fall Time2,3 TFALL 0.9 x VDD to 0.1 x VDD,
CL = 10 pF,
DRV<1:0> = LL
— 2 — ns
Input Capacitance CIN — 2 — pF
Logic High Level Input
Voltage
VIH VDD x 0.7 — — V
Logic Low Level Input
Voltage
VIL — — VDD x 0.3 V
Input Current IIN 0<VIN< VDD –10 —10 µA
Input Current If Pullup is
Activated
IINP VIL = 0 V 1 — 10 µA
Drive Strength for Output
Low Level2
IOmaxLL DRV[1:0] = LL —6.66 —mA
IOmaxLH DRV[1:0] = LH —5.03 —mA
IOmaxHL DRV[1:0] = HL —3.16 —mA
IOmaxHH DRV[1:0] = HH —1.13 —mA
Notes:
1. 8 ns is typical for GPIO0 rise time.
2. Assuming VDD = 3.3 V, drive strength is specified at Voh (min) = 2.64 V and Vol(max) = 0.66 V at room
temperature.
3. 2.4 ns is typical for GPIO0 fall time.
Si106x/108x
76 Rev. 1.0
Drive Strength for Output
High Level2
IOmaxLL DRV[1:0] = LL —5.75 —mA
IOmaxLH DRV[1:0] = LH —4.37 —mA
IOmaxHL DRV[1:0] = HL —2.73 —mA
IOmaxHH DRV[1:0] = HH —0.96 —mA
Drive Strength for Output
High Level for GPIO02
IOmaxLL DRV[1:0] = LL —2.53 —mA
IOmaxLH DRV[1:0] = LH —2.21 —mA
IOmaxHL DRV[1:0] = HL —1.7 —mA
IOmaxHH DRV[1:0] = HH —0.80 —mA
Logic High Level Output
Voltage
VOH DRV[1:0] = HL VDD x 0.8 — — V
Logic Low Level Output
Voltage
VOL DRV[1:0] = HL — — VDD x 0.2 V
Table 4.20. Digital IO Specifications (GPIO_x, nIRQ) (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. 8 ns is typical for GPIO0 rise time.
2. Assuming VDD = 3.3 V, drive strength is specified at Voh (min) = 2.64 V and Vol(max) = 0.66 V at room
temperature.
3. 2.4 ns is typical for GPIO0 fall time.
Rev. 1.0 77
Si106x/108x
Table 4.21. Absolute Maximum Ratings (Radio)
Parameter Value Unit
VDD to GND –0.3, +3.6 V
Instantaneous VRF-peak to GND on TX Output Pin –0.3, +8.0 V
Sustained VRF-peak to GND on TX Output Pin –0.3, +6.5 V
Voltage on Digital Control Inputs –0.3, VDD + 0.3 V
Voltage on Analog Inputs –0.3, VDD + 0.3 V
RX Input Power +10 dBm
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at or beyond these ratings in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper
load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin.
Caution: ESD sensitive device.
Table 4.22. Thermal Properties
Parameter Value Unit
Operating Ambient Temperature Range TA–40 to +85 C
Thermal Impedance JA 30 C/W
Maximum Junction Temperature TJ+125 C
Storage Temperature Range TSTG –55 to +125 C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
Rev. 1.0 78
Si106x/108x
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on the Si106x/108x is a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power
Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in
a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automati-
cally oversample and average the ADC results.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multi-
plexer described in “5.5. ADC0 Analog Multiplexer” on page 95. The voltage reference for the ADC is
selected as described in “5.7. Voltage and Ground Reference Options” on page 100.
Figure 5.1. ADC0 Functional Block Diagram
5.1. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the
ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the
setting of the AD0SJST[2:0]. When the repeat count is set to 1, conversion codes are represented as 10-
bit unsigned integers. Inputs are measured from 0 to VREF x 1023/1024. Example codes are shown below
for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to 0.
ADC0CF
AMP0GN
AD0TM
AD08BE
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
10-bit
SAR
ADC
REF
SYSCLK
ADC0H
32
ADC0CN
AD0CM0
AD0CM1
AD0CM2
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
Start
Conversion
000 AD0BUSY (W)
VDD
ADC0LTH
AD0WINT
001
010
011
100 CNVSTR Input
Window
Compare
Logic
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
AIN+
From
AMUX0
Burst Mode Logic
ADC0TK
ADC0PWR
16-Bit Accumulator
Si106x/108x
79 Rev. 1.0
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage Right-Justified ADC0H:ADC0L
(AD0SJST = 000) Left-Justified ADC0H:ADC0L
(AD0SJST = 100)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
00x0000 0x0000
Input Voltage Repeat Count = 4 Repeat Count = 16 Repeat Count = 64
VREF x 1023/1024 0x0FFC 0x3FF0 0xFFC0
VREF x 512/1024 0x0800 0x2000 0x8000
VREF x 511/1024 0x07FC 0x1FF0 0x7FC0
00x0000 0x0000 0x0000
Input Voltage Repeat Count = 4
Shift Right = 1
11-Bit Result
Repeat Count = 16
Shift Right = 2
12-Bit Result
Repeat Count = 64
Shift Right = 3
13-Bit Result
VREF x 1023/1024 0x07F7 0x0FFC 0x1FF8
VREF x 512/1024 0x0400 0x0800 0x1000
VREF x 511/1024 0x03FE 0x04FC 0x0FF8
00x0000 0x0000 0x0000
Rev. 1.0 80
Si106x/108x
5.2. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK) is a divided
version of the system clock when Burst Mode is disabled (BURSTEN = 0), or a divided version of the low
power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide value is determined by the
AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See “31. Timers” on page 311 for timer configuration.
Import ant Note Ab out Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See
“20. Si106x/108xPort Input/Output” on page 217 for details on Port I/O configuration.
Important Note: When operating the device in one-cell mode, there is an option available to automatically
synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle. Activat-
ing this option may help to reduce interference from internal or external power supply noise generated by
the dc-dc converter. Asserting this bit will hold off the start of an ADC conversion initiated by any of the
methods described above until the ADC receives a synchronizing signal from the dc-dc converter. The
delay in initiation of the conversion can be as much as one cycle of the dc-dc converter clock, which is
625 ns at the minimum dc-dc clock frequency of 1.6 MHz. The synchronization feature also causes the dc-
dc converter clock to be used as the ADC0 conversion clock. The maximum conversion rate will be limited
to approximately 170 ksps at the maximum dc-dc converter clock rate of 3.2 MHz. In this mode, the ADC0
SAR Conversion Clock Divider must be set to 1 by setting AD0SC[4:0] = 00000b in SFR register ADC0CF.
To provide additional flexibility in minimizing noise, the ADC0 conversion clock provided by the dc-dc con-
verter can be inverted by setting the AD0CKINV bit in the DC0CF register. For additional information on the
synchronization feature, see the description of the SYNC bit in “SFR Definition 15.1. DC0CN: DC-DC
Converter Control” on page 181 and the description of the AD0CKINV bit in “SFR Definition 15.2. DC0CF:
DC-DC Converter Configuration” on page 182. This bit must be set to 0 in two-cell mode for the ADC to
operate.
Si106x/108x
81 Rev. 1.0
5.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state when Burst Mode is disabled, the ADC0 input is contin-
uously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in
low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of
CNVSTR (see Figure 5.2). Tracking can also be disabled (shutdown) when the device is in low power
standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are fre-
quently changed, due to the settling time requirements described in “5.2.4. Settling Time Requirements” on
page 84.
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1 Track Convert Low Power Mode
AD0TM=0 Track or
Convert Convert Track
Low Power
or Convert
SAR
Clocks
SAR
Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power
Mode
Low Power
or Convert
10 11 12 13 14
123456789
10 11 12 13 14
123456789
10 11 12 13 14 15 16 17
Rev. 1.0 82
Si106x/108x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e., the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 84 for more
details.
Notes:
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
A rising edge of external start-of-conversion (CNVSTR) will cause only one ADC conversion in Burst
Mode, regardless of the value of the Repeat Count field. The end-of-conversion interrupt will occur after
the number of conversions specified in Repeat Count have completed. In other words, if Repeat Count
is set to 4, four pulses on CNVSTR will cause an ADC end-of-conversion interrupt. Refer to the bottom
portion of Figure 5.3, “Burst Mode Tracking Example with Repeat Count Set to 4,” on page 83 for an
example.
To start multiple conversions in Burst Mode with one external start-of-conversion signal, the external
interrupts (/INT0 or /INT1) or Port Match can be used to trigger an ISR that writes to AD0BUSY.
External interrupts are configurable to be active low or active high, edge or level sensitive, but is only
avail-able on a limited number of pins. Port Match is only level sensitive, but is available on more port
pins than the external interrupts. Refer to section “11.6. External Interrupts INT0 and INT1” on
page 147 for details on external interrupts and section “20.4. Port Match” on page 226 for details on
Port Match.
Si106x/108x
83 Rev. 1.0
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
Track..
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Powered
Down
T C
Power-Up
and Idle T C T C T C Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Powered
Down
T C
Power-Up
and Track T C T C T C Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle IdleT C T C T C T C T C..
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track TrackT C T C T C T C T C..
T C T C
T C T C
T = Tracking
C = Converting
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down
Powered
Down
T C
Power-Up
and Idle
Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Powered
Down
T C
Power-Up
and Track
Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1
Idle IdleT C
Dual-Tracking
AD0TM = 11
AD0EN = 1
Track TrackT C T C
T C
T = Tracking
C = Converting
Idle..
Rev. 1.0 84
Si106x/108x
5.2.4. Settling Ti me Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
VDD with respect to GND, RTOTAL reduces to RMUX. See Ta b l e 4.9 for ADC0 minimum settling time require-
ments as well as the mux impedance and sampling capacitor values.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (10).
Figure 5.4. ADC0 Equivalent Input Circuits
t2n
SA
-------
RTOTALCSAMPLE
ln=
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
MUX Select
P0.x
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details.
Si106x/108x
85 Rev. 1.0
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by VREF
. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2.
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF volt-
age, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are con-
trolled by the AMP0GN bit in register ADC0CF.
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
Rev. 1.0 86
Si106x/108x
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable;
SFR Definition 5.1. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN BURSTEN AD0INT AD0BUSY AD0WINT ADC0CM
Type R/W R/W R/W WR/W R/W
Reset 00000000
Bit Name Function
7AD0ENADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
6 BURSTEN ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
5AD0INT
ADC0 Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst
of conversions (BURSTEN=1). Can trigger an interrupt. Must be cleared by soft-
ware.
4 AD0BUSY ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
3 AD0WINT ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window speci-
fied by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt.
Must be cleared by software.
2:0 ADC0CM[2:0] ADC0 Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
Si106x/108x
87 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xBC
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD08BE AD0TM AMP0GN
Type R/W R/W R/W R/W
Reset 11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
2AD08BE
ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1AD0TM
ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately fol-
lowing the start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock
cycles following the start-of-conversion signal. The ADC is allowed to track during
this time.
0AMP0GN
ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
*
*Round the result up.
or
AD0SC FCLK
CLKSAR
-------------------- 1–=
CLKSAR FCLK
AD0SC 1+
----------------------------
=
Rev. 1.0 88
Si106x/108x
SFR Page = 0x0; SFR Address = 0xBA
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
Bit76543210
Name Reserved AD0AE AD0SJST AD0RPT
Type R/W WR/W R/W
Reset 00000000
Bit Name Function
7 Reserved Read = 0b.
6AD0AE
ADC0 Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is
disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode
is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumu-
lated result.
This bit is write-only. Always reads 0b.
5:3 AD0SJST[2:0] ADC0 Accumulator Shift and Justify.
Specifies the format of data read from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
2:0 AD0RPT[2:0] ADC 0 Repeat Count.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
Si106x/108x
89 Rev. 1.0
SFR Page = 0xF; SFR Address = 0xBA
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit76543210
Name Reserved AD0PWR[3:0]
Type RRRR R/W
Reset 00001111
Bit Name Function
7 Reserved Read = 0b; Must write 0b.
6:4 Unused Read = 0000b; Write = Don’t Care.
3:0 AD0PWR[3:0] ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does not enter a low power state after all conver-
sions are complete.
Conversions can begin immediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state (as specified in Table 5.1) after all conversions
are complete.
Conversions can begin a programmed delay after the start-of-conversion sig-
nal.
The ADC0 Burst Mode Power-Up time is programmed according to the follow-
ing equation:
or
AD0PWR Tstartup
400ns
---------------------- 1–=
Tstartup AD0PWR 1+400ns=
Rev. 1.0 90
Si106x/108x
SFR Page = 0xF; SFR Address = 0xBD
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit76543210
Name AD0TK[5:0]
Type R R R/W
Reset 00010110
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 AD0TK[5:0] ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
Notes:
1. If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
or
AD0TK 63 Ttrack
50ns
-----------------1–
–=
Ttrack 64 AD0TK–50ns=
Si106x/108x
91 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xBE
SFR Page = 0x0; SFR Address = 0xBD;
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit76543210
Name ADC0[15:8]
Type R/W
Reset 00000000
Bit Name Description Read Write
7:0 ADC0[15:8] ADC0 Data Word High
Byte.
Most Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the most significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit76543210
Name ADC0[7:0]
Type R/W
Reset 00000000
Bit Name Description Read Write
7:0 ADC0[7:0] ADC0 Data Word Low Byte. Least Significant Byte of the
16-bit ADC0 Accumulator
formatted according to the
settings in AD0SJST[2:0].
Set the least significant
byte of the 16-bit ADC0
Accumulator to the value
written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
Rev. 1.0 92
Si106x/108x
5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Page = 0x0; SFR Address = 0xC4
SFR Page = 0x0; SFR Address = 0xC3
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte
Bit76543210
Name AD0GT[15:8]
Type R/W
Reset 11111111
Bit Name Function
7:0 AD0GT[15:8] ADC0 Greater-Than High Byte.
Most Significant Byte of the 16-bit Greater-Than window compare register.
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte
Bit76543210
Name AD0GT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 AD0GT[7:0] ADC0 Greater-Than Low Byte.
Least Significant Byte of the 16-bit Greater-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
Si106x/108x
93 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xC6
SFR Page = 0x0; SFR Address = 0xC5
5.4.1. Window Detector In Single-Ended Mode
Figure 5.5 shows two example window comparisons for right-justified data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justi-
fied data with the same comparison values.
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit76543210
Name AD0LT[15:8]
Type R/W
Reset 00000000
Bit Name Function
7:0 AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit76543210
Name AD0LT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
Rev. 1.0 94
Si106x/108x
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data
5.4.2. ADC0 Specifications
See “4. Electrical Characteristics” on page 42 for a detailed listing of ADC0 specifications.
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
Rev. 1.0 95
Si106x/108x
5.5. ADC0 Analog Multiplexer
ADC0 on Si106x/108x has an analog multiplexer, referred to as AMUX0.
AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the
positive input: Port I/O pins, the on-chip temperature sensor, Regulated Digital Supply Voltage (Output of
VREG0), VDD_MCU Supply, or the positive input may be connected to GND. The ADC0 input channels
are selected in the ADC0MX register described in SFR Definition 5.12.
Figure 5.7. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT = 0 and
Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP.
See Section “20. Si106x/108xPort Input/Output” on page 217 for more Port I/O configuration details.
ADC0
Temp
Sensor
AMUX
ADC0MX
AD0MX4
AD0MX3
AD0MX2
AD0MX1
AM0MX0
AIN+
P0.0
P2.6*
Digital Supply
VDD_MCU
Programmable
Attenuator
Gain = 0. 5 or 1
Si106x/108x
96 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xBB
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
Bit76543210
Name AD0MX
Type RRRR/W R/W R/W R/W R/W
Reset 00011111
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care.
4:0 AD0MX AMUX0 Positive Input Selection.
Selects the positive input channel for ADC0.
00000: P0.0 10000: P2.0
00001: P0.1 10001: P2.1
00010: P0.2 10010: P2.2
00011: P0.3 10011: P2.3
00100: P0.4 10100: P2.4
00101: P0.5 10101: P2.5
00110: P0.6 10110: P2.6
00111: P0.7 10111: Reserved.
01000: Reserved. 11000: Reserved.
01001: Reserved. 11001: Reserved.
01010: Reserved. 11010: Reserved.
01011: Reserved. 11011: Temperature Sensor*
01100: Reserved. 11100: VDD_MCU Supply Voltage
(1.8–3.6 V)
01101: P1.5
01110: P1.6 11101: Digital Supply Voltage
(VREG0 Output, 1.7 V Typical)
01111: P1.7
11110: VDD_MCU Supply Voltage
(1.8–3.6 V)
11111: Ground
*Note: Before switching the ADC multiplexer from another channel to the temperature sensor, the ADC mux should
select the “Ground” channel as an intermediate step. The intermediate “Ground” channel selection step will
discharge any voltage on the ADC sampling capacitor from the previous channel selection. This will prevent
the possibility of a high voltage (> 2 V) being presented to the temperature sensor circuit, which can otherwise
impact its long-term reliability.
Rev. 1.0 97
Si106x/108x
5.6. Temperature Sensor
An on-chip temperature sensor is included on the Si106x/108x which can be directly accessed via the ADC
multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC
mux channel should select the temperature sensor. The temperature sensor transfer function is shown in
Figure 5.8. The output voltage (VTEMP) is the positive ADC input when the ADC multiplexer is set correctly.
The TEMPE bit in register REF0CN enables/disables the temperature sensor, as described in SFR Defini-
tion 5.15. While disabled, the temperature sensor defaults to a high impedance state and any ADC mea-
surements performed on the sensor will result in meaningless data. Refer to Table 4.9 for the slope and
offset parameters of the temperature sensor.
Note: Before switching the ADC multiplexer from another channel to the temperature sensor, the ADC mux should
select the “Ground” channel as an intermediate step. The intermediate “Ground” channel selection step will
discharge any voltage on the ADC sampling capacitor from the previous channel selection. This will prevent the
possibility of a high voltage (> 2 V) being presented to the temperature sensor circuit, which can otherwise
impact its long-term reliability.
Figure 5.8. Temperature Sensor Transfer Function
5.6.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 4.10 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
1. Control/measure the ambient temperature (this temperature must be known).
2. Power the device, and delay for a few seconds to allow for self-heating.
3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND
Temperature
Voltage
VTEMP = Slope x (TempC
Offset ( V at 25 Celsius)
Slope ( V / deg C)
TempC = 25 + (
- 25) + Offset
VTEMP - Offset) / Slope
Si106x/108x
98 Rev. 1.0
selected as the negative input.
4. Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent
temperature sensor measurements.
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame-
ters that affect ADC measurement, in particular the voltage reference value, will also affect tem-
perature measurement.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The measurement is performed at 25 °C ±5 °C, using the ADC with the internal high speed refer-
ence buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in the
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
-40.00 -20.00 0.00 20.00
40.00 60.00 80.00
Temperature (degrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
Rev. 1.0 99
Si106x/108x
SFR Page = 0xF; SFR Address = 0x86
SFR Page = 0xF; SFR Address = 0x85
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte
Bit76543210
Name TOFF[9:2]
Type RRRRRRRR
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 TOFF[9:2] Temperature Sensor Offset High Bits.
Most Significant Bits of the 10-bit temperature sensor offset measurement.
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte
Bit76543210
Name TOFF[1:0]
Type R R
Reset Varies Varies 000000
Bit Name Function
7:6 TOFF[1:0] Temperat ure Sensor Offset Low Bits.
Least Significant Bits of the 10-bit temperature sensor offset measurement.
5:0 Unused Read = 0; Write = Don't Care.
Rev. 1.0 100
Si106x/108x
5.7. Voltage and Ground Reference Options
The voltage reference MUX is configurable to use an externally connected voltage reference, one of two
internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference
MUX allows the ground reference for ADC0 to be selected between the ground pin (GND) or a port pin
dedicated to analog ground (P0.1/AGND).
The voltage and ground reference options are configured using the REF0CN SFR described on page 102.
Electrical specifications are can be found in the Electrical Specifications Chapter.
Important Note About the VREF and AGND Inputs: Port pins are used as the external VREF and AGND
inputs. When using an external voltage reference or the internal precision reference, P0.0/VREF should be
configured as an analog input and skipped by the Digital Crossbar. When using AGND as the ground refer-
ence to ADC0, P0.1/AGND should be configured as an analog input and skipped by the Digital Crossbar.
Refer to Section “20. Si106x/108xPort Input/Output” on page 217 for complete Port I/O configuration
details. The external reference voltage must be within the range 0 VREF VDD_MCU and the external
ground reference must be at the same DC voltage potential as GND.
Figure 5.10. Voltage Reference Functional Block Diagram
VREF
(to ADC)
ADC
Input
Mux
P0.0/VREF
R1
VDD External
Voltage
Reference
Circuit
GND
Temp Sensor
EN
00
01
10
11
REF0CN
REFSL0
TEMPE
REFOE
REFSL1
REFGND
Internal 1.68V
Reference
Recommended
Bypass Capacitors
+
4.7F0.1F
Internal 1.8V
Regulated Digital Supply
EN
VDD/DC+
Internal 1.65V
High Speed Reference
GND
P0.1/AGND
0
1
Ground
(to ADC)
REFOE
REFGND
Si106x/108x
101 Rev. 1.0
5.8. External Voltage References
To use an external voltage reference, REFSL[1:0] should be set to 00 and the internal 1.68 V precision ref-
erence should be disabled by setting REFOE to 0. Bypass capacitors should be added as recommended
by the manufacturer of the external voltage reference.
5.9. Internal Voltage References
For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the
1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal
reference is selected by setting REFSL[1:0] to 11. When selected, the high speed internal reference will be
automatically enabled/disabled on an as-needed basis by ADC0.
For applications requiring the highest absolute accuracy, the 1.68 V precision voltage reference will be the
best internal reference option to choose. The 1.68 V precision reference may be enabled and selected by
setting REFOE to 1 and REFSL[1:0] to 00. An external capacitor of at least 0.1 µF is recommended when
using the precision voltage reference.
In applications that leave the precision internal oscillator always running, there is no additional power
required to use the precision voltage reference. In all other applications, using the high speed reference
will result in lower overall power consumption due to its minimal startup time and the fact that it remains in
a low power state when an ADC conversion is not taking place.
Note: When using the precision internal oscillator as the system clock source, the precision voltage refer-
ence should not be enabled from a disabled state. To use the precision oscillator and the precision voltage
reference simultaneously, the precision voltage reference should be enabled first and allowed to settle to
its final value (charging the external capacitor) before the precision oscillator is started and selected as the
system clock.
For applications with a non-varying power supply voltage, using the power supply as the voltage reference
can provide ADC0 with added dynamic range at the cost of reduced power supply noise rejection. To use
the 1.8 to 3.6 V power supply voltage (VDD_MCU) or the 1.8 V regulated digital supply voltage as the ref-
erence source, REFSL[1:0] should be set to 01 or 10, respectively.
5.10. Analog Ground Reference
To prevent ground noise generated by switching digital logic from affecting sensitive analog measure-
ments, a separate analog ground reference option is available. When enabled, the ground reference for
ADC0 during both the tracking/sampling and the conversion periods is taken from the P0.1/AGND pin. Any
external sensors sampled by ADC0 should be referenced to the P0.1/AGND pin. This pin should be con-
nected to the ground terminal of any external sensors sampled by ADC0. If an external voltage reference is
used, the P0.1/AGND pin should be connected to the ground of the external reference and its associated
decoupling capacitor. If the 1.68 V precision internal reference is used, then P0.1/AGND should be con-
nected to the ground terminal of its external decoupling capacitor. The separate analog ground reference
option is enabled by setting REFGND to 1. Note that when sampling the internal temperature sensor, the
internal device ground is always used for the sampling operation, regardless of the setting of the REFGND
bit. Similarly, whenever the internal 1.65 V high-speed reference is selected, the internal device ground is
always used during the conversion period, regardless of the setting of the REFGND bit.
5.11. Temperature Sensor Enable
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the tem-
perature sensor defaults to a high impedance state and any ADC0 measurements performed on the sen-
sor result in meaningless data. See Section “5.6. Temperature Sensor” on page 97 for details on
temperature sensor characteristics when it is enabled.
Rev. 1.0 102
Si106x/108x
SFR Page = 0x0; SFR Address = 0xD1
5.12. Voltage Reference Electrical Specifications
See Table 4.11 on page 62 for detailed Voltage Reference Electrical Specifications.
SFR Definition 5.15. REF0CN: Voltage Reference Control
Bit76543210
Name REFGND REFSL TEMPE REFOE
Type R R R/W R/W R/W R/W RR/W
Reset 00011000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5REFGND
Analog Ground Reference.
Selects the ADC0 ground reference.
0: The ADC0 ground reference is the GND pin.
1: The ADC0 ground reference is the P0.1/AGND pin.
4:3 REFSL Voltage Reference Select.
Selects the ADC0 voltage reference.
00: The ADC0 voltage reference is the P0.0/VREF pin.
01: The ADC0 voltage reference is the VDD_MCU pin.
10: The ADC0 voltage reference is the internal 1.8 V digital supply voltage.
11: The ADC0 voltage reference is the internal 1.65 V high speed voltage reference.
2 TEMPE Temperature Sensor Enable.
Enables/Disables the internal temperature sensor.
0: Temperature Sensor Disabled.
1: Temperature Sensor Enabled.
1 Unused Read = 0b; Write = Don’t Care.
0REFOE
Internal Voltage Reference Output Enable.
Connects/Disconnects the internal voltage reference to the P0.0/VREF pin.
0: Internal 1.68 V Precision Voltage Reference disabled and not connected to
P0.0/VREF.
1: Internal 1.68 V Precision Voltage Reference enabled and connected to
P0.0/VREF.
Rev. 1.0 103
Si106x/108x
6. Comparators
Si106x/108x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is
shown in Figure 6.1; Comparator 1 (CPT1) is shown in Figure 6.2. The two comparators operate identi-
cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter
and the Power Management chapter for details on reset sources and low power mode wake-up sources,
respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
6.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their posi-
tive and negative comparator inputs using analog input multiplexers. The analog input multiplexers are
completely under software control and configured using SFR registers. See Section “6.6. Comparator0 and
Comparator1 Analog Multiplexers” on page 110 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how to
configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level of
digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
Figure 6.1. Comparator 0 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP0 +
Px.x
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0 CPT0MD
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0
CP0A
CP0
Rising-edge
CP0
Falling-edge
CP0
Interrupt
Px.x
Px.x
Px.x
CP0 -
(ASYNCHRONOUS)
Analog Input Multiplexer
Si106x/108x
104 Rev. 1.0
6.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 6.2. The synchronous “latched” output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin through the
Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used by the low power mode wakeup logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The asyn-
chronous comparator output can also be routed directly to a Port pin through the Crossbar, and is available
for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to gen-
erate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and global
interrupts must be enabled. See the Interrupt Handler chapter for additional information.
Figure 6.2. Comparator 1 Functional Block Diagram
VDD
CPT0CN
Reset
Decision
Tree
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CP1 +
Px.x
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0 CPT0MD
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1
CP1A
CP1
Rising-edge
CP1
Falling-edge
CP1
Interrupt
Px.x
Px.x
Px.x
CP1 -
(ASYNCHRONOUS)
Analog Input Multiplexer
Rev. 1.0 105
Si106x/108x
6.3. Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on
“CPT0MD: Comparator 0 Mode Selection” on page 107 and “CPT1MD: Comparator 1 Mode Selection” on
page 109. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2,
and Mode 3 (Lowest Power). Selecting a longer response time reduces the Comparator active supply cur-
rent. The Comparators also have low power shutdown state, which is entered any time the comparator is
disabled. Comparator rising edge and falling edge response times are typically not equal. See Table 4.12
on page 63 for complete comparator timing and supply current specifications.
6.4. Comparator Hysteresis
The Comparators feature software-programmable hysteresis that can be used to stabilize the comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym-
metry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 6.3 shows that when positive hysteresis is enabled, the comparator output does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysteresis. It also shows that when negative hysteresis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the programmed hysteresis.
The amount of positive hysteresis is determined by the settings of the CPnHYP bits in the CPTnCN regis-
ter and the amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits in the
same register. Settings of 20, 10, 5, or 0 mV can be programmed for both positive and negative hysteresis.
See Section “Table 4.12. Comparator Electrical Characteristics” on page 63 for complete comparator hys-
teresis specifications.
Figure 6.3. Comparator Hysteresis Plot
Positive Hysteresis Voltage
(Programm ed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programm ed by CP 0H YN B its)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CPn+
CPn- CPn
VIN+
VIN- OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
Si106x/108x
106 Rev. 1.0
6.5. Comparator Register Descriptions
The SFRs used to enable and configure the comparators are described in the following register descrip-
tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. From an
enabled state, a comparator can be disabled and placed in a low power state by clearing the CPnEN bit to
logic 0.
Import ant Note About Compar ator Sett ings: False rising and falling edges can be detected by the Com-
parator while powering on or if changes are made to the hysteresis or response time control bits. There-
fore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short
time after the comparator is enabled or its mode bits have been changed. The Comparator Power Up Time
is specified in Section “Table 4.12. Comparator Electrical Characteristics” on page 63.
SFR Page= 0x0; SFR Address = 0x9B
SFR Definition 6.1. CPT0CN: Comparator 0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP0ENComparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6CP0OUT
Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIF
Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIF
Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bit s.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.0 107
Si106x/108x
SFR Page = All Pages; SFR Address = 0x9D
SFR Definition 6.2. CPT0MD: Comparator 0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type R/W RR/W R/W R R R/W
Reset 10000010
Bit Name Function
7 Reserved Read = 1b, Must Write 1b.
6 Unused Read = 0b, Write = don’t care.
5CP0RIE
Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE
Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Si106x/108x
108 Rev. 1.0
SFR Page= 0x0; SFR Address = 0x9A
SFR Definition 6.3. CPT1CN: Comparator 1 Control
Bit76543210
Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1ENComparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6CP1OUT
Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5CP1RIF
Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4CP1FIF
Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bit s.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 1.0 109
Si106x/108x
SFR Page = 0x0; SFR Address = 0x9C
SFR Definition 6.4. CPT1MD: Comparator 1 Mode Selection
Bit76543210
Name CP1RIE CP1FIE CP1MD[1:0]
Type R/W RR/W R/W R R R/W
Reset 10000010
Bit Name Function
7 Reserved Read = 1b, Must Write 1b.
6 Unused Read = 00b, Write = don’t care.
5CP1RIE
Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4CP1FIE
Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP1MD[1:0] Comparator1 Mode Select
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
Rev. 1.0 110
Si106x/108x
6.6. Comparator0 and Comparator1 Analog Multiplexers
Comparator0 and Comparator1 on Si106x/108x devices have analog input multiplexers to connect Port I/O
pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplex-
ers for Comparator0 and CP1+/CP1- are the positive and negative input multiplexers for Comparator1.
The comparator input multiplexers directly support capacitive touch switches. When the Capacitive Touch
Sense Compare input is selected on the positive or negative multiplexer, any Port I/O pin connected to the
other multiplexer can be directly connected to a capacitive touch switch with no additional external compo-
nents. The Capacitive Touch Sense Compare provides the appropriate reference level for detecting when
the capacitive touch switches have charged or discharged through the on-chip Rsense resistor. The Com-
parator outputs can be routed to Timer2 or Timer3 for capturing sense capacitor’s charge and discharge
time. See Section “31. Timers” on page 311 for details. See Application Note AN338 for details on Capaci-
tive Touch Switch sensing.
Any of the following may be selected as comparator inputs: Port I/O pins, Capacitive Touch Sense Com-
pare, VDD_MCU Supply Voltage, Regulated Digital Supply Voltage (Output of VREG0) or ground. The
Comparator’s supply voltage divided by 2 is also available as an input; the resistors used to divide the volt-
age only draw current when this setting is selected. The Comparator input multiplexers are configured
using the CPT0MX and CPT1MX registers described in SFR Definition 6.5 and SFR Definition 6.6.
Figure 6.4. CPn Multiplexer Block Diagram
Import ant Not e About Co mp ar ator Input Configurat ion: Port pins selected as comparator inputs should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “20. Si106x/108xPort Input/Output” on page 217 for more Port I/O configuration
details.
CPn-
Input
MUX
Digital Supply
P0.1
VDD_MCU
+
-
GND
VDD_MCU
P0.3
P0.5
P0.7
P1.5
P1.7
P2.1
P2.3
P2.5
VDD_MCU
R
R
VDD_MCU
R
R
CPnOUT
R
½ x VDD_MCU
(1/3 or 2/3) x VDD_MCU
Capacitive
Touch
Sense
Compare
CPn+
Input
MUX
VBAT
CPTnMX
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
P0.0
P0.2
P0.4
P0.6
P1.6
P2.0
P2.2
P2.4
P2.6
VDD_MCU
R
R
VDD_MCU
R
R
CPnOUT
R
½ x VDD_MCU
(1/3 or 2/3) x VDD_MCU
CPnOUT
Rsense
Only enabled when
Capacitive Touch
Sense Compare is
selected on CPn+
Input MUX.
CPnOUT
Rsense
GND
Capacitive
Touch
Sense
Compare
Only enabled when
Capacitive Touch
Sense Compare is
selected on CPn-
Input MUX.
Si106x/108x
111 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x9F
SFR Definition 6.5. CPT0MX: Comparator0 Input Channel Select
Bit76543210
Name CMX0N[3:0] CMX0P[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 CMX0N Comparator0 Negative Input Selection.
Selects the negative input channel for Comparator0.
0000: P0.1 1000: P2.1
0001: P0.3 1001: P2.3
0010: P0.5 1010: P2.5
0011: P0.7 1011: Reserved
0100: Reserved 1100: Capacitive Touch Sense
Compare
0101: Reserved 1101: VDD_MCU divided by 2
0110: P1.5 1110: Digital Supply Voltage
0111: P1.7 1111: Ground
3:0 CMX0P Comparator0 Positive Input Selection.
Selects the positive input channel for Comparator0.
0000: P0.0 1000: P2.0
0001: P0.2 1001: P2.2
0010: P0.4 1010: P2.4
0011: P0.6 1011: P2.6
0100: Reserved 1100: Capacitive Touch Sense
Compare
0101: Reserved 1101: VDD_MCU divided by 2
0110: Reserved 1110: VBAT Supply Voltage
0111: P1.6 1111: VDD_MCU Supply Voltage
Rev. 1.0 112
Si106x/108x
SFR Page = 0x0; SFR Address = 0x9E
SFR Definition 6.6. CPT1MX: Comparator1 Input Channel Select
Bit76543210
Name CMX1N[3:0] CMX1P[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 CMX1N Comparator1 Negative Input Selection.
Selects the negative input channel for Comparator1.
0000: P0.1 1000: P2.1
0001: P0.3 1001: P2.3
0010: P0.5 1010: P2.5
0011: P0.7 1011: Reserved
0100: Reserved 1100: Capacitive Touch Sense
Compare
0101: Reserved 1101: VDD_MCU divided by 2
0110: P1.5 1110: Digital Supply Voltage
0111: P1.7 1111: Ground
3:0 CMX1P Comparator1 Positive Input Selection.
Selects the positive input channel for Comparator1.
0000: P0.0 1000: P2.0
0001: P0.2 1001: P2.2
0010: P0.4 1010: P2.4
0011: P0.6 1011: P2.6
0100: Reserved 1100: Capacitive Touch Sense
Compare
0101: Reserved 1101: VDD_MCU divided by 2
0110: Reserved 1110: VBAT Supply Voltage
0111: P1.6 1111: VDD_MCU Supply Voltage
Rev. 1.0 113
Si106x/108x
7. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 33), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 7.1 for a block diagram).
The CIP-51 includes the following features:
7.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Figure 7.1. CIP-51 Block Diagram
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
D8
STACK POINTER
D8
Si106x/108x
114 Rev. 1.0
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
7.2. Programming and Debugging Support
In-system programming of the flash program memory and communication with on-chip debug support logic
is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “33. Device Specific Behavior” on page 352.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
7.3. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
7.3.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 7.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26 50 5 14 7 3 1 2 1
Rev. 1.0 115
Si106x/108x
Table 7.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
Si106x/108x
116 Rev. 1.0
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
Table 7.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Rev. 1.0 117
Si106x/108x
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 22/3
JNC rel Jump if Carry is not set 22/3
JB bit, rel Jump if direct bit is set 33/4
JNB bit, rel Jump if direct bit is not set 33/4
JBC bit, rel Jump if direct bit is set and clear bit 33/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 22/3
JNZ rel Jump if A does not equal zero 22/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 34/5
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal
33/4
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal
34/5
DJNZ Rn, rel Decrement Register and jump if not zero 22/3
DJNZ direct, rel Decrement direct byte and jump if not zero 33/4
NOP No operation 1 1
Table 7.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Si106x/108x
118 Rev. 1.0
Notes on Registers, Oper ands and Addressing Modes:
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Rev. 1.0 119
Si106x/108x
7.4. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the data sheet associated with their corresponding sys-
tem function.
SFR Page = All Pages; SFR Address = 0x82
SFR Page = All Pages; SFR Address = 0x83
SFR Definition 7.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed flash memory or XRAM.
SFR Definition 7.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed flash memory or XRAM.
Si106x/108x
120 Rev. 1.0
SFR Page = All Pages; SFR Address = 0x81
SFR Page = All Pages; SFR Address = 0xE0; Bit-Addressable
SFR Page = All Pages; SFR Address = 0xF0; Bit-Addressable
SFR Definition 7.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 7.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 7.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
Rev. 1.0 121
Si106x/108x
SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable
SFR Definition 7.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CYCarry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
Rev. 1.0 122
Si106x/108x
8. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si106x device family is shown in Figure 8.1 and the Si108x device family is shown in Figure 8.2.
Figure 8.1. Si106x Memory Map
PROGRAM /DATA MEMO RY
(FLASH)
64KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
0x0000
0xFFFF RESERVED
0xFC00
0xFBFF
Scrachpad Memory
(DATA only)
0x03FF
0x0000
(Direct and Indirect
Addressing)
Upper 128 RAM
(Indirect Addressing Only)
Special Function
Registers
(Direct Addressing Only)
DATA MEMORY
(RAM)
General Purpose
Registers
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XR AM - 4096 Bytes
(accessable using M OVX
instruction)
0x0000
0x0FFF
Reserved
0x1000
0xFFFF
F
0
Si1060/2/4
32KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
0x0000
0x7FFF
Scrachpad Memory
(DATA only)
0x03FF
0x0000
Si1061/3/5
Si106x/108x
123 Rev. 1.0
Figure 8.2. Si108x Memory Map
Rev. 1.0 124
Si106x/108x
8.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The Si106x implements 64 kB (Si1060/2/4) and
32 kB (Si1061/3/5) of this program memory space as in-system, re-programmable flash memory, orga-
nized in a contiguous block from addresses 0x0000 to 0xFBFF (Si1060/2/4) or 0x7FFF (Si1061/3/5). The
address 0xFBFF (Si1060/2/4) or 0x7FFF (Si1061/3/5) serves as the security lock byte for the device. Any
addresses above the lock byte are reserved.
Figure 8.3. Si106x Flash Program Memory Map
The Si108x implements 16 kB (Si1080/2/4) or 8 kB (Si1081/3/5) of this program memory space as in-sys-
tem, re-programmable Flash memory, organized in a contiguous block from address 0x0000 to 0x3BFFF
(Si1080/2/4) or 0x1FFF (Si1018/3/5). The last byte of this contiguous block of addresses serves as the
security lock byte for the device. Any addresses above the lock byte are reserved.
Figure 8.4. Si108x Flash Program Memory Map
Lock Byte
0x0000
FLASH memory organized in
1024-byte pages
Flash Memory Space
Lock By te P a ge
Lock By te
Flash Memory Space
Lock Byte Page
Reserved Area
0x0000
0xFBFE
0xFC00
0xF800
0xFFFF
0xFBFF
0x7FFF
0x7FFE
0x7C00
0x7BFF
0xF7FF
Scratchpad
(Data Only)
Unpopulated
Address Space
(Reserved)
0xFFFF
0x8000
0x0000
0x03FF
Si1060/2/4
(SFLE=0)
Si1061/3/5
(SFLE=0)
Si1060/2/4
Si1061/3/5
(SFLE=1)
Si106x/108x
125 Rev. 1.0
When creating applications that program their own Flash such as bootloaders, data loggers, etc, it is possi-
ble to write generic Flash management routines that operate on either 512 byte or 1024 byte Flash pages;
however, this may not result in the most optimal memory usage. For example, in such a system, the logical
Flash page size must be set to 1024 bytes. This can pose limitations on devices with a small Flash size.
For example, an 8 kB device would only have 8 logical Flash pages. For larger Flash devices that have
1024 byte pages, each Flash page must be erased twice in order for the same code to support smaller
devices that have 512 bytes per physical Flash page. In most applications, the most efficient method to
support various devices is to use conditional compilation to tailor the Flash write/erase routines for each
device.
8.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
Si106x/108x/S108x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but
can be re-configured to write and erase on-chip flash memory space. MOVC instructions are always used
to read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the Si106x/108x to update program code and use the program memory
space for non-volatile data storage. Refer to Section “12. Flash Memory” on page 149 for further details.
8.2. Data Memory
The Si106x/108x device family includes 4352 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip “external” memory.
The data memory map is shown in Figure 8.1 for reference.
The Si108x device family include 768 bytes of RAM data memory. 256 bytes of this memory is mapped to
the internal RAM space of the 8051. The remainder of this memory is on-chip “external” memory. The data
memory map is shown in Figure 8.2 for reference.
8.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.1 and Figure 8.2 illustrate the data memory organization of the
Si106x/108x and Si108x.
8.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 7.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
Rev. 1.0 126
Si106x/108x
8.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
8.2.2. External RAM
There are 512 bytes (Si108x) or 4096 bytes (Si106x) of on-chip RAM mapped into the external data mem-
ory space. All of these address locations may be accessed using the external move instruction (MOVX)
and the data pointer (DPTR), or using MOVX indirect addressing mode (such as @R1) in combination with
the EMI0CN register.
Rev. 1.0 127
Si106x/108x
9. On-Chip XRAM
The Si106x/108x MCUs include on-chip RAM mapped into the external data memory space (XRAM). The
external memory space may be accessed using the external move instruction (MOVX) with the target
address specified in either the data pointer (DPTR), or with the target address low byte in R0 or R1 and the
target address high byte in the External Memory Interface Control Register (EMI0CN, shown in SFR Defi-
nition 9.1).
When using the MOVX instruction to access on-chip RAM, no additional initialization is required and the
MOVX instruction execution time is as specified in the CIP-51 chapter.
Important No te: MOVX write operations can be configured to target flash memory, instead of XRAM. See
Section “12. Flash Memory” on page 149 for more details. The MOVX instruction accesses XRAM by
default.
9.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
9.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)
MOVX A, @DPTR ; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
9.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV EMI0CN, #12h ; load high byte of address into EMI0CN
MOV R0, #34h ; load low byte of address into R0 (or R1)
MOVX a, @R0 ; load contents of 0x1234 into accumulator A
Si106x/108x
128 Rev. 1.0
9.2. Special Function Registers
The special function register used for configuring XRAM access is EMI0CN.
SFR Page = 0x0; SFR Address = 0xAA
SFR Definition 9.1. EMI0CN: External Memory Interface Control
Bit76543210
Name PGSEL[3:0]
Type RRRR R/W
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b; Write = Don’t Care.
3:0 PGSEL XRAM Page Select.
The EMI0CN register provides the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page
of RAM. Since the upper (unused) bits of the register are always zero, EMI0CN deter-
mines which page of XRAM is accessed.
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
If EMI0CN = 0x0F, addresses 0x0F00 through 0x0FFF will be accessed.
Rev. 1.0 129
Si106x/108x
10. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si106x/108x's resources and peripherals.
The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple-
menting additional SFRs used to configure and access the sub-systems unique to the Si106x/108x. This
allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
Table 10.1 and Table 10.2 list the SFRs implemented in the Si106x/108x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 10.3, for a detailed description of each register.
Table 10.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0 BP0MDIN P1MDIN P2MDIN SMB0ADR SMB0ADM EIP1 EIP2
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF EIE1 EIE2
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0PWM
D0 PSW REF0CN PCA0CPL5 PCA0CPH5 P0SKIP P1SKIP P2SKIP P0MAT
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPM5 P1MAT
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
B8 IP ADC0AC ADC0MX ADC0CF ADC0L ADC0H P1MASK
B0 SPI1CN OSCXCN OSCICN OSCICL PMU0CF FLSCL FLKEY
A8 IE CLKSEL EMI0CN Reserved RTC0ADR RTC0DAT RTC0KEY Reserved
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H DC0CF DC0CN
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH SPI1CFG SPI1CKR SPI1DAT PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Si106x/108x
130 Rev. 1.0
10.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple-
mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 10.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 10.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs accessible only from Page 0xF are in bold.
The following procedure should be used when accessing SFRs from Page 0xF:
1. Save the current interrupt state (EA_save = EA).
2. Disable Interrupts (EA = 0).
3. Set SFRPAGE = 0xF.
4. Access the SFRs located on SFR Page 0xF.
5. Set SFRPAGE = 0x0.
6. Restore interrupt state (EA = EA_save).
Table 10.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0 BEIP1 EIP2
E8
E0 ACC EIE1 EIE2
D8
D0 PSW
C8
C0
B8 ADC0PWR ADC0TK
B0
A8 IE CLKSEL
A0 P2 P0DRV P1DRV P2DRV SFRPAGE
98
90 P1 CRC0DAT CRC0CN CRC0IN CRC0FLIP CRC0AUTO CRC0CNT
88
80 P0 SP DPL DPH TOFFL TOFFH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Rev. 1.0 131
Si106x/108x
SFR Page = All Pages; SFR Address = 0xA7
SFR Definition 10.1. SFRPage: SFR Page
Bit76543210
Name SFRPAGE[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SFRPAGE[7:0] SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function
registers.
Table 10.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address SFR Page Description Page
ACC 0xE0 All Accumulator 120
ADC0AC 0xBA 0x0 ADC0 Accumulator Configuration 88
ADC0CF 0xBC 0x0 ADC0 Configuration 87
ADC0CN 0xE8 0x0 ADC0 Control 86
ADC0GTH 0xC4 0x0 ADC0 Greater-Than Compare High 92
ADC0GTL 0xC3 0x0 ADC0 Greater-Than Compare Low 92
ADC0H 0xBE 0x0 ADC0 High 91
ADC0L 0xBD 0x0 ADC0 Low 91
ADC0LTH 0xC6 0x0 ADC0 Less-Than Compare Word High 93
ADC0LTL 0xC5 0x0 ADC0 Less-Than Compare Word Low 93
ADC0MX 0xBB 0x0 AMUX0 Channel Select 96
ADC0PWR 0xBA 0xF ADC0 Burst Mode Power-Up Time 89
ADC0TK 0xBD 0xF ADC0 Tracking Control 90
B 0xF0 All B Register 120
CKCON 0x8E 0x0 Clock Control 312
CLKSEL 0xA9 All Clock Select 197
CPT0CN 0x9B 0x0 Comparator0 Control 107
CPT0MD 0x9D 0x0 Comparator0 Mode Selection 107
CPT0MX 0x9F 0x0 Comparator0 Mux Selection 111
CPT1CN 0x9A 0x0 Comparator1 Control 108
CPT1MD 0x9C 0x0 Comparator1 Mode Selection 109
CPT1MX 0x9E 0x0 Comparator1 Mux Selection 112
CRC0AUTO 0x96 0xF CRC0 Automatic Control 173
Si106x/108x
132 Rev. 1.0
CRC0CN 0x92 0xF CRC0 Control 171
CRC0CNT 0x97 0xF CRC0 Automatic Flash Sector Count 173
CRC0DAT 0x91 0xF CRC0 Data 172
CRC0FLIP 0x95 0xF CRC0 Flip 174
CRC0IN 0x93 0xF CRC0 Input 172
DC0CF 0x96 0x0 DC0 (DC-DC Converter) Configuration 182
DC0CN 0x97 0x0 DC0 (DC-DC Converter) Control 181
DPH 0x83 All Data Pointer High 119
DPL 0x82 All Data Pointer Low 119
EIE1 0xE6 All Extended Interrupt Enable 1 143
EIE2 0xE7 All Extended Interrupt Enable 2 145
EIP1 0xF6 0x0 Extended Interrupt Priority 1 144
EIP2 0xF7 0x0 Extended Interrupt Priority 2 146
EMI0CN 0xAA 0x0 EMIF Control 128
FLKEY 0xB7 0x0 Flash Lock And Key 158
FLSCL 0xB6 0x0 Flash Scale 158
IE 0xA8 All Interrupt Enable 141
IP 0xB8 0x0 Interrupt Priority 142
IT01CF 0xE4 0x0 INT0/INT1 Configuration 148
OSCICL 0xB3 0x0 Internal Oscillator Calibration 198
OSCICN 0xB2 0x0 Internal Oscillator Control 198
OSCXCN 0xB1 0x0 External Oscillator Control 199
P0 0x80 All Port 0 Latch 230
P0DRV 0xA4 0xF Port 0 Drive Strength 232
P0MASK 0xC7 0x0 Port 0 Mask 227
P0MAT 0xD7 0x0 Port 0 Match 227
P0MDIN 0xF1 0x0 Port 0 Input Mode Configuration 231
P0MDOUT 0xA4 0x0 Port 0 Output Mode Configuration 231
P0SKIP 0xD4 0x0 Port 0 Skip 230
P1 0x90 All Port 1 Latch 233
P1DRV 0xA5 0xF Port 1 Drive Strength 235
P1MASK 0xBF 0x0 Port 1 Mask 228
P1MAT 0xCF 0x0 Port 1 Match 228
P1MDIN 0xF2 0x0 Port 1 Input Mode Configuration 234
P1MDOUT 0xA5 0x0 Port 1 Output Mode Configuration 234
P1SKIP 0xD5 0x0 Port 1 Skip 233
P2 0xA0 All Port 2 Latch 235
Table 10.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address SFR Page Description Page
Rev. 1.0 133
Si106x/108x
P2DRV 0xA6 0xF Port 2 Drive Strength 237
P2MDIN 0xF3 0x0 Port 2 Input Mode Configuration 236
P2MDOUT 0xA6 0x0 Port 2 Output Mode Configuration 237
P2SKIP 0xD6 0x0 Port 2 Skip 236
PCA0CN 0xD8 0x0 PCA0 Control 346
PCA0CPH0 0xFC 0x0 PCA0 Capture 0 High 351
PCA0CPH1 0xEA 0x0 PCA0 Capture 1 High 351
PCA0CPH2 0xEC 0x0 PCA0 Capture 2 High 351
PCA0CPH3 0xEE 0x0 PCA0 Capture 3 High 351
PCA0CPH4 0xFE 0x0 PCA0 Capture 4 High 351
PCA0CPH5 0xD3 0x0 PCA0 Capture 5 High 351
PCA0CPL0 0xFB 0x0 PCA0 Capture 0 Low 351
PCA0CPL1 0xE9 0x0 PCA0 Capture 1 Low 351
PCA0CPL2 0xEB 0x0 PCA0 Capture 2 Low 351
PCA0CPL3 0xED 0x0 PCA0 Capture 3 Low 351
PCA0CPL4 0xFD 0x0 PCA0 Capture 4 Low 351
PCA0CPL5 0xD2 0x0 PCA0 Capture 5 Low 351
PCA0CPM0 0xDA 0x0 PCA0 Module 0 Mode Register 349
PCA0CPM1 0xDB 0x0 PCA0 Module 1 Mode Register 349
PCA0CPM2 0xDC 0x0 PCA0 Module 2 Mode Register 349
PCA0CPM3 0xDD 0x0 PCA0 Module 3 Mode Register 349
PCA0CPM4 0xDE 0x0 PCA0 Module 4 Mode Register 349
PCA0CPM5 0xCE 0x0 PCA0 Module 5 Mode Register 349
PCA0H 0xFA 0x0 PCA0 Counter High 350
PCA0L 0xF9 0x0 PCA0 Counter Low 350
PCA0MD 0xD9 0x0 PCA0 Mode 347
PCA0PWM 0xDF 0x0 PCA0 PWM Configuration 348
PCON 0x87 0x0 Power Control 166
PMU0CF 0xB5 0x0 PMU0 Configuration 165
PSCTL 0x8F 0x0 Program Store R/W Control 157
PSW 0xD0 All Program Status Word 121
REF0CN 0xD1 0x0 Voltage Reference Control 102
REG0CN 0xC9 0x0 Voltage Regulator (VREG0) Control 184
RSTSRC 0xEF 0x0 Reset Source Configuration/Status 191
RTC0ADR 0xAC 0x0 RTC0 Address 205
RTC0DAT 0xAD 0x0 RTC0 Data 206
RTC0KEY 0xAE 0x0 RTC0 Key 204
SBUF0 0x99 0x0 UART0 Data Buffer 296
Table 10.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address SFR Page Description Page
Si106x/108x
134 Rev. 1.0
SCON0 0x98 0x0 UART0 Control 295
SFRPAGE 0xA7 All SFR Page 131
SMB0ADM 0xF5 0x0 SMBus Slave Address Mask 278
SMB0ADR 0xF4 0x0 SMBus Slave Address 278
SMB0CF 0xC1 0x0 SMBus0 Configuration 273
SMB0CN 0xC0 0x0 SMBus0 Control 275
SMB0DAT 0xC2 0x0 SMBus0 Data 281
SP 0x81 All Stack Pointer 120
SPI0CFG 0xA1 0x0 SPI0 Configuration 305
SPI0CKR 0xA2 0x0 SPI0 Clock Rate Control 307
SPI0CN 0xF8 0x0 SPI0 Control 306
SPI0DAT 0xA3 0x0 SPI0 Data 307
SPI1CFG 0x84 0x0 SPI1 Configuration 305
SPI1CKR 0x85 0x0 SPI1 Clock Rate Control 307
SPI1CN 0xB0 0x0 SPI1 Control 306
SPI1DAT 0x86 0x0 SPI1 Data 307
TCON 0x88 0x0 Timer/Counter Control 317
TH0 0x8C 0x0 Timer/Counter 0 High 320
TH1 0x8D 0x0 Timer/Counter 1 High 320
TL0 0x8A 0x0 Timer/Counter 0 Low 319
TL1 0x8B 0x0 Timer/Counter 1 Low 319
TMOD 0x89 0x0 Timer/Counter Mode 318
TMR2CN 0xC8 0x0 Timer/Counter 2 Control 324
TMR2H 0xCD 0x0 Timer/Counter 2 High 326
TMR2L 0xCC 0x0 Timer/Counter 2 Low 326
TMR2RLH 0xCB 0x0 Timer/Counter 2 Reload High 325
TMR2RLL 0xCA 0x0 Timer/Counter 2 Reload Low 325
TMR3CN 0x91 0x0 Timer/Counter 3 Control 330
TMR3H 0x95 0x0 Timer/Counter 3 High 332
TMR3L 0x94 0x0 Timer/Counter 3 Low 332
TMR3RLH 0x93 0x0 Timer/Counter 3 Reload High 331
TMR3RLL 0x92 0x0 Timer/Counter 3 Reload Low 331
TOFFH 0x86 0xF Temperature Offset High 99
TOFFL 0x85 0xF Temperature Offset Low 99
VDM0CN 0xFF 0x0 VDD Monitor Control 189
XBR0 0xE1 0x0 Port I/O Crossbar Control 0 224
XBR1 0xE2 0x0 Port I/O Crossbar Control 1 225
XBR2 0xE3 0x0 Port I/O Crossbar Control 2 226
Table 10.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address SFR Page Description Page
Rev. 1.0 135
Si106x/108x
Devices in the Si106x device family share the same SFR address locations for most registers. This allows
the si1060_defs.h and the si1080_defs.h header files to be used interchangeably in applications that target
devices in the Si106x and Si108x family. It also allows code developed on one device to be executed on
any other device in the product family without modification.
There are few minor differences between the si1060_defs.h and the si1080_defs.h files. When writing soft-
ware that targets multiple devices in the Si106x and Si108x family, the si1060_defs.h header file is recom-
mended because it does not contain definitions for the “plus” registers which are only found on the Si106x
devices. When using this header file, a compiler error will be generated if any of the “plus” registers are
used in the software.
Table 10.4 highlights the registers that are not identical in all devices in the Si106x and Si108x product
family.
Table 10.4. Select Registers with Varying Function
Register
Name Descriptio n of diffe r en c e
Registers Found only in C8051F930_defs.h
EMI0CF
EMI0TC
Only apply to 32-pin devices. EMIF is
not available on 24-pin devices.
P2SKIP
P2MDIN
Only apply to 32-pin devices. On 24-pin
devices, P2 does not have Crossbar or
analog functionality.
Registers Found only in C8051F912_defs.h
PMU0MD
DC0MD
IREF0CF
Only apply to the ‘F912 and ‘F902. Not
available on the ‘F911 or ‘F901.
Registers with bit differences
PCA0MD On ‘F912 and ‘F902 devices, SmaRT-
Clock/8 may be selected as the PCA
timebase.
VDM0CN On ‘F912 and ‘F902 devices, configura-
tion bits for the VBAT supply monitor can
be used to enable a VBAT low “early
warning” interrupt.
DC0CF On ‘F912 and ‘F902 devices, bit 7
enables the low power mode for the dc-
dc converter. This low power mode is a
“plus” feature.
ADC0AC On ‘F912 and ‘F902 devices, bit 7
enables the 12-bit mode for ADC0. The
12-bit mode is a “plus” feature.
Si106x/108x
136 Rev. 1.0
ADC0PWR On ‘F912 and ‘F902 devices, bit 7
enables the low power mode for ADC0.
This low power mode is a “plus” feature.
Indirect SmaRTClock registers with bit differences
RTC0XCN On ‘F912 and ‘F902 devices, bit 3
enables the SmaRTClock’s internal low
frequency oscillator. The LFO is a “plus”
feature.
RTC0PIN On C8051F930/31/20/21 devices, this
register is write only. It is R/W on all
other devices.
Table 10.4. Select Registers with Varying Function (Continued)
Register
Name Descriptio n of diffe r en c e
Rev. 1.0 137
Si106x/108x
11. Interrupt Handler
The Si106x/108x microcontroller family includes an extended interrupt system supporting multiple interrupt
sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and exter-
nal input pins varies according to the specific version of the device. Refer to Table 11.1, “Interrupt Sum-
mary,” on page 139 for a detailed listing of all interrupt sources supported by the device. Refer to the data
sheet section associated with a particular on-chip peripheral for information regarding valid interrupt condi-
tions for the peripheral and the behavior of its interrupt-pending flag(s).
Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR or an indi-
rect register. When a peripheral or external source meets a valid interrupt condition, the associated inter-
rupt-pending flag is set to logic 1. If both global interrupts and the specific interrupt source is enabled, a
CPU interrupt request is generated when the interrupt-pending flag is set.
As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predeter-
mined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Some interrupt-pending flags are automatically cleared by hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
11.1. Enabling Interrupt Sources
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be
globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recog-
nized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-
enable settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1.
11.2. MCU Interrupt Sources and Vectors
The CPU services interrupts by generating an LCALL to a predetermined address (the interrupt vector
address) to begin execution of an interrupt service routine (ISR). The interrupt vector addresses associ-
ated with each interrupt source are listed in Table 11.1 on page 139. Software should ensure that the inter-
rupt vector for each enabled interrupt source contains a valid interrupt service routine.
Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled
for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated
with the interrupt-pending flag.
Si106x/108x
138 Rev. 1.0
11.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish
execution after the high priority interrupt completes. Each interrupt has an associated interrupt priority bit in
in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority level. Low pri-
ority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 11.1 on
page 139 to determine the fixed priority order used to arbitrate between simultaneously recognized inter-
rupts.
11.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a sin-
gle instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maxi-
mum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt
is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the next
instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the interrupt,
5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock cycles to
execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority,
the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
Rev. 1.0 139
Si106x/108x
Table 11.1. Interrupt Summary
Interrupt Source
Interrupt Vector
Priority Order
Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled
Always
Highest
External Interrupt 0 (INT0)0x0003 0IE0 (TCON.1) YYEX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1TF0 (TCON.5) YYET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (INT1)0x0013 2IE1 (TCON.3) YYEX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3TF1 (TCON.7) YYET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4RI0 (SCON0.0)
TI0 (SCON0.1)
Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow 0x002B 5TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0 0x003B 7SI (SMB0CN.0) Y N ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm 0x0043 8ALRM (RTC0CN.2)* NNEARTC0
(EIE1.1)
PARTC0
(EIP1.1)
ADC0 Window
Comparator
0x004B 9AD0WINT
(ADC0CN.3)
Y N EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
ADC0 End of Conversion 0x0053 10 AD0INT (ADC0STA.5) Y N EADC0
(EIE1.3)
PADC0
(EIP1.3)
Programmable Counter
Array
0x005B 11 CF (PCA0CN.7)
CCFn (PCA0CN.n)
Y N EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
Comparator0 0x0063 12 CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
NNECP0
(EIE1.5)
PCP0
(EIP1.5)
Comparator1 0x006B 13 CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
NNECP1
(EIE1.6)
PCP1
(EIP1.6)
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
NNET3
(EIE1.7)
PT3
(EIP1.7)
VDD_MCU Supply
Monitor Early Warning
0x007B 15 VDDOK
(VDM0CN.5)1EWARN
(EIE2.0)
PWARN
(EIP2.0)
Port Match 0x0083 16 None EMAT
(EIE2.1)
PMAT
(EIP2.1)
Si106x/108x
140 Rev. 1.0
11.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
SmaRTClock Oscillator
Fail
0x008B 17 OSCFAIL
(RTC0CN.5)2NNERTC0F
(EIE2.2)
PFRTC0F
(EIP2.2)
Radio Serial
Interface (SPI1)
0x0093 18 SPIF (SPI1CN.7)
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
NNESPI1
(EIE2.3)
PSPI1
(EIP2.3)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
Table 11.1. Interrupt Summary (Continued)
Interrupt Source
Interrupt Vector
Priority Order
Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Rev. 1.0 141
Si106x/108x
SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable
SFR Definition 11.1. IE: Interrupt Enable
Bit76543210
Name EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EAEnable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6 ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
4 ES0 Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
3ET1
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2 EX1 Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1ET0
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0 EX0 Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
Si106x/108x
142 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable
SFR Definition 11.2. IP: Interrupt Priority
Bit76543210
Name PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type RR/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7 Unused Read = 1b, Write = don't care.
6 PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2
Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4 PS0 UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupt set to high priority level.
3PT1
Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2 PX1 External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0
Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0 PX0 External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
Rev. 1.0 143
Si106x/108x
SFR Page = All Pages; SFR Address = 0xE6
SFR Definition 11.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 ERTC0A ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ET3Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6ECP1
Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
5ECP0
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4 EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3 EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2EWADC0
Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1ERTC0A
Enable SmaRTClock Alarm Interrupts.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by a SmaRTClock Alarm.
0 ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Si106x/108x
144 Rev. 1.0
SFR Page = All Pages; SFR Address = 0xF6
SFR Definition 11.4. EIP1: Extended Interrupt Priority 1
Bit76543210
Name PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PRTC0A PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PT3Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6PCP1
Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
5PCP0
Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2PWADC0
ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1PRTC0A
SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
Rev. 1.0 145
Si106x/108x
SFR Page = All Pages;SFR Address = 0xE7
SFR Definition 11.5. EIE2: Extended Interrupt Enable 2
Bit76543210
Name ESPI1 ERTC0F EMAT EWARN
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = Don’t care.
3 ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
2ERTC0F
Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
1EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0EWARN
Enable VDD_MCU Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD_MCU Supply Monitor Early Warning interrupt.
0: Disable the VDD_MCU Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD_MCU Supply Monitor.
Si106x/108x
146 Rev. 1.0
SFR Page = All Pages; SFR Address = 0xF7
SFR Definition 11.6. EIP2: Extended Interrupt Priority 2
Bit76543210
Name PSPI1 PRTC0F PMAT PWARN
Type RRRRR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:4 Unused Read = 0000b. Write = Don’t care.
3PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
2PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
1PMAT
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0PWARN VDD_MCU Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD_MCU Supply Monitor Early Warning interrupt.
0: VDD_MCU Supply Monitor Early Warning interrupt set to low priority level.
1: VDD_MCU Supply Monitor Early Warning interrupt set to high priority level.
Rev. 1.0 147
Si106x/108x
11.6. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “31.1. Timer 0 and Timer 1” on page 313) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 11.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “20.3. Priority Crossbar
Decoder” on page 221 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
IT0 IN0PL INT0 Interrupt IT1 IN1PL INT1 Interrupt
1 0 Active low, edge sensitive 1 0 Active low, edge sensitive
1 1 Active high, edge sensitive 1 1 Active high, edge sensitive
0 0 Active low, level sensitive 0 0 Active low, level sensitive
0 1 Active high, level sensitive 0 1 Active high, level sensitive
Si106x/108x
148 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xE4
SFR Definition 11.7. IT01CF: INT0/INT1 Configuration
Bit76543210
Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000001
Bit Name Function
7IN1PLINT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
3IN0PL
INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Port pin without disturb-
ing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P0.0
001: Select P0.1
010: Select P0.2
011: Select P0.3
100: Select P0.4
101: Select P0.5
110: Select P0.6
111: Select P0.7
Rev. 1.0 149
Si106x/108x
12. Flash Memory
On-chip, re-programmable flash memory is included for program code and non-volatile data storage. The
flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during flash write/erase operations. Refer to Table 4.6
for complete flash memory electrical characteristics.
12.1. Programming the Flash Memory
The simplest means of programming the flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program flash memory, see Section “33. Device
Specific Behavior” on page 352.
The flash memory can be programmed by software using the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before programming flash memory using
MOVX, flash programming operations must be enabled by: (1) setting the PSWE Program Store Write
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target flash memory); and (2) Writing the
flash key codes in sequence to the flash lock register (FLKEY). The PSWE bit remains set until cleared by
software.
For detailed guidelines on programming flash from firmware, please see Section “12.5. Flash
Write and Erase Guidelines” on page 154.
To ensure the integrity of the flash contents, the on-chip VDD Monitor must be enabled and enabled as a
reset source in any system that includes code that writes and/or erases flash memory from software. Fur-
thermore, there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Any attempt to write or erase flash memory while the VDD Monitor is disabled, or not enabled
as a reset source, will cause a flash error device reset.
12.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The flash lock and key
register (FLKEY) must be written with the correct key codes, in sequence, before flash operations may be
performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in
order. If the key codes are written out of order, or the wrong codes are written, flash writes and erases will
be disabled until the next system reset. Flash writes and erases will also be disabled if a flash write or
erase is attempted before the key codes have been written properly. The flash lock resets after each write
or erase; the key codes must be written again before a following flash operation can be performed. The
FLKEY register is detailed in SFR Definition 12.2.
Si106x/108x
150 Rev. 1.0
12.1.2. Flash Erase Procedure
The flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps:
1. Save current interrupt state and disable interrupts.
2. Set the PSEE bit (register PSCTL).
3. Set the PSWE bit (register PSCTL).
4. Write the first key code to FLKEY: 0xA5.
5. Write the second key code to FLKEY: 0xF1.
6. Using the MOVX instruction, write a data byte to any location within the 1024-byte page to be erased.
7. Clear the PSWE and PSEE bits.
8. Restore previous interrupt state.
Steps 4–6 must be repeated for each 1024-byte page to be erased.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent erasure of some flash pages, such as the reserved area and the page
containing the lock bytes. For a summary of flash security settings and restrictions affecting flash erase
operations, please see Section “12.3. Security Options” on page 151.
3. 8-bit MOVX instructions cannot be used to erase or write to flash memory at addresses higher than 0x00FF.
12.1.3. Flash Write Procedure
A write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in flash. A byte location to be programmed should be erased before a new value is written.
The recommended procedure for writing a single byte in flash is as follows:
1. Save current interrupt state and disable interrupts.
2. Ensure that the flash byte has been erased (has a value of 0xFF).
3. Set the PSWE bit (register PSCTL).
4. Clear the PSEE bit (register PSCTL).
5. Write the first key code to FLKEY: 0xA5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a single data byte to the desired location within the 1024-byte sector.
8. Clear the PSWE bit.
9. Restore previous interrupt state.
Steps 5–7 must be repeated for each byte to be written.
Notes:
1. Future 16 and 8 kB derivatives in this product family will use a 512-byte page size. To maintain code
compatibility across the entire family, the erase procedure should be performed on each 512-byte section of
memory.
2. Flash security settings may prevent writes to some areas of flash, such as the reserved area. For a summary of
flash security settings and restrictions affecting flash write operations, please see Section “12.3. Security
Options” on page 151.
Rev. 1.0 151
Si106x/108x
12.2. Non-Volatile Data Storage
The flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
An additional 1024-byte scratchpad is available for non-volatile data storage. It is accessible at addresses
0x0000 to 0x03FF when SFLE is set to 1. The scratchpad area cannot be used for code execution.
12.3. Security Options
The CIP-51 provides security options to protect the flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase flash memory. Additional security features prevent proprietary program code and data con-
stants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of flash user space offers protection of the flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The flash security
mechanism allows the user to lock n 1024-byte flash pages, starting at page 0 (addresses 0x0000 to
0x03FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the
page containing the flash Security Lock Byte is unlocked when no other flash pages are locked (all
bits of the Lock Byte are 1) and locked when any other flash pages are locked (any bit of the Lock
Byte is 0). See the example below.
Figure 12.1. Si106x Flash Program Memory Map
Security Lock Byte: 11111101b
ones Complement: 00000010b
Flash pages locked: 3 (First two flash pages + Lock Byte Page)
Addresses locked: 0x0000 to 0x07FF (first two flash pages) and
0xF800 to 0xFBFF (Lock Byte Page)
Lock Byte Page
Access limit
set according
to the Flash
security lock
byte 0x0000
0x7FFF
Lock Byte
0x7FFE
0x8000
Flash
memory
organized in
1024-byte
pages
0x7C00
Unlocked Flash Pages
Locked when
any other
Flash pages
are locked
Lock Byte Page
0x0000
0xFBFF Lock Byte
Reserved
0xFBFE
0xFC00
0xF800
Unlocked Flash Pages
64KB Flash Device
(SFLE = 0) 32KB Flash Device
(SFLE = 0)
0x0000
Scratchpad Area
(Data Only)
0x03FF
64/32KB Flash Device
(SFLE = 1)
0xFFFF
Unpopulated
Address Space
(Reserved)
0xFFFF
Si106x/108x
152 Rev. 1.0
Figure 12.2. Si108x Flash Program Memory Map
The level of flash security depends on the flash access method. The three flash access methods that can
be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 12.1 summarizes the flash security
features of the Si106x/108x devices.
Table 12.1. Flash Security Summary
Action C2 Debug
Interface User Firmware executing from:
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte)
Permitted Permitted Permitted
Read, Write or Erase locked pages
(except page with Lock Byte)
Not Permitted FEDR Permitted
Read or Write page containing Lock Byte
(if no pages are locked)
Permitted Permitted Permitted
Read or Write page containing Lock Byte
(if any page is locked)
Not Permitted FEDR Permitted
Read contents of Lock Byte
(if no pages are locked)
Permitted Permitted Permitted
Read contents of Lock Byte
(if any page is locked)
Not Permitted FEDR Permitted
Erase page containing Lock Byte
(if no pages are locked)
Permitted FEDR FEDR
Erase page containing Lock Byte - Unlock all pages
(if any page is locked)
Only by C2DE FEDR FEDR
Lock additional pages
(change 1s to 0s in the Lock Byte)
Not Permitted FEDR FEDR
Unlock individual pages
(change 0s to 1s in the Lock Byte)
Not Permitted FEDR FEDR
Rev. 1.0 153
Si106x/108x
Read, Write or Erase Reserved Area Not Permitted FEDR FEDR
C2DE—C2 Device Erase (Erases all flash pages including the page containing the Lock Byte)
FEDR—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is 1 after reset)
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
- The scratchpad is locked when all other flash pages are locked.
- The scratchpad is erased when a Flash Device Erase command is performed.
Table 12.1. Flash Security Summary (Continued)
Si106x/108x
154 Rev. 1.0
12.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the flash
byte at address 0xFFFE.
The value of the flash byte at address 0xFFFE can be decoded as follows:
0xE0—Si1060/Si1080
0xE1—Si1061/Si1081
0xE2—Si1062/Si1082
0xE3—Si1063/Si1083
0xE4—Si1064/Si1084
0xE5—Si1065/Si1085
12.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of flash modi-
fying code can result in alteration of flash memory contents causing a system failure that is only recover-
able by re-flashing the code in the device.
To help prevent the accidental modification of flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on Si106x devices for the flash to be successfully modified. If either the VDD
Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be gener-
ated when the firmware attempts to modify the flash.
The following guidelines are recommended for any system that contains routines which write or erase flash
from code.
12.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts RST if
VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Notes: On Si106x/108x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write or
erase flash without generating a Flash Error Device Reset.
On Si106x/108x devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the flash write or erase
operation instruction.
Rev. 1.0 155
Si106x/108x
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
12.5.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
9. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the flash write or erase operation will be serviced in priority
order after the flash operation has been completed and interrupts have been re-enabled by software.
10.Make certain that the flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
11.Add address bounds checking to the routines that write or erase flash memory to ensure that a routine
called with an illegal address does not result in modification of the flash.
12.5.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
13.If operating from the external oscillator, switch to the internal oscillator during flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the flash operation has completed.
Additional flash recommendations and example code can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
Si106x/108x
156 Rev. 1.0
12.6. Minimizing Flash Read Current
The flash memory in the Si106x/108x devices is responsible for a substantial portion of the total digital sup-
ply current when the device is executing code. Below are suggestions to minimize flash read current.
1. Use Idle, Suspend, or Sleep Modes while waiting for an interrupt, rather than polling the interrupt flag.
Idle Mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no
more than three system clock cycles. See the Power Management chapter for details on the various
low-power operating modes.
2. Si106x/108x devices have a one-shot timer that saves power when operating at system clock
frequencies of 10 MHz or less. The one-shot timer generates a minimum-duration enable signal for the
flash sense amps on each clock cycle in which the flash memory is accessed. This allows the flash to
remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the one-shot
timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces
power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting
the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot, clear the BYPASS bit to logic 0. After
changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed
by a benign 3-byte instruction whose third byte is a don't care. An example of such an instruction is a 3-
byte MOV that targets the FLWR register. When programming in C, the dummy value written to FLWR
should be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
3. Flash read current depends on the number of address lines that toggle between sequential flash read
operations. In most cases, the difference in power is relatively small (on the order of 5%).
4. The flash memory is organized in rows. Each row in the Si106x/108x flash contains 128 bytes. A
substantial current increase can be detected when the read address jumps from one row in the flash
memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a 128-byte
flash row boundary. The flash address jumps from one row to another on two of every three clock
cycles. This can result in a current increase of up 30% when compared to the same 3-cycle loop
contained entirely within a single row.
5. To minimize the power consumption of small loops, it is best to locate them within a single row, if
possible. To check if a loop is contained within a flash row, divide the starting address of the first
instruction in the loop by 128. If the remainder (result of modulo operation) plus the length of the loop is
less than 127, then the loop fits inside a single flash row. Otherwise, the loop will be straddling two
adjacent flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to
another will occur on relatively few clock cycles, and any resulting increase in operating current will be
negligible.
Note: Future 16 and 8 kB derivatives in this product family will use a flash memory that is organized in rows of 64
bytes each. To maintain code compatibility across the entire family, it is best to locate small loops within a single
64-byte segment.
Rev. 1.0 157
Si106x/108x
SFR Page =0x0; SFR Address = 0x8F
SFR Definition 12.1. PSCTL: Program Store R/W Control
Bit76543210
Name SFLE PSEE PSWE
Type RRRRRR/W R/W R/W
Reset 00000000
Bit Name Function
7:3 Unused Read = 00000b, Write = don’t care.
2SFLE
Scratchpad Flash Memory Access Enable.
When this bit is set, flash MOVC reads and MOVX writes from user software are
directed to the Scratchpad flash sector. Flash accesses outside the address range
0x0000-0x03FF should not be attempted and may yield undefined results when SFLE
is set to 1.
0: Flash access from user software directed to the Program/Data Flash sector.
1: Flash access from user software directed to the Scratchpad Sector.
1 PSEE Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of flash program
memory to be erased. If this bit is logic 1 and flash writes are enabled (PSWE is logic
1), a write to flash memory using the MOVX instruction will erase the entire page that
contains the location addressed by the MOVX instruction. The value of the data byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
0 PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the flash program memory using the
MOVX write instruction. The flash location should be erased before writing data.
0: Writes to flash program memory disabled.
1: Writes to flash program memory enabled; the MOVX write instruction targets flash
memory.
Si106x/108x
158 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xB6
SFR Definition 12.2. FLKEY: Flash Lock and Key
Bit76543210
Name FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disabled after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a flash write or erase
operation is attempted while these operations are disabled, the flash will be perma-
nently
locked from writes or erasures until the next device reset. If an application never
writes to flash, it can intentionally lock the flash by writing a non-0xA5 value to FLKEY
from software.
Read:
When read, bits 1–0 indicate the current flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
Rev. 1.0 159
Si106x/108x
SFR Page = 0x0; SFR Address = 0xB6
SFR Page = 0x0; SFR Address = 0xE5
SFR Definition 12.3. FLSCL: Flash Scale
Bit 7 6 5 4 3 2 1 0
Name BYPASS
Type RR/W RRRRRR
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7 Reserved Always Write to 0.
6 BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0 Reserved Always Write to 000000.
Note: When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the FLWR register. When programming in C, the dummy value written to FLWR should be a non-
zero value to prevent the compiler from generating a 2-byte MOV instruction.
SFR Definition 12.4. FLWR: Flash Write Only
Bit 7 6 5 4 3 2 1 0
Name FLWR[7:0]
Type W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
Rev. 1.0 160
Si106x/108x
13. Power Management
Si106x/108x devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power man-
agement unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief
description of each power mode is provided in Table 13.1. Detailed descriptions of each mode can be
found in the following sections.
In battery powered systems, the system should spend as much time as possible in Sleep mode in order to
preserve battery life. When a task with a fixed number of clock cycles needs to be performed, the device
should switch to Normal mode, finish the task as quickly as possible, and return to Sleep mode. Idle Mode
and Suspend modes provide a very fast wake-up time; however, the power savings in these modes will not
be as much as in Sleep Mode. Stop Mode is included for legacy reasons; the system will be more power
efficient and easier to wake up when Idle, Suspend, or Sleep Mode are used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
buses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
Table 13.1. Power Modes
Power Mode Description Wake-Up
Sources Power Savings
Normal Device fully functional N/A Excellent MIPS/mW
Idle All peripherals fully functional.
Very easy to wake up.
Any Interrupt Good
No Code Execution
Stop Legacy 8051 low power mode.
A reset is required to wake up.
Any Reset Good
No Code Execution
Precision Oscillator Disabled
Suspend Similar to Stop Mode, but very fast
wake-up time and code resumes
execution at the next instruction.
SmaRTClock,
Port Match,
Comparator0,
RST pin
Very Good
No Code Execution
All Internal Oscillators Disabled
System Clock Gated
Sleep Ultra Low Power and flexible
wake-up sources. Code resumes
execution at the next instruction.
Comparator0 only functional in
two-cell mode.
SmaRTClock,
Port Match,
Comparator0,
RST pin
Excellent
Power Supply Gated
All Oscillators except SmaRT-
Clock Disabled
Si106x/108x
161 Rev. 1.0
13.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 13.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the device: VBAT, VDD/DC+,
and the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from
the VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in
one-cell mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from
the 1.8 V internal core supply. The RAM is also powered from the core supply in Normal mode.
Figure 13.1. Si106x/108x Power Distribution
RAM
VREG0
PMU0
Sleep Active/Idle/
Stop/Suspend
VBAT VDD/DC+
One-cell: 0.9 to 1.8 V
Two-cell: 1.8 to 3.6 V One-cell or Two-cell: 1.8 to 3.6 V
Analog Peripherals
10-bit
300 ksps
ADC
TEMP
SENSOR
A
M
U
X
VOLTAGE
COMPARATORS
+
-
+
-
VREF
Digital Peripherals
Flash
CIP-51
Core
UART
SPI
SMBusTimers
GPIO
1.8 V
DC0
SmaRTClock
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
1.9 V
typical Note: VDD/DC+ must be > VBAT
Rev. 1.0 162
Si106x/108x
13.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Note: To ensure the MCU enters a low power state upon entry into Idle Mode, the one-shot circuit should be enabled
by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 12.3. FLSCL: Flash Scale for
more information on how to properly clear the BYPASS bit.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “17.6. PCA Watchdog Timer
Reset” on page 190 for more information on the use and configuration of the WDT.
13.3. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the precision internal oscillator and CPU are
stopped; the state of the low power oscillator and the external oscillator circuit is not affected. Each analog
peripheral (including the external oscillator circuit) may be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µs.
Stop Mode is a legacy 8051 power mode; it will not result in optimal power savings. Sleep or Suspend
mode will provide more power savings if the MCU needs to be inactive for a long period of time.
On Si106x/108x devices, the Precision Oscillator Bias is not automatically disabled and should be disabled
by software to achieve the lowest possible Stop mode current.
Note: To ensure the MCU enters a low power state upon entry into Stop Mode, the one-shot circuit should be enabled
by clearing the BYPASS bit (FLSCL.6) to logic 0. See the note in SFR Definition 12.3. FLSCL: Flash Scale for
more information on how to properly clear the BYPASS bit.
Si106x/108x
163 Rev. 1.0
13.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops
functioning until one of the enabled wake-up sources occurs.
Important Notes:
When entering Suspend Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
The one-shot circ uit should be enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See the
note in SFR Definition 12.3. FLSCL: Flash Scale for more information on how to properly clear
the BYPASS bit.
Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the
PMU0CF wake-up flags. All flags will read back a value of 0 during the first two system clocks
following a wake-up from suspend mode.
The system clock source must be set to the low power internal oscillator or the precision
oscillator prior to entering suspend mode.
The following wake-up sources can be configured to wake the device from suspend mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 k
pullup resistor to VDD_MCU/DC+ is recommend for RST to prevent noise glitches from waking the device.
13.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VDD_MCU pin (see Figure 13.1). Power to most digital logic on
the device is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain
powered. The Comparators remain functional when the device enters sleep mode. All other analog periph-
erals (ADC0, External Oscillator, etc.) should be disabled prior to entering sleep mode. The system clock
source must be set to the low power internal oscillator or the precision oscillator prior to entering sleep
mode.
Important Notes:
When entering Slee p M od e , th e global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
Any write to PMU0CF which places the device in sleep mode should be immediately followed by two
NOP instructions. Software that does not place two NOP instructions immediately following the write to
PMU0CF should continue to behave the same way as during software development.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD_MCU/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage
level and the source and sink current drive capability.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specifications in sleep mode as
they have in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower
the switching threshold and increase the propagation delay.
Rev. 1.0 164
Si106x/108x
Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the
VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the
decoupling capacitance on the VDD/DC+ supply to maintain the supply rail until the capacitors are discharged.
For relatively short sleep intervals, this can result in substantial power savings because the decoupling
capacitance is not continuously charged and discharged.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT (or
VDD_MCU on Si1060/61/80/81 devices) does not fall below VPOR. The PC counter and all other volatile
state information is preserved allowing the device to resume code execution upon waking up from sleep
mode. The following wake-up sources can be configured to wake the device from sleep mode:
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD_MCU/DC+ is recommend for RST to prevent noise glitches from waking the device.
13.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any
interrupt. For stop mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for suspend and sleep modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in suspend or sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from sleep mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
13.7. Determining the Event that Caused the Last Wakeup
When waking from Idle Mode, the CPU will vector to the interrupt which caused it to wake up. When wak-
ing from Stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from Suspend or Sleep mode, the wake-up flags in the PMU0CF register can be read to deter-
mine the event which caused the device to wake up. After waking up, the wake-up flags will continue to be
updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as wake-up sources.
All wake-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
suspend or sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
Si106x/108x
165 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xB5
SFR Definition 13.1. PMU0CF: Power Management Unit Configuration1,2
Bit 76 543210
Name SLEEP SUSPEND CLEAR RSTWK RTCFWK RTCAWK PMATWK CPT0WK
Type W W W R R/W R/W R/W R/W
Reset 0 0 0 Varies Varies Varies Varies Varies
Bit Name Description Write Read
7 SLEEP Sleep Mode Select Writing 1 places the
device in Sleep Mode.
N/A
6 SUSPEND Suspend Mode Select Writing 1 places the
device in Suspend Mode.
N/A
5 CLEAR Wake-up Flag Clear Writing 1 clears all wake-
up flags.
N/A
4RSTWKReset Pin Wake-up Flag N/A Set to 1 if a falling edge has
been detected on RST.
3RTCFWKSmaRTClock Oscillator
Fail Wake-up Source
Enable and Flag
0: Disable wake-up on
SmaRTClock Osc. Fail.
1: Enable wake-up on
SmaRTClock Osc. Fail.
Set to 1 if the SmaRTClock
Oscillator has failed.
2RTCAWKSmaRTClock Alarm
Wake-up Source Enable
and Flag
0: Disable wake-up on
SmaRTClock Alarm.
1: Enable wake-up on
SmaRTClock Alarm.
Set to 1 if a SmaRTClock
Alarm has occurred.
1PMATWKPort Match Wak e-up
Source Enable and Flag 0: Disable wake-up on
Port Match Event.
1: Enable wake-up on
Port Match Event.
Set to 1 if a Port Match
Event has occurred.
0CPT0WKComparator0 Wake-u p
Source Enable and Flag 0: Disable wake-up on
Comparator0 rising edge.
1: Enable wake-up on
Comparator0 rising edge.
Set to 1 if Comparator0 ris-
ing edge caused the last
wake-up.
Notes:
1. Read-modify-write operations (ORL, ANL, etc.) should not be used on this register. Wake-up sources must be
re-enabled each time the SLEEP or SUSPEND bits are written to 1.
2. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
Rev. 1.0 166
Si106x/108x
SFR Page = All Pages; SFR Address = 0x87
13.8. Power Management Specifications
See Table 4.5 on page 58 for detailed Power Management Specifications.
SFR Definition 13.2. PCON: Power Management Control Register
Bit 76 543210
Name GF[5:0] STOP IDLE
Type R/W W W
Reset 00 000000
Bit Name Description Write Read
7:2 GF[5:0] General Purpose Flags Sets the logic value. Returns the logic value.
1STOPStop Mode Select Writing 1 places the
device in Stop Mode.
N/A
0IDLEIdle Mode Select Writing 1 places the
device in Idle Mode.
N/A
Rev. 1.0 167
Si106x/108x
14. Cyclic Redundancy Check Unit (CRC0)
Si106x/108x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit
or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the
16-bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using
the CRC0PNT bits and CRC0DAT register, as shown in Figure 14.1. CRC0 also has a bit reverse register
for quick data manipulation.
Figure 14.1. CRC0 Block Diagram
14.1. 16-bit CRC Algorithm
The Si106x/108x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16-bit CRC algorithm performed by the hardware:
1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the
CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
2a. If the MSB of the CRC result is set, left-shift the CRC result and XOR the result with the selected
polynomial (0x1021).
2b. If the MSB of the CRC result is not set, left-shift the CRC result.
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-
ple.
The 16-bit Si106x/108x CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
#define POLY 0x1021
CRC0IN 8
CRC0DAT
CRC0CN
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC Engine
4 to 1 MUX
RESULT
32
8 8 8 8
8
CRC0AUTO
CRC0CNT
Automatic CRC
Controller
Flash
Memory
8
CRC0FLIP
Write
CRC0FLIP
Read
Si106x/108x
168 Rev. 1.0
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ (CRC_input << 8);
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 16-bit Si106x/108x CRC
algorithm:
Table 14.1. Example 16-bit CRC Outputs
Input Output
0x63 0xBD35
0x8C 0xB1F4
0x7D 0x4ECA
0xAA, 0xBB, 0xCC 0x6CF6
0x00, 0x00, 0xAA, 0xBB, 0xCC 0xB166
Rev. 1.0 169
Si106x/108x
14.2. 32-bit CRC Algorithm
The Si106x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algorithm is
"reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the processing
engine. The following is a description of a simplified CRC algorithm that produces results identical to the
hardware:
Step 1. XOR the least-significant byte of the current CRC result with the input byte. If this is the
first iteration of the CRC unit, the current CRC result will be the set initial value
(0x00000000 or 0xFFFFFFFF).
Step 2. Right-shift the CRC result.
Step 3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial
(0xEDB88320).
Step 4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit Si106x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
}
}
// Return the final remainder (CRC value)
return CRC_acc;
}
The following table lists several input values and the associated outputs using the 32-bit Si106x CRC algo-
rithm (an initial value of 0xFFFFFFFF is used):
Si106x/108x
170 Rev. 1.0
14.3. Preparing for a CRC Calculation
To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial
value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0
result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF. The following steps can be
used to initialize CRC0.
1. Select a polynomial (Set CRC0SEL to 0 for 32-bit or 1 for 16-bit).
2. Select the initial result value (Set CRC0VAL to 0 for 0x00000000 or 1 for 0xFFFFFFFF).
3. Set the result to its initial value (Write 1 to CRC0INIT).
14.4. Performing a CRC Calculation
Once CRC0 is initialized, the input data stream is sequentially written to CRC0IN, one byte at a time. The
CRC0 result is automatically updated after each byte is written. The CRC engine may also be configured to
automatically perform a CRC on one or more Flash sectors. The following steps can be used to automati-
cally perform a CRC on Flash memory.
1. Prepare CRC0 for a CRC calculation as shown above.
2. Write the index of the starting page to CRC0AUTO.
3. Set the AUTOEN bit in CRC0AUTO.
4. Write the number of Flash sectors to perform in the CRC calculation to CRC0CNT.
Note: Each Flash sector is 1024 bytes.
5. Write any value to CRC0CN (or OR its contents with 0x00) to initiate the CRC calculation. The CPU will
not execute code any additional code until the CRC operation completes.
6. After initiating an automatic CRC calculation, the third opcode byte fetched from program memory is
indeterminate. Therefore, writes to CRC0CN that initiate a CRC operation must be immediately
followed by a benign 3-byte instruction whose third byte is a don't care. An example of such an
instruction is a 3-byte MOV that targets the CRC0FLIP register. When programming in C, the dummy
value written to CRC0FLIP should be a non-zero value to prevent the compiler from generating a 2-byte
MOV instruction.
7. Clear the AUTOEN bit in CRC0AUTO.
8. Read the CRC result using the procedure below.
14.5. Accessing the CRC0 Result
The internal CRC0 result is 32-bits (CRC0SEL = 0b) or 16-bits (CRC0SEL = 1b). The CRC0PNT bits
select the byte that is targeted by read and write operations on CRC0DAT and increment after each read or
write. The calculation result will remain in the internal CR0 result register until it is set, overwritten, or addi-
tional data is written to CRC0IN.
Table 14.2. Example 32-bit CRC Outputs
Input Output
0x63 0xF9462090
0xAA, 0xBB, 0xCC 0x41B207B3
0x00, 0x00, 0xAA, 0xBB, 0xCC 0x78D129BC
Rev. 1.0 171
Si106x/108x
SFR Page = 0xF; SFR Address = 0x92
SFR Definition 14.1. CRC0CN: CRC0 Control
Bit 76543210
Name CRC0SEL CRC0INIT CRC0VAL CRC0PNT[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care.
4 CRC0SEL CRC0 Polynomial Select Bit.
This bit selects the CRC0 polynomial and result length (32-bit or 16-bit).
0: CRC0 uses the 32-bit polynomial 0x04C11DB7 for calculating the CRC result.
1: CRC0 uses the 16-bit polynomial 0x1021 for calculating the CRC result.
3 CRC0INIT CRC0 Result Initialization Bit.
Writing a 1 to this bit initializes the entire CRC result based on CRC0VAL.
2 CRC0VAL CRC0 Set Value Initialization Bit.
This bit selects the set value of the CRC result.
0: CRC result is set to 0x00000000 on write of 1 to CRC0INIT.
1: CRC result is set to 0xFFFFFFFF on write of 1 to CRC0INIT.
1:0 CRC0PNT[1:0] CRC0 Result Pointer.
Specifies the byte of the CRC result to be read/written on the next access to
CRC0DAT. The value of these bits will auto-increment upon each read or write.
For CRC0SEL = 0:
00: CRC0DAT accesses bits 7–0 of the 32-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 32-bit CRC result.
10: CRC0DAT accesses bits 23–16 of the 32-bit CRC result.
11: CRC0DAT accesses bits 31–24 of the 32-bit CRC result.
For CRC0SEL = 1:
00: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
01: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
10: CRC0DAT accesses bits 7–0 of the 16-bit CRC result.
11: CRC0DAT accesses bits 15–8 of the 16-bit CRC result.
Note: Upon initiation of an automatic CRC calculation, the third opcode byte fetched from program memory is
indeterminate. Therefore, writes to CRC0CN that initiate a CRC operation must be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the CRC0FLIP register. When programming in ‘C’, the dummy value written to CRC0FLIP should
be a non-zero value to prevent the compiler from generating a 2-byte MOV instruction.
Si106x/108x
172 Rev. 1.0
SFR Page = 0xF; SFR Address = 0x93
SFR Page = 0xF; SFR Address = 0x91
SFR Definition 14.2. CRC0IN: CRC0 Data Input
Bit 76543210
Name CRC0IN[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 14.1
SFR Definition 14.3. CRC0DAT: CRC0 Data Output
Bit 76543210
Name CRC0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
Rev. 1.0 173
Si106x/108x
SFR Page = 0xF; SFR Address = 0x96
SFR Page = 0xF; SFR Address = 0x97
SFR Definition 14.4. CRC0AUTO: CRC0 Automatic Control
Bit 7 6 5 4 3 2 1 0
Name AUTOEN CRCDONE CRC0ST[5:0]
Type R/W R/W
Reset 0 1 0 0 0 0 0 0
Bit Name Function
7AUTOENAutomatic CRC Calculation Enable.
When AUTOEN is set to 1, any write to CRC0CN will initiate an automatic CRC
starting at Flash sector CRC0ST and continuing for CRC0CNT sectors.
6 CRCDONE CRCDONE Automatic CRC Calculation Complete.
Set to '0' when a CRC calculation is in progress. Note that code execution is
stopped during a CRC calculation, therefore reads from firmware will always
return '1'.
5:0 CRC0ST[5:0] Automatic CRC Calculation Starting Flash Sector.
These bits specify the Flash sector to start the automatic CRC calculation. The
starting address of the first Flash sector included in the automatic CRC calculation
is CRC0ST x 1024.
SFR Definition 14.5. CRC0CNT: CRC0 Automatic Flash Sector Count
Bit 76543210
Name CRC0CNT[5:0]
Type R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 CRC0CNT[5:0] Automatic CRC Calculation Flash Sector Count.
These bits specify the number of Flash sectors to include in an automatic CRC
calculation. The starting address of the last Flash sector included in the automatic
CRC calculation is (CRC0ST+CRC0CNT) x 1024.
Si106x/108x
174 Rev. 1.0
14.6. CRC0 Bit Reverse Feature
CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 14.2. Each byte
of data written to CRC0FLIP is read back bit reversed. For example, if 0xC0 is written to CRC0FLIP, the
data read back is 0x03. Bit reversal is a useful mathematical function used in algorithms such as the FFT.
Figure 14.2. Bit Reverse Register
SFR Page = 0xF; SFR Address = 0x95
SFR Definition 14.6. CRC0FLIP: CRC0 Bit Flip
Bit 76543210
Name CRC0FLIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 CRC0FLIP[7:0] CRC0 Bit Flip.
Any byte written to CRC0FLIP is read back in a bit-reversed order, i.e. the written
LSB becomes the MSB. For example:
If 0xC0 is written to CRC0FLIP, the data read back will be 0x03.
If 0x05 is written to CRC0FLIP, the data read back will be 0xA0.
CRC0FLIP
Write
CRC0FLIP
Read
Rev. 1.0 175
Si106x/108x
15. On-Chip DC-DC Converter (DC0)
Si1062/3/4/5, Si1082/3/4/5 devices include an on-chip dc-dc converter to allow operation from a single cell
battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an
input voltage range of 0.9 to 1.8 V and a programmable output voltage range of 1.8 to 3.3 V. The default
output voltage is 1.9 V. The dc-dc converter can supply the system with up to 65 mW of regulated power
(or up to 100 mW in some applications) and can be used for powering other devices in the system. This
allows the most flexibility when interfacing to sensors and other analog signals which typically require a
higher supply voltage than a single-cell battery can provide.
Figure 15.1 shows a block diagram of the dc-dc converter. During normal operation in the first half of the
switching cycle, the Duty Cycle Control switch is closed and the Diode Bypass switch is open. Since the
output voltage is higher than the voltage at the DCEN pin, no current flows through the diode and the load
is powered from the output capacitor. During this stage, the DCEN pin is connected to ground through the
Duty Cycle Control switch, generating a positive voltage across the inductor and forcing its current to ramp
up.
In the second half of the switching cycle, the Duty Cycle control switch is opened and the Diode Bypass
switch is closed. This connects DCEN directly to VDD_MCU/DC+ and forces the inductor current to charge
the output capacitor. Once the inductor transfers its stored energy to the output capacitor, the Duty Cycle
Control switch is closed, the Diode Bypass switch is opened, and the cycle repeats.
The dc-dc converter has a built in voltage reference and oscillator, and will automatically limit or turn off the
switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises
above the programmed target value. This allows the dc-dc converter output to be safely overdriven by a
secondary power source (when available) in order to preserve battery life. The dc-dc converter’s settings
can be modified using SFR registers which provide the ability to change the target output voltage, oscillator
frequency or source, Diode Bypass switch resistance, peak inductor current, and minimum duty cycle.
Figure 15.1. DC-DC Converter Block Diagram
VBAT
VDD_MCU/DC+
DCEN
GND_MCU/DC-GND/VBAT-
1uF Cload
Iload
Control Logic
Duty
Cycle
Control
Diode
Bypass
0.68 uH
DC/DC Converter
DC0CF
DC0CN
DC/DC
Oscillator
Voltage
Reference
Lparasitic
4.7 uF
Lparasitic
Si106x/108x
176 Rev. 1.0
15.1. Startup Behavior
On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage
on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur-
rent present during startup will determine the length of time it takes to charge the output capacitor.
During initial power-on reset, the maximum peak inductor current threshold, which triggers the overcurrent
protection circuit, is set to approximately 125 mA. This generates a “soft-start” to limit the output voltage
slew rate and prevent excessive in-rush current at the output capacitor. In order to ensure reliable startup
of the dc-dc converter, the following restrictions have been imposed:
• The maximum dc load current allowed during startup is given in Table 4.14 on page 66. If the dc-dc
converter is powering external sensors or devices through the VDD_MCU/DC+ pin or through GPIO
pins, then the current supplied to these sensors or devices is counted towards this limit. The in-rush
current into capacitors does not count towards this limit.
• The maximum total output capacitance is given in Tab le 4.14 on page 66. This value includes the
required 1 µF ceramic output capacitor and any additional capacitance connected to the
VDD_MCU/DC+ pin.
Once initial power-on is complete, the peak inductor current limit can be increased by software as shown in
Table 15.1. Limiting the peak inductor current can allow the device to start up near the battery’s end of life.
.
The peak inductor current is dependent on several factors including the dc load current and can be esti-
mated using following equation:
efficiency = 0.80
inductance = 0.68 µH
frequency = 2.4 MHz
Table 15.1. IPeak Inductor Current Limit Settings
SWSEL ILIMIT Peak Current (mA)
1 0 100
0 0 125
1 1 250
0 1 500
IPK 2 ILOAD VDD/DC+ VBAT–
efficiency inductancefrequency
-------------------------------------------------------------------------------------------=
Rev. 1.0 177
Si106x/108x
15.2. High Power Applications
The dc-dc converter is designed to provide the system with 65 mW of output power, however, it can safely
provide up to 100 mW of output power without any risk of damage to the device. For high power applica-
tions, the system should be carefully designed to prevent unwanted VBAT and VDD_MCU/DC+ Supply
Monitor resets, which are more likely to occur when the dc-dc converter output power exceeds 65mW. In
addition, output power above 65 mW causes the dc-dc converter to have relaxed output regulation, high
output ripple and more analog noise. At high output power, an inductor with low DC resistance should be
chosen in order to minimize power loss and maximize efficiency.
The combination of high output power and low input voltage will result in very high peak and average
inductor currents. If the power supply has a high internal resistance, the transient voltage on the VBAT ter-
minal could drop below 0.9 V and trigger a VBAT Supply Monitor Reset, even if the open-circuit voltage is
well above the 0.9 V threshold. While this problem is most often associated with operation from very small
batteries or batteries that are near the end of their useful life, it can also occur when using bench power
supplies that have a slow transient response; the supply’s display may indicate a voltage above 0.9 V, but
the minimum voltage on the VBAT pin may be lower. A similar problem can occur at the output of the dc-dc
converter: using the default low current limit setting (125 mA) can trigger VDD Supply Monitor resets if there
is a high transient load current, particularly if the programmed output voltage is at or near 1.8 V.
15.3. Pulse Skipping Mode
The dc-dc converter allows the user to set the minimum pulse width such that if the duty cycle needs to
decrease below a certain width in order to maintain regulation, an entire "clock pulse" will be skipped.
Pulse skipping can provide substantial power savings, particularly at low values of load current. The con-
verter will continue to maintain a minimum output voltage at its programmed value when pulse skipping is
employed, though the output voltage ripple can be higher. Another consideration is that the dc-dc will oper-
ate with pulse-frequency modulation rather than pulse-width modulation, which makes the switching fre-
quency spectrum less predictable; this could be an issue if the dc-dc converter is used to power a radio.
Figure 4.5 and Figure 4.6 on page 50 and page 51 show the effect of pulse skipping on power consump-
tion.
15.4. Enabling the DC-DC Converter
On power-on reset, the state of the DCEN pin is sampled to determine if the device will power up in one-
cell or two-cell mode. In two-cell mode, the dc-dc converter always remains disabled. In one-cell mode, the
dc-dc converter remains disabled in Sleep Mode, and enabled in all other power modes. See Section
“13. Power Management” on page 160 for complete details on available power modes.
The dc-dc converter is enabled (one-cell mode) in hardware by placing a 0.68 µH inductor between DCEN
and VBAT. The dc-dc converter is disabled (two-cell mode) by shorting DCEN directly to GND. The DCEN
pin should never be left floating. Note that the device can only switch between one-cell and two-cell mode
during a power-on reset. See Section “17. Reset Sources” on page 185 for more information regarding
reset behavior.
Figure 15.2 shows the two dc-dc converter configuration options.
Si106x/108x
178 Rev. 1.0
Figure 15.2. DC-DC Converter Configuration Options
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
In most cases, the GND/VBAT– pin should not be externally connected to GND.
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
The 4.7 µF capacitor should be placed as close as possible to the inductor.
The current loop including GND/VBAT–, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin
should be made as short as possible to minimize capacitance.
The PCB traces connecting VDD_MCU/DC+ to the output capacitor and the output capacitor to
GND_MCU/DC– should be as short and as thick as possible in order to minimize parasitic inductance.
VBAT VDD_MCU/
DC+
DCEN GND_MCU/
DC-
1 uF
0
.
68 uH
GND/VBAT-
4.7 uF
VBAT
VDD_MCU/
DC+
DCEN GND_MCU/
DC-
GND/VBAT-
DC-DC Converter
Enabled
0.9 to 1.8 V
Supply Voltage
(one-cell mode)
DC-DC Converter
Disabled
1.8 to 3.6 V
Supply Voltage
(two-cell mode)
Rev. 1.0 179
Si106x/108x
15.5. Minimizing Power Supply Noise
To minimize noise on the power supply lines, the GND/VBAT– and GND_MCU/DC- pins should be kept
separate, as shown in Figure 15.2; GND_MCU/DC- should be connected to the pc board ground plane.
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g., connecting an
external device between VDD_MCU/DC+ and GND/VBAT-, or between VBAT and GND_MCU/DC-) can
result in high supply noise across that circuit element.
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section
5.12. This option prevents any voltage differences between the internal chip ground and the external
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the
ground reference of the external analog input signal. When using the ADC with the dc-dc converter, we
also recommend enabling the SYNC bit in the DC0CN register to minimize interference.
These general guidelines provide the best performance in most applications, though some situations may
benefit from experimentation to eliminate any residual noise issues. Examples might include tying the
grounds together, using additional low-inductance decoupling caps in parallel with the recommended ones,
investigating the effects of different dc-dc converter settings, etc.
15.6. Selecting the Optimum Switch Size
The dc-dc converter has two built-in switches (the diode bypass switch and duty cycle control switch). To
maximize efficiency, one of two switch sizes may be selected. The large switches are ideal for carrying
high currents and the small switches are ideal for low current applications. The ideal switchover point to
switch from the small switches to the large switches varies with the programmed output voltage. At an out-
put voltage of 2 V, the ideal switchover point is at approximately 4 mA total output current. At an output
voltage of 3 V, the ideal switchover point is at approximately 8 mA total output current.
15.7. DC-DC Converter Clocking Options
The dc-dc converter may be clocked from its internal oscillator, or from any system clock source, select-
able by the CLKSEL bit (DC0CF.0). The dc-dc converter internal oscillator frequency is approximately
2.4 MHz. For a more accurate clock source, the system clock, or a divided version of the system clock may
be used as the dc-dc clock source. The dc-dc converter has a built in clock divider (configured using
DC0CF[6:5]) which allows any system clock frequency over 1.6 MHz to generate a valid clock in the range
of 1.6 to 3.2 MHz.
When the precision internal oscillator is selected as the system clock source, the OSCICL register may be
used to fine tune the oscillator frequency and the dc-dc converter clock. The oscillator frequency should
only be decreased since it is factory calibrated at its maximum frequency. The minimum frequency which
can be reached by the oscillator after taking into account process variations is approximately 16 MHz. The
system clock routed to the dc-dc converter clock divider also may be inverted by setting the CLKINV bit
(DC0CF.3) to logic 1. These options can be used to minimize interference in noise sensitive applications.
Si106x/108x
180 Rev. 1.0
15.8. DC-DC Converter Behavior in Sleep Mode
When the Si106x/108x devices are placed in Sleep mode, the dc-dc converter is disabled, and the
VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO
pins are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as
inputs or outputs during sleep mode, then the VDD_MCU/DC+ output can be made to float during Sleep
mode by setting the VDDSLP bit in the DC0CF register to 1.
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the
VDD_MCU/DC+ load current (include leakage currents) is negligible, then the capacitor on
VDD_MCU/DC+ will maintain the output voltage near the programmed value, which means that the
VDD_MCU/DC+ capacitor will not need to be recharged upon every wake up event. The second power
advantage is that internal or external low-power circuits that require more than 1.8 V can continue to func-
tion during Sleep mode without operating the dc-dc converter, powered by the energy stored in the 1 µF
output decoupling capacitor. For example, the comparators require about 0.4 µA when operating in their
lowest power mode. If the dc-dc converter output were increased to 3.3 V just before putting the device
into Sleep mode, then the comparator could be powered for more than 3 seconds before the output voltage
dropped to 1.8 V. In this example, the overall energy consumption would be much lower than if the dc-dc
converter were kept running to power the comparator.
If the load current on VDD_MCU/DC+ is high enough to discharge the VDD_MCU/DC+ capacitance to a
voltage lower than VBAT during the sleep interval, an internal diode will prevent VDD_MCU/DC+ from
dropping more than a few hundred millivolts below VBAT. There may be some additional leakage current
from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be
small compared to the current from VDD_MCU/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL and
ILIMIT bits, the battery internal resistance, the load current, and the difference between the VBAT voltage
level and the programmed output voltage. The wake up time can be as short as 2 µs, though it is more
commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.
See Section “13. Power Management” on page 160 for more information about sleep mode.
Rev. 1.0 181
Si106x/108x
15.9. DC-DC Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions. The
reset values for these registers can be used as-is in most systems; therefore, no software intervention or
initialization is required.
SFR Page = 0x0; SFR Address = 0x97
SFR Definition 15.1. DC0CN: DC-DC Converter Control
Bit 76543210
Name MINPW SWSEL Reserved SYNC VSEL
Type R/W R/W R/W R/W R/W
Reset 00100001
Bit Name Function
7:6 MINPW[1:0] DC-DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: No minimum duty cycle.
01: Minimum pulse width is 20 ns.
10: Minimum pulse width is 40 ns.
11: Minimum pulse width is 80 ns.
5 SWSEL DC-DC Converter Switch Select.
Selects one of two possible converter switch sizes to maximize efficiency.
0: The large switches are selected (best efficiency for high output currents).
1: The small switches are selected (best efficiency for low output currents).
4 Reserved Always Write to 0.
3SYNCADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b. Behavior as described is valid in REVC and later devices.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
2:0 VSEL[2:0] DC-DC Converter Output Voltage Select.
Specifies the target output voltage.
000: Target output voltage is 1.8 V.
001: Target output voltage is 1.9 V.
010: Target output voltage is 2.0 V.
011: Target output voltage is 2.1 V.
100: Target output voltage is 2.4 V.
101: Target output voltage is 2.7 V.
110: Target output voltage is 3.0 V.
111: Target output voltage is 3.3 V.
Si106x/108x
182 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x96
SFR Definition 15.2. DC0CF: DC-DC Converter Configuration
Bit 7 6 5 4 3 2 1 0
Name Reserved CLKDIV[1:0] AD0CKINV CLKINV ILIMIT VDDSLP CLKSEL
Type RR/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7 Reserved Read = 0b; Must write 0b.
6:5 CLKDIV[1:0] DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4 AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3CLKINV
DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2ILIMITPeak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current. See Table 15.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1 VDDSLP VDD_MCU/DC+ Sleep Mode Connection.
Specifies the power source for VDD_MCU/DC+ in Sleep Mode when the dc-dc con-
verter is enabled.
0: VDD_MCU/DC+ connected to VBAT in Sleep Mode.
1: VDD_MCU/DC+ is floating in Sleep Mode.
0CLKSEL
DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
Rev. 1.0 184
Si106x/108x
16. Voltage Regulator (VREG0)
Si106x/108x devices include an internal voltage regulator (VREG0) to regulate the internal core supply to
1.8 V from a VDD_MCU supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are spec-
ified in the Electrical Specifications chapter.
The REG0CN register allows the Precision Oscillator Bias to be disabled, saving approximately 80 µA in
all non-Sleep power modes. This bias should only be disabled when the precision oscillator is not being
used.
The internal regulator (VREG0) is disabled when the device enters Sleep Mode and remains enabled
when the device enters Suspend Mode. See Section “13. Power Management” on page 160 for complete
details about low power modes.
SFR Page = 0x0; SFR Address = 0xC9
16.1. Voltage Regulator Electrical Specifications
See Table 4.14 on page 66 for detailed Voltage Regulator Electrical Specifications.
SFR Definition 16.1. REG0CN: Voltage Regulator Control
Bit76543210
Name Reserved Reserved OSCBIAS Reserved
Type R R/W R/W R/W R R R R/W
Reset 00010000
Bit Name Function
7 Unused Read = 0b. Write = Don’t care.
6:5 Reserved Read = 0b. Must Write 0b.
4 OSCBIAS Precision Oscillator Bias.
When set to 1, the bias used by the precision oscillator is forced on. If the precision
oscillator is not being used, this bit may be cleared to 0 to save approximately 80 µA
of supply current in all non-Sleep power modes. If disabled then re-enabled, the pre-
cision oscillator bias requires 4 µs of settling time.
3:1 Unused Read = 000b. Write = Don’t care.
0 Reserved Read = 0b. Must Write 0b.
Rev. 1.0 185
Si106x/108x
17. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are unaf-
fected during a reset; any previously stored data is preserved as long as power is not lost. Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled
during and after the reset. For power-on resets, the RST pin is high-impedance with the weak pull-up off
until the device exits the reset state. For VDD monitor resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “18. Clocking Sources” on page 192 for information on selecting and configur-
ing the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its
clock source (Section “32.4. Watchdog Timer Mode” on page 344 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
Figure 17.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN
SWRSF
System
Clock CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Illegal Flash
Operation
RST
(wired-OR)
0
+
-
Comparator 0
VDD_MCU/DC+
+
-
Supply
Monitor
Enable
SmaRTClock RTC0RE
C0RSEF
Power-On Reset
Power Management
Block (PMU0)
System Reset
VBAT
Power On
Reset
Reset
Si106x/108x
186 Rev. 1.0
17.1. MCU Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VBAT settles above
VPOR. An additional delay occurs before the device is released from reset; the delay decreases as the
VBAT ramp time increases (VBAT ramp time is defined as how fast VBAT ramps from 0 V to VPOR).
Figure 17.3 plots the power-on and VDD monitor reset timing. For valid ramp times (less than 3 ms), the
power-on reset delay (TPORDelay) is typically 3 ms (VBAT = 0.9 V), 7 ms (VBAT = 1.8 V), or 15 ms (VBAT =
3.6 V).
Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before VBAT reaches the VPOR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
Figure 17.2. Power-Fail Reset Timing Diagram
Power-On
Reset
Power-On
Reset
RST
t
volts
~0.5
0.6
Logic HIGH
Logic LOW
TPORDelay
VBAT
~0.8 VPOR
VBAT
See specification
table for min/max
voltages.
TPORDelay
Rev. 1.0 187
Si106x/108x
17.2. Power-Fail (VDD_MCU Supply Monitor) Reset
Si106x/108x devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source
after each power-on or power-fail reset. When enabled and selected as a reset source, any power down
transition or power irregularity that causes VDD_MCU to drop below VRST will cause the RST pin to be
driven low and the CIP-51 will be held in a reset state (see Figure 17.3). When VDD_MCU returns to a
level above VRST
, the CIP-51 will be released from the reset state.
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the VDD_MCU supply
monitor is enabled and selected as a reset source. The enable state of the VDD_MCU supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD_MCU supply monitor is de-selected as a reset source and disabled by software, then a software
reset is performed, the VDD_MCU supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below VPOR. A large capacitor can be used to hold the power supply voltage
above VPOR while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
source select state of the VDD_MCU supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD_MCU supply falls below the VWARN threshold. The VDDOK bit can be configured to generate an
interrupt. See Section “11. Interrupt Handler” on page 137 for more details.
Important Note: To protect the integrity of Flash contents, the VDD_MCU supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD_MCU supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
Figure 17.3. Power-Fail Reset Timing Diagram
t
volts
VRST
VDD_MCU/DC+
VPOR
VWARN
VBAT
Note: Wakeup signal
required after new
battery insertion
VDDOK
SLEEP
RST
Active Mode
Power-Fail Reset
Sleep Mode
RAM Retained - No Reset
Si106x/108x
188 Rev. 1.0
Important Notes:
The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section
“4. Electrical Characteristics” on page 42 for complete electrical characteristics of the VDD_MCU
monitor.
Software should take care not to inadvertently disable the VDD Monitor as a reset source when writing
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source.
The VDD_MCU supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD_MCU supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD_MCU supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 42 for minimum VDD_MCU Supply Monitor turn-on time. No delay should be introduced in
systems where softwa re contains routines that er ase or write Flash memory. The procedure for
enabling the VDD_MCU supply monitor and selecting it as a reset source is shown below:
1. Enable the VDD_MCU Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD_MCU Supply Monitor to stabilize (optional).
3. Select the VDD_MCU Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
Rev. 1.0 189
Si106x/108x
SFR Page = 0x0; SFR Address = 0xFF
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST pin spec-
ifications. The external reset remains functional even when the device is in the low power Suspend and
Sleep Modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power Suspend or
Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
SFR Definition 17.1. VDM0CN: VDD_MCU Supply Monitor Control
Bit 76543210
Name VDMEN VDDSTAT VDDOK Reserved Reserved Reserved
Type R/W R R R/W R/W R/W R/W R/W
Reset 1Varies Varies 00000
Bit Name Function
7VDMENVDD_MCU Supply Monitor Enable.
This bit turns the VDD_MCU supply monitor circuit on/off. The VDD_MCU Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 17.2).
0: VDD_MCU Supply Monitor Disabled.
1: VDD_MCU Supply Monitor Enabled.
6VDDSTATVDD_MCU Supply Status.
This bit indicates the current power supply status.
0: VDD_MCU is at or below the VRST threshold.
1: VDD_MCU is above the VRST threshold.
5VDDOKVDD_MCU Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD_MCU is at or below the VWARN threshold.
1: VDD_MCU is above the VWARN monitor threshold.
4:2 Reserved Read = 000b. Must Write 000b.
1:0 Unused Read = 00b. Write = Don’t Care.
Si106x/108x
190 Rev. 1.0
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The Comparator0 reset source remains functional even when the
device is in the low power Suspend and Sleep states as long as Comparator0 is also enabled as a wake-
up source. The state of the RST pin is unaffected by this reset.
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “32.4. Watchdog Timer Mode” on
page 344; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The PCA Watchdog Timer reset source is automatically disabled when the device is in the low
power Suspend or Sleep mode. Upon exit from either low power state, the enabled/disabled state of this
reset source is restored to its previous value.The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“12.3. Security Options” on page 151).
A Flash write or erase is attempted while the VDD Monitor is disabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag
(RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power Sus-
pend or Sleep mode. The state of the RST pin is unaffected by this reset.
17.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.0 191
Si106x/108x
SFR Page = 0x0; SFR Address = 0xEF.
SFR Definition 17.2. RSTSRC: Reset Source
Bit 76543210
Name RTC0RE FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R/W RR/W R/W RR/W R/W R
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7RTC0RESmaRTClock Reset Enab le
and Flag 0: Disable SmaRTClock
as a reset source.
1: Enable SmaRTClock as
a reset source.
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
6FERRORFlash Error Reset Flag. N/A Set to 1 if Flash
read/write/erase error
caused the last reset.
5 C0RSEF C omparator0 Reset Enab le
and Flag. 0: Disable Comparator0 as
a reset source.
1: Enable Comparator0 as
a reset source.
Set to 1 if Comparator0
caused the last reset.
4SWRSFSoftware Reset Force and
Flag. Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
3 WDTRSF Watchdog Timer Reset Flag. N/A Set to 1 if Watchdog Timer
overflow caused the last
reset.
2 MCDRSF Missing Clock Detector
(MCD) Enable and Flag. 0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1PORSFPower-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
0: Disable the VDD_MCU
Supply Monitor as a reset
source.
1: Enable the VDD_MCU
Supply Monitor as a reset
source.3
Set to 1 anytime a power-
on or VDD monitor reset
occurs.2
0PINRSFHW Pin Rese t Flag. N/A Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD_MCU Supply Monitor is stabilized may generate a system reset.
Rev. 1.0 192
Si106x/108x
18. Clocking Sources
Si106x/108x devices include a programmable precision internal oscillator, an external oscillator drive cir-
cuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal
oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 18.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaRT-
Clock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical
specifications can be found in the Electrical Specifications Chapter.
Figure 18.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
External
Oscillator
Drive Circuit
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10M
Option 4
XTAL2
OSCXCN
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
Precision
Internal Oscillator
EN
OSCICL OSCICN
IOSCEN
IFRDY
SYSCLK
CLKSEL
CLKDIV2
CLKDIV1
CLKDIV0
CLKRDY
CLKSL1
CLKSL0
smaRTClock
Oscillator
Clock Divider
n
Low Power
Internal Oscillator
Low Power Internal Oscillator
smaRTClock Oscillator
External Oscillator
Precision Internal Oscillator CLKRDY
Option 3
XTAL2
Si106x/108x
193 Rev. 1.0
18.1. Programmable Precision Internal Oscillator
All Si106x/108x devices include a programmable precision internal oscillator that may be selected as the
system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Table 4.7, “Internal Preci-
sion Oscillator Electrical Characteristics,” on page 59 for complete oscillator specifications.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The deviation from the nominal oscillator frequency is +0%, –1.6%,
and the step size is typically 0.26% of the nominal frequency. When using this mode, the typical average
oscillator frequency is lowered from 24.5 MHz to 24.3 MHz.
18.2. Low Power Internal Oscillator
All Si106x/108x devices include a low power internal oscillator that defaults as the system clock after a
system reset. The low power internal oscillator frequency is 20 MHz ± 10% and is automatically enabled
when selected as the system clock and disabled when not in use. See Table 4.8, “Internal Low-Power
Oscillator Electrical Characteristics,” on page 59 for complete oscillator specifications.
18.3. External Oscillator Drive Circuit
All Si106x/108x devices include an external oscillator circuit that may drive an external crystal, ceramic
resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. Figure 18.1 shows a
block diagram of the four external oscillator options. The external oscillator is enabled and configured
using the OSCXCN register.
The external oscillator output may be selected as the system clock or used to clock some of the digital
peripherals (e.g., Timers, PCA, etc.). See the data sheet chapters for each digital peripheral for details.
See Section “4. Electrical Characteristics” on page 42 for complete oscillator specifications.
18.3.1. External Crystal Mode
If a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 Mresis-
tor must be wired across the XTAL1 and XTAL2 pins as shown in Figure 18.1, Option 1. Appropriate load-
ing capacitors should be added to XTAL1 and XTAL2, and both pins should be configured for analog I/O
with the digital output drivers disabled.
Figure 18.2 shows the external oscillator circuit for a 20 MHz quartz crystal with a manufacturer recom-
mended load capacitance of 12.5 pF. Loading capacitors are "in series" as seen by the crystal and "in par-
allel" with the stray capacitance of the XTAL1 and XTAL2 pins. The total value of the each loading
capacitor and the stray capacitance of each XTAL pin should equal 12.5pF x 2 = 25 pF. With a stray capac-
itance of 10 pF per pin, the 15 pF capacitors yield an equivalent series capacitance of 12.5 pF across the
crystal.
Note: The recommended load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal
data sheet when completing these calculations.
Rev. 1.0 194
Si106x/108x
Figure 18.2. 25 MHz External Crystal Example
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crys-
tal Oscillator Mode or Cryst al Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
Table 18.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock has stabilized. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the
crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
Table 18.1. Recommended XFCN Settings for Crystal Mode
XFCN Crystal Frequency Bias Current Typical Supply Current
(VDD = 2.4 V)
000 f 20 kHz 0.5 µA 3.0 µA, f = 32.768 kHz
001 20 kHz f 58 kHz 1.5 µA 4.8 µA, f = 32.768 kHz
010 58 kHz f 155 kHz 4.8 µA 9.6 µA, f = 32.768 kHz
011 155 kHz f 415 kHz 14 µA 28 µA, f = 400 kHz
100 415 kHz f 1.1 MHz 40 µA 71 µA, f = 400 kHz
101 1.1 MHz f 3.1 MHz 120 µA 193 µA, f = 400 kHz
110 3.1 MHz f 8.2 MHz 550 µA 940 µA, f = 8 MHz
111 8.2 MHz f 25 MHz 2.6 mA 3.9 mA, f = 25 MHz
15 pF
15 pF
25 MHz
XTAL1
XTAL2
10 M
Si106x/108x
195 Rev. 1.0
18.3.2. External RC Mode
If an RC network is used as the external oscillator, the circuit should be configured as shown in
Figure 18.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for
analog I/O with the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The resistor should be no smaller than
10k. The oscillation frequency can be determined by the following equation:
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscillation. For example, if the fre-
quency desired is 100 kHz, let R = 246 k and C = 50 pF:
where
f = frequency of clock in MHz; R = pull-up resistor value in k
VDD = power supply voltage in Volts; C = capacitor value on the XTAL2 pin in pF
Referencing Table 18.2, the recommended XFCN setting is 010.
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
Table 18.2. Recommended XFCN Settings for RC and C modes
XFCN Approximate
Frequency Range (RC
and C Mode)
K Factor (C Mode) Typical Supply Current/ Actual
Measured Frequency
(C Mode, VDD = 2.4 V)
000 f 25 kHz K Factor = 0.87 3.0 µA, f = 11 kHz, C = 33 pF
001 25 kHz f 50 kHz K Factor = 2.6 5.5 µA, f = 33 kHz, C = 33 pF
010 50 kHz f 100 kHz K Factor = 7.7 13 µA, f = 98 kHz, C = 33 pF
011 100 kHz f 200 kHz K Factor = 22 32 µA, f = 270 kHz, C = 33 pF
100 200 kHz f 400 kHz K Factor = 65 82 µA, f = 310 kHz, C = 46 pF
101 400 kHz f 800 kHz K Factor = 180 242 µA, f = 890 kHz, C = 46 pF
110 800 kHz f 1.6 MHz K Factor = 664 1.0 mA, f = 2.0 MHz, C = 46 pF
111 1.6 MHz f 3.2 MHz K Factor = 1590 4.6 mA, f = 6.8 MHz, C = 46 pF
f1.23 103
RC
-------------------------
=
f1.23 103
RC
-------------------------1.23 103
246 50
-------------------------100 kHz===
Rev. 1.0 196
Si106x/108x
3. Poll for XTLVLD > 1.
4. Switch the system clock to the external oscillator.
18.3.3. External Capacitor Mode
If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 18.1,
Option 3. The capacitor should be added to XTAL2, and XTAL2 should be configured for analog I/O with
the digital output drivers disabled. XTAL1 is not affected in RC mode.
The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. The oscillation frequency and the required
External Oscillator Frequency Control value (XFCN) in the OSCXCN Register can be determined by the
following equation:
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume VDD = 3.0 V
and f = 150 kHz:
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 18.2 as KF = 22:
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
18.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
fKF
CV
DD
---------------------
=
fKF
CV
DD
---------------------
=
0.150 MHz KF
C3.0
-----------------
=
0.150 MHz 22
C 3.0 V
-----------------------
=
C22
0.150 MHz 3.0 V
-----------------------------------------------
=
C 48.8 pF=
Si106x/108x
197 Rev. 1.0
18.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on Si106x/108x devices are enabled and configured using the OSCICN, OSCICL,
OSCXCN and the SmaRTClock internal registers. See Section “19. SmaRTClock (Real Time Clock)” on
page 200 for SmaRTClock register descriptions. The system clock source for the MCU can be selected
using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash read time
should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register description for
details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
SFR Page = All Pages; SFR Address = 0xA9
SFR Definition 18.1. CLKSEL: Clock Select
Bit 76543210
Name CLKRDY CLKDIV[2:0] CLKSEL[2:0]
Type RR/W R/W R/W R/W R/W R/W R/W
Reset 00110100
Bit Name Function
7CLKRDY System Cloc k Div id e r Clo c k Rea d y F lag .
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
6:4 CLKDIV[2:0] System Clock Div id e r Bits.
Selects the clock division to be applied to the undivided system clock source.
000: System clock is divided by 1.
001: System clock is divided by 2.
010: System clock is divided by 4.
011: System clock is divided by 8.
100: System clock is divided by 16.
101: System clock is divided by 32.
110: System clock is divided by 64.
111: System clock is divided by 128.
3Unused Read = 0b. Must Write 0b.
2:0 CLKSEL[2:0] System Clock Select.
Selects the oscillator to be used as the undivided system clock source.
000: Precision Internal Oscillator.
001: External Oscillator.
010: Reserved.
011: SmaRTClock Oscillator.
1xx: Low Power Oscillator.
Rev. 1.0 198
Si106x/108x
SFR Page = 0x0; SFR Address = 0xB2
Note: It is recommended to use read-modify-write operations such as ORL and ANL to set or clear the enable bit of
this register.
SFR Page = 0x0; SFR Address = 0xB3
Note: If the Precision Internal Oscillator is selected as the system clock, the following procedure should be used when
changing the value of the internal oscillator calibration bits.
1. Switch to a different clock source.
2. Disable the oscillator by writing OSCICN.7 to 0.
SFR Definition 18.2. OSCICN: Int er n al Oscillator Control
Bit 76543210
Name IOSCEN IFRDY Reserved[5:0]
Type R/W RR/W R/W R/W R/W R/W R/W
Reset 00001111
Bit Name Function
7IOSCEN Internal Oscillat o r Enab le .
0: Internal oscillator disabled.
1: Internal oscillator enabled.
6IFRDY Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at its programmed frequency.
1: Internal oscillator is running at its programmed frequency.
5:0 Reserved Reserved.
Si106x—Read=001111b. Must write 001111b.
Si108x—Must perform read–modify–write.
SFR Definition 18.3. OSCICL: Internal Oscillator Calibration
Bit 76543210
Name SSE OSCICL[6:0]
Type R/W RR/W R/W R/W R/W R/W R/W
Reset 0Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7SSE Spread Spectrum Enable.
0: Spread Spectrum clock dithering disabled.
1: Spread Spectrum clock dithering enabled.
6:0 OSCICL Internal Oscillator Calibration.
Factory calibrated to obtain a frequency of 24.5 MHz. Incrementing this register decreases the
oscillator frequency and decrementing this register increases the oscillator frequency. The
step size is approximately 1% of the calibrated frequency. The recommended calibration fre-
quency range is between 16 and 24.5 MHz.
Si106x/108x
199 Rev. 1.0
3. Change OSCICL to the desired setting.
4. Enable the oscillator by writing OSCICN.7 to 1.
SFR Page = 0x0; SFR Address = 0xB1
SFR Definition 18.4. OSCXCN: External Oscillator Control
Bit 76543210
Name XCLKVLD XOSCMD[2:0] Reserved XFCN[2:0]
Type R R R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7XCLKVLD External Oscillator Valid Flag.
Provides External Oscillator status and is valid at all times for all modes of operation
except External CMOS Clock Mode and External CMOS Clock Mode with divide by
2. In these modes, XCLKVLD always returns 0.
0: External Oscillator is unused or not yet stable.
1: External Oscillator is running and stable.
6:4 XOSCMD External Oscillator Mode Bits.
Configures the external oscillator circuit to the selected mode.
00x: External Oscillator circuit disabled.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3Reserved Read = 0b. Must Write 0b.
2:0 XFCN External Oscillator Frequency Control Bits.
Controls the external oscillator bias current.
000-111: See Tabl e 18.1 on page 194 (Crystal Mode) or Table 18.2 on page 195 (RC
or C Mode) for recommended settings.
Rev. 1.0 200
Si106x/108x
19. SmaRTClock (Real Time Clock)
Si106x/108x devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with
alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a
crystal. No external resistor or loading capacitors are required. The on-chip loading capacitors are pro-
grammable to 16 discrete levels allowing compatibility with a wide range of crystals. The SmaRTClock can
operate directly from a 0.9–3.6 V battery voltage and remains operational even when the device goes into
its lowest power down mode.
The SmaRTClock allows a maximum of 36 hour 32-bit independent time-keeping when used with a
32.768 kHz Watch Crystal. The SmaRTClock provides an Alarm and Missing SmaRTClock events, which
could be used as reset or wakeup sources. See Section “17. Reset Sources” on page 185 and Section
“13. Power Management” on page 160 for details on reset sources and low power mode wake-up sources,
respectively.
Figure 19.1. SmaRTClock Block Diagram
19.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in Table 19.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface
SmaRTClock Oscillator
SmaRTClock
CIP-51 CPU
XTAL4 XTAL3
RTC0CN
CAPTUREn
RTC0XCF
RTC0XCN
ALARMn
RTC0KEY
RTC0ADR
RTC0DAT
Interface
Registers
Internal
Registers
SmaRTClock State Machine
Wake-Up
32-Bit
SmaRTClock
Timer
Programmable Loa d Capacitors Power/
Clock
Mgmt
Interrupt
RTC0PIN
Si106x/108x
201 Rev. 1.0
.
19.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Reg-
ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads to
RTC0ADR and RTC0DAT may be performed. The key codes are: 0xA5, 0xF1. There are no timing restric-
tions, but the key codes must be written in order. If the key codes are written out of order, the wrong codes
are written, or an indirect register read or write is attempted while the interface is locked, the SmaRTClock
interface will be disabled, and the RTC0ADR and RTC0DAT registers will become inaccessible until the
next system reset. Once the SmaRTClock interface is unlocked, software may perform any number of
accesses to the SmaRTClock registers until the interface is re-locked or the device is reset. Any write to
RTC0KEY while the SmaRTClock interface is unlocked will re-lock the interface.
Reading the RTC0KEY register at any time will provide the SmaRTClock Interface status and will not inter-
fere with the sequence that is being written. The RTC0KEY register description in SFR Definition 19.1 lists
the definition of each status code.
19.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock Internal Registers
The SmaRTClock internal registers can be read and written using RTC0ADR and RTC0DAT. The
RTC0ADR register selects the SmaRTClock internal register that will be targeted by subsequent reads or
writes. Recommended instruction timing is provided in this section. If the recommended instruction timing
is not followed, then BUSY (RTC0ADR.7) should be checked prior to each read or write operation to make
sure the SmaRTClock Interface is not busy performing the previous read or write operation. A SmaRT-
Clock Write operation is initiated by writing to the RTC0DAT register. Below is an example of writing to a
SmaRTClock internal register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
3. Write 0x00 to RTC0DAT. This operation writes 0x00 to the internal RTC0CN register.
A SmaRTClock Read operation is initiated by setting the SmaRTClock Interface Busy bit. This transfers
the contents of the internal register selected by RTC0ADR to RTC0DAT. The transferred data will remain in
Table 19.1. SmaRTClock Internal Registers
SmaRTClock
Address SmaRTClock
Register Register Name Description
0x00–0x03 CAPTUREn SmaRTClock Capture
Registers
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
0x04 RTC0CN SmaRTClock Control
Register
Controls the operation of the SmaRTClock State
Machine.
0x05 RTC0XCN SmaRTClock Oscillator
Control Register
Controls the operation of the SmaRTClock
Oscillator.
0x06 RTC0XCF SmaRTClock Oscillator
Configuration Register
Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
0x07 RTC0PIN SmaRTClock Pin
Configuration Register Note: Forces XTAL3 and XTAL4 to be internally
shorted.
This register also contains other reserved bits
which should not be modified.
0x08–0x0B ALARMn SmaRTClock Alarm
Registers
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
Rev. 1.0 202
Si106x/108x
RTC0DAT until the next read or write operation. Below is an example of reading a SmaRTClock internal
register.
1. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommended instruction timing.
2. Write 0x05 to RTC0ADR. This selects the internal RTC0CN register at SmaRTClock Address 0x05.
3. Write 1 to BUSY. This initiates the transfer of data from RTC0CN to RTC0DAT.
4. Poll BUSY (RTC0ADR.7) until it returns 0 or follow recommend instruction timing.
5. Read data from RTC0DAT. This data is a copy of the RTC0CN register.
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
19.1.3. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6 sys-
tem clocks. The Short Strobe feature is automatically enabled on reset and can be manually enabled/dis-
abled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a single register write with short strobe enabled:
mov RTC0ADR, #095h
mov RTC0DAT, #000h
nop
19.1.4. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the begin-
ning of each series of consecutive reads. Software should follow recommended instruction timing or check
if the SmaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting AUTORD
(RTC0ADR.6) to logic 1.
19.1.5. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically incre-
ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting
an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with short strobe and autoread enabled:
mov RTC0ADR, #0d0h
nop
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
Si106x/108x
203 Rev. 1.0
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov RTC0ADR, #010h
mov RTC0DAT, #05h
nop
mov RTC0DAT, #06h
nop
mov RTC0DAT, #07h
nop
mov RTC0DAT, #08h
nop
Rev. 1.0 204
Si106x/108x
SFR Page = 0x0; SFR Address = 0xAE
SFR Definition 19.1. RTC0KEY: SmaRTClock Lock and Key
Bit 76543210
Name RTC0ST[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 RTC0ST SmaRTClock Interf ace Lock/Key and Status.
Locks/unlocks the SmaRTClock interface when written. Provides lock status when
read.
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRT-
Clock Interface.
When RTC0ST = 0x03 (disabled), writes to RTC0KEY have no effect.
Si106x/108x
205 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xAC
SFR Definition 19.2. RTC0ADR: SmaRTClock Address
Bit 76543210
Name BUSY AUTORD SHORT ADDR[3:0]
Type R/W R/W RR/W R/W
Reset 00000000
Bit Name Function
7BUSYSmaRTClock Interface Busy Indicator.
Indicates SmaRTClock interface status. Writing 1 to this bit initiates an indirect read.
6AUTORDSmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5 Unused Read = 0b; Write = Don’t Care.
4SHORTShort Strobe Enable.
Enables/disables the Short Strobe Feature.
0: Short Strobe disabled.
1: Short Strobe enabled.
3:0 ADDR[3:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 19.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn
internal SmaRTClock register.
Rev. 1.0 206
Si106x/108x
SFR Page= 0x0; SFR Address = 0xAD
SFR Definition 19.3. RTC0DAT: SmaRTClock Data
Bit 76543210
Name RTC0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 RTC0DAT SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
Si106x/108x
207 Rev. 1.0
19.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of opera-
tion: Crystal Mode, and Self-Oscillate Mode. The oscillation frequency is 32.768 kHz in Crystal Mode and
can be programmed in the range of 10 kHz to 40 kHz in Self-Oscillate Mode. The frequency of the SmaRT-
Clock oscillator can be measured with respect to another oscillator using an on-chip timer. See Section
“31. Timers” on page 311 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
“18. Clocking Sources” on page 192 for information on selecting the system clock source and Section
“20. Si106x/108xPort Input/Output” on page 217 for information on how to route the system clock to a port pin.
19.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to start the SmaRTClock crystal
oscillator in software:
1. Set SmaRTClock to Crystal Mode (XMODE = 1).
2. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal startup.
3. Set the desired loading capacitance (RTC0XCF).
4. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
5. Wait 20 ms.
6. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
7. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance reaches its
programmed value.
8. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum power
savings.
9. Enable the SmaRTClock missing clock detector.
10.Wait 2 ms.
11. Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL4 should be left floating. The input low voltage (VIL) and input high volt-
age (VIH) for XTAL3 when used with an external CMOS clock are 0.1 and 0.8 V, respectively. The SmaRT-
Clock oscillator should be configured to its lowest bias setting with AGC disabled. The CLKVLD bit is
indeterminate when using a CMOS clock, however, the OSCFAIL bit may be checked 2 ms after SmaRT-
Clock oscillator is powered on to ensure that there is a valid clock on XTAL3.
19.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode
When using Self-Oscillate Mode, the XTAL3 and XTAL4 pins should be shorted together. The RTC0PIN
register can be used to internally short XTAL3 and XTAL4. The following steps show how to configure
SmaRTClock for use in Self-Oscillate Mode:
1. Set SmaRTClock to Self-Oscillate Mode (XMODE = 0).
2. Set the desired oscillation frequency:
For oscillation at about 20 kHz, set BIASX2 = 0.
For oscillation at about 40 kHz, set BIASX2 = 1.
3. The oscillator starts oscillating instantaneously.
4. Fine tune the oscillation frequency by adjusting the load capacitance (RTC0XCF).
Rev. 1.0 208
Si106x/108x
19.2.3. Using the Low Frequency Oscillator (LFO)
The low frequency oscillator provides an ultra low power, on-chip clock source to the SmaRTClock. The
typical frequency of oscillation is 16.4 kHz 20%. No external components are required to use the LFO,
and the XTAL3 and XTAL4 pins do not need to be shorted together. The LFO is only available on the
Si108x devices.
The following steps show how to configure SmaRTClock for use with the LFO:
1. Enable and select the Low Frequency Oscillator (LFOEN=1).
2. The LFO starts oscillating instantaneously. When the LFO is enabled, the SmaRTClock oscillator
increments bit 1 of the 32-bit timer (instead of bit 0). This effectively multiplies the LFO frequency by 2,
making the RTC timebase behave as if a 32.768 kHz crystal is connected at the output.
19.2.4. Programmable Load Capacitance
The programmable load capacitance has 16 values to support crystal oscillators with a wide range of rec-
ommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capaci-
tors start at the smallest setting to allow a fast startup time, then slowly increase the capacitance until the
final programmed value is reached. The final programmed loading capacitor value is specified using the
LOADCAP bits in the RTC0XCF register. The LOADCAP setting specifies the amount of on-chip load
capacitance and does not include any stray PCB capacitance. Once the final programmed loading capaci-
tor value is reached, the LOADRDY flag will be set by hardware to logic 1.
When using the SmaRTClock oscillator in Self-Oscillate mode, the programmable load capacitance can be
used to fine tune the oscillation frequency. In most cases, increasing the load capacitor value will result in
a decrease in oscillation frequency.Table 19.2 shows the crystal load capacitance for various settings of
LOADCAP.
.Table 19.2. SmaRTClock Load Capacitance Settings
LOADCAP Crystal Load Capacitance Equivalent Capacitance seen on
XTAL3 and XTAL4
0000 4.0 pF 8.0 pF
0001 4.5 pF 9.0 pF
0010 5.0 pF 10.0 pF
0011 5.5 pF 11.0 pF
0100 6.0 pF 12.0 pF
0101 6.5 pF 13.0 pF
0110 7.0 pF 14.0 pF
0111 7.5 pF 15.0 pF
1000 8.0 pF 16.0 pF
1001 8.5 pF 17.0 pF
1010 9.0 pF 18.0 pF
1011 9.5 pF 19.0 pF
1100 10.5 pF 21.0 pF
1101 11.5 pF 23.0 pF
Si106x/108x
209 Rev. 1.0
19.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most sys-
tems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal spec-
ifications and operating conditions when Automatic Gain Control is enabled:
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system condi-
tions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
ness. As shown in Figure 19.2, duty cycles less than 55% indicate a robust oscillation. As the duty cycle
approaches 60%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Figure 19.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
1110 12.5 pF 25.0 pF
1111 13.5 pF 27.0 pF
Table 19.2. SmaRTClock Load Capacitance Settings (Continued)
LOADCAP Crystal Load Capacitance Equivalent Capacitance seen on
XTAL3 and XTAL4
Duty Cycle
25% 55% 60%
Safe Operating Zone Low Risk of Clock
Failure
High Risk of Clock
Failure
Rev. 1.0 210
Si106x/108x
Table 19.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor environmen-
tal conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2
(RTC0XCN.5) to 1.
.
19.2.6. Missing SmaRTClock Detector
The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN.6) to 1.
When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is set by hardware if
SmaRTClock oscillator remains high or low for more than 100 µs.
A SmaRTClock Missing Clock detector timeout can trigger an interrupt, wake the device from a low power
mode, or reset the device. See Section “11. Interrupt Handler” on page 137, Section “13. Power Manage-
ment” on page 160, and Section “17. Reset Sources” on page 185 for more information.
Note: The SmaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in
RTC0XCN.
19.2.7. SmaRTClock Oscillator Crystal Valid Detector
The SmaRTClock oscillator crystal valid detector is an oscillation amplitude detector circuit used during
crystal startup to determine when oscillation has started and is nearly stable. The output of this detector
can be read from the CLKVLD bit (RTX0XCN.4).
Notes:
The CLKVLD bit has a blanking interval of 2 ms. During the first 2 ms after turning on the crystal
oscillator, the output of CLKVLD is not valid.
This SmaRTClock crystal valid detector (CLKVLD) is not intended for detecting an oscillator failure. The
missing SmaRTClock detector (CLKFAIL) should be used for this purpose.
Table 19.3. SmaRTClock Bias Settings
Mode Setting Power
Consumption
Crystal Bias Double Off, AGC On Lowest
600 nA
Bias Double Off, AGC Off Low
800 nA
Bias Double On, AGC On High
Bias Double On, AGC Off Highest
Self-Oscillate Bias Double Off Low
Bias Double On High
Si106x/108x
211 Rev. 1.0
19.3. SmaRTClock Timer and Alarm Function
The SmaRTClock timer is a 32-bit counter that, when running (RTC0TR = 1), is incremented every
SmaRTClock oscillator cycle. The timer has an alarm function that can be set to generate an interrupt,
wake the device from a low power mode, or reset the device at a specific time. See Section “11. Interrupt
Handler” on page 137, Section “13. Power Management” on page 160, and Section “17. Reset Sources”
on page 185 for more information.
The SmaRTClock timer includes an Auto Reset feature, which automatically resets the timer to zero one
SmaRTClock cycle after the alarm signal is deasserted. When using Auto Reset, the Alarm match value
should always be set to 2 counts less than the desired match value. Auto Reset can be enabled by writing
a 1 to ALRM (RTC0CN.2).
19.3.1. Setting and Reading the SmaRTClock Timer Value
The 32-bit SmaRTClock timer can be set or read using the six CAPTUREn internal registers. Note that the
timer does not need to be stopped before reading or setting its value. The following steps can be used to
set the timer value:
1. Write the desired 32-bit set value to the CAPTUREn registers.
2. Write 1 to RTC0SET. This will transfer the contents of the CAPTUREn registers to the SmaRTClock
timer.
3. Operation is complete when RTC0SET is cleared to 0 by hardware.
The following steps can be used to read the current timer value:
1. Write 1 to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers.
2. Poll RTC0CAP until it is cleared to 0 by hardware.
3. A snapshot of the timer value can be read from the CAPTUREn registers
19.3.2. Setting a SmaRTClock Alarm
The SmaRTClock alarm function compares the 32-bit value of SmaRTClock Timer to the value of the
ALARMn registers. An alarm event is triggered if the SmaRTClock timer is equal to the ALARMn registers.
If Auto Reset is enabled, the 32-bit timer will be cleared to zero one SmaRTClock cycle after the alarm
event.
The SmaRTClock alarm event can be configured to reset the MCU, wake it up from a low power mode, or
generate an interrupt. See Section “11. Interrupt Handler” on page 137, Section “13. Power Management”
on page 160, and Section “17. Reset Sources” on page 185 for more information.
The following steps can be used to set up a SmaRTClock Alarm:
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes:
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling
SmaRTClock Alarm Events (RTC0AEN = 0).
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1)
after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next
alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See
Section “13. Power Management” on page 160 for information on how to capture a SmaRTClock Alarm
event using a flag which is not automatically cleared by hardware.
Rev. 1.0 212
Si106x/108x
19.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes
are described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36
hours, the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software
managed and is added to the ALRMn registers by software after each alarm. This allows the alarm match
value to always stay ahead of the timer by one software managed interval. If software uses 32-bit unsigned
addition to increment the alarm match value, then it does not need to handle overflows since both the timer
and the alarm match value will overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g. 24 or 36 hours) and/or have a
need for a perpetual timebase. An example of an application that needs a perpetual timebase is one
whose wake-up interval is constantly changing. For these applications, software can keep track of the
number of timer overflows in a 16-bit variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year)
perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero
by hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn regis-
ters. Software only needs to set the alarm interval once during device initialization. After each alarm, soft-
ware should keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm
interval. This mode is the most power efficient since it requires less CPU time per alarm.
Si106x/108x
213 Rev. 1.0
SmaRTClock Address = 0x04
Internal Register Definition 19.4. RTC0CN: SmaRTClock Control
Bit 76543210
Name RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN ALRM RTC0SET RTC0CAP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 Varies 00000
Bit Name Function
7RTC0ENSmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6MCLKENMissing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5OSCFAILSmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
4RTC0TRSmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3 RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
2ALRMSmaRTClock Alarm Event
Flag and Auto Reset
Enable
Reads return the state of the
alarm event flag.
Writes enable/disable the
Auto Reset function.
Read:
0: SmaRTClock alarm
event flag is de-asserted.
1: SmaRTClock alarm
event flag is asserted.
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
1 RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
0RTC0CAPSmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 160 for information on how to capture a SmaRTClock Alarm event using a flag which is
not automatically cleared by hardware.
Rev. 1.0 214
Si106x/108x
SmaRTClock Address = 0x05
Internal Register Definition 19.5. RTC0XCN: SmaRTClock Oscillator Control
Bit 76543210
Name AGCEN XMODE BIASX2 CLKVLD
Type R/W R/W R/W RRRRR
Reset 00000000
Bit Name Function
7AGCENSmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
0: AGC disabled.
1: AGC enabled.
6XMODESmaRTClock Osci llator Mode.
Selects Crystal or Self Oscillate Mode.
0: Self-Oscillate Mode selected.
1: Crystal Mode selected.
5 BIASX2 SmaRTClock Oscillator Bias Double Enable.
Enables/disables the Bias Double feature.
0: Bias Double disabled.
1: Bias Double enabled.
4 CLKVLD SmaRTClock Oscillator Crystal Valid Indicator.
Indicates if oscillation amplitude is sufficient for maintaining oscillation.
0: Oscillation has not started or oscillation amplitude is too low to maintain oscillation.
1: Sufficient oscillation amplitude detected.
3:0 Unused Read = 0000b; Write = Don’t Care.
Si106x/108x
215 Rev. 1.0
SmaRTClock Address = 0x06
SmaRTClock Address = 0x07
Internal Register Definition 19.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit 7 6 5 4 3 2 1 0
Name AUTOSTP LOADRDY LOADCAP
Type R/W R R R R/W
Reset 0 0 0 0 Varies Varies Varies Varies
Bit Name Function
7AUTOSTPAutomatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6 LOADRDY Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it programmed value.
5:4 Unused Read = 00b; Write = Don’t Care.
3:0 LOADCAP Load Capacitance Programmed Value.
Holds the user’s desired value of the load capacitance. See Table 19.2 on
page 208.
Internal Register Definition 19.7. RTC0PIN: SmaRTClock Pin Configuration
Bit 76543210
Name RTC0PIN
Type W
Reset 01100111
Bit Name Function
7:0 RTC0PIN SmaRTClock Pin Configuration.
Writing 0xE7 to this register forces XTAL3 and XTAL4 to be internally shorted for use
with Self Oscillate Mode.
Writing 0x67 returns XTAL3 and XTAL4 to their normal configuration.
Rev. 1.0 216
Si106x/108x
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Internal Register Definition 19.8. CAPTUREn: SmaRTClock Timer Capture
Bit 76543210
Name CAPTURE[31:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Internal Register Definition 19.9. ALARMn: SmaRTClock Alarm Programmed Value
Bit 76543210
Name ALARM[31:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
Rev. 1.0 217
Si106x/108x
20. Si106x/108xPort Input/Output
Digital and analog resources are available through 11 I/O pins. The radio peripheral provides an additional
4 GPIO pins which are independent of the pins described in this chapter. Port pins are organized as three
byte-wide ports. Port pins P0.0–P0.6, P1.4–P1.6, and P2.7 can be defined as digital or analog I/O. Digital
I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO).
Analog I/O pins are used by the internal analog resources. P0.7, P1.0–P1.3 are dedicated for communica-
tion with the radio peripheral. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal
(C2D). See Section “33. Device Specific Behavior” on page 352 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 20.3 for more information on the Crossbar.
All Px.x Port I/Os are 5V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD_MCU supply. Port I/Os used for analog func-
tions can operate up to the VDD_MCU supply voltage. See Section 20.1 for more information on Port I/O
operating modes and the electrical specifications chapter for detailed electrical specifications.
Figure 20.1. Port I/O Functional Block Diagram
XBR0, XBR1,
XBR2, PnSKIP
Registers
Digital
Crossbar
Priority
Decoder
2
P0
I/O
Cells
P0.0
P0.6
8
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
UART
(Internal Digital Signals)
Highest
Priority
Lowest
Priority
SYSCLK
2
SMBus
T0, T1 2
7
PCA
4
CP0
CP1
Outputs
SPI0
SPI1
4
P1
I/O
Cells
P1.4
P1.5
8
(Port Latches)
P0 (P0.0-P0.7)
(P1.0-P1.7)
8
8
P1
P2
I/O
Cell
P2 (P2.0-P2.7)
8
8
PnMDOUT,
PnMDIN Registers
No analog functionality
available on P2.7
P1.6
P2.7
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, AGND)
Note: P0.7, P1.0, P1.1, P1.2 and P1.3 are internally connected to the
radio peripheral. P1.7 and P2.0 – P2.6 are not internally or externally
connected.
External Interrupts
EX0 and EX1
Si106x/108x
218 Rev. 1.0
20.1. Port I/O Modes of Operation
Port pins P0.0–P0.6 and P1.4–P1.6 use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be
configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells
default to a digital high impedance state with weak pull-ups enabled.
20.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Cur-
rent Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
20.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD_MCU or GND supply rails based on the
output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they
only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both
high and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD_MCU supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are dis-
abled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by
setting WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled or
driven to a valid logic state. Port pins configured for digital I/O always read back the logic state of the Port
pad, regardless of the output logic value of the Port pin.
Figure 20.2. Port I/O Cell Block Diagram
GND
VDD/DC+ VDD/DC+
(WEAK)
PORT
PAD
To/From Analog
Peripheral
PnMDIN.x
(1 for digital)
(0 for analog)
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
XBARE
(Crossbar
Enable)
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
WEAKPUD
(Weak Pull-Up Disable)
Rev. 1.0 219
Si106x/108x
20.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than 4.5 V and less than 5.25 V. When the supply voltage is in the range of 1.8 to
2.2 V, the I/O may also interface to digital logic operating between 3.0 to 3.6 V if the input signal frequency
is less than 12.5 MHz or less than 25 MHz if the signal rise time (10% to 90%) is less than 1.2 ns. When
operating at a supply voltage above 2.2 V, the device should not interface to 3.3 V logic; however, interfac-
ing to 5 V logic is permitted. An external pull-up resistor to the higher supply voltage is typically required for
most systems.
Important Notes:
When interfacing to a signal that is between 4.5 and 5.25 V, the maximum clock frequency that may be
input on a GPIO pin is 12.5 MHz. The exception to this rule is when routing an external CMOS clock to
P0.3, in which case, a signal up to 25 MHz is valid as long as the rise time (10% to 90%) is shorter than
1.8 ns.
When the supply voltage is less than 2.2 V and interfacing to a signal that is between 3.0 and 3.6 V, the
maximum clock frequency that may be input on a GPIO pin is 3.125 MHz. The exception to this rule is
when routing an external CMOS clock to P0.3, in which case, a signal up to 25 MHz is valued as long
as the rise time (10% to 90%) is shorter than 1.2 ns.
In a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least
150 µA to flow into the Port pin when the supply voltage is between (VDD_MCU/DC+ plus 0.4 V) and
(VDD_MCU/DC+ plus 1.0 V). Once the Port pad voltage increases beyond this range, the current
flowing into the Port pin is minimal.
These guidelines only apply to multi-voltage interfaces. Port I/Os may always interface to digital logic oper-
ating at the same supply voltage.
20.1.4. Increasing Port I/O Drive Strength
Port I/O output drivers support a high and low drive strength; the default is low drive strength. The drive
strength of a Port I/O can be configured using the PnDRV registers. See Section “4. Electrical Characteris-
tics” on page 42 for the difference in output drive strength between the two modes.
20.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P0.6 and P1.4–P1.6 can be assigned to various analog, digital, and external interrupt
functions. The Port pins assuaged to analog functions should be configured for analog I/O and Port pins
assuaged to digital or external interrupt functions should be configured for digital I/O.
20.2.1. Assigning Port I/O Pins to Analog Functions
Table 20.1 shows all available analog functions that need Port I/O assignments. Port pins selected for
these analog functions should have their digita l drivers disabled (PnMDOUT.n = 0 and Port Latch =
1) and their corresponding bit in PnSKIP set to 1. This reserves the pin for use by the analog function
and does not allow it to be claimed by the Crossbar. Table 20.1 shows the potential mapping of Port I/O to
each analog function.
Si106x/108x
220 Rev. 1.0
20.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins sele cted for use as GPIO should hav e their corresponding bit in Pn SKIP set
to 1. Table 20.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 20.3
shows all available external digital event capture functions.
Table 20.1. Port I/O Assignment for Analog Functions
Analog Function Potentially Assigna bl e
Port Pins SFR(s) used for
Assignment
ADC Input P0.0–P0.6 and P1.4–P1.6 ADC0MX, PnSKIP
Comparator0 Input P0.0–P0.6 and P1.4–P1.6 CPT0MX, PnSKIP
Comparator1 Input P0.0–P0.6 and P1.4–P1.6 CPT1MX, PnSKIP
Voltage Reference (VREF0) P0.0 REF0CN, PnSKIP
Analog Ground Reference (AGND) P0.1 REF0CN, PnSKIP
External Oscillator Input (XTAL1) P0.2 OSCXCN, PnSKIP
External Oscillator Output (XTAL2) P0.3 OSCXCN, PnSKIP
Table 20.2. Port I/O Assignment for Digital Functions
Digital Function Potentially As sig n a bl e Po rt Pi ns SFR(s) used for
Assignment
UART0, SPI1, SPI0, SMBus,
CP0 and CP1 Outputs, Sys-
tem Clock Output, PCA0,
Timer0 and Timer1 External
Inputs.
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P2.6 pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
and SPI1 pins to fixed locations.
XBR0, XBR1, XBR2
Any pin used for GPIO P0.0–P0.6 and P1.4–P1.6 P0SKIP, P1SKIP,
P2SKIP
Rev. 1.0 221
Si106x/108x
20.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 20.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 20.1, SFR Definition 20.2, and SFR Definition 20.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 20.3, the highest priority peripheral is UART0. If UART0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. SPI1 is dedicated to the radio and must always be enabled. The user should ensure that the pins to
be assigned by the Crossbar have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 20.3 going down,
the least-significant unskipped, unassigned Port pin(s) are assigned to that function. If a Port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 20.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 20.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and
XTAL2) skipped (P0SKIP = 0x0C).
Notes:
The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output
drivers are disabled while the Crossbar is disabled.
When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is
selected. When SPI0 is selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 20.3 and Figure 20.4.
Table 20.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function Potentially As sig n a bl e Po rt Pi ns SFR(s) used for
Assignment
External Interrupt 0 P0.0–P0.6 IT01CF
External Interrupt 1 P0.0–P0.6 IT01CF
Port Match P0.0–P0.6 and P1.4–P1.6 P0MASK, P0MAT
P1MASK, P1MAT
Si106x/108x
222 Rev. 1.0
Figure 20.3. Crossbar Priority Decoder with No Pins Skipped
VREF
AGND
XTAL1
XTAL2
CNVSTR
C2D
012345670123456701234567
SCK (SPI1)
MISO (SPI1)
MO SI (SPI1)
SCK (SPI0)
MISO (SPI0)
MO SI (SPI0)
NSS* (SPI0)
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1 00000000000110000000000X
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
RX0
SF Signals
PIN I/O
TX0
SDA
P0SKIP[0:7]
SCL
P2
P2SKIP[0:7]
P0 P1
P1SKIP[0:7]
Radio S erial I nter face Sel ect I nput
Radio
Seri al
Interface
Radi o Shutdown I nput
No Connect
No Connect
Rev. 1.0 223
Si106x/108x
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped
VREF
AGND
XTAL1
XTAL2
CNVSTR
C2D
012345670123456701234567
SCK (SPI1)
MISO (SPI1)
MO SI (SPI1)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MO SI (SPI0)
NSS* (SPI0)
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1 00000001110111110000000X
No Connect
No Connect
No Connect
P2
P2SKIP[0:7]
P0 P1
P1SKIP[0:7]
Radio
Serial
Interface
No Connect
Radi o Shutdown Input
SF Signals
PIN I/O
TX0
No Connect
SDA
P0SKIP[0:7]
SCL
RX0
No Connect
No Connect
No Connect
Radio S eri al Int erf ace Select Input
Si106x/108x
224 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xE1
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit 76543210
Name CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 output unavailable at Port pin.
1: Asynchronous CP1 output routed to Port pin.
6CP1EComparator1 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
5 CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 output unavailable at Port pin.
1: Asynchronous CP0 output routed to Port pin.
4CP0EComparator0 Output Enable.
0: CP1 output unavailable at Port pin.
1: CP1 output routed to Port pin.
3 SYSCKE SYSCLK Output Enable.
0: SYSCLK output unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2SMB0ESMBus I/O Enable.
0: SMBus I/O unavailable at Port pin.
1: SDA and SCL routed to Port pins.
1 SPI0E SPI0 I/O Enable
0: SPI0 I/O unavailable at Port pin.
1: SCK, MISO, and MOSI (for SPI0) routed to Port pins.
NSS (for SPI0) routed to Port pin only if SPI0 is configured to 4-wire mode.
0URT0EUART0 Output Enable.
0: UART I/O unavailable at Port pin.
1: TX0 and RX0 routed to Port pins P0.4 and P0.5.
Note: SPI0 can be assigned either 3 or 4 Port I/O pins.
Rev. 1.0 225
Si106x/108x
SFR Page = 0x0; SFR Address = 0xE2
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
Bit 76543210
Name SPI1E T1E T0E ECIE PCA0ME[2:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 Unused Read = 0b; Write = Don’t Care.
6 SPI1E Radio Serial Interface (SPI1) Enable.
0: Radio peripheral unavailable.
1: SCK (for radio) routed to P1.0.
SDO (for radio) routed to P1.1.
SDI (for radio) routed to P1.2
nSEL (for radio) is routed to P1.3.
SDN1 (for radio) routed to P0.7
5T1ETimer1 Input Enable.
0: T1 input unavailable at Port pin.
1: T1 input routed to Port pin.
4T0ETimer0 Input Enable.
0: T0 input unavailable at Port pin.
1: T0 input routed to Port pin.
3ECIEPCA0 External Counter Input (ECI) Enable.
0: PCA0 external counter input unavailable at Port pin.
1: PCA0 external counter input routed to Port pin.
2:0 PCA0ME PCA0 Module I/O Enable.
000: All PCA0 I/O unavailable at Port pin.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2 CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: Reserved.
Note: SPI1 can be assigned either 3 or 4 Port I/O pins.
Si106x/108x
226 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xE3
20.4. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMAT registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMAT registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(PnMAT & P0MASK) or if (P1 & P1MASK) does not equal (PnMAT & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode.
See Section “11. Interrupt Handler” on page 137 and Section “13. Power Management” on page 160 for
more details on interrupt and wake-up sources.
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2
Bit 7 6 5 4 3 2 1 0
Name WEAKPUD XBARE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7 WEAKPUD Port I/O Weak Pullup Disable
0: Weak Pullups enabled (except for Port I/O pins configured for analog mode).
6 XBARE Crossbar Enable
0: Crossbar disabled.
1: Crossbar enabled.
5:0 Unused Read = 000000b; Write = Don’t Care.
Note: The Crossbar must be enabled (XBARE = 1) to use any Port pin as a digital output.
Rev. 1.0 227
Si106x/108x
SFR Page= 0x0; SFR Address = 0xC7
SFR Page= 0x0; SFR Address = 0xD7
SFR Definition 20.4. P0MASK: Port0 Mask Register
Bit 76543210
Name P0MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MASK[7:0] Port0 Mask Value.
Selects the P0 pins to be compared with the corresponding bits in P0MAT.
0: P0.n pin pad logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin pad logic value is compared to P0MAT.n.
SFR Definition 20.5. P0MAT: Port0 Match Register
Bit 76543210
Name P0MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
Si106x/108x
228 Rev. 1.0
SFR Page= 0x0; SFR Address = 0xBF
SFR Page = 0x0; SFR Address = 0xCF
SFR Definition 20.6. P1MASK: Port1 Mask Register
Bit 76543210
Name P1MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
SFR Definition 20.7. P1MAT: Port1 Match Register
Bit 76543210
Name P1MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
Rev. 1.0 229
Si106x/108x
20.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section “4. Electrical Characteristics” on page 42 for the difference in out-
put drive strength between the two modes.
Si106x/108x
230 Rev. 1.0
SFR Page = All Pages; SFR Address = 0x80; Bit-Addressable
SFR Page= 0x0; SFR Address = 0xD4
SFR Definition 20.8. P0: Port0
Bit 76543210
Name P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.9. P0SKIP: Port0 Skip
Bit 76543210
Name P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
Rev. 1.0 231
Si106x/108x
SFR Page= 0x0; SFR Address = 0xF1
SFR Page = 0x0; SFR Address = 0xA4
SFR Definition 20.10. P0MDIN: Port0 Input Mode
Bit 76543210
Name P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 20.11. P0MDOUT: Port0 Output Mode
Bit 76543210
Name P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
Si106x/108x
232 Rev. 1.0
SFR Page = 0xF; SFR Address = 0xA4
SFR Definition 20.12. P0DRV: Port0 Drive Strength
Bit 76543210
Name P0DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectiv ely ).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
Rev. 1.0 233
Si106x/108x
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
SFR Page = 0x0; SFR Address = 0xD5
SFR Definition 20.13. P1: Port1
Bit 76543210
Name P1[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
SFR Definition 20.14. P1SKIP: Port1 Skip
Bit 76543210
Name P1SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used
for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
Si106x/108x
234 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xF2
SFR Page = 0x0; SFR Address = 0xA5
SFR Definition 20.15. P1MDIN: Port1 Input Mode
Bit 76543210
Name P1MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
SFR Definition 20.16. P1MDOUT: Port1 Output Mode
Bit 76543210
Name P1MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
Rev. 1.0 235
Si106x/108x
SFR Page = 0xF; SFR Address = 0xA5
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
SFR Definition 20.17. P1DRV: Port1 Drive Strength
Bit 76543210
Name P1DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1DRV[7:0] Drive Strength Configuration Bits for P1.7–P1.0 (respectiv ely ).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Note: P0.7, P1.2, P1.5, P1.6 and P1.7 are internally connected to the radio peripheral. P1.0, P1.1, P1.3, P1.4, P2.2,
P2.3, P2.5, and P2.6 is not externally or internally connected.
SFR Definition 20.18. P2: Port2
Bit 76543210
Name P2[7:0]
Type R/W
Reset 11111111
Bit Name Description Read Write
7:0 P2[7:0] Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
Si106x/108x
236 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xD6
SFR Page = 0x0; SFR Address = 0xF3
SFR Definition 20.19. P2SKIP: Port2 Skip
Bit 76543210
Name P2SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Description Read Write
7:0 P2SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
SFR Definition 20.20. P2MDIN: Port2 Input Mode
Bit 76543210
Name Reserved P2MDIN[6:0]
Type R/W
Reset 11111111
Bit Name Function
7 Reserved. Read = 1b; Must Write 1b.
6:0 P2MDIN[3:0] Analog Configuration Bits for P2.6–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Rev. 1.0 237
Si106x/108x
SFR Page = 0x0; SFR Address = 0xA6
SFR Page = 0x0F; SFR Address = 0xA6
SFR Definition 20.21. P2MDOUT: Port2 Output Mode
Bit 76543210
Name P2MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
SFR Definition 20.22. P2DRV: Port2 Drive Strength
Bit 76543210
Name P2DRV[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2DRV[7:0] Drive Strength Configuration Bits for P2.7–P2.0 (res p e ct iv ely ).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P2.n Output has low output drive strength.
1: Corresponding P2.n Output has high output drive strength.
Rev. 1.0 238
Si106x/108x
21. Controller Interface
21.1. Serial Interface (SPI1)
The radio in the Si106x/8x communicates with the MCU over an internal 4-wire serial peripheral interface
(SPI): SCLK, SDI, SDO, and nSEL. Table 21.1 shows the mapping between the MCU GPIO and the radio
pins. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters are
demonstrated in Table 21.2. The host MCU writes data over the SDI pin and can read data from the device
on the SDO output pin. Figure 21.1 demonstrates an SPI write command. The nSEL pin should go low to
initiate the SPI command. The first byte of SDI data will be one of the firmware commands followed by n
bytes of parameter data which will be variable depending on the specific command. The rising edges of
SCLK should be aligned with the center of the SDI data.
Table 21.1. Internal Connection
for Radio and MCU
MCU
GPIO Radio Contr o l
Interface
P0.7 SDN
P1.0/SCK SCLK
P1.1/MISO SDO
P1.2/MOSI SDI
P1.3/NSS nSEL
Table 21.2. Serial Interface Timing Parameters
Symbol Parameter Min (ns) Diagram
tCH Clock high time 40
tCL Clock low time 40
tDS Data setup time 20
tDH Data hold time 20
tDD Output data delay time 20
tEN Output enable time 20
tDE Output disable time 50
tSS Select setup time 20
tSH Select hold time 50
tSW Select high period 80
SCLK
SDI
SDO
nSEL
tEN
tCL
tSS tCH tDS tDH tDD tSH tDE
tSW
Si106x/108x
239 Rev. 1.0
Figure 21.1. SPI Write Command
The Si106x/8x transceiver contains an internal MCU which controls all the internal functions of the radio.
For SPI read commands a typical MCU flow of checking clear-to-send (CTS) is used to make sure the
internal MCU has executed the command and prepared the data to be output over the SDO pin.
Figure 21.1 demonstrates the general flow of an SPI read command. Once the CTS value reads 0xFF then
the read data is ready to be clocked out to the host MCU. The typical time for a valid 0xFF CTS reading is
20 µs. Figure 21.3 demonstrates the remaining read cycle after CTS is set to 0xFF. The internal MCU will
clock out the SDO data on the negative edge so the host MCU should process the SDO data on the rising
edge of SCLK.
Figure 21.2. SPI Read Command—Check CTS Value
FW Command Param Byte 0 Param Byte n
nSEL
SDO
SDI
SCLK
Send Command Read CTS Retrieve
Response
CTS Value
0x00
0xFF
Firmware Flow
ReadCmdBuff
NSEL
SDO
SDI
SCK
CTS
Rev. 1.0 240
Si106x/108x
Figure 21.3. SPI Read Command—Clock Out Read Data
NSEL
SDO
SDI
SCK
Response Byte 0 Response Byte n
Si106x/108x
241 Rev. 1.0
21.2. Fast Response Registers (Si1060/61/62/63 and Si1080/81/82/83)
The fast response registers are registers that can be read immediately without the requirement to monitor
and check CTS. There are four fast response registers that can be programmed for a specific function. The
fast response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast
Response B, 0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can
be configured by the "FRR_CTL_X_MODE" properties.
The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional
eight clock cycles will clock out the contents of the next fast response register in a circular fashion. The
value of the FRRs will not be updated unless NSEL is toggled.
21.3. Operating Modes and Timing
The primary states of the Si106x transceiver are shown in Figure 21.4. The shutdown state completely
shuts down the radio to minimize current consumption. Standby/Sleep, SPI Active, Ready, TX Tune, and
RX tune are available to optimize the current consumption and response time to RX/TX for a given applica-
tion. API commands START_RX, START_TX, and CHANGE_STATE control the operating state with the
exception of shutdown which is controlled by SDN, pin 1. Figure 21.4 shows each of the operating modes
with the time required to reach either RX or TX mode as well as the current consumption of each mode.
The times in Table 21.5 are measured from the rising edge of nSEL until the device is in the desired state.
Note that these times are indicative of state transition timing but are not guaranteed and should only be
used as a reference data point. An automatic sequencer will put the device into RX or TX from any state. It
is not necessary to manually step through the states. To simplify the diagram it is not shown but any of the
lower power states can be returned to automatically after RX or TX.
Figure 21.4. State Machine Diagram
Rev. 1.0 242
Si106x/108x
Figure 21.5 shows the POR timing and voltage requirements. The power consumption (battery life)
depends on the duty cycle of the application or how often the part is in either RX or TX state. In most appli-
cations the utilization of the standby state will be most advantageous for battery life but for very low duty
cycle applications shutdown will have an advantage. For the fastest timing the next state can be selected
in the START_RX or START_TX API commands to minimize SPI transactions and internal MCU process-
ing.
Table 21.3. Operating State Response Time and Current Consumption*
Si1060/61/62/63, Si1080/81/82/83
State/Mode Response Time to Current in State /
Mode
TX RX
Shutdown State 15 ms 15 ms 30 nA
Standby State
Sleep State
SPI Active State
Ready State
TX Tune State
RX Tune State
440 µs
440 µs
340 µs
126 µs
58 µs
—
440 µs
440 µs
340 µs
122 µs
—
74 µs
50 nA
900 nA
1.35 mA
1.8 mA
8 mA
7.2 mA
TX State —138 µs 18 mA @ +10 dBm
RX State 130 µs 75 µs 10 or 13 mA
*Note: TXRX and RXTX state transition timing can be reduced to 70 µs if using Zero-IF mode.
Table 21.4. Operating State Response Time and Current Consumption
(Si1064/65, Si1084/85)
State / Mode Response Time to Current in State / Mode
Tx Rx
Shutdown 30 ms 30 ms 30 nA
Standby 500 μs460 μs50 nA
SPI Active 500 μs330 μs1.35 mA
Ready 150 μs130 μs1.8 mA
Tx Tune 75 μs6.9 mA
Rx Tune 75 μs6.5 mA
Tx 150 μs18 mA @ +10 dBm
Rx 150 μs150 μs10 mA
Si106x/108x
243 Rev. 1.0
21.3.1. Radio Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To
execute this process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms.
If VDD is removed, then it must stay below 0.15 V for at least 10 ms before being applied again. See
Figure 21.5 and Table 21.5 for details.
Figure 21.5. POR Timing Diagram
Table 21.5. POR Timing
Variable Description Min Typ Max Units
tPORH High time for VDD to fully settle POR circuit 10 — — ms
tPORL Low time for VDD to enable POR 10 — — ms
VRRH Voltage for successful POR 90% x Vdd — — V
VRRL Starting Voltage for successful POR 0 — 150 mV
tSR Slew rate of VDD for successful POR — — 1 ms
VDD
Time
VRRH
tSR tPORH
VRRL
Rev. 1.0 244
Si106x/108x
21.3.2. Shutdown State
The shutdown state is the lowest current consumption state of the device with nominally less than 30 nA of
current consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN
pin should be held low in all states except the shutdown state. In the shutdown state, the contents of the
registers are lost and there is no SPI access. When coming out of the shutdown state a power on reset
(POR) will be initiated along with the internal calibrations. After the POR the POWER_UP command is
required to initialize the radio. The SDN pin needs to be held high for at least 10us before driving low again
so that internal capacitors can discharge. Not holding the SDN high for this period of time may cause the
POR to be missed and the device to boot up incorrectly. If POR timing and voltage requirements cannot be
met, it is highly recommended that SDN be controlled using the host processor rather than tying it to GND
on the board.
21.3.3. Standby State
Standby state has the lowest current consumption with the exception of shutdown but has much faster
response time to RX or TX mode. In most cases standby should be used as the low power state. In this
state the register values are maintained with all other blocks disabled. The SPI is accessible during this
mode but any SPI event, including FIFO R/W, will enable an internal boot oscillator and automatically
move the part to SPI active state. After an SPI event the host will need to re-command the device back to
standby through the "Change State" API command to achieve the 50 nA current consumption. If an inter-
rupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum cur-
rent consumption of this mode.
21.3.4. Sleep State (Si1060/61/62/63 and Si1080/81/82/83)
Sleep state is the same as standby state but the wake-up-timer and a 32 kHz clock source are enabled.
The source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodically cali-
brated or a 32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI
event will enable an internal boot oscillator and automatically move the part to SPI active mode. After an
SPI event the host will need to re-command the device back to sleep. If an interrupt has occurred (i.e., the
nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption of this
mode.
21.3.5. SPI Active State
In SPI active state the SPI and a boot up oscillator are enabled. After SPI transactions during either
standby or sleep the device will not automatically return to these states. A "Change State" API command
will be required to return to either the standby or sleep modes.
21.3.6. Ready State
Ready state is designed to give a fast transition time to TX or RX state with reasonable current consump-
tion. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX
mode by eliminating the crystal start-up time.
21.3.7. TX State
The TX state may be entered from any of the state with the "Start TX" or "Change State" API commands. A
built-in sequencer takes care of all the actions required to transition between states from enabling the crys-
tal oscillator to ramping up the PA. The following sequence of events will occur automatically when going
from standby to TX state.
1. Enable internal LDOs.
2. Start up crystal oscillator and wait until ready (controlled by an internal timer).
3. Enable PLL.
4. Calibrate VCO/PLL.
5. Wait until PLL settles to required transmit frequency (controlled by an internal timer).
Si106x/108x
245 Rev. 1.0
6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer).
7. Transmit packet.
Steps in this sequence may be eliminated depending on which state the device is configured to prior to
commanding to TX. By default, the VCO and PLL are calibrated every time the PLL is enabled. When the
START_TX API command is utilized the next state may be defined to ensure optimal timing and turn-
around.
Figure 21.6 shows an example of the commands and timing for the START_TX command. CTS will go
high as soon as the sequencer puts the part into TX state. As the sequencer is stepping through the events
listed above, CTS will be low and no new commands or property changes are allowed. If the Fast
Response (FRR) or nIRQ is used to monitor the current state there will be slight delay caused by the inter-
nal hardware from when the event actually occurs to when the transition occurs on the FRR or nIRQ. The
time from entering TX state to when the FRR will update is 5 µs and the time to when the nIRQ will transi-
tion is 13 µs. If a GPIO is programmed for TX state or used as control for a transmit/receive switch (TR
switch) there is no delay.
Figure 21.6. Start_TX Commands and Timing
START_TX
CTS
NSEL
SDI
YYY State
Current State Tx State
nIRQ
YYY State
FRR Tx State TXCOMPLETE_STATE
TXCOMPLETE_STATE
GPIOx – TX state
Rev. 1.0 246
Si106x/108x
21.4. Application Programming Interface (API)
An application programming interface (API), which the host MCU will communicate with, is embedded
inside the device. The API is divided into two sections, commands and properties. The commands are
used to control the device and retrieve its status. The properties are general configurations which will
change infrequently. The API descriptions for the Si1060/61/62/63 and Si1080/81/82/83 can be found in
the EZRadioPRO API documentation. The API descriptions for the Si1064/65 and Si1084/85 can be found
in the EZRadio API documentation.
The radio in the Si106x/Si108x is capable of generating an interrupt signal when certain events occur. The
radio notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW
= 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding
to the Interrupt Status bits) occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt
Status Registers. The nIRQ output signal will then be reset until the next change in status is detected.
The interrupts sources are grouped into three groups: packet handler, device status, and modem. The indi-
vidual interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102,
and 0103. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must
be enabled as well as the individual interrupts in API property 0100.
Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts.
All of the interrupts may be read and cleared in the "GET_INT_STATUS" API command. By default all
interrupts will be cleared once read. If only specific interrupts want to be read in the fastest possible
method the individual interrupt groups (Packet Handler, Chip Status, Modem) may be read and cleared by
the "GET_MODEM_STATUS", "GET_PH_STATUS" (packet handler), and "GET_CHIP_STATUS" API
commands.
The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled.
The status results are provided after the interrupts and can be read with the same commands as the inter-
rupts. The status bits will give the current state of the function whether the interrupt is enabled or not.
The fast response registers can also give information about the interrupt groups but reading the fast
response registers will not clear the interrupt and reset the nIRQ pin.
Number Command Summary
0x20 GET_INT_STATUS Returns the interrupt status—packet handler, modem,
and chip
0x21 GET_PH_STATUS Returns the packet handler status.
0x22 GET_MODEM_STATUS Returns the modem status byte.
0x23 GET_CHIP_STATUS Returns the chip status.
Number Property Default Summary
0x0100 INT_CTL_ENABLE 0x04 Enables interrupt groups for PH, Modem, and
Chip.
0x0101 INT_CTL_PH_ENABLE 0x00 Packet handler interrupt enable property.
0x0102 INT_CTL_MODEM_ENABLE 0x00 Modem interrupt enable property.
0x0103 INT_CTL_CHIP_ENABLE 0x04 Chip interrupt enable property.
Si106x/108x
247 Rev. 1.0
21.5. GPIO
Four general purpose IO pins are available to utilize in the application. The GPIO are configured by the
GPIO_PIN_CFG command in address 13h. For a complete list of the GPIO options please see the API
guide. GPIO pins 0 and 1 should be used for active signals such as data or clock. GPIO pins 2 and 3 have
more susceptibility to generating spurious in the synthesizer than pins 0 and 1. The drive strength of the
GPIOs can be adjusted with the GEN_CONFIG parameter in the GPIO_PIN_CFG command. By default
the drive strength is set to minimum. The default configuration for the GPIOs and the state during SDN is
shown below in Table 21.6.The state of the IO during shutdown is also shown in Table 21.6. As indicated
previously in Table 4.20 on page 75, GPIO 0 has lower drive strength than the other GPIOs.
Table 21.6. GPIOs
Pin SDN State POR Default
GPIO0 0 POR
GPIO1 0 CTS
GPIO2 0 POR
GPIO3 0 POR
nIRQ resistive VDD pull-up nIRQ
SDO resistive VDD pull-up SDO
SDI High Z SDI
Rev. 1.0 248
Si106x/108x
22. Radio 142–1050 MHz Transceiver Functional Description
The Si106x/8x transceivers are high-performance, low-current, wireless MCUs that cover the sub-GHz
bands. The wide operating voltage range of 1.8-3.6 V and low current consumption make the Si106x/8x an
ideal solution for battery-powered applications. The Si106x operates as a time division duplexing (TDD)
transceiver where the device alternately transmits and receives data packets. The device uses a single-
conversion mixer to downconvert the 2/4-level FSK/GFSK or OOK modulated receive signal to a low IF fre-
quency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a
high performance ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the
built-in DSP increasing the receiver's performance and flexibility versus analog-based architectures. The
demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI
bus by reading the 64-byte RX FIFO.
A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmit-
ter and receiver do not operate at the same time. The LO is generated by an integrated VCO and Frac-
tional-N PLL synthesizer. The synthesizer is designed to support configurable data rates. The
Si1060/61/62/63 and Si1080/81/82/83 operate in the frequency bands of 142–175, 283–350, 420–525,
and 850–1050 MHz with a maximum frequency accuracy step size of 28.6 Hz and data rates from 100 bps
to 1 Mbps. The Si1064/65/Si1084/85 operates in the frequency bands of 283–350, 425–525 and 850–
960 MHz with a maximum frequency accuracy step size of 114.4 Hz, and a data rate from 1 to 500 kbps.
The Si1060/61/80/81 contains a power amplifier (PA) that supports output power up to +20 dBm with very
high efficiency, consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power
amplifier can also be used to compensate for the reduced performance of a lower cost, lower performance
antenna or antenna with size constraints due to a small form factor. Competing solutions require expensive
external PAs to achieve comparable performance. The Si1062/63/64/65/Si1082/83/84/85 is designed to
support single cell operation with current consumption below 18 mA for +10 dBm output power. Two match
topologies are available for the Si1062-65/Si1082-85, class-E and switched-current. Class-E matching pro-
vides optimal current consumption, while switched-current matching demonstrates the best performance
over varying battery voltage and temperature with slightly higher current consumption. The PA is single-
ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and
ramp-down control to reduce unwanted spectral spreading. The Si106x/8x family supports frequency hop-
ping, TX/RX switch control, and antenna diversity switch control to extend the link range and improve per-
formance. Built-in antenna diversity and support for frequency hopping can be used to further extend
range and enhance performance. Antenna diversity is completely integrated into the Si1060–63, Si1080-
83 and can improve the system link budget by 8–10 dB, resulting in substantial range increases under
adverse environmental conditions. A highly configurable packet handler allows for autonomous encod-
ing/decoding of nearly any packet structure. Additional system features, such as an automatic wake-up
timer, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and allows for
the use of lower-cost system MCUs. The Si106x/8x is designed to work with a crystal, and a few passive
components to create a very low-cost system.
Si106x/108x
249 Rev. 1.0
23. Modulation and Hardware Configuration Options
The Si106x/8x supports different modulation options and can be used in various configurations to tailor the
device to any specific application or legacy system for drop in replacement. The modulation and configura-
tion options are set in the API. For more information on the API commands, refer to the EZRadioPRO API
document for the Si1060-Si1063/Si1080-Si1083 and the EZRadio API Guide for the Si1064/65/84/85.
23.1. Modulation Types
The Si106x/8x supports up to five different modulation options: On-off keying (OOK), Gaussian frequency
shift keying (GFSK), frequency-shift keying (FSK), as well as four-level GFSK (4GFSK), and four-level FSK
(4FSK) for the Si1060–Si1063 devices. Minimum shift keying (MSK) can also be created by using GFSK
settings. GFSK is the recommended modulation type as it provides the best performance and cleanest
modulation spectrum. The modulation type is set by the API. A continuous-wave (CW) carrier may also be
selected for RF evaluation purposes. The modulation source may also be selected to be a pseudo-random
source for evaluation purposes.
23.2. Hardware Configuration Options
There are different receive demodulator options to optimize the performance and mutually-exclusive
options for how the RX/TX data is transferred from the host MCU to the RF device.
23.2.1. Receive Demodulator Options
There are multiple demodulators integrated into the device to optimize the performance for different appli-
cations, modulation formats, and packet structures. The calculator built into WDS will choose the optimal
demodulator based on the input criteria.
23.2.1.1. Synchronous Demodulator
The synchronous demodulator's internal frequency error estimator acquires the frequency error based on
a 101010 preamble structure. The bit clock recovery circuit locks to the incoming data stream within four
transactions of a "10" or "01" bit stream. The synchronous demodulator gives optimal performance for 2- or
4-level FSK or GFSK modulation that has a modulation index less than 2.
23.2.1.2. Asynchronous Demodulator
The asynchronous demodulator should be used OOK modulation and for FSK/GFSK/4GFSK under one or
more of the following conditions:
Modulation index > 2
Non-standard preamble (not 1010101... pattern)
When the modulation index exceeds 2, the asynchronous demodulator has better sensitivity compared to
the synchronous demodulator. An internal deglitch circuit provides a glitch-free data output and a data
clock signal to simplify the interface to the host. There is no requirement to perform deglitching in the host
MCU. The asynchronous demodulator will typically be utilized for legacy systems and will have many per-
formance benefits over devices used in legacy designs. Unlike the Si100x/Si101x solution for non-stan-
dard packet structures, there is no requirement to perform deglitching on the data in the host MCU. Glitch-
free data is output from Si106x/8x devices, and a sample clock for the asynchronous data can also be sup-
plied to the host MCU; so, oversampling or bit clock recovery is not required by the host MCU. There are
multiple detector options in the asynchronous demodulator block, which will be selected based upon the
options entered into the WDS calculator. The asynchronous demodulator's internal frequency error estima-
tor is able to acquire the frequency error based on any preamble structure.
Rev. 1.0 250
Si106x/108x
23.2.2. RX/TX Data Interface With MCU
There are two different options for transferring the data from the RF device to the host MCU. FIFO mode
uses the SPI interface to transfer the data, while direct mode transfers the data in real time over GPIO.
23.2.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing Command 66h followed directly by the data/clk that the host wants to write into the TX
FIFO. The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data
the host would like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX mode, if the packet handler is enabled, the data bytes stored in FIFO memory are "packaged"
together with other fields and bytes of information to construct the final transmit packet structure. These
other potential fields include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of
the packet structure in TX mode is determined by the Automatic Packet Handler (if enabled), in conjunction
with a variety of Packet Handler properties. If the Automatic Packet Handler is disabled, the entire desired
packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word) will
be automatically added to the bytes stored in FIFO memory. For further information on the configuration of
the FIFOs for a specific application or packet size, see Section “25. Data Handling and Packet Handler” on
page 262. In RX mode, only the bytes of the received packet structure that are considered to be "data
bytes" are stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is
determined by the Automatic Packet Handler (if enabled) in conjunction with the Packet Handler configura-
tion. If the Automatic Packet Handler is disabled, all bytes following the Sync word are considered data
bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired,
the preamble detection threshold and Sync word still need to be programmed so that the RX Modem
knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received
data may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA out-
put pin; this can be quite useful during application development. When in FIFO mode, the chip will auto-
matically exit the TX or RX State when either the PACKET_SENT or PACKET_RX interrupt occurs. The
chip will return to the IDLE state programmed in the API.
23.2.2.2. Direct Mode (Si1060–Si1063, Si1080-Si1083)
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not
be desirable to use the FIFO. For this scenario, a Direct mode is provided, which bypasses the FIFOs
entirely. In TX Direct mode, the TX modulation data is applied to an input pin of the chip and processed in
"real time" (i.e., not stored in a register for transmission at a later time). Any of the GPIOs may be config-
ured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock
output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). To achieve
direct mode, the GPIO must be configured in the API.
23.3. Preamble Length
The preamble length requirement is only relevant if using the synchronous demodulator. If the asynchro-
nous demodulator is being used, then there is no requirement for a conventional 101010 pattern.
The preamble detection threshold determines the number of valid preamble bits the radio must receive to
qualify a valid preamble. The preamble threshold should be adjusted depending on the nature of the appli-
cation. The required preamble length threshold depends on when receive mode is entered in relation to the
start of the transmitted packet and the length of the transmit preamble. With a shorter than recommended
preamble detection threshold, the probability of false detection is directly related to how long the receiver
operates on noise before the transmit preamble is received. False detection on noise may cause the actual
packet to be missed. The preamble detection threshold may be adjusted in the modem calculator by mod-
ifying the "PM detection threshold" in the "RX parameters tab" in the radio control panel. For most applica-
tions with a preamble length longer than 32 bits, the default value of 20 is recommended for the preamble
detection threshold. A shorter Preamble Detection Threshold may be chosen if occasional false detections
Si106x/108x
251 Rev. 1.0
may be tolerated. When antenna diversity is enabled, a 20-bit preamble detection threshold is recom-
mended. When the receiver is synchronously enabled just before the start of the packet, a shorter pream-
ble detection threshold may be used. Table 23.1 demonstrates the recommended preamble detection
threshold and preamble length for various modes.
Table 23.1. Recommended Preamble Length
Mode AFC Antenna
Diversity Preamble Type Recommended
Preamble Length Recommended
Preambl e De te ction
Threshold
(G)FSK Disabled Disabled Standard 4 Bytes 20 bits
(G)FSK Enabled Disabled Standard 5 Bytes 20 bits
(G)FSK Disabled Disabled Non-standard 2 Bytes 0 bits
(G)FSK Enabled Non-standard Not Supported
(G)FSK Disabled Enabled Standard 7 Bytes 24 bits
(G)FSK Enabled Enabled Standard 8 Bytes 24 bits
4(G)FSK Disabled Disabled Standard 40 symbols 16 symbols
4(G)FSK Enabled Disabled Standard 48 symbols 16 symbols
4(G)FSK Non-standard Not Supported
OOK Disabled Disabled Standard 4 Bytes 20 bits
OOK Disabled Disabled Non-standard 2 Bytes 0 bits
OOK Enabled Not Supported
Notes:
1. The recommended preamble length and preamble detection thresholds listed above are to achieve 0% PER.
They may be shortened when occasional packet errors are tolerable.
2. All recommended preamble lengths and detection thresholds include AGC and BCR settling times.
3. “Standard” preamble type should be set for an alternating data sequence at the max data rate (…10101010…)
4. “Non-standard” preamble type can be set for any preamble type including …10101010...
5. When preamble detection threshold = 0, sync word needs to be 3 Bytes to avoid false syncs. When only a 2
Byte sync word is available the sync word detection can be extended by including the last preamble Byte into
the RX sync word setting.
Rev. 1.0 252
Si106x/108x
24. Internal Functional Blocks
The following sections provide an overview to the key internal blocks and features.
24.1. RX Chain
The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three
external discrete components to cover any common range of frequencies in the sub-GHz band. The LNA
has extremely low noise to suppress the noise of the following stages and achieve optimal sensitivity; so,
no external gain or front-end modules are necessary. The LNA has gain control, which is controlled by the
internal automatic gain control (AGC) algorithm. The LNA is followed by an I-Q mixer, filter, programmable
gain amplifier (PGA), and ADC. The I-Q mixers downconvert the signal to an intermediate frequency. The
PGA then boosts the gain to be within dynamic range of the ADC. The ADC rejects out-of-band blockers
and converts the signal to the digital domain where filtering, demodulation, and processing is performed.
Peak detectors are integrated at the output of the LNA and PGA for use in the AGC algorithm.
The RX and TX pins maybe directly tied externally for output powers less than +17 dBm, see the direct-tie
reference designs on the Silicon Labs web site for more details.
24.1.1. RX Chain Architecture
It is possible to operate the RX chain in different architecture configurations: fixed-IF, zero-IF, scaled-IF,
and modulated IF (Si1064/65 and Si1084/85 support fixed-IF only). There are trade-offs between the archi-
tectures in terms of sensitivity, selectivity, and image rejection. Fixed-IF is the default configuration and is
recommended for most applications. With 35 dB native image rejection and autonomous image calibration
to achieve 55 dB, the fixed-IF solution gives the best performance for most applications. Fixed-IF obtains
the best sensitivity, but it has the effect of degraded selectivity at the image frequency. An autonomous
image rejection calibration is included in Si1060-Si1063/Si1080-Si1083 devices and described in more
detail in Section “24.2.3. Image Rejection and Calibration (Si1060–Si1063, Si1080-S1083)” on page 254.
For fixed-IF and zero-IF, the sensitivity is degraded for data rates less than 100 kbps or bandwidths less
than 200 kHz. The reduction in sensitivity is caused by increased flicker noise as dc is approached. The
benefit of zero-IF is that there is no image frequency; so, there is no degradation in the selectivity curve,
but it has the worst sensitivity. Scaled-IF is a trade-off between fixed-IF and zero-IF. In the scaled-IF archi-
tecture, the image frequency is placed or hidden in the adjacent channel where it only slightly degrades the
typical adjacent channel selectivity. The scaled-IF approach has better sensitivity than zero-IF but still
some degradation in selectivity due to the image. In scaled-IF mode, the image frequency is directly pro-
portional to the channel bandwidth selected. Figure 24.1 demonstrates the trade-off in sensitivity between
the different architecture options.
Si106x/108x
253 Rev. 1.0
Figure 24.1. RX Architecture vs. Data Rate
24.2. RX Modem
Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed
in the digital domain, which allows for flexibility in optimizing the device for particular applications. The dig-
ital modem performs the following functions:
Channel selection filter
TX modulation
RX demodulation
Automatic Gain Control (AGC)
Preamble detection
Invalid preamble detection
Radio signal strength indicator (RSSI)
Automatic frequency compensation (AFC)
Image Rejection Calibration (Si1060-Si1063, Si1080-Si1083)
Packet handling
Cyclic redundancy check (CRC)
The digital channel filter and demodulator are optimized for ultra-low-power consumption and are highly
configurable. Supported modulation types are OOK, GFSK, FSK, GMSK as well as 4FSK/4GFSK for the
Si1060–Si1063. The channel filter can be configured to support bandwidths ranging from 850 down to
1.1 kHz on the Si1060–Si1063/Si1080-Si1083. A large variety of data rates are supported ranging from
100 bps up to 1 Mbps. The configurable preamble detector is used with the synchronous demodulator to
improve the reliability of the sync-word detection. Preamble detection can be skipped using only sync
detection, which is a valuable feature of the asynchronous demodulator when very short preambles are
used in protocols, such as MBus. The received signal strength indicator (RSSI) provides a measure of the
signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high-resolution
RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense
(CS), and listen before talk (LBT) functionality. The extensive programmability of the packet header allows
-120
-115
-110
-105
-100
-95
1 10 100
Sensitivity (dBm)
Data rate (kbps)
1% PER sensitivity vs. data rate (h=1)
Fixed IF
Scaled IF
Zero IF
Rev. 1.0 254
Si106x/108x
for advanced packet filtering, which, in turn enables a mix of broadcast, group, and point-to-point commu-
nication. A wireless communication channel can be corrupted by noise and interference, so it is important
to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the pres-
ence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted
packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC
can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper micro-
controller. The digital modem includes the TX modulator, which converts the TX data bits into the corre-
sponding stream of digital modulation values to be summed with the fractional input to the sigma-delta
modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A
Gaussian filter is implemented to support GFSK and 4GFSK, considerably reducing the energy in adjacent
channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be
adjusted to other values.
24.2.1. Automatic Gain Control (AGC)
The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response
time. The AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and
PGA allow for optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity
performance.
24.2.2. Auto Frequency Correction (AFC)
Frequency mistuning caused by crystal inaccuracies can be compensated for by enabling the digital auto-
matic frequency control (AFC) in receive mode. There are two types of integrated frequency compensa-
tion: modem frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled, the
modem compensation can correct for frequency offsets up to ±0.25 times the IF bandwidth. When the AFC
is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity
and selectivity over a wider range of frequency offsets up to ±0.35 times the IF bandwidth. When AFC is
enabled, the preamble length needs to be long enough to settle the AFC. As shown in Table 23.1 on
page 251, an additional byte of preamble is typically required to settle the AFC.
24.2.3. Image Rejection and Calibration (Si1060–Si1063, Si1080-S1083)
Since the receiver utilizes a low-IF architecture, the selectivity will be affected by the image frequency. The
IF frequency is 468.75 kHz (Fxtal/64), and the image frequency will be at 937.5 kHz below the RF fre-
quency. The native image rejection of the Si106x/8x family is 35 dB. Image rejection calibration is available
in the Si106x/8x to improve the image rejection to more than 55 dB. The calibration is initiated with the
IRCAL API command. The calibration uses an internal signal source, so no external signal generator is
required. The initial calibration takes 250 ms, and periodic re-calibration takes 100 ms. Re-calibration
should be initiated when the temperature has changed more than 30 °C.
24.2.4. Received Signal Strength Indicator
The received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which
the receiver is tuned. The RSSI measurement is done after the channel filter, so it is only a measurement
of the desired or undesired in-band signal power. There are two different methods for reading the RSSI
value and several different options for configuring the RSSI value that is returned. The fastest method for
reading the RSSI is to configure one of the four fast response registers (FRR) to return a latched RSSI
value. The latched RSSI value is measured once per packet and is latched at a configurable amount of
time after RX mode is entered. The fast response registers can be read in 16 SPI clock cycles with no
requirement to wait for CTS. The RSSI value may also be read out of the GET_MODEM_STATUS com-
mand. In this command, both the current RSSI and the latched RSSI are available. The current RSSI value
represents the signal strength at the instant in time the GET_MODEM_STATUS command is processed
and may be read multiple times per packet. Reading the RSSI in the GET_MODEM_STATUS command
takes longer than reading the RSSI out of the fast response register. After the initial command, it will take
33 µs for CTS to be set and then the four or five bytes of SPI clock cycles to read out the respective current
or latched RSSI values.
Si106x/108x
255 Rev. 1.0
The RSSI configuration options are set in the MODEM_RSSI_CONTROL API property. The latched RSSI
value may be latched and stored based on the following events: preamble detection, sync detection, or a
configurable number of bit times measured after the start of RX mode (minimum of 4 bit times). The
requirement for four bit times is determined by the processing delay and settling through the modem and
digital channel filter. In MODEM_RSSI_CONTROL, the RSSI may be defined to update every bit period or
to be averaged and updated every four bit periods. If RSSI averaging over four bits is enabled, the latched
RSSI value will be delayed to a minimum of 7 bits after the start of RX mode to allow for the averaging. The
latched RSSI values are cleared when entering RX mode so they may be read after the packet is received
or after dropping back to standby mode. If the RSSI value has been cleared by the start of RX but not
latched yet, a value of 0 will be returned if it is attempted to be read.
The RSSI value read by the API could be translated to dBm by the following linear equation:
RSSI (in dBm) = (RSSI_value /2) – RSSIcal
RSSIcal in the above formula depends on the matching network, modem settings, and external LNA gain
(if present). The RSSIcal value can be obtained by a simple calibration with a signal generator connected
at the antenna input. Without external LNA, the value of RSSIcal is around 130 ±30.
During packet reception, it may be useful to detect whether a secondary interfering signal (desired or
undesired) arrives. To detect this event, a feature for RSSI jump detection is available. If the RSSI level
changes by a programmable amount during the reception of a packet, an interrupt or GPIO can be config-
ured to notify the host. The level of RSSI increase or decrease (jump) is programmable through the
MODEM_RSSI_JUMP_THRESH API property. If an RSSI jump is detected, the modem may be pro-
grammed to automatically reset so that it may lock onto the new stronger signal. The chip may also be con-
figured to automatically reset the receiver upon jump detection in order to acquire the new signal. The
configuration and options for RSSI jump detection are programmed in the MODEM_RSSI_CONTROL2
API property. By default, RSSI jump detection is not enabled.
The RSSI values and curves may be offset by the MODEM_RSSI_COMP API property. The default value
of 7'h32 corresponds to no RSSI offset. Setting a value less than 7'h32 corresponds to a negative offset,
and a value higher than 7'h32 corresponds to a positive offset. The offset value is in 1 dB steps. For exam-
ple, setting a value of 7'h3A corresponds to a positive offset of 8 dB.
Clear channel assessment (CCA) or RSSI threshold detection is also available. An RSSI threshold may be
set in the MODEM_RSSI_THRESH API property. If the RSSI value is above this threshold, an interrupt or
GPIO may notify the host. Both the latched version and asynchronous version of this threshold are avail-
able on any of the GPIOs. Automatic fast hopping based on RSSI is available. See Section
“24.3.1.2. Automatic RX Hopping and Hop Table” on page 256.
24.3. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating over the bands from
142-175, 283-350, 420-525, and 850-1050 MHz for the Si1060-Si1063/Si1080-Si1083. Using a synthe-
sizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and
channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the
fractional divider, which results in very precise accuracy and control over the transmit deviation. The fre-
quency resolution in the 850-1050 MHz band is 28.6 Hz with more resolution in the other bands. The nom-
inal reference frequency to the PLL is 30 MHz, but any XTAL frequency from 25 to 32 MHz may be used.
The modem configuration calculator in WDS will automatically account for the XTAL frequency being used.
The PLL utilizes a differential LC VCO with integrated on-chip inductors. The output of the VCO is followed
by a configurable divider, which will divide the signal down to the desired output frequency band.
Rev. 1.0 256
Si106x/108x
24.3.1. Synthesizer Frequency Control
The frequency is set by changing the integer and fractional settings to the synthesizer. The WDS calculator
will automatically provide these settings, but the synthesizer equation is shown below for convenience.
The APIs for setting the frequency are FREQ_CONTROL_INTE, FREQ_CONTROL_FRAC2, FREQ_-
CONTROL_FRAC1, and FREQ_CONTROL_FRAC0.
Note: The fc_frac/219 value in the above formula has to be a number between 1 and 2.
24.3.1.1. EZ Frequency Programming
In applications that utilize multiple frequencies or channels, it may not be desirable to write four API regis-
ters each time a frequency change is required. EZ frequency programming is provided so that only a single
register write (channel number) is required to change frequency. A base frequency is first set by first pro-
gramming the integer and fractional components of the synthesizer. This base frequency will correspond to
channel 0. Next, a channel step size is programmed into the API registers. The resulting frequency will be
RF Frequency = Base Frequency + Channe l ´ Step Size:
The second argument of the START_RX or START_TX is CHANNEL, which sets the channel number for
EZ frequency programming. For example, if the channel step size is set to 1 MHz, the base frequency is
set to 900 MHz with the INTE and FRAC API registers, and a CHANNEL number of 5 is programmed
during the START_TX command, the resulting frequency will be 905 MHz. If no CHANNEL argument is
written as part of the START_RX/TX command, it will default to the previous value. The initial value of
CHANNEL is 0; so, if no CHANNEL value is written, it will result in the programmed base frequency.
24.3.1.2. Automatic RX Hopping and Hop Table
The transceiver supports an automatic hopping feature that can be fully configured through the API. This is
intended for RX hopping where the device has to hop from channel to channel and look for packets. Once
the device is put into the RX state, it automatically starts hopping through the hop table if the feature is
enabled.
The hop table can hold up to 64 entries and is maintained in firmware. Each entry is a channel number; so,
the hop table can hold up to 64 channels. The number of entries in the table is set by RX HOP TABLE_-
SIZE API. The specified channels correspond to the EZ frequency programming method for programming
the frequency. The receiver starts at the base channel and hops in sequence from the top of the hop table
to the bottom. The table will wrap around to the base channel once it reaches the end of the table. An entry
of 0xFF in the table indicates that the entry should be skipped. The device will hop to the next non 0xFF
entry.
Table 24.1. Output Divider (Outdiv) Values for the Si1060–Si1063, Si1080-1083
Outdiv Lower (MHz) Upper (MHz)
24 142 175
12 284 350
8420 525
4850 1050
Table 24.2. Output Divider (Outdiv) for the Si1064/Si1065/Si1084/Si1085
Outdiv Lower (MHz) Upper (MHz)
12 284 350
8425 525
4850 960
Si106x/108x
257 Rev. 1.0
There are three conditions that can be used to determine whether to continue hopping or to stay on a par-
ticular channel. These conditions are:
RSSI threshold
Preamble timeout (invalid preamble pattern)
Sync word timeout (invalid or no sync word detected after preamble)
These conditions can be used individually, or they can be enabled all together by configuring the
RX_HOP_CONTROL API. However, the firmware will make a decision on whether or not to hop based on
the first condition that is met.
The RSSI that is monitored is the current RSSI value. This is compared to the threshold, and, if it is above
the threshold value, it will stay on the channel. If the RSSI is below the threshold, it will continue hopping.
There is no averaging of RSSI done during the automatic hopping from channel to channel. Since the pre-
amble timeout and the sync word timeout are features that require packet handling, the RSSI threshold is
the only condition that can be used if the user is in "direct" or "RAW" mode where packet handling features
are not used.
Note that the RSSI threshold is not an absolute RSSI value; instead, it is a relative value and should be
verified on the bench to find an optimal threshold for the application.
The turnaround time from RX to RX on a different channel using this method is 115 µs. The time spent in
receive mode will be determined by the configuration of the hop conditions. Manual RX hopping will have
the fastest turn-around time but will require more overhead and management by the host MCU.
The following are example steps for using Auto Hop:
1. Set the base frequency (inte + frac) and channel step size.
2. Define the number of entries in the hop table (RX_HOP_TABLE_SIZE).
3. Write the channels to the hop table (RX_HOP_TABLE_ENTRY_n)
4. Configure the hop condition and enable auto hopping- RSSI, preamble, or sync
(RX_HOP_CONTROL).
5. Set preamble and sync parameters if enabled.
6. Program the RSSI threshold property in the modem using "MODEM_RSSI_THRESH".
7. Set the preamble threshold using "PREAMBLE_CONFIG_STD_1".
8. Program the preamble timeout property using "PREAMBLE_CONFIG_STD_2".
9. Set the sync detection parameters if enabled.
10.If needed, use "GPIO_PIN_CFG" to configure a GPIO to toggle on hop and hop table wrap.
11.Use the "START_RX" API with channel number set to the first valid entry in the hop table (i.e., the first
non 0xFF entry).
12.Device should now be in auto hop mode.
Rev. 1.0 258
Si106x/108x
24.3.1.3. Manual RX Hopping
The RX_HOP command provides the fastest method for hopping from RX to RX but it requires more over-
head and management by the host MCU. Using the RX_HOP command, the turn-around time is 75 µs.
The timing is faster with this method than Start_RX or RX hopping because one of the calculations
required for the synthesizer calibrations is offloaded to the host and must be calculated/stored by the host,
VCO_CNT0. For information about using fast manual hopping, contact customer support.
24.4. Transmitter (TX)
The Si1060/Si1061/Si1080/Si1081 contains an integrated +20 dBm transmitter or power amplifier that is
capable of transmitting from –20 to +20 dBm. The output power steps are less than 0.25 dB within 6 dB of
max power but become larger and more non-linear close to minimum output power. The PA is designed to
provide the highest efficiency and lowest current consumption possible. The Si1062–Si1065/Si1082-
Si1085 is designed to supply +10 dBm output power for less than 20 mA for applications that require oper-
ation from a single coin cell battery. The Si1062-Si1065/Si1082-Si1085 can also operate with either class-
E or switched current matching and output up to +13 dBm TX power. All PA options are single-ended to
allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is performed to
reduce unwanted spectral spreading.
The Si1060–Si1063/Si1080-Si1083 TXRAMP pin is disabled by default to save current in cases where on-
chip PA will be able to drive the antenna.
In cases where on-chip PA will drive the external PA, and the external PA needs a ramping signal,
TXRAMP is the signal to use.
TXRAMP will start to ramp up, and ramp down at the same time as the internal on-chip PA ramps up/down.
The ramping speed is programmed by TC[3:0] in the PA_RAMP_EX API property, which has the following
characteristics:
The ramping profile is close to a linear ramping profile with smoothed out corner when approaching Vhi
and Vlo. The TXRAMP pin can source up to 1 mA without voltage drooping.
TC Ramp Time (µs)
0.0 2.0
1.0 2.1
2.0 2.2
3.0 2.4
4.0 2.6
5.0 2.8
6.0 3.1
7.0 3.4
8.0 3.7
9.0 4.1
10.0 4.5
11.0 5.0
12.0 6.0
13.0 8.0
14.0 10.0
15.0 20.0
Si106x/108x
259 Rev. 1.0
The TXRAMP pin's sinking capability is equivalent to a 10 k pull-down resistor.
Vhi = 3 V when Vdd > 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time
will be smaller also.
Vlo = 0 V when no current needs to be sunk into the TXRAMP pin. If 10 µA needs to be sunk into the chip,
Vlo will be 10 µA x 10k = 100 mV.
24.4.1. Si1060/Si1061/Si1080/Si1081: +20 dBm PA
The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz
band for output power steps, voltage, and temperature are shown in Figure 24.2–Figure 24.4. The output
power is changed in 128 steps through PA_PWR_LVL API. For detailed matching values, BOM, and per-
formance at other frequencies, refer to the PA Matching application note.
Figure 24.2. +20 dBm TX Power vs. PA_PWR_LVL
Number Command Summary
0x2200 PA_MODE Sets PA type.
0x2201 PA_PWR_LVL Adjust TX power in fine steps.
0x2202 PA_BIAS_CLKDUTY
Adjust TX power in coarse steps
and optimizes for different
match configurations.
0x2203 PA_TC Changes the ramp up/down time
of the PA.
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
0 10 20 30 40 50 60 70 80 90 100 110 120
TX Power(dBm)
PA_PWR_LVL
TX Power vs. PA_PWR_LVL
Rev. 1.0 260
Si106x/108x
Figure 24.3. +20 dBm TX Power vs. VDD
Figure 24.4. +20 dBm TX Power vs. Temp
10
12
14
16
18
20
22
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
TX Power (dBm)
Supply Voltage (VDD)
TX Power vs. VDD
18
18.5
19
19.5
20
20.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TX Power (dBm)
Temperature (C)
TX Power vs Temp
Si106x/108x
261 Rev. 1.0
24.5. Crystal Oscillator
The Si106x/8x includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The
design is differential with the required crystal load capacitance integrated on-chip to minimize the number
of external components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz,
but the circuit is designed to handle any crystal from 25 to 32 MHz. If a crystal different than 30 MHz is
used, the POWER_UP API boot command must be modified. The WDS calculator crystal frequency field
must also be changed to reflect the frequency being used. The crystal load capacitance can be digitally
programmed to accommodate crystals with various load capacitance requirements and to adjust the fre-
quency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the
GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps
(70 fF/step). The crystal frequency adjustment can be used to compensate for crystal production toler-
ances. The frequency offset characteristics of the capacitor bank are demonstrated in Figure 24.5.
Figure 24.5. Capacitor Bank Frequency Offset Characteristics
A TCXO or external signal source can easily be used in place of a conventional XTAL and should be con-
nected to the XIN pin. The incoming clock signal is recommended to have a peak-to-peak swing in the
range of 600 mV to 1.4 V and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds
1.4 V peak-to-peak, then dc coupling to the XIN pin should be used. The maximum allowed swing on XIN
is 1.8 V peak-to-peak.
The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition,
the POWER_UP command should be invoked with the TCXO option whenever external drive is used.
Rev. 1.0 262
Si106x/108x
25. Data Handling and Packet Handler
25.1. RX and TX FIFOs
Two 64-byte FIFOs are integrated into the Si106x/8x, one for RX and one for TX, as shown in Figure 25.1.
Writing to command Register 66h loads data into the TX FIFO, and reading from command Register 77h
reads data from the RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is
set by the "TX_FIFO_EMPTY" property. An interrupt event occurs when the data in the TX FIFO reaches
the almost empty threshold. If more data is not loaded into the FIFO, the chip automatically exits the TX
state after the PACKET_SENT interrupt occurs. The RX FIFO has one programmable threshold, which is
programmed by setting the "RX_FIFO_FULL" property. When the incoming RX data crosses the Almost
Full Threshold, an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller
will then need to read the data from the RX FIFO. The RX Almost Full Threshold indication implies that the
host can read at least the threshold number of bytes from the RX FIFO at that time. Both the TX and RX
FIFOs may be cleared or reset with the "FIFO_RESET" command.
Figure 25.1. TX and RX FIFOs
25.2. Packet Handler
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The
usual fields for network communication, such as preamble, synchronization word, headers, packet length,
and CRC, can be configured to be automatically added to the data payload. The fields needed for packet
generation normally change infrequently and can therefore be stored in registers. Automatically adding
these fields to the data payload in TX mode and automatically checking them in RX mode greatly reduces
the amount of communication between the microcontroller and Si106x. It also greatly reduces the required
computational power of the microcontroller. The general packet structure is shown in Figure 25.2. Any or
all of the fields can be enabled and checked by the internal packet handler.
Figure 25.2. Packet Handler Structure
TX FIFO RX FIFO
TX FIFO Almost
Empty Threshold
RX FIFO Almost
Full Threshold
1-255 Bytes 1-4 Bytes
0, 2, or 4
Bytes
Sync Word
Preamble
CRC Field 1 (opt)
Fie ld 1
Header or Da ta
Field 2 (opt)
Pk t Length or Data
CRC Field 2 (opt)
Fie ld 3 ( opt )
Data
CRC Field 3 (opt)
Fie ld 4 ( opt )
Data
CRC Field 4 (opt)
Fie ld 5 ( opt )
Data
CRC Field 5 (opt)
Config Config
0, 2, or 4
Bytes
Config
0, 2, or 4
Bytes 0, 2, or 4
Bytes 0, 2, or 4
Bytes
Config Config
Si106x/108x
263 Rev. 1.0
The fields are highly programmable and can be used to check any kind of pattern in a packet structure.
The general functions of the packet handler include the following:
Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal)
Detection of Sync word in RX mode (SYNC_OK signal)
Detection of valid packets in RX mode (PKT_VALID signal)
Detection of CRC errors in RX mode (CRC_ERR signal)
Data de-whitening and/or Manchester decoding (if enabled) in RX mode
Match/Header checking in RX mode
Storage of Data Field bytes into FIFO memory in RX mode
Construction of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
For details on how to configure the packet handler, see "AN626: Packet Handler Operation for Si106x
RFICs".
26. RX Modem Configuration
The Si106x/8x can easily be configured for different data rate, deviation, frequency, etc. by using the WDS
settings calculator, which generates an example file for use by the host MCU.
27. Auxiliary Blocks
27.1. Wake-Up Timer and 32 kHz Clock Source
The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep
mode. The wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz
crystal.
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_-
CONFIG property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by
the GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will
be generated on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The
microcontroller will then need to verify the interrupt by reading the chip interrupt status either via
GET_INT_STATUS or a fast response register. The formula for calculating the Wake-Up Period is as fol-
lows:
The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC
oscillator is automatically calibrated during the POWER_UP command and exits from the Shutdown state.
To enable the recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the
desired calibration period should be selected via WUT_CAL_PERIOD[2:0] in the same API property.
During the calibration, the 32 kHz RC oscillator frequency is compared to the 30 MHz crystal and then
adjusted accordingly. The calibration needs to start the 30 MHz crystal, which increases the average cur-
rent consumption; so, a longer CAL_PERIOD results in a lower average current consumption. The 32 kHz
crystal accuracy is comprised of both the crystal parameters and the internal circuit. The crystal accuracy
can be defined as the initial error + aging + temperature drift + detuning from the internal oscillator circuit.
The error caused by the internal circuit is typically less than 10 ppm. Refer to the API documentation for
WUT related API commands and properties.
WUT WUT_M 42
WUT_R
32 768
----------------------------
ms=
Rev. 1.0 264
Si106x/108x
Table 27.1. WUT Specific Commands and Properties
API Properties Description Requirements/Notes
GLOBAL_WUT_CON-
FIG
GLOBAL WUT
configuration
WUT_EN—Enable/disable wake up timer.
WUT_LBD_EN—Enable/disable low battery detect mea-
surement on WUT interval.
WUT_LDC_EN:
0 = Disable low duty cycle operation.
1 = RX LDC operation
treated as wake up START_RX
WUT state is used
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_EN—Enable calibration of the 32 kHz RC oscillator
WUT_CAL_PERIOD[2:0]—Sets calibration period.
GLOBAL_WUT_M_15_
8
Sets HW
WUT_M[15:8]
WUT_M—Parameter to set the actual wakeup time. See
equation above.
GLOBAL_ WUT_M_7_0 Sets HW
WUT_M[7:0]
WUT_M—Parameter to set the actual wakeup time. See
equation above.
GLOBAL_WUT_R Sets WUT_R[4:0]
Sets
WUT_SLEEP to
choose WUT
state
WUT_R—Parameter to set the actual wakeup time. See
equation above.
WUT_SLEEP:
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
GLOBAL_WUT_LDC Sets FW internal
WUT_LDC
WUT_LDC—Parameter to set the actual wakeup time. See
equation in “27.2. Low Duty Cycle Mode (Auto RX Wake-
Up)” .
Si106x/108x
265 Rev. 1.0
27.2. Low Duty Cycle Mode (Auto RX Wake-Up)
The Low Duty Cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid
signal is available or to enable the transmitter to send a packet. It allows low average current polling oper-
ation by the Si106x for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via
the GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined
by the following formula:
where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must
be set in conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer
(WUT) section.
Figure 27.1. RX and TX LDC Sequences
The basic operation of RX LDC mode is shown in Figure 27.2. The receiver periodically wakes itself up to
work on RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is
detected, or an entire packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at
the end of LDC mode duration and remains in that mode until the beginning of the next wake-up period. If
a valid preamble or sync word is detected, the receiver delays the LDC mode duration to receive the entire
packet. If a packet is not received during two LDC mode durations, the receiver returns to the WUT state at
the last LDC mode duration until the beginning of the next wake-up period.
Figure 27.2. Low Duty Cycle Mode for RX
In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If
a packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up
time expires.
LDC WUT_LDC 42
WUT_R
32 768
----------------------------
ms=
Rev. 1.0 266
Si106x/108x
27.3. Antenna Diversity (Si1060–Si1063, Si1080-Si1083)
To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver
systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the
transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation
process takes place during the preamble portion of the packet. The antenna with the strongest received
signal is then used for the remainder of that RX packet. The same antenna will also be used for the next
corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity
control algorithm. The required signals needed to control an external SPDT RF switch (such as a PIN
diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is
programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits
are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna
diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to
forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth
between the antennas until the packet starts to arrive. The recommended preamble length for optimal
antenna selection is 8 bytes.
Rev. 1.0 267
Si106x/108x
28. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 28.1.
Figure 28.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567
SMB0DAT SDA
FILTER
N
SMB0ADR
S
L
V
4
S
L
V
2
S
L
V
1
S
L
V
0
G
C
S
L
V
5
S
L
V
6
S
L
V
3
SMB0ADM
S
L
V
M
4
S
L
V
M
2
S
L
V
M
1
S
L
V
M
0
E
H
A
C
K
S
L
V
M
5
S
L
V
M
6
S
L
V
M
3
Arbitration
SCL Synchronization
Hardware ACK Generation
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
IRQ Generation
Si106x/108x
268 Rev. 1.0
28.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
28.2. SMBus Configuration
Figure 28.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 28.2. Typical SMBus Configuration
28.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 28.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
VDD = 5V
Master
Device
Slave
Device 1
Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SDA
SCL
Rev. 1.0 269
Si106x/108x
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 28.3 illustrates a typical
SMBus transaction.
Figure 28.3. SMBus Transaction
28.3.1. Transmitter vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bus. A device is a “receiver” when an address or data byte is being sent
to it from another device on the bus. The transmitter controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
28.3.2. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see Section “28.3.5. SCL High (SMBus Free) Timeout” on
page 270). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
28.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
SLA6
SDA
SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
Si106x/108x
270 Rev. 1.0
28.3.4. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
28.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only
implementation.
28.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgment of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgment is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an
ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgment is enabled,
these interrupts are always generated after the ACK cycle. See Section 28.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 28.4.2;
Table 28.5 provides a quick SMB0CN decoding reference.
Rev. 1.0 271
Si106x/108x
28.4.1. SMBus Configuration Re gister
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 28.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “31. Timers” on page 311.
Equation 28.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 28.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 28.2.
Equation 28.2. Typical SMBus Bit Rate
Figure 28.4 shows the typical SCL generation described by Equation 28.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 28.1.
Figure 28.4. Typical SMBus SCL Generation
Table 28.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0 0 Timer 0 Overflow
0 1 Timer 1 Overflow
1 0 Timer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow
THighMin TLowMin 1
fClockSourceOverflow
----------------------------------------------
==
BitRate fClockSourceOverflow
3
----------------------------------------------
=
SCL
Timer Source
Overflows
SCL High TimeoutT
Low
T
High
Si106x/108x
272 Rev. 1.0
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 28.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “28.3.4. SCL Low Timeout” on page 270). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 28.4).
Table 28.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0T
low – 4 system clocks
or
1 system clock + s/w delay*
3 system clocks
1 11 system clocks 12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgment, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
Rev. 1.0 273
Si106x/108x
SFR Page = 0x0; SFR Address = 0xC1
SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration
Bit 76543210
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Type R/W R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ENSMB
SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6INH
SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively removes the SMBus slave from the bus. Master Mode
interrupts are not affected.
5BUSY
SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
4 EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 28.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3SMBTOE
SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low.
If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms,
and the Timer 3 interrupt service routine should reset SMBus communication.
2SMBFTE
SMBus Free T imeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0] SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 28.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Si106x/108x
274 Rev. 1.0
28.4.2. SMB0CN Control Regi st er
SMB0CN is used to control the interface and to provide status information (see SFR Definition 28.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 28.3 for more details.
Import ant Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
28.4.2.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect incom-
ing slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver, writing
the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value
received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing
ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK
bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI.
SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will
remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be
ignored until the next START is detected.
28.4.2.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK gen-
eration is enabled. More detail about automatic slave address recognition can be found in Section 28.4.3.
As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus during the
ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value received on
the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If a received
slave address is NACKed by hardware, further slave events will be ignored until the next START is
detected, and no interrupt will be generated.
Table 28.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 28.5 for SMBus sta-
tus decoding using the SMB0CN register.
Refer to “Limitations for Hardware Acknowledge Feature” on page 279 when using hardware ACK genera-
tion.
Rev. 1.0 275
Si106x/108x
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
SFR Definition 28.2. SMB0CN: SMBus Control
Bit 76543210
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Type R R R/W R/W R R R/W R/W
Reset 00000000
Bit Name Description Read Write
7 MASTER SMBus Master/Slave
Indicator. This read-only bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6TXMODESMBus Transmit Mode
Indicator. This read-only bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5STASMBus Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STOSMBus Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
3ACKRQSMBus Acknowledge
Request. 0: No Ack requested
1: ACK requested
N/A
2ARBLOSTSMBus Arbitration Lost
Indicator. 0: No arbitration error.
1: Arbitration Lost
N/A
1ACKSMBus Acknowledge. 0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0SISMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
Si106x/108x
276 Rev. 1.0
Table 28.3. Sources for Hardware Changes to SMB0CN
Bit Set by Hardware When: Cleared by Hardware When:
MASTER A START is generated. A STOP is generated.
Arbitration is lost.
TXMODE START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
STA A START followed by an address byte is
received.
Must be cleared by software.
STO A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A pending STOP is generated.
ACKRQ A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
After each ACK cycle.
ARBLOST A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
Each time SI is cleared.
ACK The incoming ACK value is low
(ACKNOWLEDGE).
The incoming ACK value is high
(NOT ACKNOWLEDGE).
SI A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Must be cleared by software.
Rev. 1.0 277
Si106x/108x
28.4.3. Hardware Slave Address Recognition
The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an
ACK without software intervention. Automatic slave address recognition is enabled by setting the EHACK
bit in register SMB0ADM to 1. This will enable both automatic slave address recognition and automatic
hardware ACK generation for received bytes (as a master or slave). More detail on automatic hardware
ACK generation can be found in Section 28.4.2.2.
The registers used to define which address(es) are recognized by the hardware are the SMBus Slave
Address register (SFR Definition 28.3) and the SMBus Slave Address Mask register (SFR Definition 28.4).
A single address or range of addresses (including the General Call Address 0x00) can be specified using
these two registers. The most-significant seven bits of the two registers are used to define which
addresses will be ACKed. A 1 in bit positions of the slave address mask SLVM[6:0] enable a comparison
between the received slave address and the hardware’s slave address SLV[6:0] for those bits. A 0 in a bit
of the slave address mask means that bit will be treated as a “don’t care” for comparison purposes. In this
case, either a 1 or a 0 value are acceptable on the incoming slave address. Additionally, if the GC bit in
register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 28.4 shows
some example parameter settings and the slave addresses that will be recognized by hardware under
those conditions. Refer to “Limitations for Hardware Acknowledge Feature” on page 279 when using hard-
ware slave address recognition.
Table 28.4. Hardware Address Recognition Examples (EHACK = 1)
Hardware Slave Address
SLV[6:0] Slave Address Ma sk
SLVM[6:0] GC bit Slave Addresses Recognized by
Hardware
0x34 0x7F 00x34
0x34 0x7F 10x34, 0x00 (General Call)
0x34 0x7E 00x34, 0x35
0x34 0x7E 10x34, 0x35, 0x00 (General Call)
0x70 0x73 00x70, 0x74, 0x78, 0x7C
Si106x/108x
278 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xF4
SFR Page = 0x0; SFR Address = 0xF5
SFR Definition 28.3. SMB0ADR: SMBus Slave Address
Bit 76543210
Name SLV[6:0] GC
Type R/W R/W
Reset 00000000
Bit Name Function
7:1 SLV[6:0] SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a 1 in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0GCGeneral Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask
Bit 76543210
Name SLVM[6:0] EHACK
Type R/W R/W
Reset 11111110
Bit Name Function
7:1 SLVM[6:0] SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
0EHACKHardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
Rev. 1.0 279
Si106x/108x
28.4.4. Limitations for Hardware Acknowledge Feature
In some system management bus (SMBus) configurations, the Hardware Acknowledge mechanism of the
SMBus peripheral can cause incorrect or undesired behavior. The Hardware Acknowledge mechanism is
enabled when the EHACK bit (SMB0ADM.0) is set to logic 1.
The configurations to which these limitations do not apply are as follows:
a. All SMBus configurations when Hardware Acknowledge is disabled.
b. All single-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master or slave.
c. All multi-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a slave.
d. All single-master/multi-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master.
These limitations only apply to the following configurations:
a. All multi-slave SMBus configurations when Hardware Acknowledge is enabled and the MCU is
operating as a slave.
b. All multi-master SMBus configurations when Hardware Acknowledge is enabled and the MCU
is operating as a master.
The following issues are present when operating as a slave in a multi-slave SMBus configuration:
a. When Hardware Acknowledge is enabled and SDA setup and hold times are not extended
(EXTHOLD = 0 in the SMB0CF register), the SMBus hardware will always generate an SMBus
interrupt following the ACK/NACK cycle of any slave address transmission on the bus, whether
or not the address matches the conditions of SMB0ADR and SMB0MASK. The expected
behavior is that an interrupt is only generated when the address matches.
b. When Hardware Acknowledge is enabled and SDA setup and hold times are extended
(EXTHOLD = 1 in the SMB0CF register), the SMBus hardware will only generate an SMBus
interrupt as expected when the slave address transmission on the bus matches the conditions of
SMB0ADR and SMB0MASK. However, in this mode, the Start bit (STA) will be incorrectly
cleared on reception of a slave address before software vectors to the interrupt service routine.
c. When Hardware Acknowledge is enabled and the ACK bit (SMB0CN.1) is set to 1, an
unaddressed slave may cause interference on the SMBus by driving SDA low during an ACK
cycle. The ACK bit of the unaddressed slave may be set to 1 if any device on the bus generates
an ACK.
Impact:
a. Once the CPU enters the interrupt service routine, SCL will be asserted low until SI is cleared,
causing the clock to be stretched when the MCU is not being addressed. This may limit the
maximum speed of the SMBus if the master supports SCL clock stretching. Incompliant SMBus
masters that do not support SCL clock stretching will not recognize that the clock is being
stretched. If the CPU issues a write to SMB0DAT, it will have no effect on the bus. No data
collisions will occur.
b. Once the hardware has matched an address and entered the interrupt service routine, the
firmware will not be able to use the Start bit to distinguish between the reception of an address
byte versus the reception of a data byte. However, the hardware will still correctly acknowledge
the address byte (SLA+R/W).
c. The SMBus master and the addressed slave are prevented from generating a NACK by the
unaddressed slave because it is holding SDA low during the ACK cycle. There is a potential for
the SMBus to lock up.
Si106x/108x
280 Rev. 1.0
Workarounds:
a. The SMBus interrupt service routine should verify an address when it is received and clear SI as
soon as possible if the address does not match to minimize clock stretching. To prevent clock
stretching when not being addressed, enable setup and hold time extensions (EXTHOLD = 1).
b. Detection of Initial Start:
To distinguish between the reception of an address byte at the beginning of a transfer versus
the reception of a data byte when setup and hold time extensions are enabled (EXTHOLD = 1),
software should maintain a status bit to determine whether it is currently inside or outside a
transfer. Once hardware detects a matching slave address and interrupts the MCU, software
should assume a start condition and set the software bit to indicate that it is currently inside a
transfer. A transfer ends any time the STO bit is set or on an error condition (e.g., SCL Low
Timeout).
Detection of Repeated Start:
To detect the reception of an address byte in the middle of a transfer when setup and hold time
extensions are enabled (EXTHOLD = 1), disable setup and hold time extensions (EXTHOLD =
0) upon entry into a transfer and re-enable setup and hold time extensions (EXHOLD = 1) at the
end of a transfer.
c. Schedule a timer interrupt to clear the ACK bit at an interval shorter than 7 bit periods when the
slave is not being addressed. For example, on a 400 kHz SMBus, the ACK bit should be cleared
every 17.5 µs (or at 1/7 the bus frequency, 57 kHz). As soon as a matching slave address is
detected (a transfer is started), the timer which clears the ACK bit should be stopped and its
interrupt flag cleared. The timer should be re-started once a stop or error condition is detected
(the transfer has ended).
A code example demonstrating these workarounds can be found in the SMBus examples folder with the
following default location:
Si106x
C:\SiLabs\MCU\Examples\C8051F93x_92x\SMBus\F93x_SMBus_Slave_Multibyte_HWACK.c
Si108x
C:\SiLabs\MCU\Examples\C8051F91x_90x\SMBus\F91x_SMBus_Slave_Multibyte_HWACK.c
The SMBus examples folder, along with examples for many additional peripherals, is created when the Sil-
icon Laboratories IDE is installed. The latest version of the IDE may be downloaded from the software
downloads page www.silabs.com/MCUDownloads on the Silicon Laboratories website.
The following issue is present when operating as a master in a multi-master SMBus configuration:
If the SMBus master loses arbitration in a multi-master system, it may cause interference on the SMBus by
driving SDA low during the ACK cycle of transfers which it is not participating. This will occur regardless of
the state of the ACK bit (SMB0CN.1).
Impact:
The SMBus master and slave participating in the transfer are prevented from generating a NACK by the
MCU because it is holding SDA low during the ACK cycle. There is a potential for the SMBus to lock up.
Workaround:
Disable Hardware Acknowledge (EHACK = 0) when the MCU is operating as a master in a multi-master
SMBus configuration.
Rev. 1.0 281
Si106x/108x
28.4.5. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Page = 0x0; SFR Address = 0xC2
SFR Definition 28.5. SMB0DAT: SMBus Data
Bit 76543210
Name SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
Si106x/108x
282 Rev. 1.0
28.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-
tion is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK gen-
eration is enabled or not.
28.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 28.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode, regardless of whether hardware ACK generation is enabled.
Figure 28.5. Typical Master Write Sequence
28.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more
bytes of serial data.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
A AAS W PData Byte Data ByteSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Rev. 1.0 283
Si106x/108x
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0-
DAT is written while an active Master Receiver. Figure 28.6 shows a typical master read sequence. Two
received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte
transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK gen-
eration is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and after
the ACK when hardware ACK generation is enabled.
Figure 28.6. Typical Master Read Sequence
28.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received.
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 28.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
Data ByteData Byte A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Si106x/108x
284 Rev. 1.0
that the “data byte transferred” interrupts occur at different places in the sequence, depending on whether
hardware ACK generation is enabled. The interrupt occurs before the ACK with hardware ACK generation
disabled, and after the ACK when hardware ACK generation is enabled.
Figure 28.7. Typical Slave Write Sequence
28.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received
NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a
STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a
Slave Transmitter interrupt. Figure 28.8 shows a typical slave read sequence. Two transmitted data bytes
are shown, though any number of bytes may be transmitted. Notice that all of the ‘data byte transferred’
interrupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is
enabled.
PWSLASData ByteData Byte A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Rev. 1.0 285
Si106x/108x
Figure 28.8. Typical Slave Read Sequence
28.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 28.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 28.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
PRSLASData ByteData Byte A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Si106x/108x
286 Rev. 1.0
Table 28.5. SMBus S tatus Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
00X1100
1100 000A master data or address byte
was transmitted; NACK
received.
Set STA to restart transfer. 10X1110
Abort transfer. 0 1 X -
001A master data or address byte
was transmitted; ACK
received.
Load next data byte into SMB0-
DAT.
00X1100
End transfer with STOP. 0 1 X -
End transfer with STOP and start
another transfer.
1 1 X -
Send repeated START. 10X1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
00X1000
Master Receiver
1000 1 0 X A master data byte was
received; ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0011000
Send NACK to indicate last byte,
and send STOP.
0 1 0 -
Send NACK to indicate last byte,
and send STOP followed by
START.
1101110
Send ACK followed by repeated
START.
1011110
Send NACK to indicate last byte,
and send repeated START.
1001110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0011100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0001100
Rev. 1.0 287
Si106x/108x
Slave Transmitter
0100 000A slave byte was transmitted;
NACK received.
No action required (expecting
STOP condition).
00X0001
001A slave byte was transmitted;
ACK received.
Load SMB0DAT with next data
byte to transmit.
00X0100
0 1 X A Slave byte was transmitted;
error detected.
No action required (expecting
Master to end transfer).
00X0001
0101 0XXAn illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Clear STO. 0 0 X -
Slave Receiver
0010 1 0 X A slave address + R/W was
received; ACK requested.
If Write, Acknowledge received
address
0010000
If Read, Load SMB0DAT with
data byte; ACK received address
0010100
NACK received address. 0 0 0 -
1 1 X Lost arbitration as master;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address
0010000
If Read, Load SMB0DAT with
data byte; ACK received address
0010100
NACK received address. 0 0 0 -
Reschedule failed transfer;
NACK received address.
1001110
0001 0 0 X A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Clear STO. 0 0 X -
1 1 X Lost arbitration while attempt-
ing a STOP.
No action required (transfer
complete/aborted).
0 0 0 -
0000 1 0 X A slave byte was received;
ACK requested.
Acknowledge received byte;
Read SMB0DAT.
0010000
NACK received byte. 0 0 0 -
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START.
Abort failed transfer. 0 0 X -
Reschedule failed transfer. 10X1110
0001 0 1 X Lost arbitration due to a
detected STOP.
Abort failed transfer. 0 0 X -
Reschedule failed transfer. 10X1110
0000 1 1 X Lost arbitration while transmit-
ting a data byte as master.
Abort failed transfer. 0 0 0 -
Reschedule failed transfer. 1001110
T able 28.5. SMBus St atus Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Si106x/108x
288 Rev. 1.0
Table 28.6. SMBus S tatus Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 0 0 X A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
00X1100
1100 000A master data or address byte
was transmitted; NACK
received.
Set STA to restart transfer. 10X1110
Abort transfer. 0 1 X -
001A master data or address byte
was transmitted; ACK
received.
Load next data byte into SMB0-
DAT.
00X1100
End transfer with STOP. 0 1 X -
End transfer with STOP and start
another transfer.
1 1 X -
Send repeated START. 10X1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
0011000
Master Receiver
1000 001A master data byte was
received; ACK sent.
Set ACK for next data byte;
Read SMB0DAT.
0011000
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
0001000
Initiate repeated START. 1001110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
00X1100
000A master data byte was
received; NACK sent (last
byte).
Read SMB0DAT; send STOP. 0 1 0 -
Read SMB0DAT; Send STOP
followed by START.
1101110
Initiate repeated START. 1001110
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
00X1100
Rev. 1.0 289
Si106x/108x
Slave Transmitter
0100 000A slave byte was transmitted;
NACK received.
No action required (expecting
STOP condition).
00X0001
001A slave byte was transmitted;
ACK received.
Load SMB0DAT with next data
byte to transmit.
00X0100
0 1 X A Slave byte was transmitted;
error detected.
No action required (expecting
Master to end transfer).
00X0001
0101 0XXAn illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Clear STO. 0 0 X -
Slave Receiver
0010 0 0 X A slave address + R/W was
received; ACK sent.
If Write, Set ACK for first data
byte.
0010000
If Read, Load SMB0DAT with
data byte
00X0100
0 1 X Lost arbitration as master;
slave address + R/W received;
ACK sent.
If Write, Set ACK for first data
byte.
0010000
If Read, Load SMB0DAT with
data byte
00X0100
Reschedule failed transfer 10X1110
0001 0 0 X A STOP was detected while
addressed as a Slave Trans-
mitter or Slave Receiver.
Clear STO. 0 0 X -
0 1 X Lost arbitration while attempt-
ing a STOP.
No action required (transfer
complete/aborted).
0 0 0 -
0000 0 0 X A slave byte was received. Set ACK for next data byte;
Read SMB0DAT.
0010000
Set NACK for next data byte;
Read SMB0DAT.
0000000
Bus Error Condition
0010 0 1 X Lost arbitration while attempt-
ing a repeated START.
Abort failed transfer. 0 0 X -
Reschedule failed transfer. 10X1110
0001 0 1 X Lost arbitration due to a
detected STOP.
Abort failed transfer. 0 0 X -
Reschedule failed transfer. 10X1110
0000 0 1 X Lost arbitration while transmit-
ting a data byte as master.
Abort failed transfer. 0 0 X -
Reschedule failed transfer. 10X1110
Table 28.6. SMBus S t atus Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Rev. 1.0 290
Si106x/108x
29. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “29.1. Enhanced Baud Rate Generation” on page 291). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always ac ces s the buf fe red Receive regist er;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
Figure 29.1. UART0 Block Diagram
UART Baud
Rate Generator
RI
SCON
RI
TI
RB8
TB8
REN
MCE
SMODE
Tx Control
Tx Clock
Send
SBUF
(TX Shift)
Start
Data
Write to
SBUF
Crossbar
TX
Shift
Zero Detector
Tx IRQ
SET
QD
CLR
Stop Bit
TB8
SFR Bus
Serial
Port
Interrupt
TI
Port I/O
Rx Control
Start
Rx Clock
Load
SBUF
Shift 0x1FF RB8
Rx IRQ
Input Shift Register
(9 bits)
Load SBUF
Read
SBUF
SFR Bus
Crossbar
RX
SBUF
(RX Latch)
Si106x/108x
291 Rev. 1.0
29.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 29.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Figure 29.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “31.1.3. Mode 2: 8-bit
Counter/Timer with Auto-Reload” on page 314). The Timer 1 reload value should be set so that overflows
will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of
six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an
external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by
Equation 29.1-A and Equation 29.1-B.
Equation 29.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “31.1. Timer 0 and Timer 1” on
page 313. A quick reference for typical baud rates and system clock frequencies is given in Table 29.1
through Table 29.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
RX Timer
Start
Detected
Overflow
Overflow
TH1
TL1
TX Clock
2
RX Clock
2
Timer 1 UART
UartBaudRate 1
2
---T1_Overflow_Rate=
T1_Overflow_Rate T1CLK
256 TH1–
--------------------------
=
A)
B)
Rev. 1.0 292
Si106x/108x
29.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
Figure 29.3. UART Interconnect Diagram
29.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop
bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data
bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Inter-
rupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data recep-
tion can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
RI0 must be logic 0, and if MCE0 is logic 1, the stop bit must be logic 1. In the event of a receive data over-
run, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits
are lost.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not
be set. An interrupt will occur if enabled when either TI0 or RI0 is set.
Figure 29.4. 8-Bit UART Timing Diagram
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE
Si106x/108x
293 Rev. 1.0
29.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80
(SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met:
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
Figure 29.5. 9-Bit UART Timing Diagram
29.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB80 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
D1D0 D2 D3 D4 D5 D6 D7
START
BIT
MARK STOP
BIT
BIT TIMES
BIT SAMPLING
SPACE D8
Rev. 1.0 294
Si106x/108x
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device
Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
Si106x/108x
295 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
SFR Definition 29.1. SCON0: Serial Port 0 Control
Bit 76543210
Name S0MODE MCE0 REN0 TB80 RB80 TI0 RI0
Type R/W RR/W R/W R/W R/W R/W R/W
Reset 01000000
Bit Name Function
7S0MODE Serial Port 0 Operation Mode.
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6Unused Read = 1b. Write = Don’t Care.
5MCE0 Multiprocessor Communication Enable.
For Mode 0 (8-bit UART): Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
For Mode 1 (9-bit UART): Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4REN0 Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
3TB80 Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2RB80 Ninth Rece ive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1TI0 Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0RI0 Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
Rev. 1.0 296
Si106x/108x
SFR Page = 0x0; SFR Address = 0x99
SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer
Bit 76543210
Name SBUF0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 SBUF0 Serial Data Buffer Bits 7:0 (MSB– LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
Si106x/108x
297 Rev. 1.0
Table 29.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator
Divide
Factor
Timer Clo ck
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
Internal Osc.
230400 –0.32% 106 SYSCLK XX210xCB
115200 –0.32% 212 SYSCLK XX 10x96
57600 0.15% 426 SYSCLK XX 10x2B
28800 –0.32% 848 SYSCLK/4 01 00x96
14400 0.15% 1704 SYSCLK/12 00 00xB9
9600 –0.32% 2544 SYSCLK/12 00 00x96
2400 –0.32% 10176 SYSCLK/48 10 00x96
1200 0.15% 20448 SYSCLK/48 10 00x2B
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 31.1.
2. X = Don’t care.
Table 29.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator
Divide
Factor
Time r Clock
Source SCA1–SCA0
(pre-scale
select)1
T1M1Timer 1
Reload
Value (hex)
SYSCLK from
External Osc.
230400 0.00% 96 SYSCLK XX210xD0
115200 0.00% 192 SYSCLK XX 10xA0
57600 0.00% 384 SYSCLK XX 10x40
28800 0.00% 768 SYSCLK / 12 00 00xE0
14400 0.00% 1536 SYSCLK / 12 00 00xC0
9600 0.00% 2304 SYSCLK / 12 00 00xA0
2400 0.00% 9216 SYSCLK / 48 10 00xA0
1200 0.00% 18432 SYSCLK / 48 10 00x40
SYSCLK from
Internal Osc.
230400 0.00% 96 EXTCLK / 8 11 00xFA
115200 0.00% 192 EXTCLK / 8 11 00xF4
57600 0.00% 384 EXTCLK / 8 11 00xE8
28800 0.00% 768 EXTCLK / 8 11 00xD0
14400 0.00% 1536 EXTCLK / 8 11 00xA0
9600 0.00% 2304 EXTCLK / 8 11 00x70
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 31.1.
2. X = Don’t care.
Rev. 1.0 298
Si106x/108x
30. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports
multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an
input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment,
avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers.
NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation.
Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 30.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
Si106x/108x
299 Rev. 1.0
30.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
30.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It
is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is
operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant
bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
30.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is
operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-
significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and
when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire
mode, MISO is always driven by the MSB of the shift register.
30.1.3. Serial Clock (SCK)
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0
generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the
slave is not selected (NSS = 1) in 4-wire slave mode.
30.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits:
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a master and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 30.2, Figure 30.3, and Figure 30.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bit s affects the pinout of the device. When in 3-wire master or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “20. Si106x/108xPort Input/Output” on page 217 for
general purpose port I/O and crossbar information.
30.2. SPI0 Master Mode Operation
A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex
Rev. 1.0 300
Si106x/108x
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-
master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 30.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 30.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 30.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Figure 30.2. Multiple-Master Mode Connection Diagram
Figure 30.3. 3-Wire Single Master and Slave Mode Connection Diagram
Master
Device 2
Master
Device 1 MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
Si106x/108x
301 Rev. 1.0
Figure 30.4. 4-Wire Single Master and Slave Mode Connection Diagram
30.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK
signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift
register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS
signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte
transfer. Figure 30.4 shows a connection diagram between two slave devices in 4-wire slave mode and a
master device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 30.3 shows a connection diagram between a slave device in 3-
wire slave mode and a master device.
Slave
Device
Master
Device MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
Rev. 1.0 302
Si106x/108x
30.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The
data byte which caused the overrun is lost.
Si106x/108x
303 Rev. 1.0
30.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 30.5. For slave mode, the clock and
data relationships are shown in Figure 30.6 and Figure 30.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 30.9 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s
system clock.
Figure 30.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mode)
Rev. 1.0 304
Si106x/108x
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1)
30.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
Si106x/108x
305 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xA1
SFR Definition 30.7. SPI0CFG: SPI0 Configuration
Bit 7 6 5 4 3 2 1 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type RR/W R/W R/W R R R R
Reset 0 0 0 0 0 1 1 1
Bit Name Function
7 SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6 MSTEN Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5 CKPHA SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
4CKPOLSPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3 SLVSEL Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2 NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMTShif t Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0 RXBMT Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 30.1 for timing parameters.
Rev. 1.0 306
Si106x/108x
SFR Page = 0x0; SFR Address = 0xF8; Bit-Addressable
SFR Definition 30.8. SPI0CN: SPI0 Control
Bit 7 6 5 4 3 2 1 0
Name SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Type R/W R/W R/W R/W R/W RR/W
Reset 0 0 0 0 0 1 1 0
Bit Name Function
7 SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
6WCOLWrite Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
5MODFMode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
4 RXOVRN Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 30.2 and Section 30.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1 TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0 SPIEN SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
Si106x/108x
307 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xA2
SFR Page = 0x0; SFR Address = 0xA3
SFR Definition 30.9. SPI0CKR: SPI0 Clock Rate
Bit 7 6 5 4 3 2 1 0
Name SCR[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SCR[7:0] SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Definition 30.10. SPI0DAT: SPI0 Data
Bit 7 6 5 4 3 2 1 0
Name SPI0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
fSCK SYSCLK
2 SPI0CKR[7:0] 1+
-----------------------------------------------------------
=
fSCK 2000000
241+
--------------------------
=
fSCK 200kHz=
Rev. 1.0 308
Si106x/108x
Figure 30.8. SPI Master Timing (CKPHA = 0)
Figure 30.9. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH T
MCKL
MOSI
T
MIS
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIH
SCK*
T
MCKH T
MCKL
MISO
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIS
Si106x/108x
309 Rev. 1.0
Figure 30.10. SPI Slave Timing (CKPHA = 0)
Figure 30.11. SPI Slave Timing (CKPHA = 1)
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SEZ T
SDZ
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SEZ
T
SDZ
Rev. 1.0 310
Si106x/108x
Table 30.1. SPI Slave Timing Parameters
Parameter Description Min Max Units
Master Mode Timing (See Figure 30.8 and Figure 30.9)
TMCKH SCK High Time 1 x TSYSCLK —ns
TMCKL SCK Low Time 1 x TSYSCLK —ns
TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 —ns
TMIH SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing (See Figure 30.10 and Figure 30.11)
TSE NSS Falling to First SCK Edge 2 x TSYSCLK —ns
TSD Last SCK Edge to NSS Rising 2 x TSYSCLK —ns
TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns
TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns
TCKH SCK High Time 5 x TSYSCLK —ns
TCKL SCK Low Time 5 x TSYSCLK —ns
TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK —ns
TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK —ns
TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns
TSLH Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x TSYSCLK 8 x TSYSCLK ns
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 1.0 311
Si106x/108x
31. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock or a Comparator period with
respect to another oscillator. This is particularly useful when using Capacitive Touch Switches. See Appli-
cation Note AN338 for details on Capacitive Touch Switch sensing.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 31.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Timer 0 and Timer 1 Modes: Timer 2 Modes: Timer 3 Modes:
13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-
reload
Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
Si106x/108x
312 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x8E
SFR Definition 31.1. CKCON: Clock Control
Bit 76543210
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MHTimer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3MLTimer 3 Low Byte Clock Select.
Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MHTimer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2MLTimer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1MTimer 1 Clo ck Select.
Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0MTimer 0 Clo ck Select.
Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bits.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
Rev. 1.0 313
Si106x/108x
31.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
ter (Section “11.5. Interrupt Register Descriptions” on page 140); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “11.5. Interrupt Register Descriptions” on page 140). Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
31.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“20.3. Priority Crossbar Decoder” on page 221 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 31.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 11.7). Setting GATE0 to 1
allows the timer to be controlled by the external input signal INT0 (see Section “11.5. Interrupt Register
Descriptions” on page 140), facilitating pulse width measurements
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 11.7).
Table 31.1. Timer 0 Running Modes
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
Si106x/108x
314 Rev. 1.0
Figure 31.1. T0 Mode 0 Block Diagram
31.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
31.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “11.6. External Interrupts INT0 and INT1”
on page 147 for details on the external input signals INT0 and INT1).
TCLK TL0
(5 bits)
TH0
(8 bits)
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL XOR
Rev. 1.0 315
Si106x/108x
Figure 31.2. T0 Mode 2 Block Diagram
31.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 bits)
Reload
TH0
(8 bits)
0
1
0
1
SYSCLK
Pre-scaled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Si106x/108x
316 Rev. 1.0
Figure 31.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock
TR1 TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL XOR
INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
Rev. 1.0 317
Si106x/108x
SFR Page = 0x0; SFR Address = 0x88; Bit-Addressable
SFR Definition 31.2. TCON: Timer Control
Bit 76543210
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF1 Timer 1 Overflow Flag.
Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5 TF0 Timer 0 Overflow Flag.
Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2IT1Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 11.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1IE0External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0IT0Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 11.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
Si106x/108x
318 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x89
SFR Definition 31.3. TMOD: Timer Mode
Bit 76543210
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1Timer 1 Gate Con trol.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 11.7).
6C/T1Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3GATE0Timer 0 Gate Con trol.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 11.7).
2C/T0Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counter/Timers
Rev. 1.0 319
Si106x/108x
SFR Page = 0x0; SFR Address = 0x8A
SFR Page = 0x0; SFR Address = 0x8B
SFR Definition 31.4. TL0: Timer 0 Low Byte
Bit 76543210
Name TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 31.5. TL1: Timer 1 Low Byte
Bit 76543210
Name TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Si106x/108x
320 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x8C
SFR Page = 0x0; SFR Address = 0x8D
SFR Definition 31.6. TH0: Timer 0 High Byte
Bit 76543210
Name TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 31.7. TH1: Timer 1 High Byte
Bit 76543210
Name TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
Rev. 1.0 321
Si106x/108x
31.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
31.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 31.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
Figure 31.4. Timer 2 16-Bit Mode Block Diagram
31.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 31.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH
Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
SmaRTClock / 8
SYSCLK / 12 00
T2XCLK[1:0]
01
11
Comparator 0
Si106x/108x
322 Rev. 1.0
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 31.5. Timer 2 8-Bit Mode Block Diagram
T2MH T2XCLK[1:0] TMR2H Clock
Source T2ML T2XCLK[1:0] TMR2L Clock
Source
0 00 SYSCLK / 12 0 00 SYSCLK / 12
0 01 SmaRTClock / 8 0 01 SmaRTClock / 8
0 10 Reserved 0 10 Reserved
0 11 Comparator 0 0 11 Comparator 0
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR2
1
0
TMR2H
TMR2RLH Reload
Reload
TCLK TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
SmaRTClock / 8
SYSCLK / 12 00
T2XCLK[1:0]
01
11
Comparator 0
Rev. 1.0 323
Si106x/108x
31.2.3. Comparator 0/SmaRTClock Capture Mode
The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured
against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can
also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2
should be in 16-bit auto-reload mode when using Capture Mode.
When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge
or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs,
the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers
(TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled).
By recording the difference between two successive timer capture values, the Comparator 0 or SmaRT-
Clock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster
than the capture clock to achieve an accurate reading.
For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and cap-
ture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the SmaRTClock clock is as follows:
24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the
time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capaci-
tance of a Touch Sense Switch.
Figure 31.6. Timer 2 Capture Mode Block Diagram
SmaRTClock/8
SYSCLK
0
1
T2XCLK1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2L TMR2H
TCLK
TR2
TMR2RLL TMR2RLH
Capture
TMR2CN
T2SPLIT
T2XCLK1
TF2CEN
TF2L
TF2H
T2XCLK0
TR2
TF2LEN
TF2CEN Interrupt
SYSCLK/12 X0
T2XCLK[1:0]
01
11
Comparator 0
0
1
SmaRTClock/8
Comparator 0
Si106x/108x
324 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xC8; Bit-Addressable
SFR Definition 31.8. TMR2CN: Timer 2 Control
Bit 76543210
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7TF2HTimer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the
Timer 2 interrupt service routine. This bit is not automatically cleared by hardware.
6TF2LT imer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
5 TF2LEN Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts
are also enabled, an interrupt will be generated when the low byte of Timer 2 over-
flows.
4 TF2CEN Timer 2 Capture Enable.
When set to 1, this bit enables Timer 2 Capture Mode.
3 T2SPLIT Timer 2 S plit Mode Enable.
When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise,
Timer 2 operates in 16-bit auto-reload mode.
2TR2Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
1:0 T2XCLK[1:0] Timer 2 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 2. If
Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8.
01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8.
10: External Clock is SYSCLK/12. Capture trigger is Comparator 0.
11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0.
Rev. 1.0 325
Si106x/108x
SFR Page = 0x0; SFR Address = 0xCA
SFR Page = 0x0; SFR Address = 0xCB
SFR Definition 31.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit 76543210
Name TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 31.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit 76543210
Name TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Si106x/108x
326 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xCC
SFR Page = 0x0; SFR Address = 0xCD
SFR Definition 31.11. TMR2L: Timer 2 Low Byte
Bit 76543210
Name TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 31.12. TMR2H Timer 2 High Byte
Bit 76543210
Name TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
Rev. 1.0 327
Si106x/108x
31.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
31.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 31.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
Figure 31.7. Timer 3 16-Bit Mode Block Diagram
31.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 31.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH
Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
Interrupt
TF3LEN
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
T3XCLK[1:0]
SYSCLK / 12 00
External Clock / 8 01
11Comparator 1
SYSCLK / 12 10
Si106x/108x
328 Rev. 1.0
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 31.8. Timer 3 8-Bit Mode Block Diagram.
T3MH T3XCLK[1:0] TMR3H Clock
Source T3ML T3XCLK[1:0] TMR3L Clock
Source
0 00 SYSCLK / 12 0 00 SYSCLK / 12
0 01 External Clock / 8 0 01 External Clock / 8
0 10 SYSCLK / 12 0 10 SYSCLK / 12
0 11 Comparator 1 0 11 Comparator 1
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1
TR3
1
0
TMR3H
TMR3RLH Reload
Reload
TCLK TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK0
TR3
To ADC
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
T3XCLK[1:0]
SYSCLK / 12 00
External Clock / 8 01
11Comparator 1
SYSCLK / 12 10
Rev. 1.0 329
Si106x/108x
31.3.3. Comparator 1/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either Comparator 1 or the external oscillator period to be measured
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator
period can also be compared against each other.
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this
mode, T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-
ence between two successive timer capture values, the Comparator 1 or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the Comparator 1 period is:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
Figure 31.9. Timer 3 Capture Mode Block Diagram
External Clock / 8
SYSCLK
0
1
T3XCLK1
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3L TMR3H
TCLK
TR3
TMR3RLL TMR3RLH
Capture
TMR3CN
T3SPLIT
T3XCLK1
TF3CEN
TF3L
TF3H
T3XCLK0
TR3
TF3LEN
TF3CEN Interrupt
T3XCLK[1:0]
0
1
Comparator 1
SYSCLK / 12 00
External Clock / 8 01
11Comparator 1
SYSCLK / 12 10
Si106x/108x
330 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x91
SFR Definition 31.13. TMR3CN: Timer 3 Control
Bit 76543210
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7 TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6 TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared by hardware.
5 TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CENTimer 3 Comparator 1/External Oscillator Capture Enable.
When set to 1, this bit enables Timer 3 Capture Mode.
3 T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2TR3Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode.
1:0 T3XCLK[1:0] T imer 3 External Clock Select.
This bit selects the “external” and “capture trigger” clock sources for Timer 3. If
Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer
bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be
used to select between the “external” clock and the system clock for either timer.
Note: External clock sources are synchronized with the system clock.
00: External Clock is SYSCLK /12. Capture trigger is Comparator 1.
01: External Clock is External Oscillator/8. Capture trigger is Comparator 1.
10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8.
11: External Clock is Comparator 1. Capture trigger is External Oscillator/8.
Rev. 1.0 331
Si106x/108x
SFR Page = 0x0; SFR Address = 0x92
SFR Page = 0x0; SFR Address = 0x93
SFR Definition 31.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit 76543210
Name TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 31.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit 76543210
Name TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Si106x/108x
332 Rev. 1.0
SFR Page = 0x0; SFR Address = 0x94
SFR Page = 0x0; SFR Address = 0x95
SFR Definition 31.16. TMR3L: Timer 3 Low Byte
Bit 76543210
Name TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In
8-bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 31.17. TMR3H Timer 3 High Byte
Bit 76543210
Name TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In
8-bit mode, TMR3H contains the 8-bit high byte timer value.
Rev. 1.0 333
Si106x/108x
32. Si106x/108xSi106x/108x Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between the following sources: system clock, system clock divided
by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 over-
flows, or an external clock signal on the ECI input pin. Each capture/compare module may be configured to
operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output,
Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“32.3. Capture/Compare Modules” on page 336). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 32.1
Import ant Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 32.4 for details.
Figure 32.1. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0
Capture/Compare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 4
Capture/Compare
Module 3
Capture/Compare
Module 5 / WDT
CEX4
CEX5
CEX3
Si106x/108x
334 Rev. 1.0
32.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Regist er first guaran tees an a ccurate read ing of t he entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 32.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Figure 32.2. PCA Counter/Timer Block Diagram
Table 32.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
000System clock divided by 12
001System clock divided by 4
010Timer 0 overflow
011High-to-low transitions on ECI (max rate = system clock divided
by 4)
100System clock
101External oscillator source divided by 8*
110Reserved
111Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
5
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
IDLE
0
1PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
Rev. 1.0 335
Si106x/108x
32.2. PCA0 Interrupt Sources
Figure 32.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can
be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set
upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an
overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
Figure 32.3. PCA Interrupt Block Diagram
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
5
C
C
F
4
C
C
F
3
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow
0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 5)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
0
1
Set 8, 9, 10, or 11 bit Operation
0
1
PCA Module 3
(CCF3)
PCA Module 4
(CCF4)
ECCF4
0
1
PCA Module 5
(CCF5)
ECCF5
ECCF3
0
1
Si106x/108x
336 Rev. 1.0
32.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 32.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Table 32.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number 765432107654-2 1–0
Capture triggered by positive edge on CEXn X X 1 0 0 0 0 A 0 X B XXX XX
Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A 0 X B XXX XX
Capture triggered by any transition on CEXn X X 1 1 0 0 0 A 0 X B XXX XX
Software Timer X C 0 0 1 0 0 A 0 X B XXX XX
High Speed Output X C 0 0 1 1 0 A 0 X B XXX XX
Frequency Output X C 0 0 0 1 1 A 0 X B XXX XX
8-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
Rev. 1.0 337
Si106x/108x
32.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Figure 32.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
x000xx
Si106x/108x
338 Rev. 1.0
32.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 32.5. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
Rev. 1.0 339
Si106x/108x
32.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Figure 32.6. PCA High-Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn Crossbar Port I/O
Toggle
0
1
TOGn
PCA0CN
C
F
C
R
C
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
Si106x/108x
340 Rev. 1.0
32.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 32.1.
Equation 32.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Figure 32.7. PCA Frequency Output Mode
32.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channe ls configured for 8/9 /10/11-bit PWM mode will use
the same cycle leng th. It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
FCEXn FPCA
2PCA0CPHn
-----------------------------------------
=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn Crossbar Port I/O
Toggle
0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
Rev. 1.0 341
Si106x/108x
32.3.5.1. 8-Bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 32.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 32.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 32.2. 8-Bit PWM Duty Cycle
Using Equation 32.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 32.8. PCA 8-Bit PWM Mode Diagram
Duty Cycle 256 PCA0CPHn–
256
---------------------------------------------------
=
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x000
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
C
O
V
F
Si106x/108x
342 Rev. 1.0
32.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 32.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 32.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 32.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 32.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
Duty Cycle 2NPCA0CPn–
2N
--------------------------------------------
=
N-bit Comparator
PCA0H:L
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
CEXn Crossbar Port I/O
Enable
Overflow of N
th
Bit
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
R/W when
ARSEL = 1
R/W when
ARSEL = 0 Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
C
O
V
F
Rev. 1.0 343
Si106x/108x
32.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 32.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 32.4. 16-Bit PWM Duty Cycle
Using Equation 32.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Figure 32.10. PCA 16-Bit PWM Mode
Duty Cycle 65536 PCA0CPn–
65536
-----------------------------------------------------
=
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Comparator CEXn Crossbar Port I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
Si106x/108x
344 Rev. 1.0
32.4. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH5) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-
ule 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
32.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 32.11).
Figure 32.11. PCA Module 5 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 32.5, where PCA0L is the value of the PCA0L register
at the time of the update.
PCA0H
Enable
PCA0L Overflow
Reset
PCA0CPL5 8-bit Adder
PCA0CPH5
Adder
Enable
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
Match
Write to
(PCA0CPH5)
8-bit
Comparator
Rev. 1.0 345
Si106x/108x
Equation 32.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
32.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 32.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 32.3 lists some example tim-
eout intervals for typical system clocks.
Table 32.3. Watchdog Timer Timeout Intervals1
System Clock (Hz) PCA0CPL5 Timeout Interval (ms)
24,500,000 255 32.1
24,500,000 128 16.2
24,500,000 32 4.1
3,062,5002255 257
3,062,5002128 129.5
3,062,500232 33.1
32,000 255 24576
32,000 128 12384
32,000 32 3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Offset 256 PCA0CPL5256 PCA0L–+=
Si106x/108x
346 Rev. 1.0
32.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
SFR Definition 32.1. PCA0CN: PCA Control
Bit 76543210
Name CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CFPCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6CRPCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:0 CCF[5:0] PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
Rev. 1.0 347
Si106x/108x
SFR Page = 0x0; SFR Address = 0xD9
SFR Definition 32.2. PCA0MD: PCA Mode
Bit 76543210
Name CIDL WDTE WDLCK CPS2 CPS1 CPS0 ECF
Type R/W R/W R/W RR/W R/W R/W R/W
Reset 01000000
Bit Name Function
7CIDLPCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6WDTEWatchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
5 WDLCK Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4 Unused Read = 0b, Write = don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Reserved
111: Reserved
0ECFPCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
Si106x/108x
348 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xDF
SFR Definition 32.3. PCA0PWM: PCA PWM Configuration
Bit 76543210
Name ARSEL ECOV COVF CLSEL[1:0]
Type R/W R/W R/W RRR R/W
Reset 00000000
Bit Name Function
7ARSELAuto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other
modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6ECOVCycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5COVFCycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for this flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Read = 000b; Write = don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. These bits are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.0 349
Si106x/108x
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
SFR Definition 32.4. PCA0CPMn: PCA Capture/Compare Mode
Bit 76543210
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6ECOMnComparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5 CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATnMatch Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGnToggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1PWMnPulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
0ECCFnCapture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
Si106x/108x
350 Rev. 1.0
SFR Page = 0x0; SFR Address = 0xF9
SFR Page = 0x0; SFR Address = 0xFA
SFR Definition 32.5. PCA0L: PCA Counter/Timer Low Byte
Bit 76543210
Name PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 32.6. PCA0H: PCA Counter/Timer High Byte
Bit 76543210
Name PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register, whose contents
are updated only when the contents of PCA0L are read (see Section 32.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
Rev. 1.0 351
Si106x/108x
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB,
PCA0CPL3 = 0xED, PCA0CPL4 = 0xFD, PCA0CPL5 = 0xD2
SFR Pages: PCA0CPL0 = 0x0, PCA0CPL1 = 0x0, PCA0CPL2 = 0x0,
PCA0CPL3 = 0x0, PCA0CPL4 = 0x0, PCA0CPL5 = 0x0
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC,
PCA0CPH3 = 0xEE, PCA0CPH4 = 0xFE, PCA0CPH5 = 0xD3
SFR Pages: PCA0CPH0 = 0x0, PCA0CPH1 = 0x0, PCA0CPH2 = 0x0,
PCA0CPH3 = 0x0, PCA0CPH4 = 0x0, PCA0CPH5 = 0x0
SFR Definition 32.7. PCA0CPLn: PCA Capture Module Low Byte
Bit 76543210
Name PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
This register address also allows access to the low byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this register will clear the module’s ECOMn bit to a 0.
SFR Definition 32.8. PCA0CPHn: PCA Capture Module High Byte
Bit 76543210
Name PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also allows access to the high byte of the corresponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
Rev. 1.0 352
Si106x/108x
33. Device Specific Behavior
This chapter contains behavioral differences between the silicon revisions of Si106x/108x devices. These
differences do not affect the functionality or performance of most systems and are described below.
33.1. Device Identification
The Part Number Identifier on the top side of the device package can be used for decoding device informa-
tion. The first character of the trace code identifies the silicon revision. On Si106x/108x devices, the trace
code will be the fifth letter on the second line. Figure 33.1 show how to find the part number on the top side
of the device package.
Figure 33.1. Si106x Revision Information
This fifth character identifies
the device revision.
Si106x/108x
353 Rev. 1.0
34. C2 Interface
Si106x/108x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash program-
ming and in-system debugging with the production part installed in the end application. The C2 interface
uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the
device and a host system. See the C2 Interface Specification for details on the C2 protocol.
34.1. C2 Interface Registers
The following describes the C2 registers necessary to perform flash programming through the C2 inter-
face. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
C2 Register Definition 34.1. C2ADD: C2 Address
Bit 76543210
Name C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address Description
0x00 Selects the Device ID register for Data Read instructions
0x01 Selects the Revision ID register for Data Read instructions
0x02 Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4 Selects the C2 Flash Programming Data register for Data
Read/Write instructions
Rev. 1.0 354
Si106x/108x
C2 Address: 0x00
C2 Address: 0x01
C2 Register Definition 34.2. DEVICEID: C2 Device ID
Bit 76543210
Name DEVICEID[7:0]
Type R/W
Reset 00010100
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x16 (Si106x/108x).
C2 Register Definition 34.3. REVID: C2 Revision ID
Bit 76543210
Name REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
Si106x/108x
355 Rev. 1.0
C2 Address: 0x02
C2 Address: 0xB4
C2 Register Definition 34.4. FPCTL: C2 Flash Programming Control
Bit 76543210
Name FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable flash programming via the C2 interface. To enable C2
flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 flash programming is enabled, a system reset must be issued to resume
normal operation.
C2 Register Definition 34.5. FPDAT: C2 Flash Programming Data
Bit 76543210
Name FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Prog ramming Data Register.
This register is used to pass flash commands, addresses, and data during C2 flash
accesses. Valid commands are listed below.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
Rev. 1.0 356
Si106x/108x
34.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and flash
programming may be performed. This is possible because C2 communication is typically performed when
the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted
state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications, external
resistors are required to isolate C2 interface traffic from the user application. A typical isolation configura-
tion is shown in Figure 34.1.
Figure 34.1. Typical C2 Pin Sharing
The configuration in Figure 34.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the specific application.
C2D
C2CK
RST (a)
Input (b)
Output (c)
C2 Interface Master
Si106x/Si108x
357 Rev. 1.0
Si106x/108x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.5
Updated data sheet to include Si108x family
information.
Updated block diagram figure 1.1 to include Si108x
functionality.
Updated application examples for Figures 1.2 and
1.3.
Revised package drawing in Figure 3.4 and Table
3.4.
Revision 0.5 to Revision 1.0
Updated the XIN and XOUT descriptions in Tables
3.1, 3.2, and 3.3
Updated the notes in Tables 4.11-4.20 to reflect final
production parts.
Removed the section entitled Definition of Test
Conditions.
Updated Figure 21.4 to reflect both EZRadio and
EZRadioPRO.
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations
thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
http://www.silabs.com
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
Smart.
Connected.
Energy-Friendly
Products
www.silabs.com/products Quality
www.silabs.com/quality Support and Community
community.silabs.com
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Silicon Laboratories:
Si1060-A-GM Si1064-A-GM Si1082-A-GM Si1085-A-GM Si1065-A-GM Si1083-A-GM Si1061-A-GM Si1084-A-GM
Si1062-A-GM Si1081-A-GM Si1063-A-GM Si1080-A-GM Si1085-A-GMR Si1084-A-GMR Si1082-A-GMR Si1062-
A-GMR Si1063-A-GMR Si1061-A-GMR Si1060-A-GMR Si1064-A-GMR Si1083-A-GMR Si1081-A-GMR Si1080-A-
GMR Si1065-A-GMR SI1060-A-GM SI1060-A-GMR SI1061-A-GM SI1061-A-GMR SI1062-A-GM SI1062-A-GMR
SI1083-A-GM SI1083-A-GMR SI1084-A-GM SI1084-A-GMR SI1085-A-GM SI1085-A-GMR SI1080-A-GM SI1080-
A-GMR SI1081-A-GM SI1081-A-GMR SI1082-A-GM SI1082-A-GMR SI1063-A-GM SI1063-A-GMR SI1064-A-GM
SI1064-A-GMR SI1065-A-GM SI1065-A-GMR
