TC358746AXBG/TC358748XBG
1 / 19 2020-12-14
Rev.1.85
© 2014-2020
Toshiba Electronic Devices & Storage Corporation
CMOS Digital Integr at ed Circuit Silicon Monolithi c
TC358746AXBG/TC358748XBG
Mobile Per i pheral Devices
Overview
The MIPI® CSI-2 to Par allel port and Par allel port to CSI -2
(TC358746AXBG/T C3 58748XBG) is a bridge device t hat converts
MIPI data t r ansfers from dev ices such as a camera to an applicati on
processor over a Parallel port interface. All internal registers can b e
access through I2C or SPI ( in C SI out case only).
Features
● CSI-2 TX/RX Interface
MIPI CSI-2 compliant (Version 1.01 Revision
0.04 – 2 April 2009)
Configurable to TX or RX controller
Supports up to 1Gbp s per data lane
Supports up to 4 data lanes
Supports video data formats
- RX: RAW8/ 10/12/14, YUV422 ( C CIR/ITU 8/10-
bit), RGB 888/ 666/565 and User -Defined 8-bit
- TX: YUV422 (CCIR/ITU 8/10-bit), YUV444,
RGB888/6 66/56 5 and RAW8/ 10/12/14
● Parallel P or t Interface
Support s data formats
- 24-bit bus – un-packed format (Both Input and
Output mode)
RGB888/666/565, R AW8/10/12/14 and
YUV422 8-bit (on 8/16-b it dat a bus ) and 10-bit
data format s .
YUV444 (Paralle l I nput mode only)
- YUV422 8-bit – ITU BT.656 and I TU BT.601
(Parallel i nput mode only)
Up to 100 MHz PCLK freq uency for Output
mode, and 166 MHz for Input mo de.
● I2C Slave I nterface (CS = L)
Support for normal (1 00 kHz), fast mo de ( 400
kHz) and spe ci al mode (1 MHz)
Configure all TC358746AXBG/TC358748XBG
internal registers
● SPI Slav e Interface (Only app lic able in CSIOut
configurat i on, MSEL = H, and C S = H)
SPI int er fa ce support for up t o 25 M Hz
operation.
Configur e all TC358746A XBG/TC358 748X BG
internal registers
● GPIO signals
3 GPIO signals
- Three GPI O signals can be con fi gur ed as
control sig nals (MCLK, CXRST, XShutdow n) f or
CSI-2 RX device.
- Or one GPIO signal can be con fi gur ed as INT
signal for P arallel interfa ce.
● System
Cloc k and pow er manage me nt support t o
achieve low power states.
● Power supply inputs
Core and M I PI D-PHY: 1.2 V
I/O: 1.8 V – 3.3 V
P-VFBGA72-0404-0.40A3
Weight:
32 mg (Typ.)
Weight: 68 mg (T yp.)
P-VFBGA80-0707-0.65-001
TC358746AXBG
TC358748XBG
TC358746AXBG/TC358748XBG
2 / 19 2020-12-14
Table of content
REFERENCES ..................................................................................................................................................... 5
1. Ov erv iew .......................................................................................................................................................... 6
2. Features ........................................................................................................................................................... 8
2.1. Typical Power Consumption ...................................................................................................................... 9
3. Externa l P ins .................................................................................................................................................. 10
3.1. TC358746AXBG pi nout descript io n ........................................................................................................ 10
3.2. TC358746AXBG BGA72 pin Count Summary ........................................................................................ 11
3.3. TC358748XBG BG A 80 Pin Count Summary .......................................................................................... 11
3.4. TC358746AXBG P in Layout .................................................................................................................... 12
3.5. TC358748X BG Pin Lay out ...................................................................................................................... 13
4. Package ......................................................................................................................................................... 14
4.1. TC358746AXBG Package ....................................................................................................................... 14
4.2. TC358748X BG Pac kage ......................................................................................................................... 15
5. Electrical Character ist i cs ................................................................................................................................ 16
5.1. Absolut e M aximum Rat ings ..................................................................................................................... 16
5.2. Operating Condit ion ................................................................................................................................. 16
5.3. DC Elect r ical Specific at ion ...................................................................................................................... 17
6. Revision History ............................................................................................................................................. 18
RES TRICTIONS ON PRODUCT USE ............................................................................................................... 19
Table of Figures
Figure 1.1 System Overview with TC358746AXBG/TC358748XBG in CSI-2 RX to Parallel Port
Configuration ......................................................................................................................................... 6
Figure 1.2 System Overview with TC358746AXBG/TC358748XBG in Parallel Port to CSI-2 TX
Configuration ......................................................................................................................................... 7
Figure 3.1 TC358746AXBG BG A72-Pin Layout (Top V iew ) ................................................................... 12
Figure 3.2 TC358748XBG 80-Pin Layout (Top View) .............................................................................. 13
Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package ........................................................... 14
Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 pac kage ........................................................... 15
List of Tables
Table 3.1 TC3 58746AXBG/ TC358748XBG Function al S ig nal List ........................................................ 10
Table 3.2 TC3 58746AXBG BG A 72Pin Count Summary ........................................................................ 11
Table 3.3 TC3 58748XBG BGA 80 Pin Count Su m mary ......................................................................... 11
Table 4.1 TC3 58746AXBG P-VFBGA72-0404-0.40A3 Mecha nical Dim ensio n...................................... 14
Table 4.2 TC3 58748XBG P-VFBGA80-0707-0.65-001 Mechanical Di me nsion ..................................... 15
Table 6.1 Revision History ....................................................................................................................... 18
TC358746AXBG/TC358748XBG
3 / 19 2020-12-14
● MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc.
TC358746AXBG/TC358748XBG
4 / 19 2020-12-14
1 NOTI C E OF DISCLAIM E R
2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on
4 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
5 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
6 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if
7 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpos e, of
8 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of
9 negligence.
10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
11 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express
12 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
13 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and
14 cannot be used without its express prior written permission.
15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
16 POSS E SS I ON , CO RR E S PO N DENCE T O DESCRIPTIO N OR N ON-INF RI NGE M E NT W I T H RE G A RD
17 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
18 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
19 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
20 GOOD S OR SERVI C ES, L OS T PR OF ITS, L OSS OF USE, L OSS OF DATA, OR A N Y I NCIDEN TAL,
21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
22 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
23 ANY OTHER AGREEMENT, S PE CI F ICATI ON O R D OCUMENT RELATI NG TO THI S M AT ERIAL ,
24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
25 DAMAGES.
26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
27 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
28 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
29 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
30 with the contents of this Document. The use or implementation of the contents of this Document may
31 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,
32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
33 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
34 IPR or claims of IPR as respects the contents of this Document or otherwise.
35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
36 MIPI Alliance, Inc.
37 c/o IEEE-ISTO
38 445 Hoes Lane
39 Piscataway , NJ 08854
40 Attn: Board Secretary
TC358746AXBG/TC358748XBG
5 / 19 2020-12-14
REFERENCES
1. MIPI D-PHY, “MIPI_D-PHY_specification_v01-00-00, May 14, 2009"
2. MIPI CSI-2, "MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01 Revision Nov 2010"
3. I2C bus specification, version 2.1, January 2000, Philips Semiconductor
TC358746AXBG/TC358748XBG
6 / 19 2020-12-14
1. Overview
The MIPI CSI-2 to Parallel port and Parallel port to CSI-2 (TC358746AXBG/TC358748XBG) is a bridge device
that converts MIPI data transfers from devices such as a camera to an application processor over a Parallel port
interface. All internal registers can be access through I2C or SPI (in CSI out case only).
There are several system configurations where TC358746AXBG/TC358748XBG are typically be used
● CSI-2 TX with Parallel Input mode for Analog TV, Tele-presence Type, and Specialty/Older Cameras
application. In this mode, TC358746AXBG/TC358748XBG (Parallel to CSI-2 converter) is a bridge device that
converts parallel data transfers to an application over a MIPI CSI-2 interface. Toshiba Bridge Chip provides a
low power bridge solution to efficiently translate parallel transfers to serial transfers.
● CSI-2 RX with Parallel output mode for scanner application. In this mode, TC358746AXBG/TC358748XBG
(CSI-2 to Parallel converter) is a bridge device that converts serial data transfers from devices such as a camera
to an application processor over a parallel interface. Toshiba Bridge Chip provides a low power bridge solution
to efficiently translate serial transfers to parallel transfers.
Camera
TC358746AXBG
MIPI
To
Paralle l Port
Converter
MI PI Li nk
Q uad Data La n es Pa rallel Por t
24-b it d ata
Asic
I
2
C
Figure 1.1 System Overview with TC358746AXBG/TC35 8748XBG in CS I-2 RX to Parallel Port
Configuration
TC358746AXBG/TC358748XBG
7 / 19 2020-12-14
Application
Processor
Or
Baseband
TC358746AXBG
Paralle l Port
To
MIPI
Converter
MIPI Link
Quad Data Lanes
Parallel Port
24-bit data
I
2
C
Mobile
Analog TV
or
Telepresence
or
M obi le Phone
Specialty cams
(RAW, YUV, RGB)
Figure 1.2 System Overview with TC358746AXBG/TC35 8748XBG in Parallel Port t o C SI -2 TX
Configuration
TC358746AXBG/TC358748XBG
8 / 19 2020-12-14
2. Features
Below are the main features supported by TC35874 6AX BG / TC358748X BG .
● CSI-2 TX/ RX Interfac e
MIPI CSI-2 compliant ( Version 1.01 Revision 0.04 – 2 April 2009)
Configurable to TX or RX c ont r ol ler
Supports up to 1Gbps per data lane
Supports up to 4 data lan es
Supports video data formats
- RX: RAW8/10/ 12/14, YUV422 (CCIR/ITU 8/10-b it) , RGB888/666/ 565 and User -Defined 8-bit
- TX: YUV422 (CCIR/ITU 8/10-bit), YUV444, RGB8 88 /666/ 565 and RA W8/10/1 2/14
● Parallel Por t Interface
Supports data formats
- 24-bit bus – un-packed format (Both Input and Output mod e)
RGB888/666/565, RAW8/10/12/14 and YUV422 8-bit (on 8/16-bit data bus) and 10-bit d ata
formats.
YUV444 (Parallel I nput mode only)
- YUV422 8-bit – I TU BT.656 and I TU BT.601 (Par allel input mode o nly)
Up to 100 MHz PCLK freq uency for Output mode, and 166 MHz for Input mode.
● I2C Slave Interface (CS = L)
Support for normal (1 00 kHz), fast mo de ( 400 kHz) and special mode (1 MHz)
Configure all TC358746AXBG/ TC 358748XBG internal registers
● SPI Slave Interface (Only app lic able in CSIOut configuration, M SEL = H, and CS = H)
SPI interface support for up t o 25 M Hz oper at ion.
Configure all TC358746AXBG/ TC 358748XBG internal registers
● GPIO signals
3 GPIO signals
- Three GPIO signals can be con fi gur ed as control si gnals (MCLK, CXRST, XShutdown) for
CSI-2 RX device.
- Or one GPIO signal can b e configured as I NT s ignal for Parallel interface.
● System
Clock and power manag ement supp ort to achieve low pow er states.
● Power supply inputs
Core and MIPI D-PHY: 1.2 V
I/O: 1.8 V – 3.3 V
TC358746AXBG/TC358748XBG
9 / 19 2020-12-14
2.1. Typical P ow e r Cons um pt ion
Parallel_In CSI_Out, 500 MHz CSICLk, 1080P @60fps
VDDIO (3.3 V)
VDD_MI PI (1.2 V)
Total Power
Current (mA)
0.44
24.5
Power (mW)
1.452
29.4
79.33
CSI_In
Parallel_Out, 500 MHz CSICLk, 100 MH z PClk ColorBar @60fps
VDDIO (3.3 V)
VDDC (1.2 V)
VDD_MI PI (1.2 V)
Current (mA)
18.9
13.9
12.3
Power (mW)
62.37
16.68
14.76
TC358746AXBG/TC358748XBG
10 / 19 2020-12-14
3. External Pins
3.1. TC358746AXBG pinout description
TC358746AXBG/TC358748XBG resides in BGA pin packages. The following table gives the signals of
TC358746AXBG/TC358748XBG and their function.
Table 3.1 TC358746AXBG/ TC358748XBG Func tional Signal List
Group Pin Name
I/O
Type Initial
(O)
Function Note
MSEL=0
MSEL=1
System:
Reset &
Clock
(4)
RESX
I
I
Sch
-
System reset input, active low
-
REFCLK
I
I
N
-
Reference clo ck inp ut (6MHz – 40MHz)
-
MSEL I I N -
Mode Select
1'b0: CSI-2 RX in –> Par_out
1'b1: Par_in -> CSI-2 TX
-
CS I I N -
Chip Select, active low
MSEL= 0 (CSI-2 RX in –> Par_out)
- When CS = 0, chip selected
Normal operatio n
- When CS = 1, chip not sele cted
Cannot access to internal registers and
optionally Parallel output ports can be tri-state
when 0x0004[15] is set
MSEL= 1 (Par_in -> CSI-2 TX)
- CS = 0, I2C I/F is selected
- CS = 1, SPI I/F is chosen
-
MIPI-CSI
(10)
MIPI_CP
I
O
PHY
LP11
MIPI-CSI clock positive
-
MIPI_CN
I
O
PHY
LP11
MIPI-CSI clock negative
-
MIPI_D0P I O PHY LP11 MIPI-CSI Data 0 positive -
MIPI_D0N
I
O
PHY
LP11
MIPI-CSI Data 0 negative
-
MIPI_D1P
I
O
PHY
LP11
MIPI-CSI Data 1 positive
-
MIPI_D1N
I
O
PHY
LP11
MIPI-CSI Data 1 negative
-
MIPI_D2P
I
O
PHY
LP11
MIPI-CSI Data 2 positi v e
-
MIPI_D2N
I
O
PHY
LP11
MIPI-CSI Data 2 negative
-
MIPI_D3P
I
O
PHY
LP11
MIPI-CSI Data 3 positi v e
-
MIPI_D3N
I
O
PHY
LP11
MIPI-CSI Data 3 negative
-
I2C I/F
(2)
I2C_SCL
I
I
Sch
-
I2C serial cl o ck or SPI_SCLK
4 mA
I2C_SDA
I
I
Sch
-
I2C serial data or SPI_MOSI
4 mA
Parallel
Port I/F
(27)
PD[23:0] O I N L
Parallel Port Data
- PD[23:12] can configure to be GPIO[15:4]
4 mA
VVALID
O
I
N
H
Parallel port VVALID signal
4 mA
HVALID
O
I
N
L
Parallel port HVALID signal
4 mA
PCLK
O
I
N
L
Parallel Port Clock signal
4 mA
GPIO (3) GPIO[2:0] I I N -
GPIO[2:0] signals
CSI-2 RX in –> Par_out
- (GPIO[0] option to become MCLK signal)
- (GPIO[1] option to become CXRST or INT)
- (GPIO[2] option to become XShutdown)
Par_in -> CSI-2 TX
- (GPIO[0] option to become MCLK signal)
- (GPIO[1] option to become SPI_SS or INT)
- (GPIO[2] option to become SPI_MISO)
4 mA
POWER
(9)
VDDC (1.2 V)
NA
-
-
-
VDD for Internal Core (2)
-
VDDIO (1.8 V –
3.3 V)
NA - - - VDDIO is for IO power supply (3) -
VDD_MIPI
(1.2 V)
NA - - - VDD for the MIPI CSI2 (2) -
Ground
NOTE1
VSS NA - - - Ground -
NOTE1: TC358746AXBG = 17, TC358748XBG = 25
TC358746AXBG/TC358748XBG
11 / 19 2020-12-14
3.2. TC358746AXBG BGA72 pin Count Summary
Table 3.2 TC358746AXBG BGA 72Pin Count Summary
Group Name
Pin
Count
Notes
SYSTEM
4
-
MIPI-CSI
10
-
I2C I/F
2
-
GPIO
3
-
Parallel Por t I/F
27
-
POWER
9
IO, MIPI and Core Power
GROUND
17
-
TOTAL
72
3.3. TC358748XBG BGA80 Pin Count Summa ry
Table 3.3 TC358748XBG BGA 80 Pin Co unt Summary
Group Name
Pin
Count
Notes
SYSTEM
4
-
MIPI-CSI
10
-
I2C I/F
2
-
GPIO
3
-
Parallel Por t I/F
27
-
POWER
9
IO, MIPI and Core Power
GROUND
25
-
TOTAL
80
TC358746AXBG/TC358748XBG
12 / 19 2020-12-14
3.4. TC358746AXBG Pin Layout
Figure 3.1 TC358746A XBG BGA72-Pin Lay out (Top View)
A1
A2
A3
A4
A5
A6
A7
A8
A9
VSS
PD17
PD19
PD21
PD23
GPIO2
I2C_SCL
MSEL
VSS
B1
B2
B3
B4
B5
B6
B7
B8
B9
VDDC
PD16
PD18
PD20
PD22
GPIO1
I2C_SDA
RESX
VDDIO
C1
C2
C3
C4
C5
C6
C7
C8
C9
PD15
PD14
VSS
VSS
VSS
VSS
VDD_MIPI
MIPI_D3P
MIPI_D3N
D1
D2
D3
D7
D8
D9
PD13
PD12
VSS
VSS
MIPI_D2P
MIPI_D2N
E1
E2
E3
E7
E8
E9
VSS
VSS
VDDC
VDD_MIPI
MIPI_CP
MIPI_CN
F1
F2
F3
F7
F8
F9
VSS
VSS
VSS
VSS
MIPI_D1P
MIPI_D1N
G1
G2
G3
G4
G5
G6
G7
G8
G9
PD11
PD10
VDDIO
VSS
VSS
VDDIO
VDDIO
MIPI_D0P
MIPI_D0N
H1
H2
H3
H4
H5
H6
H7
H8
H9
VDDC
PD8
PD6
PD4
PD2
PD0
PCLK
GPIO0
CS
J1
J2
J3
J4
J5
J6
J7
J8
J9
VSS
PD9
PD7
PD5
PD3
PD1
REFCLK
VVALID
HVALID
TC358746AXBG/TC358748XBG
13 / 19 2020-12-14
3.5. TC358748XBG Pin La yout
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
VSS PD17 PD19 PD21 PD23 GPIO2 VDDC I2C_SCL MSEL VSS
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
VDDC PD16 PD18 PD20 PD22 GPIO1 VSS I2C_SDA RESX VDDIO
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
PD15 PD14 MIPI_D3P MIPI_D3N
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
PD13 PD12 VSS VSS VSS VSS MIPI_D2P MIPI_D2N
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
PD11 PD10 VSS VSS VSS VSS VSS VDD_MIPI
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
PD9 PD8 VSS VSS VSS VSS MIPI_CP MIPI_CN
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
PD7 PD6 VSS VSS VSS VSS MIPI_D1P MIPI_D1N
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
VDDIO VSS VSS VDD_MIPI
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
PD4 PD2 PD0 VSS VSS PCLK HVALID CS MIPI_D0P MIPI_D0N
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
PD5 PD3 PD1 VDDC VDDIO REFCLK VVALID GPIO0 VDDIO VSS
Figure 3.2 TC358748XBG 80-Pin Layout (To p View)
TC358746AXBG/TC358748XBG
14 / 19 2020-12-14
4. Package
4.1. TC358746AXBG Package
The packages for TC358746AXBG are described in the figures below.
Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package
Table 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 Mech ani cal Dimension
Dimension
Min
Typ.
Max
Solder bal l pitch
-
0.4 mm
-
Solder bal l hei ght
0.15 mm
0.2 mm
0.25 mm
Package dimension - 4.5 x 4.5 mm2 -
Package height
-
-
1.0 mm
Weight: 32mg (Typ.)
TC358746AXBG/TC358748XBG
15 / 19 2020-12-14
4.2. TC358748XBG Package
The packages for TC358748XBG are described in the figures below.
Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 package
Table 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension
Dimension
Min
Typ.
Max
Solder bal l pitch
-
0.65 mm
-
Solder bal l hei ght
0.20 mm
0.25 mm
0.30 mm
Package dimension - 7.0 × 7.0 mm2 -
Package height
-
-
1.0 mm
Unit: mm
Weight: 68 mg (Typ.)
TC358746AXBG/TC358748XBG
16 / 19 2020-12-14
5. Electrical Characteristics
5.1. Absolute Maximum Ratings
VSS= 0V reference
Parameter
Symbol
Rating
Unit
Supply voltage
(1.8V - Digital IO)
VDDIO -0.3 to +3.9 V
Supply voltage
(1.2V – Digital Core)
VDDC -0.3 to +1.8 V
Supply voltage
(1.2V – MIPI CSI PHY)
VDD_MIPI -0.3 to +1.8 V
Input v oltage
(CSI IO)
VIN_CSI -0.3 to VDD_MIPI+0.3 V
Output voltage
(CSI IO)
VOUT_CSI -0.3 to VDD_MIPI+0.3 V
Input v oltage
(Digital IO)
VIN_IO -0.3 to VDDIO+0.3 V
Output voltage
(Digital IO)
VOUT_IO -0.3 to VDDIO+0.3 V
Junction temperature
Tj
125
oC
Storage temperature
Tstg
-40 to +125
oC
5.2. Opera ti ng Condition
VSS= 0V reference
Parameter
Symbol
Min
Typ.
Max
Unit
Supply voltage (1.8V – Digital IO)
VDDIO
1.65
1.8
1.95
V
Supply voltage (3.3V – Digital IO)
VDDIO
3.0
3.3
3.6
V
Supply voltage (1.2V – Digital Core)
VDDC
1.1
1.2
1.3
V
Supply voltage (1.2V – MIPI CSI
PHY)
VDD_MIPI 1.1 1.2 1.3 V
Operating temperature (ambient
temperature with voltage applied)
Ta -30 +25 +85 oC
Supply Noise Voltage
VSN
-
-
100
mVpp
TC358746AXBG/TC358748XBG
17 / 19 2020-12-14
5.3. DC Electr ical Specification
Parameter
Symbol
Min
Typ.
Max
Unit
Input v oltage, High level
input
Note1
VIH 0. 7 VD DIO - VDDIO V
Input v oltage, Low leve l
input
Note1
VIL 0 - 0.3 VDDIO V
Input v oltage Hi gh leve l
CMOS Schmitt Trigger
Note1
,
Note2
VIHS 0.7 VDDIO - VDDIO V
Input v oltage Low level
CMOS Schmitt Trigger
Note1
,
Note2
VILS 0 - 0.3 VDDIO V
Output voltage High l evel
Note1, Note2
(Condition: IOH = -0.4mA)
VOH 0.8 VDDIO - VDDIO V
Output voltage Low level
Note1, Note2
(Condition: IOL = 2mA)
VOL 0 - 0.2 VDDIO V
Input le ak current, High level
(Normal IO or Pull-up IO)
(Condition: VIN = +VDDIO,
VDDIO = 3.6V)
IILH1 (Note4) -10 - 10 µA
Input le ak current, High level
(Pull-down IO)
(Condition: VIN = +VDDIO,
VDDIO = 3.6V)
IILH2 (Note4) - - 100 µA
Input le ak current, Lo w level
(Normal IO or Pull-down IO)
(Condition: VIN = 0V, VDDIO
= 3.6V)
IILL1 (Note5) -10 - 10 µA
Input le ak current, Lo w level
(Pull-up IO)
(Condition: VIN = 0V, VDDIO
= 3.6V)
IILL2 (Note5) - - 200 µA
Note1: Each power source is operating within recommended operation condition.
Note2: Current output value is specified to each IO buffer individually. Output voltage changes with output
current value.
Note4: Normal pin or Pull-up IO pin applied VDDIO supply voltage to Vin (input voltage)
Note5: Normal pin or Pull-down IO pin applied VSSIO (0V) to Vin (input voltage)
TC358746AXBG/TC358748XBG
18 / 19 2020-12-14
6. Revision History
Table 6.1 Revision History
Revision
Date
Description
0.91
2014-05-29
Newly r eleased
1.11 2015-10-07
1. Remove Fail safe I2 C pad operation
2. Change H Sync/ VSync to HVALID/VVALID
3. Updat e t able 3-1 for I/O init direction and its output value
1.12 2016-04-01
1. Packages’ weight is c ut of f after t he decimal poi nt .
2. TC358746A’s pac kage code :
P-VFBGA72-0505-0.40-001 → P-VFBGA72-0404-0.40A3
3. Replaced TC358746A’s p ackage drawing
1.4
2017-02-07
Corrected c ondition in 2.1.Typical Power Consumpti on.
1.5
2017-02-23
Corrected Typo in Table 4.1.
1.6a 2017-10-11
Changed header, footer and the last page.
Changed cor porate name.
1.85
2020-12-14
Modified Table 3.1 VVALID init ial va lue
TC358746AXBG/TC358748XBG
19 / 19 2020-12-14
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