TC358746AXBG/TC358748XBG CMOS Digital Integrated Circuit Silicon Monolithic TC358746AXBG/TC358748XBG Mobile Peripheral Devices TC358746AXBG Overview The MIPI(R) CSI-2 to Parallel port and Parallel port to CSI-2 (TC358746AXBG/TC358748XBG) is a bridge device that converts MIPI data transfers from devices such as a camera to an application processor over a Parallel port interface. All internal registers can be access through I2C or SPI (in CSI out case only). P-VFBGA72-0404-0.40A3 Weight: 32 mg (Typ.) TC358748XBG Features CSI-2 TX/RX Interface MIPI CSI-2 compliant (Version 1.01 Revision 0.04 - 2 April 2009) Configurable to TX or RX controller Supports up to 1Gbps per data lane Supports up to 4 data lanes Supports video data formats - RX: RAW8/10/12/14, YUV422 (CCIR/ITU 8/10bit), RGB888/666/565 and User-Defined 8-bit - TX: YUV422 (CCIR/ITU 8/10-bit), YUV444, RGB888/666/565 and RAW8/10/12/14 Parallel Port Interface Supports data formats - 24-bit bus - un-packed format (Both Input and Output mode) RGB888/666/565, RAW8/10/12/14 and YUV422 8-bit (on 8/16-bit data bus) and 10-bit data formats. YUV444 (Parallel Input mode only) - YUV422 8-bit - ITU BT.656 and ITU BT.601 (Parallel input mode only) Up to 100 MHz PCLK frequency for Output mode, and 166 MHz for Input mode. P-VFBGA80-0707-0.65-001 Weight: 68 mg (Typ.) GPIO signals 3 GPIO signals - Three GPIO signals can be configured as control signals (MCLK, CXRST, XShutdown) for CSI-2 RX device. - Or one GPIO signal can be configured as INT signal for Parallel interface. System Clock and power management support to achieve low power states. Power supply inputs Core and MIPI D-PHY: 1.2 V I/O: 1.8 V - 3.3 V I2C Slave Interface (CS = L) Support for normal (100 kHz), fast mode (400 kHz) and special mode (1 MHz) Configure all TC358746AXBG/TC358748XBG internal registers SPI Slave Interface (Only applicable in CSIOut configuration, MSEL = H, and CS = H) SPI interface support for up to 25 MHz operation. Configure all TC358746AXBG/TC358748XBG internal registers (c) 2014-2020 Toshiba Electronic Devices & Storage Corporation 1 / 19 2020-12-14 Rev.1.85 TC358746AXBG/TC358748XBG Table of content REFERENCES ..................................................................................................................................................... 5 1. Overview .......................................................................................................................................................... 6 2. Features ........................................................................................................................................................... 8 2.1. Typical Power Consumption...................................................................................................................... 9 3. External Pins .................................................................................................................................................. 10 3.1. TC358746AXBG pinout description ........................................................................................................ 10 3.2. TC358746AXBG BGA72 pin Count Summary ........................................................................................ 11 3.3. TC358748XBG BGA80 Pin Count Summary .......................................................................................... 11 3.4. TC358746AXBG Pin Layout.................................................................................................................... 12 3.5. TC358748XBG Pin Layout ...................................................................................................................... 13 4. Package ......................................................................................................................................................... 14 4.1. TC358746AXBG Package....................................................................................................................... 14 4.2. TC358748XBG Package ......................................................................................................................... 15 5. Electrical Characteristics ................................................................................................................................ 16 5.1. Absolute Maximum Ratings..................................................................................................................... 16 5.2. Operating Condition................................................................................................................................. 16 5.3. DC Electrical Specification ...................................................................................................................... 17 6. Revision History ............................................................................................................................................. 18 RESTRICTIONS ON PRODUCT USE............................................................................................................... 19 Table of Figures Figure 1.1 System Overview with TC358746AXBG/TC358748XBG in CSI-2 RX to Parallel Port Configuration ......................................................................................................................................... 6 Figure 1.2 System Overview with TC358746AXBG/TC358748XBG in Parallel Port to CSI-2 TX Configuration ......................................................................................................................................... 7 Figure 3.1 TC358746AXBG BGA72-Pin Layout (Top View) ................................................................... 12 Figure 3.2 TC358748XBG 80-Pin Layout (Top View).............................................................................. 13 Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package ........................................................... 14 Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 package ........................................................... 15 List of Tables Table 3.1 Table 3.2 Table 3.3 Table 4.1 Table 4.2 Table 6.1 TC358746AXBG/ TC358748XBG Functional Signal List ........................................................ 10 TC358746AXBG BGA 72Pin Count Summary ........................................................................ 11 TC358748XBG BGA 80 Pin Count Summary ......................................................................... 11 TC358746AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension...................................... 14 TC358748XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension ..................................... 15 Revision History ....................................................................................................................... 18 2 / 19 2020-12-14 TC358746AXBG/TC358748XBG MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc. 3 / 19 2020-12-14 TC358746AXBG/TC358748XBG 1 2 3 4 5 6 7 8 9 NOTICE OF DISCLAIMER The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an "AS IS" basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. 10 11 12 13 14 All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. 15 16 17 18 19 20 21 22 23 24 25 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. 26 27 28 29 30 31 32 33 34 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. 35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 36 37 38 39 40 MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary 4 / 19 2020-12-14 TC358746AXBG/TC358748XBG REFERENCES 1. MIPI D-PHY, "MIPI_D-PHY_specification_v01-00-00, May 14, 2009" 2. MIPI CSI-2, "MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01 Revision Nov 2010" 3. I2C bus specification, version 2.1, January 2000, Philips Semiconductor 5 / 19 2020-12-14 TC358746AXBG/TC358748XBG 1. Overview The MIPI CSI-2 to Parallel port and Parallel port to CSI-2 (TC358746AXBG/TC358748XBG) is a bridge device that converts MIPI data transfers from devices such as a camera to an application processor over a Parallel port interface. All internal registers can be access through I2C or SPI (in CSI out case only). There are several system configurations where TC358746AXBG/TC358748XBG are typically be used CSI-2 TX with Parallel Input mode for Analog TV, Tele-presence Type, and Specialty/Older Cameras application. In this mode, TC358746AXBG/TC358748XBG (Parallel to CSI-2 converter) is a bridge device that converts parallel data transfers to an application over a MIPI CSI-2 interface. Toshiba Bridge Chip provides a low power bridge solution to efficiently translate parallel transfers to serial transfers. CSI-2 RX with Parallel output mode for scanner application. In this mode, TC358746AXBG/TC358748XBG (CSI-2 to Parallel converter) is a bridge device that converts serial data transfers from devices such as a camera to an application processor over a parallel interface. Toshiba Bridge Chip provides a low power bridge solution to efficiently translate serial transfers to parallel transfers. I2C TC358746AXBG MIPI Link Quad Data Lanes Camera MIPI To Parallel Port 24-bit data Asic Parallel Port Converter Figure 1.1 System Overview with TC358746AXBG/TC358748XBG in CSI-2 RX to Parallel Port Configuration 6 / 19 2020-12-14 TC358746AXBG/TC358748XBG I2C TC358746AXBG Mobile Analog TV Parallel Port 24-bit data or (RAW, YUV, RGB) Application Processor Or MIPI Baseband Mobile Phone Specialty cams Figure 1.2 MIPI Link Quad Data Lanes To Telepresence or Parallel Port Converter System Overview with TC358746AXBG/TC358748XBG in Parallel Port to CSI-2 TX Configuration 7 / 19 2020-12-14 TC358746AXBG/TC358748XBG 2. Features Below are the main features supported by TC358746AXBG/TC358748XBG. CSI-2 TX/RX Interface MIPI CSI-2 compliant (Version 1.01 Revision 0.04 - 2 April 2009) Configurable to TX or RX controller Supports up to 1Gbps per data lane Supports up to 4 data lanes Supports video data formats - RX: RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565 and User-Defined 8-bit - TX: YUV422 (CCIR/ITU 8/10-bit), YUV444, RGB888/666/565 and RAW8/10/12/14 Parallel Port Interface Supports data formats 24-bit bus - un-packed format (Both Input and Output mode) RGB888/666/565, RAW8/10/12/14 and YUV422 8-bit (on 8/16-bit data bus) and 10-bit data formats. YUV444 (Parallel Input mode only) YUV422 8-bit - ITU BT.656 and ITU BT.601 (Parallel input mode only) Up to 100 MHz PCLK frequency for Output mode, and 166 MHz for Input mode. I2C Slave Interface (CS = L) Support for normal (100 kHz), fast mode (400 kHz) and special mode (1 MHz) Configure all TC358746AXBG/TC358748XBG internal registers SPI Slave Interface (Only applicable in CSIOut configuration, MSEL = H, and CS = H) SPI interface support for up to 25 MHz operation. Configure all TC358746AXBG/TC358748XBG internal registers GPIO signals 3 GPIO signals - Three GPIO signals can be configured as control signals (MCLK, CXRST, XShutdown) for CSI-2 RX device. - Or one GPIO signal can be configured as INT signal for Parallel interface. System Clock and power management support to achieve low power states. Power supply inputs Core and MIPI D-PHY: 1.2 V I/O: 1.8 V - 3.3 V 8 / 19 2020-12-14 TC358746AXBG/TC358748XBG 2.1. Typical Power Consumption Current (mA) Power (mW) Parallel_In CSI_Out, 500 MHz CSICLk, 1080P @60fps VDDIO (3.3 V) VDDC (1.2 V) VDD_MIPI (1.2 V) 0.44 40.4 24.5 1.452 48.48 29.4 Total Power 79.33 CSI_In Parallel_Out, 500 MHz CSICLk, 100 MHz PClk ColorBar @60fps VDDIO (3.3 V) VDDC (1.2 V) VDD_MIPI (1.2 V) Total Power Current (mA) 18.9 13.9 12.3 Power (mW) 62.37 16.68 14.76 93.81 9 / 19 2020-12-14 TC358746AXBG/TC358748XBG 3. External Pins 3.1. TC358746AXBG pinout description TC358746AXBG/TC358748XBG resides in BGA pin packages. The following table gives the signals of TC358746AXBG/TC358748XBG and their function. Table 3.1 TC358746AXBG/ TC358748XBG Functional Signal List I/O Type Initial (O) I Sch - I N - I I N CS I I N MIPI_CP I O MIPI_CN I O MIPI_D0P I MIPI_D0N I MIPI-CSI MIPI_D1P (10) MIPI_D1N MIPI_D2P MIPI_D2N MIPI_D3P MIPI_D3N I2C I/F I2C_SCL (2) I2C_SDA Group Pin Name MSEL=0 MSEL=1 RESX I REFCLK I MSEL Ground NOTE1 System reset input, active low - PHY PHY LP11 MIPI-CSI clock negative - O PHY LP11 MIPI-CSI Data 0 positive - O PHY LP11 MIPI-CSI Data 0 negative - I O PHY LP11 MIPI-CSI Data 1 positive - I I I I I I I O O O O O I I PHY PHY PHY PHY PHY Sch Sch LP11 LP11 LP11 LP11 LP11 - PD[23:0] O I N L VVALID O I N HVALID O I N PCLK O I N GPIO (3) GPIO[2:0] POWER (9) Note Reference clock input (6MHz - 40MHz) Mode Select 1'b0: CSI-2 RX in -> Par_out 1'b1: Par_in -> CSI-2 TX Chip Select, active low MSEL= 0 (CSI-2 RX in -> Par_out) - When CS = 0, chip selected Normal operation - When CS = 1, chip not selected Cannot access to internal registers and optionally Parallel output ports can be tri-state when 0x0004[15] is set MSEL= 1 (Par_in -> CSI-2 TX) - CS = 0, I2C I/F is selected - CS = 1, SPI I/F is chosen LP11 MIPI-CSI clock positive System: Reset & Clock (4) Parallel Port I/F (27) Function - - - 4 mA 4 mA H MIPI-CSI Data 1 negative MIPI-CSI Data 2 positive MIPI-CSI Data 2 negative MIPI-CSI Data 3 positive MIPI-CSI Data 3 negative I2C serial clock or SPI_SCLK I2C serial data or SPI_MOSI Parallel Port Data - PD[23:12] can configure to be GPIO[15:4] Parallel port VVALID signal L Parallel port 4 mA L Parallel Port Clock signal GPIO[2:0] signals CSI-2 RX in -> Par_out HVALID signal 4 mA 4 mA 4 mA - (GPIO[0] option to become MCLK signal) - (GPIO[1] option to become CXRST or INT) - (GPIO[2] option to become XShutdown) Par_in -> CSI-2 TX - (GPIO[0] option to become MCLK signal) - (GPIO[1] option to become SPI_SS or INT) - (GPIO[2] option to become SPI_MISO) I I N - 4 mA VDDC (1.2 V) VDDIO (1.8 V - 3.3 V) VDD_MIPI (1.2 V) NA - - - VDD for Internal Core (2) - NA - - - VDDIO is for IO power supply (3) - NA - - - VDD for the MIPI CSI2 (2) - VSS NA - - - Ground - NOTE1: TC358746AXBG = 17, TC358748XBG = 25 10 / 19 2020-12-14 TC358746AXBG/TC358748XBG 3.2. TC358746AXBG BGA72 pin Count Summary Table 3.2 TC358746AXBG BGA 72Pin Count Summary Group Name SYSTEM MIPI-CSI I2C I/F GPIO Parallel Port I/F POWER GROUND TOTAL Pin Count 4 10 2 3 27 9 17 72 Notes IO, MIPI and Core Power - 3.3. TC358748XBG BGA80 Pin Count Summary Table 3.3 TC358748XBG BGA 80 Pin Count Summary Group Name SYSTEM MIPI-CSI I2C I/F GPIO Parallel Port I/F POWER GROUND TOTAL Pin Count 4 10 2 3 27 9 25 80 Notes IO, MIPI and Core Power - 11 / 19 2020-12-14 TC358746AXBG/TC358748XBG 3.4. TC358746AXBG Pin Layout A1 A2 A3 A4 A5 A6 A7 A8 A9 VSS PD17 PD19 PD21 PD23 GPIO2 I2C_SCL MSEL VSS B1 B2 B3 B4 B5 B6 B7 B8 B9 VDDC PD16 PD18 PD20 PD22 GPIO1 I2C_SDA RESX VDDIO C1 C2 C3 C4 C5 C6 C7 C8 C9 PD15 PD14 VSS VSS VSS VSS D1 D2 D3 D7 PD13 PD12 VSS VSS E1 E2 E3 E7 E8 E9 VSS VSS VDDC VDD_MIPI MIPI_CP MIPI_CN F1 F2 F3 F7 F8 F9 VSS VSS VSS VSS G1 G2 G3 G4 G5 G6 G7 PD11 PD10 VDDIO VSS VSS VDDIO VDDIO H1 H2 H3 H4 H5 H6 H7 H8 H9 VDDC PD8 PD6 PD4 PD2 PD0 PCLK HVALID CS J1 J2 J3 J4 J5 J6 J7 J8 J9 VSS PD9 PD7 PD5 PD3 PD1 REFCLK VVALID GPIO0 Figure 3.1 VDD_MIPI MIPI_D3P MIPI_D3N D8 D9 MIPI_D2P MIPI_D2N MIPI_D1P MIPI_D1N G8 G9 MIPI_D0P MIPI_D0N TC358746AXBG BGA72-Pin Layout (Top View) 12 / 19 2020-12-14 TC358746AXBG/TC358748XBG 3.5. TC358748XBG Pin Layout A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 VSS PD17 PD19 PD21 PD23 GPIO2 VDDC I2C_SCL MSEL VSS B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 VDDC PD16 PD18 PD20 PD22 GPIO1 VSS I2C_SDA RESX VDDIO C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 PD15 PD14 D1 D2 PD13 PD12 E1 E2 PD11 PD10 F1 F2 PD9 PD8 G1 G2 PD7 PD6 MIPI_D3P MIPI_D3N D3 E3 F3 G3 H3 D4 D5 D6 D7 VSS VSS VSS VSS E4 E5 E6 E7 VSS VSS VSS VSS F4 F5 F6 F7 VSS VSS VSS VSS G4 G5 G6 G7 VSS VSS VSS VSS H4 H5 H6 H7 D8 D9 D10 MIPI_D2P MIPI_D2N E8 F8 G8 E9 E10 VSS VDD_MIPI F9 F10 MIPI_CP MIPI_CN G9 G10 MIPI_D1P MIPI_D1N H1 H2 VDDIO VSS J1 J2 J3 J4 J5 J6 J7 J8 PD4 PD2 PD0 VSS VSS PCLK HVALID CS K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 PD5 PD3 PD1 VDDC VDDIO REFCLK VVALID GPIO0 VDDIO VSS Figure 3.2 H8 H9 H10 VSS VDD_MIPI J9 J10 MIPI_D0P MIPI_D0N TC358748XBG 80-Pin Layout (Top View) 13 / 19 2020-12-14 TC358746AXBG/TC358748XBG 4. Package 4.1. TC358746AXBG Package The packages for TC358746AXBG are described in the figures below. Weight: 32mg (Typ.) Figure 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 package Table 4.1 TC358746AXBG P-VFBGA72-0404-0.40A3 Mechanical Dimension Dimension Solder ball pitch Solder ball height Min 0.15 mm Typ. 0.4 mm 0.2 mm Max 0.25 mm Package dimension - 4.5 x 4.5 mm2 - Package height - - 1.0 mm 14 / 19 2020-12-14 TC358746AXBG/TC358748XBG 4.2. TC358748XBG Package The packages for TC358748XBG are described in the figures below. Unit: mm Weight: 68 mg (Typ.) Figure 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 package Table 4.2 TC358748XBG P-VFBGA80-0707-0.65-001 Mechanical Dimension Dimension Solder ball pitch Solder ball height Min 0.20 mm Typ. 0.65 mm 0.25 mm Max 0.30 mm Package dimension - 7.0 x 7.0 mm2 - Package height - - 1.0 mm 15 / 19 2020-12-14 TC358746AXBG/TC358748XBG 5. Electrical Characteristics 5.1. Absolute Maximum Ratings VSS= 0V reference Parameter Supply voltage (1.8V - Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (1.2V - MIPI CSI PHY) Input voltage (CSI IO) Output voltage (CSI IO) Input voltage (Digital IO) Output voltage (Digital IO) Junction temperature Storage temperature Symbol Rating Unit VDDIO -0.3 to +3.9 V VDDC -0.3 to +1.8 V VDD_MIPI -0.3 to +1.8 V VIN_CSI -0.3 to VDD_MIPI+0.3 V VOUT_CSI -0.3 to VDD_MIPI+0.3 V VIN_IO -0.3 to VDDIO+0.3 V VOUT_IO -0.3 to VDDIO+0.3 V Tj Tstg 125 -40 to oC Parameter Supply voltage (1.8V - Digital IO) Supply voltage (3.3V - Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (1.2V - MIPI CSI PHY) Operating temperature (ambient temperature with voltage applied) Supply Noise Voltage Symbol VDDIO VDDIO VDDC Min 1.65 3.0 1.1 Typ. 1.8 3.3 1.2 Max 1.95 3.6 1.3 Unit V V V VDD_MIPI 1.1 1.2 1.3 V Ta -30 +25 +85 oC VSN - - 100 mVpp oC +125 5.2. Operating Condition VSS= 0V reference 16 / 19 2020-12-14 TC358746AXBG/TC358748XBG 5.3. DC Electrical Specification Parameter Input voltage, High level input Note1 Input voltage, Low level input Note1 Input voltage High level CMOS Schmitt Trigger Note1 Note2 , Input voltage Low level CMOS Schmitt Trigger Note1, Note2 Output voltage High level Note1, Note2 (Condition: IOH = -0.4mA) Output voltage Low level Note1, Note2 (Condition: IOL = 2mA) Input leak current, High level (Normal IO or Pull-up IO) (Condition: VIN = +VDDIO, VDDIO = 3.6V) Input leak current, High level (Pull-down IO) (Condition: VIN = +VDDIO, VDDIO = 3.6V) Input leak current, Low level (Normal IO or Pull-down IO) (Condition: VIN = 0V, VDDIO = 3.6V) Input leak current, Low level (Pull-up IO) (Condition: VIN = 0V, VDDIO = 3.6V) Note1: Note2: Note4: Note5: Symbol Min Typ. Max Unit VIH 0.7 VDDIO - VDDIO V VIL 0 - 0.3 VDDIO V VIHS 0.7 VDDIO - VDDIO V VILS 0 - 0.3 VDDIO V VOH 0.8 VDDIO - VDDIO V VOL 0 - 0.2 VDDIO V IILH1 (Note4) -10 - 10 A IILH2 (Note4) - - 100 A IILL1 (Note5) -10 - 10 A IILL2 (Note5) - - 200 A Each power source is operating within recommended operation condition. Current output value is specified to each IO buffer individually. Output voltage changes with output current value. Normal pin or Pull-up IO pin applied VDDIO supply voltage to Vin (input voltage) Normal pin or Pull-down IO pin applied VSSIO (0V) to Vin (input voltage) 17 / 19 2020-12-14 TC358746AXBG/TC358748XBG 6. Revision History Table 6.1 Revision History Revision 0.91 1.11 1.12 1.4 1.5 1.6a 1.85 Date Description 2014-05-29 Newly released 1. Remove Fail safe I2C pad operation 2015-10-07 2. Change HSync/VSync to HVALID/VVALID 3. Update table 3-1 for I/O init direction and its output value 1. Packages' weight is cut off after the decimal point. 2. TC358746A's package code : 2016-04-01 P-VFBGA72-0505-0.40-001 P-VFBGA72-0404-0.40A3 3. Replaced TC358746A's package drawing 2017-02-07 Corrected condition in 2.1.Typical Power Consumption. 2017-02-23 Corrected Typo in Table 4.1. Changed header, footer and the last page. 2017-10-11 Changed corporate name. 2020-12-14 Modified Table 3.1 VVALID initial value 18 / 19 2020-12-14 TC358746AXBG/TC358748XBG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". * TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. * PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative or contact us via our website. * Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. * Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. * The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. https://toshiba.semicon-storage.com/ 19 / 19 2020-12-14