REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
OP470
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Very Low Noise Quad
Operational Amplifier
FEATURES
Very Low-Noise, 5 nV/÷Hz @ 1 kHz Max
Excellent Input Offset Voltage, 0.4 mV Max
Low Offset Voltage Drift, 2 V/C Max
Very High Gain, 1000 V/mV Min
Outstanding CMR, 110 dB Min
Slew Rate, 2 V/s Typ
Gain-Bandwidth Product, 6 MHz Typ
Industry Standard Quad Pinouts
Available in Die Form
GENERAL DESCRIPTION
The OP470 is a high-performance monolithic quad operational
amplifier with exceptionally low voltage noise, 5 nV/÷Hz at
1 kHz max, offering comparable performance to ADI’s industry
standard OP27.
The OP470 features an input offset voltage below 0.4 mV,
excellent for a quad op amp, and an offset drift under 2 mV/∞C,
guaranteed over the full military temperature range. Open loop
gain of the OP470 is over 1,000,000 into a 10 kW load ensuring
excellent gain accuracy and linearity, even in high gain applica-
tions. Input bias current is under 25 nA, which reduces errors
due to signal source resistance. The OP470’s CMR of over 110
dB and PSRR of less than 1.8 mV/V significantly reduce errors
due to ground noise and power supply fluctuations. Power
consumption of the quad OP470 is half that of four OP27s, a
significant advantage for power conscious applications. The
OP470 is unity-gain stable with a gain bandwidth product of
6 MHz and a slew rate of 2 V/ms.
PIN CONNECTIONS
14-Lead Hermetic DIP
(Y-Suffix)
14-Lead Plastic DIP
(P-Suffix)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP470
16-Lead SOIC Package
(S-Suffix)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
NC = NO CONNECT
OUT A OUT D
OP470
–IN A –IN D
+IN A +IN D
V+ V–
+IN B +IN C
–IN B –IN C
OUT B OUT C
NC NC
SIMPLIFIED SCHEMATIC
–
IN +IN
BIAS
V–
V+
The OP470 offers excellent amplifier matching which is impor-
tant for applications such as multiple gain blocks, low noise
instrumentation amplifiers, quad buffers, and low noise active
filters.
The OP470 conforms to the industry standard 14-lead DIP
pinout. It is pin compatible with the LM148/149, HA4741,
HA5104, and RM4156 quad op amps and can be used to up-
grade systems using these devices.
For higher speed applications, the OP471, with a slew rate of 8
V/ms, is recommended.
REV. B
–2–
OP470–SPECIFICATIONS
OP470A/E OP470F OP470G
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
INPUT OFFSET
VOLTAGE V
OS
0.1 0.4 0.2 0.8 0.4 1.0 mV
INPUT OFFSET
CURRENT I
OS
V
CM
= 0 V 3 10 6 20 12 30 nA
INPUT BIAS
CURRENT I
B
V
CM
= 0 V 6 25 15 50 25 60 nA
INPUT NOISE
VOLTAGE e
np-p
0.1 Hz to 10 Hz 80 200 80 200 80 200 nV p-p
(Note 1)
INPUT NOISE f
O
= 10 Hz 3.8 6.5 3.8 6.5 3.8 6.5
Voltage Density e
n
f
O
= 100 Hz 3.3 5.5 3.3 5.5 3.3 5.5 nV÷Hz
f
O
=
1 kHz 3.2 5.0 3.2 5.0 3.2 5.0
(Note 2)
INPUT NOISE f
O
= 10 Hz 1.7 1.7 1.7
Current Density i
n
f
O
= 100 Hz 0.7 0.7 0 7 pA÷Hz
f
O
= 1 kHz 0.4 0.4 0.4
LARGE-SIGNAL V = ±10 V
Voltage Gain A
VO
R
L
= 10 kW1000 2300 800 1700 800 1700 V/mV
R
L
= 2 kW500 1200 400 900 400 900
INPUT VOLTAGE
RANGE IVR (Note 3) ±11 ±12 ±11 ±12 ±11 ±12 V
OUTPUT VOLTAGE
SWING V
O
R
L
≥
2 kW±12 ±13 ±12 ±13 ±12 ±13 V
COMMON-MODE
REJECTION CMR V
CM
= ±11 V 110 125 100 120 100 120 dB
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±4.5 V to ±18 V 0.56 1.8 1.0 5.6 1.0 5.6 mV/V
SLEW RATE SR 1.4 2 1.4 2 1.4 2 V/ms
SUPPLY CURRENT
(All Amplifiers) I
SY
No Load 9 11911911mA
GAIN BANDWIDTH
PRODUCT GBW A
V
= 10 666MHz
CHANNEL
SEPARATION CS V
O
= 20 V p-p 125 155 125 155 125 155 dB
f
O
= 10 Hz (Note 1)
INPUT
CAPACITANCE C
IN
222pF
INPUT RESISTANCE R
IN
0.4 0.4 0.4 MW
Differential-Mode
INPUT RESISTANCE
Common-Mode R
INCM
11 11 11 GW
A
V
= 1
SETTLING TIME t
S
to 0.1% 5.5 5.5 5.5 ms
to 0.01 % 6.0 6.0 6.0
NOTES
1
Guaranteed but not 100% tested
2
Sample tested
3
Guaranteed by CMR test
ELECTRICAL CHARACTERISTICS
(at VS = 15 V, TA = 25C, unless otherwise noted.)
REV. B –3–
OP470
OP470A
Parameter Symbol Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE V
OS
0.14 0.6 mV
AVERAGE INPUT
Offset Voltage Drift TCV
OS
0.4 2 mV/∞C
INPUT OFFSET CURRENT I
OS
V
CM
= 0 V 5 20 nA
INPUT BIAS CURRENT I
B
V
CM
= 0 V 15 20 nA
LARGE-SIGNAL V
O
= ±10 V
Voltage Gain A
VO
R
L
= 10 kW750 1600 V/mV
R
L
= 2 kW400 800
INPUT VOLTAGE RANGE
*
IVR ±11 ±12 V
OUTPUT VOLTAGE SWING V
O
R
L
≥
2 kW±12 ±13 V
COMMON-MODE
REJECTION CMR V
CM
= ±11 V 100 120 dB
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±4.5 V to ±18 V 1.0 5.6 mV/V
SUPPLY CURRENT
(All Amplifiers) I
SY
No Load — 9.2 11 mA
*
Guaranteed by CMR test
(at VS = 15 V, –55C £ TA £ 125C for OP470A, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
OP470E OP470F OP470G
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
INPUT OFFSET
VOLTAGE V
OS
0.12 0.5 0.24 1.0 0.5 1.5 mV
AVERAGE INPUT
Offset Voltage Drift TCV
OS
0.4 2 0.6 4 2 mV/∞C
INPUT OFFSET
CURRENT I
OS
V
CM
= 0 V 4 20 7 40 20 50 nA
INPUT BIAS
CURRENT I
B
V
CM
= 0 V 11 50 2070 4075 nA
LARGE-SIGNAL V
O
= ±10 V
Voltage Gain A
VO
R
L
= 10 kW800 1800 600 1400 600 1500 V/mV
R
L
= 2 kW400 900 300 700 300 800
INPUT VOLTAGE
RANGE
*
IVR ±11 ±12 ±11 ±12 ±11 ±12 V
OUTPUT VOLTAGE
SWING V
O
R
L
≥
2 kW±12 ±13 ±12 ±13 ±12 ±13 V
COMMON-MODE
REJECTION CMR V
CM
= ±11 V 100 120 90 115 90 110 dB
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±4.5 V to ±18 V 0.7 5.6 1.8 10 1.8 10 mV/V
SUPPLY CURRENT
(All Amplifiers) I
SY
No Load — 9.2 11 — 9.2 11 — 9.3 11 mA
*
Guaranteed by CMR test
(at VS = 15 V, –25C £ TA £ 85C for OP470E/OP470EF, –40C £ TA £ 85C for OP470G,
unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
REV. B
–4–
OP470–SPECIFICATIONS
OP470GBC
Parameter Symbol Conditions Limit Unit
INPUT OFFSET VOLTAGE V
OS
0.8 mV Max
INPUT OFFSET CURRENT I
OS
V
CM
= 0 V 20 nA Max
INPUT BIAS CURRENT I
B
V
CM
= 0 V 50 nA Min
LARGE-SIGNAL V
O
= ±10 V
Voltage Gain A
VO
R
L
= 10 kW800 V/mV Min
R
L
= 2 kW400
INPUT VOLTAGE RANGE
*
IVR ±11 V Min
OUTPUT VOLTAGE SWING V
O
R
L
≥
2 kW±12 V Min
COMMON-MODE
REJECTION CMR V
CM
= ±11 V 100 dB
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±4.5 V to ±18 V 5.6 mV/V Max
SUPPLY CURRENT
(All Amplifiers) I
SY
No Load 11 mA Max
NOTE
*
Guaranteed by CMR test
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaran-
teed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(at VS = 15 V, 25C, unless otherwise noted.)
WAFER TEST LIMITS
REV. B
OP470
–5–
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . ±1.0 V
Differential Input Current
2
. . . . . . . . . . . . . . . . . . . . ±25 mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . .Continuous
Storage Temperature Range
P, Y Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
Junction Temperature (T
j
) . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP470A . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP470E, OP470F . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C
OP470G . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
–IN A
OUT A
OUT D
–IN D
+IN AV+
+IN B
–IN B
OUT B
OUT C
–IN C +IN C V– +IN D
DIE SIZE 0.163 0.106 INCH, 17,278 SQ. mm
(4.14 2.69 mm, 11.14 SQ. mm)
Figure 1. Dice Characteristics
Package Type
JA3
JC
Unit
14-Lead Hermetic DIP(Y) 94 10 ∞C/W
14-Lead Plastic DIP(P) 76 33 ∞C/W
16-Lead SOIC (S) 88 23 ∞C/W
NOTES
1
Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
The OP470’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ±1.0 V, the input current should be limited to ±25 mA.
3
JA
is specified for worst case mounting conditions, i.e.,
JA
is specified for device
in socket for TO, CerDIP, PDIP, packages;
JA
is specified for device soldered to
printed circuit board for SOIC packages.
ORDERING GUIDE
Package Options
T
A
= 25∞COperating
V
OS
max Cerdip Temperature
(V) 14-Pin Plastic Range
400 MIL
400 OP470AY*MIL
400 OP470EY IND
800 OP470FY*IND
1000 OP470GP XIND
1000 OP470GS XIND
*Not for new design; obsolete April 2002.
For military processed devices, please refer to the standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number ADI Equivalent
59628856501CA OP470AYMDA
596288565012A OP470ARCMDA
596288565013A
*
OP470ATCMDA
*
Not for new designs; obsolete April 2002.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP470 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
OP470
–6–
–Typical Performance Characteristics
FREQUENCY – Hz
10
1
T
A
= 25C
V
S
= 15V
9
8
7
6
5
4
3
2
1
10 100 1k
VOLTAG E N OISE – nV/ Hz
I/F CORNER = 5Hz
TPC 1. Voltage Noise Density vs.
Frequency
FREQUENCY – Hz
CURRENT NOISE – pA/ Hz
10.0
0.1
10 10k
1.0
100 1k
T
A
= 25C
V
S
= 15V
I/F CORNER = 200Hz
TPC 4. Current Noise Density vs.
Frequency
TEMPERATURE – C
INPUT BIAS CURRENT – nA
–75
20
15
10
5
0–50 –25 0 25 50 75 100 125
VS = 15V
VCM = 0V
TPC 7. Input Bias Current vs.
Temperature
SUPPLY VOLTAGE – V
VOLTAG E N OISE – nV/ Hz
5
4
10520
10 15
3
2
T
A
= 25C
AT 10Hz
AT 1kHz
TPC 2. Voltage Noise Density vs.
Supply Voltage
TEMPERATURE – C
INPUT OFFSET VOLTAGE – V
140
–75
V
S
= 15V
120
100
80
60
40
20
0–50 –25 0 25 50 75 100 125
TPC 5. Input Offset Voltage vs.
Temperature
TEMPERSTURE – C
INPUT OFFSET CURRENT – nA
10
–75 –50 –25 0 25 50 75 100 125
9
8
7
6
5
4
3
2
1
0
V
S
= 15V
V
CM
= 0V
TPC 8. Input Offset Current vs.
Temperature
10
0%
100
90
5mV 1s
0246810
TIME – Secs
NOISE VOLTAGE – 100nV/DIV
TA = 25C
VS = 15V
TPC 3. 0.1 Hz to 10 Hz Noise
TIME – Mins
CHANGE IN OFFSET VOLTAGE – V
10
0
T
A
= 25C
V
S
= 15V
9
8
7
6
5
4
3
2
1
0
12345
TPC 6. Warm-Up Offset Voltage Drift
COMMON-MODE VOLTAGE – V
INPUT BIAS CURRENT – nA
9
–12.5
TA = 25C
VS = 15V
8
7
6
5
4
–7.5 –2.5 2.5 7.5 12.5
TPC 9. Input Bias Current vs.
Common-Mode Voltage
REV. B –7–
OP470
FREQUENCY – Hz
CMR – dB
130
1
T
A
= 25C
V
S
= 15V
120
110
100
90
80
70
60
50
30
40
20
10 10 100 1k 10k 100k 1M
TPC 10. CMR vs. Frequency
FREQUENCY – Hz
PSR – dB
140
1
120
100
80
60
40
20
0
10 100 1k 10k 100k 1M 10M 100M
130
110
90
70
50
30
10
T
A
= 25C
–PSR
+PSR
TPC 13. PSR vs. Frequency
FREQUENCY – MHz
GAIN – dB
25
1
20
15
10
5
0
2345
–5
–10
67 89
10
T
A
= 25C
V
S
= 15V
80
100
120
140
160
180
200
220
PHASE SHIFT – Degrees
PHASE
GAIN
PHASE MARGIN
= 58
TPC 16. Open-Loop Gain, Phase
Shift vs. Frequency
SUPPLY VOLTAGE – V
TOTA L SUPPLY CURRENT – mA
10
8
20520
10 15
6
4
T
A
= +25C
T
A
= +125C
T
A
= –55C
TPC 11. Total Supply Current vs.
Supply Voltage
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
140
1
120
100
80
60
40
20
0
10 100 1k 10k 100k 1M 10M 100M
130
110
90
70
50
30
10
T
A
= 25C
V
S
= 15V
TPC 14. Open-Loop Gain vs. Frequency
SUPPLY VOLTAGE – V
OPEN-LOOP GAIN – V/mV
5000
0
TA = 25C
RL = 10k
4000
3000
2000
1000
0510 15 20 25
TPC 17. Open-Loop Gain vs. Supply
Voltage
TEMPERSTURE – C
TOTA L SUPPLY CURRENT – mA
10
–75 –50 –25 0 25 50 75 100 125
9
8
7
6
5
4
3
2
V
S
= 15V
TPC 12. Total Supply Current vs.
Supply Voltage
FREQUENCY – Hz
CLOSED-LOOP GAIN – dB
80
1k
60
40
20
0
–20
10k 100k 1M 10M
TPC 15. Closed-Loop Gain vs.
Frequency
TEMPERATURE – C
PHASE MARGIN – Degrees
80
–75 –50 –25 0 25 50 75 100 125 150
70
60
50
40
8
6
4
2
0
GAIN-BANDWIDTH PRODUCT – MHz
V
S
= 15V
GBW
TPC 18. Gain-Bandwidth Product,
Phase Margin vs. Temperature
REV. B
OP470
–8–
FREQUENCY – Hz
PEAK-TO-PEAK AMPLITUDE – V
28
1k
24
20
16
12
8
10k 100k 1M 10M
4
0
T
A
= 25C
V
S
= 15V
THD = 1%
TPC 19. Maximum Output Swing vs.
Frequency
FREQUENCY – Hz
OUTPUT IMPEDANCE –
360
100
300
240
180
120
60
0
1k 10k 100k 1M 10M 100M
T
A
= 25C
V
S
= 15V
A
V
= 100
A
V
= 1
TPC 22. Output Impedance vs.
Frequency
FREQUENCY – Hz
DISTORTION – %
1
10
0.1
0.01
0.001
100 1k 10k
T
A
= 25C
V
S
= 15V
V
O
= 10V p-p
R
L
= 2k
A
V
= 1
A
V
= –10
TPC 25. Total Harmonic Distortion
vs. Frequency
LOAD RESISTANCE –
MAXIMUM OUTPUT – V
20
100 1k 10k
18
16
14
12
10
8
6
4
2
0
T
A
= 25C
V
S
= 15V
POSITIVE
SWING
NEGATIVE
SWING
TPC 20. Maximum Output Voltage
vs. Load Resistance
TEMPERATURE – C
SLEW RATE – V/s
4.0
–75
3.5
3.0
2.5
2.0
1.5
1.0
–50 –25 0 25 50 75 100 125
V
S
= 15V
–SR
+SR
TPC 23. Slew Rate vs. Temperature
10
0%
100
90
T
A
= 25C
V
S
= 15V
A
V
= 1
5V 20µs
TPC 26. Large-Signal Transient
Response
CAPACITIVE LOAD – pF
OVERSHOOT – %
100
0
T
A
= 25C
V
S
= 15V
V
IN
= 100mV
A
V
= 1
80
60
40
20
0200 400 600 800 1000
TPC 21. Small-Signal Overshoot vs.
Capacitive Load
FREQUENCY – Hz
CHANNEL SEPARATION – dB
170
10
150
130
110
90
70
50
100 1k 10k 100k 1M 10M
T
A
= 25C
V
S
= 15V
V
O
= 20V p-p TO 10kHz
160
140
120
100
80
60
TPC 24. Channel Separation vs.
Frequency
10
0%
100
90
T
A
= 25C
V
S
= 15V
A
V
= 1
50mV 0.2µs
TPC 27. Small-Signal Transient
Response
REV. B
OP470
–9–
500
5k
V
1
20V p-p
1/4
OP470
50
50k
CHANNEL SEPARATION = 20 LOG V
1
V
2
/1000
V
2
1/4
OP470
Figure 2. Channel Separation Test Circuit
7
6
5
1
2
3
+1V
+18V
4
–18V
11
A
+1V
B
D14
13
12
–1V
C8
9
10
–1V
Figure 3. Burn-In Circuit
APPLICATIONS INFORMATION
Voltage and Current Noise
The OP470 is a very low-noise quad op amp, exhibiting a typi-
cal voltage noise of only 3.2 nV÷Hz @ 1 kHz. The exceptionally
low-noise characteristics of the OP470 are in part achieved by
operating the input transistors at high collector currents since
the voltage noise is inversely proportional to the square root of
the collector current. Current noise, however, is directly propor-
tional to the square root of the collector current. As a result, the
outstanding voltage noise performance of the OP470 is gained
at the expense of current noise performance, which is typical for
low noise amplifiers.
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (e
n
), current
noise (i
n
), and resistor noise (e
t
).
TOTAL NOISE AND SOURCE RESISTANCE
The total noise of an op amp can be calculated by:
EeiR e
nnnS t
=
()
+
()
+
()
222
where:
E
n
= total input referred noise
e
n
= up amp voltage noise
i
n
= op amp current noise
e
t
= source resistance thermal noise
R
S
= source resistance
The total noise is referred to the input and at the output would
be amplified by the circuit gain. Figure 4 shows the relationship
between total noise at 1 kHz and source resistance. For R
S
< 1 kW
the total noise is dominated by the voltage noise of the OP470.
As R
S
rises above 1 kW, total noise increases and is dominated
by resistor noise rather than by voltage or current noise of the
OP470. When R
S
exceeds 20 kW, current noise of the OP470
becomes the major contributor to total noise.
Figure 5 also shows the relationship between total noise and
source resistance, but at 10 Hz. Total noise increases more
quickly than shown in Figure 4 because current noise is inversely
proportional to the square root of frequency. In Figure 5, current
noise of the OP470 dominates the total noise when R
S
> 5 kW.
From Figures 4 and 5 it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP400, with lower current
noise than the OP470, will provide lower total noise.
RS – SOURCE RESISTANCE –
100
1
100 100k
TOTAL NOISE – nV/ Hz
10
10k1k
OP11
OP400
OP471
OP470
RESISTOR
NOISE ONLY
Figure 4. Total Noise vs. Source Resistance (Including
Resistor Noise) at 1 kHz
R
S
– SOURCE RESISTANCE –
100
1
100 100k
TOTAL NOISE – nV/ Hz
10
10k1k
OP11
OP400
OP471
OP470
RESISTOR
NOISE ONLY
Figure 5. Total Noise vs. Source Resistance (Including
Resistor Noise) at 10 Hz
REV. B
OP470
–10–
Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10 Hz range. Once again, at low values of R
S
, the
voltage noise of the OP470 is the major contributor to peak-to-peak
noise with current noise the major contributor as R
S
increases.
The crossover point between the OP470 and the OP400 for
peak-to-peak noise is at R
S
= 17 kW.
The OP471 is a higher speed version of the OP470, with a slew
rate of 8 V/ms. Noise of the OP471 is only slightly higher than
the OP470. Like the OP470, the OP471 is unity-gain stable.
RS – SOURCE RESISTANCE –
1000
10
100 100k
PEAK-TO-PEAK NOISE – nV/ Hz
100
10k1k
OP11
OP400
OP471
OP470
RESISTOR
NOISE ONLY
Figure 6. Peak-To-Peak Noise (0.1 Hz to 10 Hz) vs. Source
Resistance (Includes Resistor Noise)
For reference, typical source resistances of some signal sources
are listed in Table I.
R1
5
R3
1.24k
OP470
DUT
R2
5
R5
909
OP27E
R4
200
C1
2F
R6
600k
R9
306k
OP15E
R8
10k
D1
1N4148
D2
1N4148
C2
0.032F
R10
65.4k
R11
65.4k
C3
0.22FOP15E
C4
0.22F
R13
5.9k
R12
10k
R14
4.99k
C5
1F
eOUT
GAIN = 50,000
VS = 5V
Figure 7. Peak-To-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
Table I.
Device
Source Impedance Comments
Strain gage <500 WTypically used in
low frequency applications.
Magnetic <1500 WLow I
B
very important to reduce
tapehead self-magnetization problems
when direct coupling is used.
OP470 I
B
can be neglected.
Magnetic <1500 WSimilar need for low I
B
in direct
phonograph coupled applications. OP470
cartridges will not introduce any self-
magnetization problem.
Linear variable <1500 WUsed in rugged servo-feedback
differential applications. Bandwidth of
transformer interest is 400 Hz to 5 kHz.
For further information regarding noise calculations, see “Minimization of Noise
in Op Amp Applications,” Application Note AN-15.
NOISE MEASUREMENTS—
PEAK-TO-PEAK VOLTAGE NOISE
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 200 nV peak-to-peak noise speci-
fication of the OP470 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:
1. The device must be warmed up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typi-
cally changes 5 mV due to increasing chip temperature after
power-up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens of nanovolts.
2. For similar reasons, the device must be well-shielded from
air currents. Shielding also minimizes thermocouple effects.
3. Sudden motion in the vicinity of the device can also “feedthrough”
to increase the observed noise.
REV. B
OP470
–11–
4. The test time to measure 0.1 Hz to 10 Hz noise should not ex-
ceed 10 seconds. As shown in the noise-tester frequency-response
curve of Figure 8, the 0.1 Hz corner is defined by only one pole.
The test time of 10 seconds acts as an additional pole to elimi-
nate noise contribution from the frequency band below 0.1 Hz.
5. A noise-voltage-density test is recommended when measuring
noise on a large number of units. A 10 Hz noise voltage-density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1/f corner frequency.
6. Power should be supplied to the test circuit by well bypassed
low noise supplies, e.g. batteries. These will minimize output
noise introduced via the amplifier supply pins.
FREQUENCY – Hz
100
0.01
GAIN – dB
80
60
40
20
0
0.1 1 10 100
Figure 8. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise Test
Circuit Frequency Response
NOISE MEASUREMENT—NOISE VOLTAGE DENSITY
The circuit of Figure 9 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series-connected and is in unity-gain, save
the final amplifier which is in a noninverting gain of 101. Since
the ac noise voltages of each amplifier are uncorrelated, they
add in rms fashion to yield:
e=101 e + e e e
OUT nA nB nC nD
22 2 2
++
Ê
ˈ
¯
The OP470 is a monolithic device with four identical amplifiers.
The noise voltage density of each individual amplifier will match,
giving:
e101 4e = 101 2e
OUT n n
2
=Ê
ˈ
¯
()
NOISE MEASUREMENT—CURRENT NOISE DENSITY
The test circuit shown in Figure 10 can be used to measure
current noise density. The formula relating the voltage output to
current noise density is:
i
G40nV / Hz
R
n
nOUT
S
=
Ê
Ë
Áˆ
¯
˜-
()
22
where:
G = gain of 10000
R
S
= 100 kW source resistance
R2
100k
R3
1.24k
OP470
DUT
R5
8.06k
OP27E
R4
200
en OUT TO
SPECTRUM ANALYZER
R1
5
GAIN = 50,000
VS = 5V
Figure 10. Current Noise Density Test Circuit
R2
10k
1/4
OP470
1/4
OP470
1/4
OP470
1/4
OP470
R1
100
eOUT
TO SPECTRUM ANALYZER
eOUT (nV Hz) = 101(2en)
VS = 15V
Figure 9. Noise Voltage Density Test Circuit
REV. B
OP470
–12–
CAPACITIVE LOAD DRIVING AND POWER
SUPPLY CONSIDERATIONS
The OP470 is unity-gain stable and is capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP470.
In the standard feedback amplifier, the op amp’s output resistance
combines with the load capacitance to form a low pass filter that
adds phase shift in the feedback network and reduces stability.
A simple circuit to eliminate this effect is shown in Figure 11.
The added components, C1 and R3, decouple the amplifier
from the load capacitance and provide additional stability. The
values of C1 and R3 shown in Figure 11 are for a load capaci-
tance of up to 1000 pF when used with the OP470.
R1
100*
*SEE TEXT
R3
50
OP470
C5
0.1F
*
C4
10F
+
V–
V
OUT
C
L
1000pF
C1
1000pF
R2
V
IN
PLACE SUPPLY DECOUPLING
CAPACITORS AT OP470
C3
0.1F
C2
10F
+
V+
Figure 11. Driving Large Capacitive Loads
In applications where the OP470’s inverting or noninverting
inputs are driven by a low source impedance (under 100 W) or
connected to ground, if V+ is applied before V–, or when V is
disconnected, excessive parasitic currents will flow. Most applica-
tions use dual tracking supplies and with the device supply pins
properly bypassed, power-up will not present a problem. A source
resistance of at least 100 W in series with all inputs (Figure 11)
will limit the parasitic currents to a safe level if V– is discon-
nected. It should be noted that any source resistance, even 100 W,
adds noise to the circuit. Where noise is required to be kept at a
minimum, a germanium or Schottky diode can be used to clamp
the V- pin and eliminate the parasitic current flow instead of
using series limiting resistors. For most applications, only one
diode clamp is required per board or system.
UNITY-GAIN BUFFER APPLICATIONS
When Rf £ 100 W and the input is driven with a fast, large
signal pulse(> 1 V), the output waveform will look as shown
in Figure 12.
2V/s
OP470
R1
Figure 12. Pulsed Operation
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With Rf £ 500 W, the output
is capable of handling the current requirements (IL < 20 mA at
10 V); the amplifier will stay in its active mode and a smooth
transition will occur.
When Rf > 3 kW, a pole created by Rf and the amplifier’s input
capacitance (2 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel
with Rf helps eliminate this problem.
APPLICATIONS
Low Noise Amplifier
A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 13. Amplifier noise, depicted in
Figure 14, is around 2 nV/÷Hz @ 1 kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 1000. The 200 W
resistors limit circulating currents and provide an effective out-
put resistance of 50 W. The amplifier is stable with a 10 nF
capacitive load and can supply up to 30 mA of output drive.
R2
50k
1/4
OP470E
+15V
–15V
R3
200
R1
50
V
IN
R5
50k
1/4
OP470E
R6
200
R4
50
R8
50k
1/4
OP470E
R9
200
R7
50
R11
50k
1/4
OP470E
R12
200
R10
50
V
OUT
= 1000V
IN
Figure 13. Low Noise Amplifier
REV. B
OP470
–13–
NOISE DENSITY – 0.58nV/ Hz/DIV
REFERRED TO INPUT
10
0%
100
90
Figure 14. Noise Density of Low Noise Amplifier, G = 1000
DIGITAL PANNING CONTROL
Figure 15 uses a DAC-8408, quad 8-bit DAC to pan a signal
between two channels. The complementary DAC current out-
puts two of the DAC-8408’s four DACs drive current-to-voltage
converters built from a single quad OP470. The amplifiers have
complementary outputs with the amplitudes dependent upon
the digital code applied to the DAC. Figure 16 shows the comple-
mentary outputs for a 1 kHz input signal and digital ramp applied
to the DAC data inputs. Distortion of the digital panning con-
trol is less than 0.01%.
10
0%
100
90
1ms
5V5V
A OUT
A OUT
Figure 16. Digital Panning Control Output
Gain error due to the mismatching between the internal DAC
ladder resistors and the current-to-voltage feedback resistors is
eliminated by using feedback resistors internal to the DAC. Of
the four DACs available in the DAC-8408, only two DACs, A
and C, actually pass a signal. DACs B and D are used to pro-
vide the additional feedback resistors needed in the circuit. If
the VREFB and VREFD inputs remain unconnected, the
current-to-voltage converters using RFBB and RFBD are unaf-
fected by digital data reaching DACs B and D.
1/4
OP470E
+15V
–15V
1/4
OP470E
A OUT
20pF
A OUT
20pF
IOUT1A
DAC A
IOUT1B
DAC B
RFBA
IOUT2A/2B
RFBB
RFBC
1/4
OP470E
B OUT
20pF
DAC C IOUT1C
1/4
OP470E
B OUT
20pF
IOUT1D
DAC D
RFBD
IOUT2C/2D
VREF
A
DAC SELECT
1k
1k
5V
DGND
DS2
DS1
R/W
A/B
VREFC
VDD
DAC-8408GP
SIDE A IN
SIDE B IN
DAC DATA BUS
PINS 9 (LSB) – 16 (MSB)
5V
Figure 15. Digital Panning Control Circuit
REV. B
OP470
–14–
SQUELCH AMPLIFIER
The circuit of Figure 17 is a simple squelch amplifier that uses a
FET switch to cut off the output when the input signal falls
below a preset limit.
The input signal is sampled by a peak detector with a time
constant set by C1 and R6. When the output of the peak detector
(Vp), falls below the threshold voltage, (VTH), set by R8, the
comparator formed by op amp C switches from V– to V+. This
drives the gate of the N-channel FET high, turning it ON, re-
ducing the gain of the inverting amplifier formed by op amp A
to zero.
1/4
OP470E
A
R1
2k
V
OUT
– –5V
IN
R2
10k
2N5434
R5
100k
V
IN
1/4
OP470E
B
R3
2k
R4
10k
D1
1N4148
C1
1F
R6
1M
1/4
OP470E
C
R4
10M
D2
1N4148
R7
10k
+
C2
10F
V+
R6
10k
= 1 SECOND
Figure 17. Squelch Amplifier
FIVE-BAND LOW-NOISE STEREO GRAPHIC EQUALIZER
The graphic equalizer circuit shown in Figure 18 provides 15 dB
of boost or cut over a 5-band range. Signal-to-noise ratio over a
20 kHz bandwidth is better than 100 dB referred to a 3 V rms
input. Larger inductors can be replaced by active inductors but
this reduces the signal-to-noise ratio.
R1
47k
1/4
OP470E
R13
3.3k
+
R14
100
V
OUT
R4
1k
60Hz
R2
3.3k
1/4
OP470E
V
IN
C1
0.47F
C2
6.8F
TANTALUM
L1
1H
R3
680
+
R4
1k
200Hz
C3
1F
TANTALUM
L2
1H
R5
680
+
R4
1k
800Hz
C4
0.22F
TANTALUM
L3
1H
R7
680
+
R4
1k
3kHz
C5
0.047F
TANTALUM
L4
1H
R9
680
+
R4
1k
10kHz
C6
0.022F
TANTALUM
L5
1H
R11
680
Figure 18. Five-Band Low Noise Graphic Equalizer
REV. B
OP470
–15–
OUTLINE DIMENSIONS
14-Lead Ceramic Dip-Glass Hermetic Seal [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
14
17
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
14-Lead Plastic Dual-in-Line Package [PDIP]
(N-14)
Dimensions shown in inches and (millimeters)
14
17
8
0.685 (17.40)
0.665 (16.89)
0.645 (16.38)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
MIN
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095-AB
16-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16 9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
0.32 (0.0126)
0.23 (0.0091)
8
0
0.75 (0.0295)
0.25 (0.0098) 45
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
REV. B
–16–
C00305–0–10/02(B)
PRINTED IN U.S.A.
ADV611/ADV612
Revision History
Location Page
10/02—Data Sheet changed from REV. A to REV. B.
Edits to 16-Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4/02—Data Sheet changed from REV. 0 to REV. A.
28-Lead LCC (RC-Suffix) deleted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
28-Lead LCC (TC-Suffix) deleted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
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