P1015NSN5DFB - NXP SEMICONDUCTORS

QorIQ P1015 and P1024

communications processors

Overview

Freescale QorIQ communications platforms are

the next-generation evolution of our leading

PowerQUICC communications processors.

Built using high-performance Power

Architecture® cores, QorIQ platforms enable

a new era of networking innovation where the

reliability, security and quality of service for

every connection matters.

QorIQ P1015 and P1024

Communications Processors

The QorIQ P1 family, which includes the P1015

and P1024 communications processors, offers

the value of smart integration and efficient

power for a wide variety of applications in the

networking, telecom, defense and industrial

markets. Based on 45 nm technology for low

power, the P1015 and P1024 processors

provide single- and dual-core options from

400 MHz to 667 MHz, together with advanced

security and a rich set of interfaces.

The P1015 and P1024 processors are

perfectly suited for multi-service gateways,

Ethernet switch controllers, wireless LAN

access points and high-performance general-

purpose control processor applications with

tight thermal constraints.

The P1015 and P1024 processors are pin-

compatible with the QorIQ P1016, P1025

products, and software compatible with the

P1011/P1020 and P2010/P2020 offering a six-

chip range of cost-effective solutions. Scaling

from a single core at 400 MHz (P1015) to a

dual core at 1.2 GHz per core (P2020),

the two QorIQ platforms deliver an impressive

4.5x aggregate frequency range.

The P1015 and P1024 platforms both feature

the e500 Power Architecture core and

peripherals, and are fully software compatible

with the existing PowerQUICC processors. This

enables you to create a product with multiple

performance points with a common software

architecture. The P1024 dual-core processor

supports both symmetric and asymmetric

processing, enabling you to further optimize

your design with the same applications running

on each core or serialize your application using

the cores for different processing tasks.

QorIQ P1015 and P1024 Block Diagram

32 KB

L1 I Cache

Power Architecture®

e500 Core

32 KB

L1 D Cache

256 KB

L2 Cache 32 KB

L1 I Cache

Power Architecture

e500 Core

32 KB

L1 D Cache

DDR3 SDRAM

Controller

Not on P1015

Coherency Module

System Bus

4-ch. DMA Controller4-ch. DMA Controller2x PCI Express®

On-Chip NetworkOn-Chip Network

4-lane SerDes

Security

Acceleration

XOR DUART, 2x I2C, Timers,

Interrupt Control,

SD/MMC, SPI,

2x USB 2.0/ULPI

Gigabit

Ethernet

Enhanced Local Bus

Controller (eLBC)

TDM

Accelerators and Memory Control Networking Elements

Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Basic Peripherals and Interconnect

QorIQ P1015 and P1024 Block Diagram

P Series

QorIQ Communications Platforms

Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective

owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks

Document Number: QP1024FS REV 2

For more information, please visit freescale.com/QorIQ

The P1015 and P1024 processors have an

advanced set of features for ease of use.

The 256 KB L2 cache offers incremental

configuration to partition the cache between

the two cores or to configure it as SRAM or

stashing memory. The integrated security

engine supports the cryptographic algorithms

commonly used in IPsec, SSL, 3GPP and

other networking and wireless security

protocols. The memory controller offers future-

proofing against memory technology migration

with support for DDR3. It also supports error

correction codes, a baseline requirement for

any high-reliability system.

The P1015 and P1024 processors integrate a

rich set of interfaces, including a multi-protocol

SerDes, Gigabit Ethernet, PCI Express® and

USB. The three 10/100/1000 Ethernet ports

support advanced packet parsing, flow control

and quality of service features, as well as IEEE®

1588 time-stamping—all ideal for managing

the data path traffic between the LAN and

WAN interface. A TDM interface can support

voice for legacy phone applications. Four

SerDes lanes can be portioned across two PCI

Express ports and two SGMII ports. The PCI

Express ports can provide connectivity to IEEE

802.11n radio cards for wireless support. USB

or SD/MMC interfaces can be used to support

local storage. A second USB interface is also

available to support USB attached printers or

as a console port. Multiple memory connection

ports are available, including the 16-bit local

bus, two USB 2.0 controllers, eSDHC and SPI.

Target Applications

The P1015 and P1024 processors serve in

a wide variety of applications. The devices

are well-suited for various combinations of

data plane and control plane workloads in

networking and telecom applications. With an

available junction temperature range of –40º C

to +125º C, the devices can be used in power-

sensitive defense and industrial applications,

and outdoor environments less protected

from the environment. The devices’ primary

target applications are networking and

telecom linecards.

A multi-service router or business gateway

requires a combination of high performance

and a rich set of peripherals to support

the data path throughputs and required

system functionality. The P1015 and P1024

devices offer a scalable platform to develop

a range of products that can support the

same feature set. Integrated 10/100/1000

Ethernet controllers with classification and

QoS capabilities are ideal for managing the

data path traffic between the LAN and WAN

interface. PCI Express ports can provide

connectivity to IEEE 802.11n radio cards

for wireless support, TDM for legacy phone

interfaces to support voice, the USB or SD/

MMC interfaces can be used to support local

storage, the second USB interface is also

available to support USB attached printers

or as a console port. And the integrated

security engine can provide encrypted secure

communications for remote users with

VPN support.

Technical Specifications

• Dual (P1024) or single (P1015) high-

performance Power Architecture

e500 cores

• 36-bit physical addressing

• Double-precision floating-point support

• 32 KB L1 instruction cache and 32 KB L1

data cache for each core

• 400 MHz to 667 MHz core clock frequency

• 256 KB L2 cache with ECC, also

configurable as SRAM and

stashing memory

• Three 10/100/1000 Mb/s enhanced three-

speed Ethernet controllers (eTSECs)

• TCP/IP acceleration and

classification capabilities

• IEEE 1588 support

• Lossless flow control

• RGMII, SGMII

• High-speed interfaces (not all

available simultaneously)

• Four SerDes to 3.125 GHz multiplexed

across controllers

• Two PCI Express controllers

• Two SGMII interfaces

• Two high-speed USB controllers (USB 2.0)

• Host and device support

• Enhanced host controller interface (EHCI)

• ULPI interface to PHY

• Enhanced secure digital host

controller (eSDHC)

• Serial peripheral interface

• Integrated security engine (SEC 3.3)

• Crypto algorithm support includes 3DES,

AES, RSA/ECC, MD5/SHA, ARC4, Snow

3G, and FIPS deterministic RNG

• Single pass encryption/message

authentication for common security

protocols (IPsec, SSL, SRTP, WiMAX)

• XOR acceleration

• 32-bit DDR3 SDRAM memory controller

with ECC support

• Programmable interrupt controller (PIC)

compliant with OpenPIC standard

• Four-channel DMA controller

• Two I2C controllers, DUART, timers

• Enhanced local bus controller (eLBC)

• 16 general-purpose I/O signals

• Package: 561-pin wirebond power-BGA

(TEPBGA1)