LM5035AMHX-1/NOPB - TEXAS INSTRUMENTS

1.35V DDR3L-RS SDRAM

MT41K256M8 – 32 Meg x 8 x 8 banks

MT41K128M16 – 16 Meg x 16 x 8 banks

Description

DDR3L-RS SDRAM (1.35V) is a low current self refresh

version, via a TCSR feature, of the DDR3L SDRAM

(1.35V) device. Unless stated otherwise, the DDR3L-

RS SDRAM meets the functional and timing specifica-

tions listed in the equivalent density standard or auto-

motive DDR3L SDRAM data sheets located on

www.micron.com.

Features

• VDD = VDDQ = 1.35V (1.283–1.45V)

• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Write leveling

• Output driver calibration

• Multipurpose register

• TC of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C

– 32ms at +85°C to +95°C; See (SRT)

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Temperature-compensated self refresh (TCSR)

mode

• Very low current self refresh mode when at room

temperature

Options Marking

• Configuration

– 256 Meg x 8 256M8

– 128 Meg x 16 128M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 10.5mm) Rev. M, K DA

• FBGA package (Pb-free) – x16

– 96-ball FBGA (8mm x 14mm) Rev. K JT

• Timing – cycle time

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.5ns @ CL = 9 (DDR3-1333) -15E

– 1.875ns @ CL = 7 (DDR3-1066) -187E

• Temperature

– Commercial (0°C ≤ TC ≤ +95°C) None

• Power Saving

– TCSR M

• Revision :M /:K

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-1251, 2 1600 11-11-11 13.75 13.75 13.75

-15E11333 9-9-9 13.5 13.5 13.5

2Gb: x8, x16 DDR3L-RS SDRAM

Description

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 1: Key Timing Parameters (Continued)

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

2Gb: x8, x16 DDR3L-RS SDRAM

Description

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 2: Addressing

Parameter 256 Meg x 8 128 Meg x 16

Configuration 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks

Refresh count 8K 8K

Row address 32K A[14:0] 16K A[13:0]

Bank address 8 BA[2:0] 8 BA[2:0]

Column address 1K A[9:0] 1K A[9:0]

Figure 1: DDR3L-RS Part Numbers

Package

78-ball 8mm x 10.5mm FBGA DA

Example Part Number: MT41K256M8JE-15M:M

96-ball 8mm x 14mm FBGA JT

Configuration

256 Meg x 8

128 Meg x 16

256M8

128M16

Speed Grade

tCK = 1.25ns, CL = 11

tCK = 1.5ns, CL = 9

tCK = 1.87ns, CL = 7

-125

-15E

-187E

Configuration

MT41K

Package

Speed PS

Revision

:M/:K

Temperature

Commercial

{

None

Power Saving

TCSR M

Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

2Gb: x8, x16 DDR3L-RS SDRAM

Description

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

2Gb: x8, x16 DDR3L-RS SDRAM

Important Notes and Warnings

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.

Ball Assignments and Descriptions

Figure 2: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)

1 2 3 4 6 7 8 95

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF, DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

VDD

NF, DQ7

CK#

A10/AP

A12/BC#

A11

A14

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VSSQ

DQ3

VSS

NF, DQ5

VSS

VDD

VREFCA

BA1

Notes: 1. Ball descriptions listed in Table 3 (page 7) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

2Gb: x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 3: 96-Ball FBGA – x16 Ball Assignments (Top View)

1 2 3 4 6 7 8 95

VDDQ

VSSQ

VDDQ

VSSQ

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

DQ13

VDD

DQ11

VDDQ

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ15

VSS

DQ9

UDM

DQ0

LDQS

LDQS#

DQ4

RAS#

CAS#

WE#

BA2

A13

DQ12

UDQS#

UDQS

DQ8

LDM

DQ1

VDD

DQ7

CK#

A10/AP

A12/BC#

A11

VDDQ

DQ14

DQ10

VSSQ

DQ3

VSS

DQ5

VSS

VDD

VREFCA

BA1

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

Notes: 1. Ball descriptions listed in Table 4 (page 9) are listed as “x16.”

2. A comma separates the configuration; a slash defines a selectable function.

2Gb: x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[14:13],

A12/BC#, A11,

A10/AP,

A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled

in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-

mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,

LOW = BC4 burst chop). See Truth Table - Command.

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to

VREFCA.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-

put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-

cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-

ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-

vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active

power-down (row active in any bank). CKE is synchronous for power-down entry and exit

and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-

ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-

cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to

VREFCA.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-

nal rank selection on systems with multiple ranks. CS# is considered part of the command

code. CS# is referenced to VREFCA.

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with the input data during a write access. Although the DM

ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM

is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-

mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the

x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the

LOAD MODE command. ODT is referenced to VREFCA.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered and are referenced to VREFCA.

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver

is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤

0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-

enced to VREFDQ.

2Gb: x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are refer-

enced to VREFDQ.

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write da-

ta. Center-aligned to write data.

TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,

DM is disabled, and the TDQS and TDQS# balls provide termination resistance.

VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.

VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible with 1.5V operation.

VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained

at all times (including self refresh) for proper device operation.

VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self re-

fresh) for proper device operation.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to an external

240Ω resistor (RZQ), which is tied to VSSQ.

NC – No connect: These balls should be left unconnected (the ball has no connection to the

DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured as a

x8 device, these balls are defined as TDQS#, DQ[7:4].

2Gb: x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

PDF: CCMTD-1725822587-8724

2Gb_1_35V_DDR3L-RS.pdf - Rev. G 9/18 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A13, A12/BC#,

A11, A10/AP,