a Preliminary Technical Data SHARC(R) Processor Data Sheet Addendum ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory--2M bit of on-chip SRAM and 6M bit of onchip mask programmable ROM 400 MHz maximum core clock frequency 1.3 V core VDD/3.3 V I/O Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocentric peripherals such as the digital audio interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 11. At 400 MHz (2.5 ns) core instruction rate, the processors perform 2.4 GFLOPS/800 MMACS Transfers between memory and core at a sustained 6.4G bytes/s bandwidth at 400 MHz core instruction rate GENERAL DESCRIPTION This data sheet addendum introduces the 400 MHz ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors. This addendum provides the frequency benchmark, as well as ac and dc specifications that differ from the 333 MHz ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors. All other specifications and timing data as well as package information for these devices can be found in the ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet, Rev A. The products listed in the addendum are engineering grade and have not been fully characterized. For complete ordering information, see the Ordering Guide on Page 11. SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum TABLE OF CONTENTS Preliminary Technical Data Table 1 shows performance benchmarks for these devices. Summary ................................................................1 General Description ..................................................1 Specifications ...........................................................3 Operating Conditions .............................................3 Electrical Characteristics ..........................................3 Timing Specifications .............................................4 Output Drive Currents .......................................... 10 Capacitive Loading ............................................... 10 Ordering Guide ...................................................... 11 Table 1. Processor Benchmarks (at 400 MHz) Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3x3] x [3x1] [4x4] x [4x1] Divide (y/x) Inverse Square Root PERFORMANCE BENCHMARKS The processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21367/ADSP21368/ADSP-21369 processors achieve an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computational hardware, the processors can perform 2.4 GFLOPS running at 400 MHz. Rev. PrA | 1 Speed (at 400 MHz) 23.2 s 1.25 ns 5.0 ns 11.25 ns 20.0 ns 8.75 ns 13.5 ns Assumes two files in multichannel SIMD mode. POWER SUPPLIES The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 400 MHz device. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Page 2 of 12 | March 2007 Preliminary Technical Data ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum SPECIFICATIONS OPERATING CONDITIONS Parameter1 Description Min Max Unit VDDINT AVDD VDDEXT VIH2 VIL2 VIH_CLKIN3 VIL_CLKIN3 TJ Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min Junction Temperature, 256-Ball SBGA @ TAMBIENT 0C to +70C 1.25 1.25 3.13 2.0 -0.5 1.74 -0.5 0 1.35 1.35 3.47 VDDEXT + 0.5 +0.8 VDDEXT + 0.5 +1.1 +105 V V V V V V V C 1 Specifications subject to change without notice. Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST. 3 Applies to input pin CLKIN. 2 ELECTRICAL CHARACTERISTICS Parameter1 Description Test Conditions VOH2 High Level Output Voltage @ VDDEXT = min, IOH = -1.0 mA3 2 VOL Typ Max 2.4 Unit V 3 Low Level Output Voltage @ VDDEXT = min, IOL = 1.0 mA 0.4 V 4, 5 High Level Input Current @ VDDEXT = max, VIN = VDDEXT max 10 A 4, 6, 7 IIH IIL Min Low Level Input Current @ VDDEXT = max, VIN = 0 V 10 A 6 High Level Input Current Pull-down @ VDDEXT = max, VIN = 0 V 250 A 5 Low Level Input Current Pull-up @ VDDEXT = max, VIN = 0 V 200 A 8, 9 Three-State Leakage Current @ VDDEXT = max, VIN = VDDEXT max 10 A 8, 10 Three-State Leakage Current @ VDDEXT = max, VIN = 0 V 10 A Three-State Leakage Current Pull-up @ VDDEXT = max, VIN = 0 V 200 A Supply Current (Internal) tCCLK = 2.5 ns, VDDINT = 1.3 V, 25C Supply Current (Analog) AVDD = max 10 mA Input Capacitance fIN = 1 MHz, TCASE = 25C, VIN = 1.3 V 4.7 pF IIHPD IILPU IOZH IOZL IOZLPU 9 11 IDD-INTYP 12 AIDD 13, 14 CIN 1 1.4 A Specifications subject to change without notice. Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO, CLKOUT. 3 See Output Drive Currents on Page 10 for typical drive current capabilities. 4 Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK. 5 Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST. 6 Applies to input pins with internal pull-downs: IDx. 7 Applies to input pins with internal pull-ups disabled: ACK, RPBA. 8 Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO. 9 Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 10 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 11 See Engineer-to-Engineer Note 299 for further information. 12 Characterized, but not tested. 13 Applies to all signal pins. 14 Guaranteed, but not tested. 2 Rev. PrA | Page 3 of 12 | March 2007 ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum TIMING SPECIFICATIONS The processor's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor's internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The processor's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor's internal clock. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. Rev. PrA | Preliminary Technical Data Page 4 of 12 | March 2007 Preliminary Technical Data ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum Power-Up Sequencing The timing requirements for processor startup are given in Table 2. Table 2. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD1 tCLKRST tPLLRST Switching Characteristic tCORERST Min RESET Low Before VDDINT/VDDEXT On VDDINT On Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted 0 -50 0 102 20 Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 3, 4 1 Max +200 +200 Unit ns ms ms s s Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.3 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins. 4 The 4096 cycle count depends on tsrst specification. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1-0 tPLLRST RESETOUT Figure 1. Power-Up Sequencing Rev. PrA | Page 5 of 12 | March 2007 tCORERST ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum Clock Input Preliminary Technical Data Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 3 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. Table 3. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 3 tCCLK CCLK Period tCKJ4, 5 CLKIN Jitter Tolerance 400 MHz Min Max Unit 181 81 81 1002 452 452 3 ns ns ns ns 2.51 -250 10 +250 ns ps ADSP-2136x 1 Applies only for CLK_CFG1-0 = 00 and default values for PLL control bits in PMCTL. 2 Applies only for CLK_CFG1-0 = 10 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 4 Actual input jitter should be combined with ac specifications for accurate timing analysis. 5 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. CLKIN R1 1M (TYPICAL) XTAL R2 47 (TYPICAL) C1 22pF Y1 C2 22pF 24.576MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER'S SPECIFICATIONS tCK CLKIN tCKH Figure 3. 400 MHz Operation (Fundamental Mode Crystal) tCKL Figure 2. Clock Input Rev. PrA | Page 6 of 12 | March 2007 Preliminary Technical Data ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum SDRAM Interface Timing (133 MHz SDCLK) The 133 MHz access speed is for a single processor. When multiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. Table 4. SDRAM Interface Timing1 Parameter Timing Requirements DATA Setup Before SDCLK tSSDAT tHSDAT DATA Hold After SDCLK Switching Characteristics tSDCLK SDCLK Period tSDCLKH SDCLK Width High tSDCLKL SDCLK Width Low Command, ADDR, Data Delay After SDCLK2 tDCAD tHCAD Command, ADDR, Data Hold After SDCLK2 tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK Min Max 0.78 1.23 ns ns 7.5 3.65 3.65 ns ns ns ns ns ns ns 4.8 1.2 5.3 1.2 1 For FCCLK = 400 MHz (SDCLK ratio = 1:2.5). 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. tSDCLK tSDCLKH SDCLK tSSDAT tSDCLKL tHSDAT DATA (IN) tDCAD tENSDAT tDCAD CMND ADDR (OUT) tHCAD Figure 4. SDRAM Interface Timing Rev. PrA | tDSDAT tHCAD DATA(OUT) Page 7 of 12 | March 2007 Unit ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum Preliminary Technical Data SDRAM Interface Enable/Disable Timing (133 MHz SDCLK) Table 5. SDRAM Interface Enable/Disable Timing1 Parameter Switching Characteristics tDSDC Command Disable After CLKIN Rise tENSDC Command Enable After CLKIN Rise tDSDCC SDCLK Disable After CLKIN Rise tENSDCC SDCLK Enable After CLKIN Rise tDSDCA Address Disable After CLKIN Rise tENSDCA Address Enable After CLKIN Rise 1 Min Max Unit 2 x tPCLK + 1 ns ns ns ns ns ns 4.0 8.5 3.8 9.2 4 x tPCLK 2 x tPCLK - 4 For FCCLK = 400 MHz (SDCLK ratio = 1:2.5). tDSDC tDSDCC tDSDCA CLKIN COMMAND SDCLK ADDR tENSDC tENSDCC tENSDCA COMMAND SDCLK ADDR Figure 5. SDRAM Interface Enable/Disable Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 6. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min Max Unit 1.5 12 ns DAI_Pn DPI_Pn DAI_pm DPI_Pm tDPIO Figure 6. DAI Pin to Pin Direct Routing Rev. PrA | Page 8 of 12 | March 2007 Preliminary Technical Data ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum Memory Read - Bus Master to Memory Read Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 7. Memory Read--Bus Master Parameter Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2 tDRLD RD Low to Data Valid1 tSDS Data Setup to RD High tHDRH Data Hold from RD High3, 4 tDAAK ACK Delay from Address, Selects2, 5 tDSAK ACK Delay from RD Low4 Min Max Unit W+tSDCLK -5.12 W- 2.9 tSDCLK -9.5+ W ns ns ns ns ns W - 7.0 ns 2.2 0 Switching Characteristics tDRHA Address Selects Hold After RD High RH + 0.18 tDARL Address Selects to RD Low2 tSDCLK -3.3 tRW RD Pulse Width W - 1.2 tRWR RD High to WR, RD Low HI +tSDCLK - 0.8 W = (number of wait states specified in AMICTLx register) x tSDCLK. HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) x tSDCLK IC = (number of idle cycles specified in AMICTLx register) x tSDCLK. H = (number of hold cycles specified in AMICTLx register) x tSDCLK. ns ns ns ns 1 Data delay/setup: system must meet tDAD, tDRLD, or tSDS. The falling edge of MSx is referenced. 3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. 4 Data hold: User must meet tHDA or tHDRH in asynchronous access mode. 5 ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK. 2 ADDRESS MSx RD tDRHA tDARL tRW tDRLD tDAD tSDS tHDRH DATA tDSAK tDAAK tRWR ACK WR Figure 7. Memory Read--Bus Master Rev. PrA | Page 9 of 12 | March 2007 ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum Preliminary Technical Data OUTPUT DRIVE CURRENTS RISE AND FALL TIME ns (10% to 90%) 10 CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C 9 8 7 D B T 6 5 4 3 10 RISE AND FALL TIME ns (10% to 90%) Figure 8 shows typical I-V characteristics for the output drivers of the ADSP-21367/ADSP-21368/ADSP-21369. The curves represent the current drive capability of the output drivers as a function of output voltage. CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C 9 8 7 D B T 6 5 4 3 2 1 0 0 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 10. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) 2 1 0 50 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 8. Typical Drive at Junction temperature CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads: 30 pF on all pins. Figure 11 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 9, Figure 10, and Figure 11 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. RISE AND FALL TIME ns (10% to 90%) 10 CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C 9 8 7 D B T 6 5 4 3 2 1 0 RISE AND FALL TIME ns (10% to 90%) 10 0 CLKOUT (CLKOUT DRIVER), VDDEXT (MAX) = 3.65V, TEMPERATURE = 85C 9 100 150 LOAD CAPACITANCE (pF) 200 Figure 11. Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) 8 7 D B T 6 5 4 3 2 1 0 50 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 9. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) Rev. PrA | Page 10 of 12 | March 2007 250 Preliminary Technical Data ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum ORDERING GUIDE ROM Operating Voltage Package Internal/External Description Package Option 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 400 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 400 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 0C to +70C 400 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 ADSP-21369KBP-3A 0C to +70C 400 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 ADSP-21369KBPZ-3A2 0C to +70C 400 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256 Part Number ADSP-21367KBP-3A1 ADSP-21367KBPZ-3A 2 ADSP-21368KBP-3A ADSP-21368KBPZ-3A 2 Temperature Range Instruction On-Chip Rate SRAM 0C to +70C 400 MHz 0C to +70C 0C to +70C 1 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. 2 Z = RoHS Compliant Part. Rev. PrA | Page 11 of 12 | March 2007 ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06770-0-4/07(PrA) Rev. PrA | Page 12 of 12 | March 2007 Preliminary Technical Data