80186/80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS Y Integrated Feature Set Enhanced 8086-2 CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-bit Timers Programmable Memory and Peripheral Chip-Select Logic Programmable Wait State Generator Local Bus Controller Y Available in 10 MHz and 8 MHz Versions Y High-Performance Processor 4 Mbyte/Sec Bus Bandwidth Interface @ 8 MHz (80186) 5 Mbyte/Sec Bus Bandwidth Interface @ 10 MHz (80186) Y Direct Addressing Capability to 1 Mbyte of Memory and 64 Kbyte I/O Y Completely Object Code Compatible with All Existing 8086, 8088 Software 10 New Instruction Types Y Numerics Coprocessing Capability Through 8087 Interface Y Available in 68 Pin: Plastic Leaded Chip Carrier (PLCC) Ceramic Pin Grid Array (PGA) Ceramic Leadless Chip Carrier (LCC) Y Available in EXPRESS Standard Temperature with Burn-In Extended Temperature Range ( b 40 C to a 85 C) 272430 - 1 Figure 1. Block Diagram *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. November 1994 COPYRIGHT (c) INTEL CORPORATION, 1995 Order Number: 272430-002 1 80186/80188 High-Integration 16-Bit Microprocessors CONTENTS PAGE FUNCTIONAL DESCRIPTION AAAAAAAAAAAAA 9 Introduction AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 9 CLOCK GENERATOR AAAAAAAAAAAAAAAAAAAAA 9 Oscillator AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 9 Clock Generator AAAAAAAAAAAAAAAAAAAAAAAAAAA 9 READY Synchronization AAAAAAAAAAAAAAAAAAAA 9 RESET Logic AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 9 LOCAL BUS CONTROLLER AAAAAAAAAAAAAAA 9 Memory/Peripheral Control AAAAAAAAAAAAAAA 10 Local Bus Arbitration AAAAAAAAAAAAAAAAAAAAAA 10 Local Bus Controller and Reset AAAAAAAAAAAA 10 PERIPHERAL ARCHITECTURE AAAAAAAAAA 10 Chip-Select/Ready Generation Logic AAAAAA 10 DMA Channels AAAAAAAAAAAAAAAAAAAAAAAAAAAA 11 Timers AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 11 Interrupt Controller AAAAAAAAAAAAAAAAAAAAAAAA 12 CONTENTS PAGE ABSOLUTE MAXIMUM RATINGS AAAAAAAA 15 D.C. CHARACTERISTICS AAAAAAAAAAAAAAAA 15 A.C. CHARACTERISTICS AAAAAAAAAAAAAAAA 16 EXPLANATION OF THE AC SYMBOLS AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 18 WAVEFORMS AAAAAAAAAAAAAAAAAAAAAAAAAAAA 19 EXPRESS AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 25 EXECUTION TIMINGS AAAAAAAAAAAAAAAAAAA 26 INSTRUCTION SET SUMMARY AAAAAAAAAA 27 FOOTNOTES AAAAAAAAAAAAAAAAAAAAAAAAAAAAA 32 REVISION HISTORY AAAAAAAAAAAAAAAAAAAAA 33 2 2 80186/80188 Contacts Facing Down Contacts Facing Up 272430 - 2 Figure 2. Ceramic Leadless Chip Carrier (JEDEC Type A) Pins Facing Up Pins Facing Down 272430 - 3 Figure 3. Ceramic Pin Grid Array NOTE: Pin names in parentheses apply to the 80188. 3 3 80186/80188 Leads Facing Up Leads Facing Down 272430 - 4 Figure 4. Plastic Leaded Chip Carrier NOTE: Pin names in parentheses apply to the 80188. 4 4 80186/80188 Table 1. Pin Descriptions Symbol Pin No. Type Name and Function VCC 9 43 I SYSTEM POWER: a 5 volt power supply. VSS 26 60 I System Ground. RESET 57 O Reset Output indicates that the CPU is being reset, and can be used as a system reset. It is active HIGH, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the RES signal. X1 X2 59 58 I O Crystal Inputs X1 and X2 provide external connections for a fundamental mode parallel resonant crystal for the internal oscillator. Instead of using a crystal, an external clock may be applied to X1 while minimizing stray capacitance on X2. The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT). CLKOUT 56 O Clock Output provides the system with a 50% duty cycle waveform. All device pin timings are specified relative to CLKOUT. RES 24 I An active RES causes the processor to immediately terminate its present activity, clear the internal logic, and enter a dormant state. This signal may be asynchronous to the processor clock. The processor begins fetching instructions approximately 6(/2 clock cycles after RES is returned HIGH. For proper initialization, VCC must be within specifications and the clock signal must be stable for more than 4 clocks with RES held LOW. RES is internally synchronized. This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network. TEST 47 I/O TEST is examined by the WAIT instruction. If the TEST input is HIGH when ``WAIT'' execution begins, instruction execution will suspend. TEST will be resampled until it goes LOW, at which time execution will resume. If interrupts are enabled while the processor is waiting for TEST, interrupts will be serviced. During power-up, active RES is required to configure TEST as an input. This pin is synchronized internally. TMR IN 0 TMR IN 1 20 21 I I Timer Inputs are used either as clock or control signals, depending upon the programmed timer mode. These inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized. TMR OUT 0 TMR OUT 1 22 23 O O Timer outputs are used to provide single pulse or continous waveform generation, depending upon the timer mode selected. DRQ0 DRQ1 18 19 I I DMA Request is asserted HIGH by an external device when it is ready for DMA Channel 0 or 1 to perform a transfer. These signals are level-triggered and internally synchronized. NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt. An NMI transition from LOW to HIGH is latched and synchronized internally, and initiates the interrupt at the next instruction boundary. NMI must be asserted for at least one clock. The Non-Maskable Interrupt cannot be avoided by programming. INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ 45 44 42 41 I I I/O I/O Maskable Interrupt Requests can be requested by activating one of these pins. When configured as inputs, these pins are active HIGH. Interrupt Requests are synchronized internally. INT2 and INT3 may be configured to provide activeLOW interrupt-acknowledge output signals. All interrupt inputs may be configured to be either edge- or level-triggered. To ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. When Slave Mode is selected, the function of these pins changes (see Interrupt Controller section of this data sheet). NOTE: Pin names in parentheses apply to the 80188. 5 5 80186/80188 Table 1. Pin Descriptions (Continued) Pin No. Type A19/S6 A18/S5 A17/S4 A16/S3 65 66 67 68 O O O O AD15 (A15) AD14 (A14) AD13 (A13) AD12 (A12) AD11 (A11) AD10 (A10) AD9 (A9) AD8 (A8) AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 3 5 7 10 12 14 16 2 4 6 8 11 13 15 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Address/Data Bus signals constitute the time multiplexed memory or I/O address (T1) and data (T2, T3, TW, and T4) bus. The bus is active HIGH. A0 is analogous to BHE for the lower byte of the data bus, pins D7 through D0. It is LOW during T1 when a byte is to be transferred onto the lower portion of the bus in memory or I/O operations. BHE does not exist on the 80188, as the data bus is only 8 bits wide. BHE/S7 (S7) 64 O During T1 the Bus High Enable signal should be used to determine if data is to be enabled onto the most significant half of the data bus; pins D15 -D8. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the higher half of the bus. The S7 status information is available during T2, T3, and T4. S7 is logically equivalent to BHE. BHE/S7 floats during HOLD. On the 80188, S7 is high during normal operation. Symbol Name and Function Address Bus Outputs (16-19) and Bus Cycle Status (3-6) indicate the four most significant address bits during T1. These signals are active HIGH. During T2, T3, TW, and T4, the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a DMA-initiated bus cycle. During the same T-states, S3, S4, and S5 are always LOW. The status pins float during bus HOLD or RESET. BHE and A0 Encodings (80186 Only) BHE Value A0 Value 0 0 1 1 0 1 0 1 Function Word Transfer Byte Transfer on upper half of data bus (D15-D8) Byte Transfer on lower half of data bus (D7 -D0) Reserved ALE/QS0 61 O Address Latch Enable/Queue Status 0 is provided by the processor to latch the address. ALE is active HIGH. Addresses are guaranteed to be valid on the trailing edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT immediately preceding T1 of the associated bus cycle, effectively one-half clock cycle earlier than in the 8086. The trailing edge is generated off the CLKOUT rising edge in T1 as in the 8086. Note that ALE is never floated. WR/QS1 63 O Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a memory or an I/O device. WR is active for T2, T3, and TW of any write cycle. It is active LOW, and floats during HOLD. When the processor is in queue status mode, the ALE/ QS0 and WR/QS1 pins provide information about processor/instruction queue interaction. QS1 QS0 Queue Operation 0 0 1 1 0 1 1 0 No queue operation First opcode byte fetched from the queue Subsequent byte fetched from the queue Empty the queue NOTE: Pin names in parentheses apply to the 80188. 6 6 80186/80188 Table 1. Pin Descriptions (Continued) Symbol Pin No. Type RD/QSMD 62 I/O Read Strobe is an active LOW signal which indicates that the processor is performing a memory or I/O read cycle. It is guaranteed not to go LOW before the A/D bus is floated. An internal pull-up ensures that RD is HIGH during RESET. Following RESET the pin is sampled to determine whether the processor is to provide ALE, RD, and WR, or queue status information. To enable Queue Status Mode, RD must be connected to GND. RD will float during bus HOLD. ARDY 55 I Asynchronous Ready informs the processor that the addressed memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUT, and is active HIGH. The falling edge of ARDY must be synchronized to the processor clock. Connecting ARDY HIGH will always assert the ready condition to the CPU. If this line is unused, it should be tied LOW to yield control to the SRDY pin. SRDY 49 I Synchronous Ready informs the processor that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active-HIGH input synchronized to CLKOUT. The use of SRDY allows a relaxed system timing over ARDY. This is accomplished by elimination of the one-half clock cycle required to internally synchronize the ARDY input signal. Connecting SRDY high will always assert the ready condition to the CPU. If this line is unused, it should be tied LOW to yield control to the ARDY pin. LOCK 48 O LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW. The LOCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the LOCK prefix. It remains active until the completion of that instruction. No instruction prefetching will occur while LOCK is asserted. When executing more than one LOCK instruction, always make sure there are 6 bytes of code between the end of the first LOCK instruction and the start of the second LOCK instruction. LOCK is driven HIGH for one clock during RESET and then floated. S0 S1 S2 52 53 54 O O O Bus cycle status S0 -S2 are encoded to provide bus-transaction information: Name and Function Bus Cycle Status Information S2 S1 S0 Bus Cycle Initiated 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt Acknowledge Read I/O Write I/O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (no bus cycle) The status pins float during HOLD. S2 may be used as a logical M/IO indicator, and S1 as a DT/R indicator. NOTE: Pin names in parentheses apply to the 80188. 7 7 80186/80188 Table 1. Pin Descriptions (Continued) Pin No. Type Name and Function HOLD HLDA 50 51 I O HOLD indicates that another bus master is requesting the local bus. The HOLD input is active HIGH. HOLD may be asynchronous with respect to the processor clock. The processor will issue a HLDA (HIGH) in response to a HOLD request at the end of T4 or Ti. Simultaneous with the issuance of HLDA, the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA. When the processor needs to run another bus cycle, it will again drive the local bus and control lines. UCS 34 O Upper Memory Chip Select is an active LOW output whenever a memory reference is made to the defined upper portion (1K - 256K block) of memory. This line is not floated during bus HOLD. The address range activating UCS is software programmable. LCS 33 O Lower Memory Chip Select is active LOW whenever a memory reference is made to the defined lower portion (1K - 256K) of memory. This line is not floated during bus HOLD. The address range activating LCS is software programmable. MCS0 MCS1 MCS2 MCS3 38 37 36 35 O O O O Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the defined mid-range portion of memory (8K - 512K). These lines are not floated during bus HOLD. The address ranges activating MCS0 -3 are software programmable. PCS0 PCS1 PCS2 PCS3 PCS4 25 27 28 29 30 O O O O O Peripheral Chip Select signals 0 - 4 are active LOW when a reference is made to the defined peripheral area (64 Kbyte I/O space). These lines are not floated during bus HOLD. The address ranges activating PCS0 - 4 are software programmable. PCS5/A1 31 O Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth peripheral chip select, or to provide an internally latched A1 signal. The address range activating PCS5 is software-programmable. PCS5/A1 does not float during bus HOLD. When programmed to provide latched A1, this pin will retain the previously latched value during HOLD. PCS6/A2 32 O Peripheral Chip Select 6 or Latched A2 may be programmed to provide a seventh peripheral chip select, or to provide an internally latched A2 signal. The address range activating PCS6 is software programmable. PCS6/A2 does not float during bus HOLD. When programmed to provide latched A2, this pin will retain the previously latched value during HOLD. DT/R 40 O Data Transmit/Receive controls the direction of data flow through an external data bus transceiver. When LOW, data is transferred to the processsor. When HIGH, the processor places write data on the data bus. DEN 39 O Data Enable is provided as a data bus transceiver output enable. DEN is active LOW during each memory and I/O access. DEN is HIGH whenever DT/R changes state. During RESET, DEN is driven HIGH for one clock, then floated. DEN also floats during HOLD. Symbol NOTE: Pin names in parentheses apply to the 80188. 8 8 80186/80188 FUNCTIONAL DESCRIPTION Introduction The following Functional Description describes the base architecture of the 80186. The 80186 is a very high integration 16-bit microprocessor. It combines 15-20 of the most common microprocessor system components onto one chip while providing twice the performance of the standard 8086. The 80186 is object code compatible with the 8086/8088 microprocessors and adds 10 new instruction types to the 8086/8088 instruction set. For more detailed information on the architecture, please refer to the 80C186XL/80C188XL User's Manual. The 80186 and the 80186XL devices are functionally and register compatible. CLOCK GENERATOR The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divideby-two counter, synchronous and asynchronous ready inputs, and reset circuitry. Oscillator The oscillator circuit is designed to be used with a parallel resonant fundamental mode crystal. This is used as the time base for the processor. The crystal frequency selected will be double the CPU clock frequency. Use of an LC or RC circuit is not recommended with this oscillator. If an external oscillator is used, it can be connected directly to the input pin X1 in lieu of a crystal. The output of the oscillator is not directly available outside the processor. The recommended crystal configuration is shown in Figure 5. Intel recommends the following values for crystal selection parameters: Temperature Range: 0 to 70 C ESR (Equivalent Series Resistance): 30X max C0 (Shunt Capacitance of Crystal): 7.0 pf max 20 pf g 2 pf C1 (Load Capacitance): Drive Level: 1 mW max Clock Generator The clock generator provides the 50% duty cycle processor clock for the processor. It does this by dividing the oscillator output by 2 forming the symmetrical clock. If an external oscillator is used, the state of the clock generator will change on the falling edge of the oscillator signal. The CLKOUT pin provides the processor clock signal for use outside the device. This may be used to drive other system components. All timings are referenced to the output clock. READY Synchronization The processor provides both synchronous and asynchronous ready inputs. In addition, the processor, as part of the integrated chip-select logic, has the capability to program WAIT states for memory and peripheral blocks. RESET Logic The processor provides both a RES input pin and a synchronized RESET output pin for use with other system components. The RES input pin is provided with hysteresis in order to facilitate power-on Reset generation via an RC network. RESET output is guaranteed to remain active for at least five clocks given a RES input of at least six clocks. LOCAL BUS CONTROLLER The processor provides a local bus controller to generate the local bus control signals. In addition, it employs a HOLD/HLDA protocol for relinquishing the local bus to other bus masters. It also provides outputs that can be used to enable external buffers and to direct the flow of data on and off the local bus. 272430 - 5 x 80186-10 (10 MHz) 20 80186 (8 MHz) 16 Figure 5. Recommended Crystal Configuration 9 9 80186/80188 Memory/Peripheral Control The processor provides ALE, RD, and WR bus control signals. The RD and WR signals are used to strobe data from memory or I/O to the processor or to strobe data from the processor to memory or I/O. The ALE line provides a strobe to latch the address when it is valid. The local bus controller does not provide a memory/I/O signal. If this is required, use the S2 signal (which will require external latching), make the memory and I/O spaces nonoverlapping, or use only the integrated chip-select circuitry. Local Bus Arbitration The processor uses a HOLD/HLDA system of local bus exchange. This provides an asynchronous bus exchange mechanism. This means multiple masters utilizing the same bus can operate at separate clock frequencies. The processor provides a single HOLD/HLDA pair through which all other bus masters may gain control of the local bus. External circuitry must arbitrate which external device will gain control of the bus when there is more than one alternate local bus master. When the processor relinquishes control of the local bus, it floats DEN, RD, WR, S0-S2, LOCK, AD0-AD15 (AD0-AD7), A16-A19 (A8-A19), BHE (S7), and DT/R to allow another master to drive these lines directly. Local Bus Controller and Reset During RESET the local bus controller will perform the following action: # Drive DEN, RD, and WR HIGH for one clock cycle, then float. NOTE: RD is also provided with an internal pull-up device to prevent the processor from inadvertently entering Queue Status Mode during RESET. either memory or I/O space. Internal logic will recognize control block addresses and respond to bus cycles. During bus cycles to internal registers, the bus controller will signal the operation externally (i.e., the RD, WR, status, address, data, etc., lines will be driven as in a normal bus cycle), but D15-0 (D7-0), SRDY, and ARDY will be ignored. The base address of the control block must be on an even 256-byte boundary (i.e., the lower 8 bits of the base address are all zeros). The control block base address is programmed by a 16-bit relocation register contained within the control block at offset FEH from the base address of the control block. It provides the upper 12 bits of the base address of the control block. In addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into Slave Mode, and cause the CPU to interrupt upon encountering ESC instructions. Chip-Select/Ready Generation Logic The processor contains logic which provides programmable chip-select generation for both memories and peripherals. In addition, it can be programmed to provide READY (or WAIT state) generation. It can also provide latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they be generated by the CPU or by the integrated DMA unit. MEMORY CHIP SELECTS The processor provides 6 memory chip select outputs for 3 address areas; upper memory, lower memory, and midrange memory. One each is provided for upper memory and lower memory, while four are provided for midrange memory. # Drive S0-S2 to the inactive state (all HIGH) and then float. # Drive LOCK HIGH and then float. # Float AD0-15 (AD0-AD7), A16-19 (A8-A19), BHE (S7), DT/R. # Drive ALE LOW (ALE is never floated). # Drive HLDA LOW. PERIPHERAL ARCHITECTURE All of the integrated peripherals are controlled by 16-bit registers contained within an internal 256-byte control block. The control block may be mapped into UPPER MEMORY CS The processor provides a chip select, called UCS, for the top of memory. The top of memory is usually used as the system memory because after reset the processor begins executing at memory location FFFF0H. LOWER MEMORY CS The processor provides a chip select for low memory called LCS. The bottom of memory contains the interrupt vector table, starting at location 00000H. 10 10 80186/80188 The lower limit of memory defined by this chip select is always 0H, while the upper limit is programmable. By programming the upper limit, the size of the memory block is defined. # Upon leaving RESET, the UCS line will be pro- MID-RANGE MEMORY CS # No other chip select or READY control registers The processor provides four MCS lines which are active within a user-locatable memory block. This block can be located within the 1-Mbyte memory address space exclusive of the areas defined by UCS and LCS. Both the base address and size of this memory block are programmable. grammed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to insert 3 wait states in conjunction with external READY (i.e., UMCS resets to FFFBH). have any predefined values after RESET. They will not become active until the CPU accesses their control registers. Both the PACS and MPCS registers must be accessed before the PCS lines will become active. DMA Channels PERIPHERAL CHIP SELECTS The processor can generate chip selects for up to seven peripheral devices. These chip selects are active for seven contiguous blocks of 128 bytes above a programmable base address. The base address may be located in either memory or I/O space. Seven CS lines called PCS0 -6 are generated by the processor. PCS5 and PCS6 can also be programmed to provide latched address bits A1 and A2. If so programmed, they cannot be used as peripheral selects. These outputs can be connected directly to the A0 and A1 pins used for selecting internal registers of 8-bit peripheral chips. The DMA controller provides two independent DMA channels. Data transfers can occur between memory and I/O spaces (e.g., Memory to I/O) or within the same space (e.g., Memory to Memory or I/O to I/O). Data can be transferred either in bytes or in words (80186 only) to or from even or odd addresses. Each DMA channel maintains both a 20-bit source and destination pointer which can be optionally incremented or decremented after each data transfer (by one or two depending on byte or word transfers). Each data transfer consumes 2 bus cycles (a minimum of 8 clocks), one cycle to fetch data and the other to store data. This provides a maximum data transfer rate of 1.25 Mword/sec or 2.5 Mbytes/sec at 10 MHz (half of this rate for the 80188). READY GENERATION LOGIC The processor can generate a READY signal internally for each of the memory or peripheral CS lines. The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0-3 wait states for all accesses to the area for which the chip select is active. In addition, the processor may be programmed to either ignore external READY for each chip-select range individually or to factor external READY with the integrated ready generator. CHIP SELECT/READY LOGIC AND RESET Upon RESET, the Chip-Select/Ready Logic will perform the following actions: # All chip-select outputs will be driven HIGH. DMA CHANNELS AND RESET Upon RESET, the DMA channels will perform the following actions: # The Start/Stop bit for each channel will be reset to STOP. # Any transfer in progress is aborted. Timers The processor provides three internal 16-bit programmable timers. Two of these are highly flexible and are connected to four external pins (2 per timer). They can be used to count external events, time external events, generate nonrepetitive waveforms, etc. The third timer is not connected to any external pins, and is useful for real-time coding and time delay applications. In addition, the third timer can be used as a prescaler to the other two, or as a DMA request source. 11 11 80186/80188 TIMERS AND RESET INTERRUPT CONTROLLER AND RESET Upon RESET, the Timers will perform the following actions: Upon RESET, the interrupt controller will perform the following actions: # All SFNM bits reset to 0, implying Fully Nested Mode. # All PR bits in the various control registers set to 1. This places all sources at lowest priority (level 111). # All EN (Enable) bits are reset preventing timer counting. # For Timers 0 and 1, the RIU bits are reset to zero and the ALT bits are set to one. This results in the Timer Out pins going high. # All LTM bits reset to 0, resulting in edge-sense Interrupt Controller The processor can receive interrupts from a number of sources, both internal and external. The internal interrupt controller serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources (Timers and DMA channels) can be disabled by their own control registers or by mask bits within the interrupt controller. The interrupt controller has its own control register that sets the mode of operation for the controller. mode. # # # # # All Interrupt Service bits reset to 0. All Interrupt Request bits reset to 0. All MSK (Interrupt Mask) bits set to 1 (mask). All C (Cascade) bits reset to 0 (non-Cascade). All PRM (Priority Mask) bits set to 1, implying no levels masked. # Initialized to Master Mode. 12 12 80186/80188 272430 - 6 NOTE: Pin names in parenthesis apply to 80188. (1) BHE does not exist on the 80188, this is only required for a 16-bit data bus. Figure 6. Typical 80186/80188 Computer 13 13 80186/80188 272430 - 7 NOTE: Pin names in parentheses apply to 80188. (1) BHE does not exist on the 80188, this is only required for a 16-bit data bus. Figure 7. Typical 80186/80188 Multi-Master Bus Interface 14 14 80186/80188 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifications are subject to change without notice. Ambient Temperature under Bias AAAAAA0 C to 70 C Storage Temperature AAAAAAAAAA b 65 C to a 150 C Voltage on any Pin with Respect to GroundAAAAAAAAAAAAAA b 1.0V to a 7V Power Dissipation AAAAAAAAAAAAAAAAAAAAAAAAAAA3W *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. D.C. CHARACTERISTICS (TA e 0 C to a 70 C, VCC e 5V g 10%) Applicable to 8 MHz and 10 MHz devices. Symbol Parameter Min Max Units b 0.5 a 0.8 V Input High Voltage (All except X1 and (RES) 2.0 VCC a 0.5 V VIH1 Input High Voltage (RES) 3.0 VCC a 0.5 V VOL Output Low Voltage 0.45 V Ia e 2.5 mA for S0 -S2 Ia e 2.0 mA for all other Outputs VOH Output High Voltage V Ioa e b 400 mA ICC Power Supply Current VIL Input Low Voltage VIH 2.4 Test Conditions 600* mA TA e b 40 C 550 mA T A e 0 C 415 mA TA e a 70 C Input Leakage Current g 10 mA 0V k VIN k VCC ILO Output Leakage Current g 10 mA 0.45V k VOUT k VCC VCLO Clock Output Low 0.6 V Ia e 4.0 mA VCHO Clock Output High V Ioa e b 200 mA VCLI Clock Input Low Voltage b 0.5 0.6 V VCHI Clock Input High Voltage 3.9 VCC a 1.0 V CIN Input Capacitance 10 pF CIO I/O Capacitance 20 pF ILI 4.0 *For extended temperature parts only. 15 15 80186/80188 A.C. CHARACTERISTICS (TA e 0 C to a 70 C, VCC e 5V g 10%) Timing Requirements All Timings Measured At 1.5V Unless Otherwise Noted. Symbol Parameter 8 MHz Min 10 MHz Max 20 Min Units Max TDVCL Data in Setup (A/D) 15 ns TCLDX Data in Hold (A/D) TARYHCH Asynchronous Ready (ARDY) Active Setup Time(1) 10 8 ns 20 15 ns TARYLCL ARDY Inactive Setup Time 35 25 ns TCLARX ARDY Hold Time 15 15 ns TARYCHL Asynchronous Ready Inactive Hold Time 15 15 ns TSRYCL Synchronous Ready (SRDY) Transition Setup Time(2) 20 20 ns TCLSRY SRDY Transition Hold Time(2) 15 15 ns THVCL HOLD Setup(1) 25 20 ns TINVCH INTR, NMI, TEST, TIM IN, Setup(1) 25 25 ns TINVCL DRQ0, DRQ1, Setup(1) 25 20 ns Test Conditions Master Interface Timing Responses TCLAV Address Valid Delay 5 55 5 44 ns TCLAX Address Hold TCLAZ Address Float Delay 35 TCLAX 30 ns TCHCZ Command Lines Float Delay TCHCV Command Lines Valid Delay (after Float) 45 40 ns 55 45 ns TLHLL ALE Width TCHLH ALE Active Delay 35 30 ns TCHLL ALE Inactive Delay 35 30 ns 10 TCLAX 10 TCLCL b 35 ns TCLCL b 30 TCHCL b 25 ns TLLAX Address Hold from ALE Inactive TCLDV Data Valid Delay TCLDOX Data Hold Time TWHDX Data Hold after WR TCVCTV Control Active Delay 1 5 50 5 40 ns TCHCTV Control Active Delay 2 10 55 10 44 ns TCVCTX Control Inactive Delay 5 55 5 44 ns TCVDEX DEN Inactive Delay (Non-Write Cycle) 10 70 10 56 ns 10 TCHCL b 20 44 10 CL e 20 pF-200 pF all Outputs (Except TCLTMV) @ 8 MHz and 10 MHz ns 40 ns 10 10 ns TCLCL b 40 TCLCL b 34 ns 1. To guarantee recognition at next clock. 2. To guarantee proper operation. 16 16 80186/80188 A.C. CHARACTERISTICS (TA e 0 C to a 70 C, VCC e 5V g 10%) (Continued) Master Interface Timing Responses (Continued) Symbol Parameter 8 MHz Min 10 MHz Units Max Min Max 10 56 10 44 TAZRL Address Float to RD Active 0 TCLRL RD Active Delay 10 70 0 TCLRH RD Inactive Delay 10 55 TRHAV RD Inactive to Address Active TCLHAV HLDA Valid Delay TRLRH RD Width 2TCLCL b 50 2TCLCL b 46 ns TWLWH WR Width 2TCLCL b 40 2TCLCL b 34 ns TAVLL Address Valid to ALE Low TCLCH b 25 TCLCH b 19 ns TCHSV Status Active Delay 10 55 10 45 ns TCLSH Status Inactive Delay 10 65 10 50 ns TCLTMV Timer Output Delay 60 48 ns TCLRO Reset Delay 60 48 ns TCHQSV Queue Status Delay 35 28 ns TCHDX Status Hold Time 10 10 ns TAVCH Address Valid to Clock High 10 10 ns TCLLV LOCK Valid/Invalid Delay 5 TCLCL b 40 5 ns TCLCL b 40 50 65 5 5 Test Conditions ns ns ns 40 ns 60 ns 45 ns 100 pF max @ 8 & 10 MHz Chip-Select Timing Responses TCLCSV Chip-Select Active Delay TCXCSX Chip-Select Hold from Command Inactive 35 66 TCHCSX Chip-Select Inactive Delay 5 35 5 32 62.5 250 50 250 ns 10 ns 3.5 to 1.0V 10 35 ns ns CLKIN Requirements TCKIN CLKIN Period TCKHL CLKIN Fall Time TCKLH CLKIN Rise Time ns 1.0 to 3.5V TCLCK CLKIN Low Time 25 20 ns 1.5V TCHCK CLKIN High Time 25 20 ns 1.5V 10 10 CLKOUT Timing (200 pF load) TCICO CLKIN to CLKOUT Skew TCLCL CLKOUT Period 50 125 500 100 25 ns 500 ns TCLCH CLKOUT Low Time (/2 TCLCL b 7.5 (/2 TCLCL b 6.0 TCHCL CLKOUT High Time (/2 TCLCL b 7.5 ns 1.5V (/2 TCLCL b 6.0 ns 1.5V TCH1CH2 CLKOUT Rise Time 15 12 ns 1.0 to 3.5V TCL2CL1 CLKOUT Fall Time 15 12 ns 3.5 to 1.0V 17 17 80186/80188 EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters. The first character is always a ``T'' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: ARY: C: CK: CS: CT: D: DE: H: Address Asynchronous Ready Input Clock Output Clock Input Chip Select Control (DT/R, DEN, . . . ) Data Input DEN Logic Level High IN: L: O: QS: R: S: SRY: V: W: X: Z: Input (DRQ0, TIM0, . . . ) Logic Level Low or ALE Output Queue Status (QS1, QS2) RD signal, RESET signal Status (S0, S1, S2) Synchronous Ready Input Valid WR Signal No Longer a Valid Logic Level Float Examples: TCLAV Time from Clock low to Address valid TCHLH Time from Clock high to ALE high TCLCSV Time from Clock low to Chip Select valid 18 18 80186/80188 WAVEFORMS MAJOR CYCLE TIMING 272430 - 8 NOTE: Pin names in parentheses apply to the 80188. 19 19 80186/80188 WAVEFORMS (Continued) MAJOR CYCLE TIMING (Continued) NOTES: 1. INTA occurs one clock later in slave mode. 2. Status inactive just prior to T4. 3. If latched A1 and A2 are selected instead of PCS5 and PCS6, only TCLCSV is applicable. 4. Pin names in parentheses apply to the 80188. 272430 - 9 20 20 80186/80188 WAVEFORMS (Continued) 272430 - 10 272430 - 11 272430 - 12 21 21 80186/80188 WAVEFORMS (Continued) 272430 - 13 272430 - 14 22 22 80186/80188 WAVEFORMS (Continued) READY TIMING 272430 - 15 23 23 80186/80188 272430 - 16 NOTE: Pin names in parentheses apply to the 80188. 24 24 80186/80188 WAVEFORMS (Continued) 272430 - 17 EXPRESS The Intel EXPRESS system offers enhancements to the operational specifications of the microprocessor. EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The prefixes are listed in Table 2. All A.C. and D.C. specifications not mentioned in this section are the same for both commercial and EXPRESS parts. Table 2. Prefix Identification Package Type Temperature Range Burn-In A PGA Commercial No N PLCC Commercial No The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range without burn-in. Prefix With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of 0 C to a 70 C. With the extended temperature range option, operational characteristics are guaranteed over the range of b 40 C to a 85 C. The optional burn-in is dynamic, for a minimum time of 160 hours at a 125 C with VCC e 5.5V g 0.25V, following guidelines in MIL-STD-883, Method 1015. R LCC Commercial No TA PGA Extended No QA PGA Commercial Yes QR LCC Commercial Yes NOTE: Not all package/temperature range/speed combinations are available. 25 25 80186/80188 EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions. The following instruction timings represent the minimum execution time in clock cycles for each instruction. The timings given are based on the following assumptions: # The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # No wait states or bus HOLDS occur. # All word-data is located on even-address boundaries. All instructions which involve memory accesses can also require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit. All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. The 80186 has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. The 80188 is noticeably limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time may be substantially greater than that derived from adding the instruction timings shown. 26 26 80186/80188 INSTRUCTION SET SUMMARY Function Format 80186 Clock Cycles 80188 Clock Cycles 2/12 2/12* Comments DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w mod reg r/m Register/memory to register 1000101w mod reg r/m Immediate to register/memory 1100011w mod 000 r/m data Immediate to register 1 0 1 1 w reg data Memory to accumulator 1010000w Accumulator to memory Register/memory to segment register Segment register to register/memory 2/9 2/9* 12/13 12/13 8/16-bit data if w e 1 3/4 3/4 8/16-bit addr-low addr-high 8 8* 1010001w addr-low addr-high 9 9* 10001110 mod 0 reg r/m 2/9 2/13 10001100 mod 0 reg r/m 2/11 2/15 Memory 11111111 mod 1 1 0 r/m 16 20 Register 0 1 0 1 0 reg 10 14 Segment register 0 0 0 reg 1 1 0 9 13 Immediate 011010s0 10 14 PUSHA e Push All 01100000 36 68 20 24 10 14 8 12 51 83 4/17 4/17* 3 3 10 10* 8 8* data if w e 1 PUSH e Push: data data if s e 0 POP e Pop: Memory 10001111 Register 0 1 0 1 1 reg Segment register 0 0 0 reg 1 1 1 POPA e Pop All 01100001 mod 0 0 0 r/m (reg i 01) XCHG e Exchange: Register/memory with register 1000011w Register with accumulator 1 0 0 1 0 reg mod reg r/m IN e Input from: Fixed port 1110010w Variable port 1110110w port OUT e Output to: Fixed port 1110011w Variable port 1110111w XLAT e Translate byte to AL 11010111 LEA e Load EA to register 10001101 port mod reg r/m 9 9* 7 7* 11 15 6 6 18 26 18 26 LDS e Load pointer to DS 11000101 mod reg r/m (mod i 11) LES e Load pointer to ES 11000100 mod reg r/m (mod i 11) LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 13 POPF e Pop flags 10011101 8 12 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 27 27 80186/80188 INSTRUCTION SET SUMMARY (Continued) Function Format 80186 Clock Cycles 80188 Clock Cycles Comments DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 3/10 3/10* 4/16 4/16* 3/4 3/4 3/10 3/10* 4/16 4/16* 3/4 3/4 3/15 3/15* 3 3 3/10 3/10* 4/16 4/16* 3/4 3/4 3/10 3/10* 4/16 4/16* 3/4 3/4 3/15 3/15* 3 3 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw mod reg r/m Immediate to register/memory 100000sw mod 0 0 0 r/m data Immediate to accumulator 0000010w data data if w e 1 data if s w e 01 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw mod reg r/m Immediate to register/memory 100000sw mod 0 1 0 r/m data Immediate to accumulator 0001010w data data if w e 1 Register/memory 1111111w mod 0 0 0 r/m Register 0 1 0 0 0 reg data if s w e 01 8/16-bit INC e Increment: SUB e Subtract: Reg/memory and register to either 001010dw mod reg r/m Immediate from register/memory 100000sw mod 1 0 1 r/m data Immediate from accumulator 0010110w data data if w e 1 data if s w e 01 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw mod reg r/m Immediate from register/memory 100000sw mod 0 1 1 r/m data Immediate from accumulator 0001110w data data if w e 1 Register/memory 1111111w mod 0 0 1 r/m Register 0 1 0 0 1 reg data if s w e 01 8/16-bit DEC e Decrement CMP e Compare: Register/memory with register 0011101w mod reg r/m 3/10 3/10* Register with register/memory 0011100w mod reg r/m 3/10 3/10* Immediate with register/memory 100000sw mod 1 1 1 r/m data 3/10 3/10* Immediate with accumulator 0011110w data data if w e 1 NEG e Change sign register/memory 1111011w mod 0 1 1 r/m AAA e ASCII adjust for add DAA e Decimal adjust for add data if s w e 01 3/4 3/4 3/10 3/10* 00110111 8 8 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w 26-28 35-37 32-34 41-43 26-28 35-37 32-34 41-43* 8/16-bit mod 100 r/m Register-Byte Register-Word Memory-Byte Memory-Word Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 28 28 80186/80188 INSTRUCTION SET SUMMARY (Continued) Function Format 80186 Clock Cycles 80188 Clock Cycles 25-28 34-37 31-34 40-43 25-28 34-37 31-34 40-43* 22-25/ 29-32 22-25/ 29-32 29 38 35 44 29 38 35 44* 44-52 53-61 50-58 59-67 44-52 53-61 50-58 59-67* Comments ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w mod 1 0 1 r/m Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) 011010s1 mod reg r/m DIV e Divide (unsigned): 1111011w mod 1 1 0 r/m data data if s e 0 Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed): 1111011w mod 1 1 1 r/m Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply 11010100 00001010 19 19 AAD e ASCII adjust for divide 11010101 00001010 15 15 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 2/15 2/15 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w mod TTT r/m Register/Memory by CL 1101001w mod TTT r/m Register/Memory by Count 1100000w mod TTT r/m 5 a n/17 a n 5 a n/17 a n count 5 a n/17 a n 5 a n/17 a n TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL/SAL 101 SHR 111 SAR AND e And: Reg/memory and register to either 001000dw mod reg r/m Immediate to register/memory 1000000w mod 1 0 0 r/m data Immediate to accumulator 0010010w data data if w e 1 data if w e 1 3/10 3/10* 4/16 4/16* 3/4 3/4 3/10 3/10* 4/10 4/10* 3/4 3/4 3/10 3/10* 4/16 4/16* 3/4 3/4 8/16-bit TEST e And function to flags, no result: Register/memory and register 1000010w mod reg r/m Immediate data and register/memory 1111011w mod 0 0 0 r/m data Immediate data and accumulator 1010100w data data if w e 1 data if w e 1 8/16-bit OR e Or: Reg/memory and register to either 000010dw mod reg r/m Immediate to register/memory 1000000w mod 0 0 1 r/m data Immediate to accumulator 0000110w data data if w e 1 data if w e 1 8/16-bit Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 29 29 80186/80188 INSTRUCTION SET SUMMARY (Continued) Function Format 80186 Clock Cycles 80188 Clock Cycles 3/10 3/10* 4/16 4/16* Comments LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw mod reg r/m data if w e 1 Immediate to register/memory 1000000w mod 1 1 0 r/m data Immediate to accumulator 0011010w data data if w e 1 NOT e Invert register/memory 1111011w mod 0 1 0 r/m 3/4 3/4 3/10 3/10* 8/16-bit STRING MANIPULATION MOVS e Move byte/word 1010010w 14 14* CMPS e Compare byte/word 1010011w 22 22* SCAS e Scan byte/word 1010111w 15 15* LODS e Load byte/wd to AL/AX 1010110w 12 12* STOS e Store byte/wd from AL/AX 1010101w 10 10* INS e Input byte/wd from DX port 0110110w 14 14 OUTS e Output byte/wd to DX port 0110111w 14 14 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a 8n 8 a 8n* CMPS e Compare string 1111001z 1010011w 5 a 22n 5 a 22n* SCAS e Scan string 1111001z 1010111w 5 a 15n 5 a 15n* 1010110w 6 a 11n 6 a 11n* LODS e Load string 11110010 STOS e Store string 11110010 1010101w 6 a 9n 6 a 9n* INS e Input string 11110010 0110110w 8 a 8n 8 a 8n* OUTS e Output string 11110010 0110111w 8 a 8n 8 a 8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low Register/memory indirect within segment 11111111 mod 0 1 0 r/m Direct intersegment 10011010 disp-high segment offset 15 19 13/19 17/27 23 31 38 54 14 14 segment selector Indirect intersegment 11111111 mod 0 1 1 r/m Short/long 11101011 disp-low Direct within segment 11101001 disp-low Register/memory indirect within segment 11111111 mod 1 0 0 r/m Direct intersegment 11101010 (mod i 11) JMP e Unconditional jump: disp-high segment offset 14 14 11/17 11/21 14 14 26 34 segment selector Indirect intersegment 11111111 mod 1 0 1 r/m (mod i 11) Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 30 30 80186/80188 INSTRUCTION SET SUMMARY (Continued) Function Format 80186 Clock Cycles 80188 Clock Cycles 16 20 Comments CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 Within seg adding immed to SP 11000010 Intersegment 11001011 Intersegment adding immediate to SP 11001010 data-low JE/JZ e Jump on equal/zero 01110100 disp data-low data-high data-high 18 22 22 30 25 33 4/13 4/13 JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 ENTER e Enter Procedure 11001000 data-low 15 25 22 a 16(n b 1) 19 29 26 a 20(n b 1) 8 8 data-high Le0 Le1 Ll1 LEAVE e Leave Procedure 11001001 JMP not taken/JMP taken LOOP not taken/LOOP taken L INT e Interrupt: Type specified 11001101 47 47 Type 3 11001100 type 45 45 if INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 28 28 BOUND e Detect value out of range 01100010 33-35 33-35 mod reg r/m Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. 31 31 80186/80188 INSTRUCTION SET SUMMARY (Continued) Function Format 80186 Clock Cycles 80188 Clock Cycles Comments PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 LOCK e Bus lock prefix 11110000 2 3 6 6 3 3 ESC e Processor Extension Escape 11011TTT mod LLL r/m if TEST e 0 (TTT LLL are opcode to processor extension) NOP e No Operation 10010000 Shaded areas indicate instructions not available in 8086, 8088 microsystems. NOTE: *Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer. reg is assigned according to the following: FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as REG field if mod e 00 then DISP e 0*, disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenever appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg 00 01 10 11 Segment Register ES CS SS DS REG is assigned according to the following table: 16-Bit (w e 1) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI 8-Bit (w e 0) 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register. The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden. 32 32 80186/80188 REVISION HISTORY This data sheet replaces the following data sheets: 210706-011 80188 210451-011 80186 33 33