MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
MIXED SIGNAL MICROCONTROLLER
1FEATURES
2•Low Supply-Voltage Range: 1.8 V to 3.6 V •16-Bit Timer_A With Two Capture/Compare
Registers
•Ultralow Power Consumption
•Brownout Detector
–Active Mode: 220 µA at 1 MHz, 2.2 V
•On-Chip Comparator for Analog Signal
–Standby Mode: 0.5 µACompare Function or Slope A/D (See Table 1)
–Off Mode (RAM Retention): 0.1 µA•Serial Onboard Programming,
•Five Power-Saving Modes No External Programming Voltage Needed,
•Ultrafast Wake-Up From Standby Mode in Less Programmable Code Protection by Security
Than 1 µsFuse
•16-Bit RISC Architecture, 62.5-ns Instruction •On-Chip Emulation Logic With Spy-Bi-Wire
Cycle Time Interface
•Basic Clock Module Configurations •For Family Members Details, See Table 1
–Internal Frequencies up to 16 MHz With •Available in a 14-Pin Plastic Small-Outline Thin
One Calibrated Frequency Package (TSSOP) (PW), 14-Pin Plastic Dual
–Internal Very Low Power Low-Frequency Inline Package (PDIP) (N), and 16-Pin QFN
(LF) Oscillator (RSA)
–32-kHz Crystal •For Complete Module Descriptions, See the
–External Digital Clock Source MSP430x2xx Family User’s Guide (SLAU144)
DESCRIPTION
The Texas Instruments MSP430™family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430G2x01/MSP430G2x11 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit
timer and ten I/O pins. The MSP430G2x11 family members have a versatile analog comparator. For
configuration details see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Table 1. Available Options(1)
Flash RAM Comp_A+ Package
Device BSL EEM Timer_A Clock I/O
(KB) (B) Channel Type(2)
MSP430G2211IRSA16 16-QFN
MSP430G2211IPW14 - 1 2 128 1x TA2 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2211IN14 14-PDIP
MSP430G2201IRSA16 16-QFN
MSP430G2201IPW14 - 1 2 128 1x TA2 - LF, DCO, VLO 10 14-TSSOP
MSP430G2201IN14 14-PDIP
MSP430G2111IRSA16 16-QFN
MSP430G2111IPW14 - 1 1 128 1x TA2 8 LF, DCO, VLO 10 14-TSSOP
MSP430G2111IN14 14-PDIP
MSP430G2101IRSA16 16-QFN
MSP430G2101IPW14 - 1 1 128 1x TA2 - LF, DCO, VLO 10 14-TSSOP
MSP430G2101IN14 14-PDIP
MSP430G2001IRSA16 16-QFN
MSP430G2001IPW14 - 1 0.5 128 1x TA2 - LF, DCO, VLO 10 14-TSSOP
MSP430G2001IN14 14-PDIP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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1
DVCC
2
3
4
5
6
78
P1.6/TA0.1/TDI/TCLK
9
P1.7/TDO/TDI
10
RST/NMI/SBWTDIO
11
TEST/SBWTCK
12
XOUT/P2.7
13
XIN/P2.6/TA0.1
14
DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/T CK
P1.5/TA0.0/TMS
1
2
3
4
5
P1.4/SMCLK/TCK
6
P1.5/TA0.0/TMS
7
P1.6/TA0.1/TDI/TCLK
8
P1.7/TDO/TDI
9
10
11
12
13
NC
14
DVSS
15
NC
16
DVCC
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Device Pinout, MSP430G2x01
N or PW PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
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1
DVCC
2
3
4
5
6
78
P1.6/TA0.1/CA6/TDI/TCLK
9
P1.7/CAOUT/CA7/TDO/TDI
10
RST/NMI/SBWTDIO
11
TEST/SBWTCK
12
XOUT/P2.7
13
XIN/P2.6/TA0.1
14
DVSS
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
P1.4/SMCLK/CA4/TCK
P1.5/TA0.0/CA5/TMS
1
2
3
4
5
P1.4/SMCLK/CA4/TCK
6
P1.5/TA0.0/CA5/TMS
7
P1.6/TA0.1/CA6/TDI/TCLK
8
P1.7/CAOUT/CA7/TDO/TDI
9
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
XOUT/P2.7
12
XIN/P2.6/TA0.1
13
NC
14
DVSS
15
NC
16
DVCC
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Device Pinout, MSP430G2x11
N or PW PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
RSA PACKAGE
(TOP VIEW)
NOTE: See port schematics in Application Information for detailed I/O information.
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Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
128B
Flash
2KB
1KB
Comp_A+
8
Channels
P2.x
Port P2
2 I/O
Interrupt
capability
pullup/down
resistors
2
Clock
System
Brownout
Protection
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
SMCLK
ACLK
MDB
MAB
Port P1
8 I/O
Interrupt
capability
pull-up/down
resistors
P1.x
8
Spy-Bi
Wire
XIN XOUT
RAM
128B
Flash
2KB
1KB
0.5KB
P2.x
Port P2
2 I/O
Interrupt
capability
pull-up/down
resistors
2
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Functional Block Diagram, MSP430G2x11
Functional Block Diagram, MSP430G2x01
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MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Table 2. Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME 14 16
N, PW RSA
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
2 1 I/O
ACLK/ ACLK signal output
CA0 Comparator_A+, CA0 input(1)
P1.1/ General-purpose digital I/O pin
TA0.0/ 3 2 I/O Timer0_A, capture: CCI0A input, compare: Out0 output
CA1 Comparator_A+, CA1 input(1)
P1.2/ General-purpose digital I/O pin
TA0.1/ 4 3 I/O Timer0_A, capture: CCI1A input, compare: Out1 output
CA2 Comparator_A+, CA2 input(1)
P1.3/ General-purpose digital I/O pin
CA3/ 5 4 I/O Comparator_A+, CA3 input(1)
CAOUT Comparator_A+, output(1)
P1.4/ General-purpose digital I/O pin
SMCLK/ SMCLK signal output
6 5 I/O
CA4/ Comparator_A+, CA4 input(1)
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
7 6 I/O
CA5/ Comparator_A+, CA5 input(1)
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
8 7 I/O
CA6/ Comparator_A+, CA6 input(1)
TDI/TCLK JTAG test data input or test clock input during programming and test
P1.7/ General-purpose digital I/O pin
CA7/ CA7 input(1)
9 8 I/O
CAOUT/ Comparator_A+, output(1)
TDO/TDI(2) JTAG test data output terminal or test data input during programming and test
XIN/ Input terminal of crystal oscillator
P2.6/ 13 12 I/O General-purpose digital I/O pin
TA0.1 Timer0_A, compare: Out1 output
XOUT/ Output terminal of crystal oscillator(3)
12 11 I/O
P2.7 General-purpose digital I/O pin
RST/ Reset
NMI/ 10 9 I Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test
TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11 10 I
SBWTCK Spy-Bi-Wire test clock input during programming and test
DVCC 1 16 NA Supply voltage
DVSS 14 14 NA Ground reference
NC - 15 NA Not connected
QFN Pad - Pad NA QFN package pad connection to VSS recommended.
(1) MSP430G2x11 only
(2) TDO or TDI is selected via JTAG instruction.
(3) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The
register-to-register operation execution time is one
cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT EXMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 -->R5
Single operands, destination only CALL R8 PC ->(TOS), R8->PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
Table 4. Address Mode Descriptions(1)
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 - ->R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) - ->M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) - ->M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) - ->M(TCDAT)
Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) - ->M(Tab+R6)
M(R10) - ->R11
Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2- ->R10
Immediate ✓MOV #X,TONI MOV #45,TONI #45 - ->M(TONI)
(1) S = source, D = destination
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MSP430G2x11
MSP430G2x01
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www.ti.com
Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•Active mode (AM)
–All clocks are active
•Low-power mode 0 (LPM0)
–CPU is disabled
–ACLK and SMCLK remain active, MCLK is disabled
•Low-power mode 1 (LPM1)
–CPU is disabled
–ACLK and SMCLK remain active, MCLK is disabled
–DCO's dc generator is disabled if DCO not used in active mode
•Low-power mode 2 (LPM2)
–CPU is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator remains enabled
–ACLK remains active
•Low-power mode 3 (LPM3)
–CPU is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator is disabled
–ACLK remains active
•Low-power mode 4 (LPM4)
–CPU is disabled
–ACLK is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator is disabled
–Crystal oscillator is stopped
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MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go
into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG (non)-maskable
Oscillator fault OFIFG (non)-maskable 0FFFCh 30
Flash memory access violation ACCVIFG(2)(3) (non)-maskable 0FFFAh 29
0FFF8h 28
Comparator_A+ CAIFG(4)(5) 0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A2 TACCR0 CCIFG(4) maskable 0FFF2h 25
Timer_A2 TACCR1 CCIFG, TAIFG(2)(4) maskable 0FFF0h 24
0FFEEh 23
0FFECh 22
0FFEAh 21
0FFE8h 20
I/O Port P2 (two flags) P2IFG.6 to P2IFG.7(2)(4) maskable 0FFE6h 19
I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
See (6) 0FFDEh to 15 to 0, lowest
0FFC0h
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) Devices with Comparator_A+ only
(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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MSP430G2x01
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend rw: Bit can be read and written.
rw-0,1: Bit can be read and written. It is reset or set by PUC.
rw-(0,1): Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address 76543210
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address 76543210
01h
Table 7. Interrupt Flag Register 1 and 2
Address 76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault.
PORIFG Power-On Reset interrupt flag. Set on VCC power-up.
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
NMIIFG Set via RST/NMI pin
Address 76543210
03h
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MSP430G2x11
MSP430G2x01
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SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Memory Organization
Table 8. Memory Organization
MSP430G2001 MSP430G2101 MSP430G2201
MSP430G2011 MSP430G2111 MSP430G2211
Memory Size 512B 1kB 2kB
Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0
Main: code memory Flash 0xFFFF to 0xFE00 0xFFFF to 0xFC00 0xFFFF to 0xF800
Information memory Size 256 Byte 256 Byte 256 Byte
Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h
RAM Size 128B 128B 128B
027Fh to 0200h 027Fh to 0200h 027Fh to 0200h
Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h
8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h
8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
•Segments 0 to n may be erased in one step, or each segment may be individually erased.
•Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
•Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1µs. The basic
clock module provides the following clock signals:
•Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
•Main clock (MCLK), the system clock used by the CPU.
•Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 9. DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
CALIBRATION
DCO FREQUENCY SIZE ADDRESS
REGISTER
CALBC1_1MHZ byte 010FFh
1 MHz CALDCO_1MHZ byte 010FEh
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
•All individual I/O bits are independently programmable.
•Any combination of input, output, and interrupt condition is possible.
•Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
•Read/write access to port-control registers is supported by all instructions.
•Each I/O has an individually programmable pullup/pulldown resistor.
WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
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MSP430G2x11
MSP430G2x01
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SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 10. Timer_A2 Signal Connections - Devices With No Analog
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE OUTPUT
SIGNAL INPUT NAME BLOCK
PW, N RSA PW, N RSA
SIGNAL
2 - P1.0 1 - P1.0 TACLK TACLK
ACLK ACLK Timer NA
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1
ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
CCR0 TA0
VSS GND
VCC VCC
4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2
TA1 CCI1B 8 - P1.6 7 - P1.6
CCR1 TA1
VSS GND 13 - P2.6 12 - P2.6
VCC VCC
Table 11. Timer_A2 Signal Connections - Devices With Comparator_A+
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE OUTPUT
SIGNAL INPUT NAME BLOCK
PW, N RSA PW, N RSA
SIGNAL
2 - P1.0 1 - P1.0 TACLK TACLK
ACLK ACLK Timer NA
SMCLK SMCLK
2 - P1.0 1 - P1.0 TACLK INCLK
3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1
ACLK (internal) CCI0B 7 - P1.5 6 - P1.5
CCR0 TA0
VSS GND
VCC VCC
4 - P1.2 3 - P1.2 TA1 CCI1A 4 - P1.2 3 - P1.2
CAOUT CCI1B 8 - P1.6 7 - P1.6
(internal) CCR1 TA1
VSS GND 13 - P2.6 12 - P2.6
VCC VCC
Comparator_A+ (MSP430G2x11 Only)
The primary function of the comparator_A+module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Peripheral File Map
Table 12. Peripherals With Word Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
Timer_A Capture/compare register TACCR1 0174h
Capture/compare register TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control TACCTL1 0164h
Capture/compare control TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
Table 13. Peripherals With Byte Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
Comparator_A+ Comparator_A+ port disable CAPD 05Bh
(MSP430G2x11 only) Comparator_A+ control 2 CACTL2 05Ah
Comparator_A+ control 1 CACTL1 059h
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
14 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
16 MHz
System Frequency - MHz
12 MHz
6 MHz
1.8 V
Supply Voltage - V
3.3 V
2.7 V
2.2 V 3.6 V
MSP430G2x11
MSP430G2x01
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SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Absolute Maximum Ratings(1)
Voltage applied at VCC to VSS -0.3 V to 4.1 V
Voltage applied to any pin(2) -0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Unprogrammed device -55°C to 150°C
Storage temperature range, Tstg (3) Programmed device -55°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions MIN NOM MAX UNIT
During program execution 1.8 3.6
VCC Supply voltage V
During flash program/erase 2.2 3.6
VSS Supply voltage 0 V
I version -40 85
TAOperating free-air temperature °C
T version -40 105
VCC = 1.8 V, dc 6
Duty cycle = 50% ±10%
VCC = 2.7 V,
fSYSTEM Processor frequency (maximum MCLK frequency)(1)(2) dc 12 MHz
Duty cycle = 50% ±10%
VCC ≥3.3 V, dc 16
Duty cycle = 50% ±10%
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 1. Safe Operating Area
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
0.0
1.0
2.0
3.0
4.0
5.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
Active Mode Current − mA
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
0.0
1.0
2.0
3.0
4.0
0.0 4.0 8.0 12.0 16.0
fDCO − DCO Frequency − MHz
Active Mode Current − mA
TA= 25 °C
TA= 85 °C
VCC = 2.2 V
VCC = 3 V
TA= 25 °C
TA= 85 °C
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 220
fACLK = 32768 Hz,
Program executes in flash,
Active mode (AM)
IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA
current (1 MHz) 3 V 300 370
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics - Active Mode Supply Current (Into VCC)
Figure 2. Active Mode Current vs VCC, TA= 25°C Figure 3. Active Mode Current vs DCO Frequency
16 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
-40
I – Low-Power Mode Current – µA
LPM4
Vcc = 3.6 V
T – Temperature – °C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 020 40 60 80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
-40
I – Low-Power Mode Current – µA
LPM3
Vcc = 3.6 V
T – Temperature – °C
A
Vcc = 1.8 V
Vcc = 3 V
Vcc = 2.2 V
-20 020 40 60 80
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 0
ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 65 µA
(LPM0) current(3) DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = 0 MHz, 25°C 22
fDCO = 1 MHz,
fACLK = 32768 Hz,
Low-power mode 2
ILPM2 BCSCTL1 = CALBC1_1MHZ, 2.2 V µA
(LPM2) current(4) 105°C 31
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.7 1.5
Low-power mode 3 fACLK = 32768 Hz,
ILPM3,LFXT1 2.2 V µA
(LPM3) current(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 105°C 3 6
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.5 0.7
Low-power mode 3 fACLK from internal LF oscillator (VLO),
ILPM3,VLO 2.2 V µA
current, (LPM3)(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 105°C 2 5
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.1 0.5
Low-power mode 4 fACLK = 0 Hz, 85°C 0.8 1.5
ILPM4 2.2 V µA
(LPM4) current(5) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 105°C 2 4
OSCOFF = 1
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 4. LPM3 Current vs Temperature Figure 5. LPM4 Current vs Temperature
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MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
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Schmitt-Trigger Inputs - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.45 VCC 0.75 VCC
VIT+ Positive-going input threshold voltage V
3 V 1.35 2.25
0.25 VCC 0.55 VCC
VIT- Negative-going input threshold voltage V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ - VIT-) 3 V 0.3 1 V
For pullup: VIN = VSS
RPull Pullup/pulldown resistor 3 V 20 35 50 kΩ
For pulldown: VIN = VCC
CIInput capacitance VIN = VSS or VCC 5 pF
Leakage Current - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current (1) (2) 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH High-level output voltage I(OHmax) = -6 mA(1) 3 V VCC - 0.3 V
VOL Low-level output voltage I(OLmax) = 6 mA(1) 3 V VSS + 0.3 V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Port output frequency
fPx.y Px.y, CL= 20 pF, RL= 1 kΩ(1) (2) 3 V 12 MHz
(with load)
fPort_CLK Clock output frequency Px.y, CL= 20 pF(2) 3 V 16 MHz
(1) A resistive divider with 2 ×0.5 kΩbetween VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
18 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOL − Low-Level Output Voltage − V
0
10
20
30
40
50
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7 TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOH − High-Level Output Voltage − V
−25
−20
−15
−10
−5
0
0 0.5 1 1.5 2 2.5
VCC = 2.2 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOH − High-Level Output Voltage − V
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5
VCC = 3 V
P1.7
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Typical Characteristics - Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 6. Figure 7.
Figure 8. Figure 9.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
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POR/Brownout Reset (BOR)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.7 ×
VCC(start) See Figure 10 dVCC/dt ≤3 V/s V
V(B_IT-)
V(B_IT-) See Figure 10 through Figure 12 dVCC/dt ≤3 V/s 1.35 V
Vhys(B_IT-) See Figure 10 dVCC/dt ≤3 V/s 130 mV
td(BOR) See Figure 10 2000 µs
Pulse length needed at RST/NMI pin to
t(reset) 2.2 V/3 V 2 µs
accepted reset internally
(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-)is ≤1.8 V.
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
20 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
VCC(drop)
VCC
3 V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − µs
VCC(drop) − V
tpw − Pulse Width − µs
VCC = 3 V
VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw − Pulse Width − µs
VCC(drop) − V
3 V
0.001 1 1000 tftr
tpw − Pulse Width − µs
tf= tr
Typical Conditions
VCC = 3 V
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Typical Characteristics - POR/Brownout Reset (BOR)
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 21
DCO(RSEL,DCO+1)
DCO(RSEL,DCO)
average DCO(RSEL,DCO) DCO(RSEL,DCO+1)
32 × f × f
f = MOD × f + (32 – MOD) × f
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Main DCO Characteristics
•All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
•DCO control bits DCOx have a step size as defined by parameter SDCO.
•Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
RSELx <14 1.8 3.6 V
VCC Supply voltage RSELx = 14 2.2 3.6 V
RSELx = 15 3 3.6 V
fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz
fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.12 MHz
fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3 V 0.15 MHz
fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3 V 0.21 MHz
fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3 V 0.3 MHz
fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3 V 0.41 MHz
fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3 V 0.58 MHz
fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3 V 0.8 MHz
fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3 V 0.8 1.5 MHz
fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3 V 1.6 MHz
fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3 V 2.3 MHz
fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3 V 3.4 MHz
fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3 V 4.25 MHz
fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3 V 4.3 7.3 MHz
fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3 V 7.8 MHz
fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3 V 8.6 13.9 MHz
fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 15.25 MHz
fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 21 MHz
Frequency step between
SRSEL range RSEL and SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3 V 1.35 ratio
RSEL+1
Frequency step between
SDCO SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3 V 1.08 ratio
tap DCO and DCO+1
Duty cycle Measured at SMCLK output 3 V 50 %
22 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
DCO Frequency − MHz
0.10
1.00
10.00
0.10 1.00 10.00
DCO Wake Time − µs
RSELx = 0...11
RSELx = 12...15
MSP430G2x11
MSP430G2x01
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SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Calibrated DCO Frequencies - Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT
BCSCTL1= CALBC1_1MHz, 0°C to 85°C
1-MHz tolerance over temperature(1) DCOCTL = CALDCO_1MHz, 3 V -3 ±0.5 +3 %
-40°C to 105°C
calibrated at 30°C and 3 V
BCSCTL1= CALBC1_1MHz,
1-MHz tolerance over VCC DCOCTL = CALDCO_1MHz, 30°C 1.8 V to 3.6 V -3 ±2 +3 %
calibrated at 30°C and 3 V
BCSCTL1= CALBC1_1MHz, -40°C to 85°C
1-MHz tolerance overall DCOCTL = CALDCO_1MHz, 1.8 V to 3.6 V -6 ±3 +6 %
-40°C to 105°C
calibrated at 30°C and 3 V
(1) This is the frequency change from the measured frequency at 30°C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4) Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DCO clock wake-up time from BCSCTL1= CALBC1_1MHz,
tDCO,LPM3/4 3 V 1.5 µs
LPM3/4(1) DCOCTL = CALDCO_1MHz 1/fMCLK +
tCPU,LPM3/4 CPU wake-up time from LPM3/4(2) tClock,LPM3/4
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4
Figure 13. DCO Wake-Up Time From LPM3 vs DCO Frequency
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 23
MSP430G2x11
MSP430G2x01
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Crystal Oscillator, XT1, Low-Frequency Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
LFXT1 oscillator crystal
fLFXT1,LF XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz
LF mode XTS = 0, LFXT1Sx = 0, 500
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF kΩ
LF crystals XTS = 0, LFXT1Sx = 0, 200
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 1
XTS = 0, XCAPx = 1 5.5
Integrated effective load
CL,eff pF
capacitance, LF mode(2) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 11
XTS = 0, Measured at P2.0/ACLK,
Duty cycle, LF mode 2.2 V 30 50 70 %
fLFXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0, XCAPx = 0, LFXT1Sx = 3(4) 2.2 V 10 10000 Hz
LF mode(3)
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TAVCC MIN TYP MAX UNIT
-40°C to 85°C 4 12 20
fVLO VLO frequency 3 V kHz
105°C 22
I: -40°C to 85°C
dfVLO/dTVLO frequency temperature drift 3 V 0.5 %/°C
T: -40°C to 105°C
dfVLO/dVCC VLO frequency supply voltage drift 25°C 1.8 V to 3.6 V 4 %/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK, ACLK
fTA Timer_A input clock frequency External: TACLK, INCLK fSYSTEM MHz
Duty cycle = 50% ±10%
tTA,cap Timer_A capture timing TA0, TA1 3 V 20 ns
24 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
CC
CC
Voltage @ 0.25 V node
V
CC
CC
Voltage @ 0.5 V node
V
MSP430G2x11
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SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Comparator_A+ (MSP430G2x11 only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I(DD) CAON = 1, CARSEL = 0, CAREF = 0 3 V 45 µA
CAON = 1, CARSEL = 0, CAREF = 1/2/3,
I(Refladder/RefDiode) 3 V 45 µA
No load at CA0 and CA1
V(IC) Common-mode input voltage CAON = 1 3 V 0 VCC-1 V
PCA0 = 1, CARSEL = 1, CAREF = 1,
V(Ref025) 3 V 0.24
No load at CA0 and CA1
PCA0 = 1, CARSEL = 1, CAREF = 2,
V(Ref050) 3 V 0.48
No load at CA0 and CA1
PCA0 = 1, CARSEL = 1, CAREF = 3,
V(RefVT) See Figure 14 and Figure 15 3 V 490 mV
No load at CA0 and CA1, TA = 85°C
V(offset) Offset voltage(1) 3 V ±10 mV
Vhys Input hysteresis CAON = 1 3 V 0.7 mV
TA= 25°C, Overdrive 10 mV, 120 ns
Without filter: CAF = 0
Response time
t(response) 3 V
(low-high and high-low) TA= 25°C, Overdrive 10 mV, 1.5 µs
With filter: CAF = 1
(1) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 25
T – Free-Air Temperature – °C
A
400
450
500
550
600
650
V = 3 V
CC
V – Reference Voltage – mV
(RefVT)
Typical
-45 -25 -5 15 35 55 75 95 115
400
450
500
550
600
650
V = 2.2 V
CC
Typical
T – Free-Air Temperature – °C
A
V – Reference Voltage – mV
(RefVT)
-45 -25 -5 15 35 55 75 95 115
V /V – Normalized Input Voltage – V/V
IN CC
1
10
100
0
Short Resistance – kW
V = 1.8 V
CC
V = 3.6 V
CC
V = 2.2 V
CC
V = 3 V
CC
0.2 0.4 0.6 0.8 1
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Typical Characteristics - Comparator_A+
Figure 14. V(RefVT) vs Temperature, VCC = 3 V Figure 15. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 16. Short Resistance vs VIN/VCC
26 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
PARAMETER VCC MIN TYP MAX UNIT
CONDITIONS
VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA
IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA
tCPT Cumulative program time(1) 2.2 V/3.6 V 10 ms
tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 ms
Program/erase endurance 104105cycles
tRetention Data retention duration TJ= 25°C 100 years
tWord Word or byte program time (2) 30 tFTG
tBlock, 0 Block program time for first byte or word (2) 25 tFTG
Block program time for each additional byte or
tBlock, 1-63 (2) 18 tFTG
word
tBlock, End Block program end-sequence wait time (2) 6 tFTG
tMass Erase Mass erase time (2) 10593 tFTG
tSeg Erase Segment erase time (2) 4819 tFTG
(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V(RAMh) RAM retention supply voltage (1) CPU halted 1.6 V
(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 27
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V/3 V 0.025 15 µs
Spy-Bi-Wire enable time
tSBW,En 2.2 V/3 V 1 µs
(TEST high to acceptance of first clock edge(1))
tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V/3 V 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency(2) 3 V 0 10 MHz
RInternal Internal pulldown resistance on TEST 2.2 V/3 V 25 60 90 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA= 25°C 2.5 V
VFB Voltage level on TEST for fuse blow 6 7 V
IFB Supply current into TEST during fuse blow 100 mA
tFB Time to blow fuse 1 ms
(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
28 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
To Module
From Timer
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
APPLICATION INFORMATION
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x01
Table 14. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x01
CONTROL BITS/SIGNALS
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x
P1.0/ P1.x (I/O) I: 0; O: 1 0
TA0CLK/ 0 TA0CLK 0 1
ACLK ACLK 1 1
P1.1/ P1.x (I/O) I: 0; O: 1 0
TA0.0 1 TA0.CCI0A 0 1
TA0.0 1 1
P1.2/ P1.x (I/O) I: 0; O: 1 0
TA0.1 2 TA0.CCI1A 0 1
TA0.1 1 1
P1.3 3 P1.x (I/O) I: 0; O: 1 0
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 29
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TDO/TDI
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x01
Table 15. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x01
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x JTAG Mode
P1.4/ P1.x (I/O) I: 0; O: 1 0 0
SMCLK/ 4 SMCLK 1 1 0
TCK TCK X X 1
P1.5/ P1.x (I/O) I: 0; O: 1 0 0
TA0.0/ 5 TA0.0 1 1 0
TMS TMS X X 1
P1.6/ P1.x (I/O) I: 0; O: 1 0 0
TA0.1/ 6 TA0.1 1 1 0
TDI/TCLK TDI/TCLK X X 1
P1.7/ P1.x (I/O) I: 0; O: 1 0 0
7
TDO/TDI TDO/TDI X X 1
(1) X = Don't care
30 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
To Module
ACLK
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
To Comparator
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From Comparator
CAPD.y
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x11
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 31
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Table 16. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x11
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x CAPD.y
P1.0/ P1.x (I/O) I: 0; O: 1 0 0
TA0CLK/ TA0.TACLK 0 1 0
0
ACLK/ ACLK 1 1 0
CA0 CA0 X X 1 (y = 0)
P1.1/ P1.x (I/O) I: 0; O: 1 0 0
TA0.0/ TA0.0 1 1 0
1TA0.CCI0A 0 1 0
CA1 CA1 X X 1 (y = 1)
P1.2/ P1.x (I/O) I: 0; O: 1 0 0
TA0.1/ TA0.1 1 1 0
2TA0.CCI1A 0 1 0
CA2 CA2 X X 1 (y = 2)
P1.3/ P1.x (I/O) I: 0; O: 1 0 0
CAOUT/ 3 CAOUT 1 1 0
CA3 CA3 X X 1 (y = 3)
(1) X = Don't care
32 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
1
0
PxIN.y
PxSEL.y
PxREN.y
1
0
From Comparator
To Comparator
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.y
0
1
From JTAG
To JTAG
CAPD.y
P1.4/SMCLK/CA4/TCK
P1.5/TA0.0/CA5/TMS
P1.6/TA0.1/CA6/TDI/TCLK
P1.7/CAOUT/CA7/TDO/TDI
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x11
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 33
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Table 17. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x11
CONTROL BITS / SIGNALS(1)
PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x JTAG Mode CAPD.y
P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0
SMCLK/ SMCLK 1 1 0 0
4
CA4/ CA4 X X 0 1 (y = 4)
TCK TCK X X 1 0
P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0
TA0.0/ TA0.0 1 1 0 0
5
CA5/ CA5 X X 0 1 (y = 5)
TMS TMS X X 1 0
P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0
TA0.1/ TA0.1 1 1 0 0
6
CA6/ CA6 X X 0 1 (y = 6)
TDI/TCLK TDI/TCLK X X 1 0
P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0
CAOUT/ CAOUT 1 1 0 0
7
CA7/ CA7 X X 0 1 (y = 7)
TDO/TDI TDO/TDI X X 1 0
(1) X = Don't care
34 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
XIN/P2.6/TA0.1
1
0
XOUT/P2.7
LF off
LFXT1CLK
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.6
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.6
0
1
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger - MSP430G2x01 and
MSP430G2x11
Table 18. Port P2 (P2.6) Pin Functions - MSP430G2x01 and MSP430G2x11
CONTROL BITS / SIGNALS(1)
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL.7
XIN XIN 0 1 1
P2.6 6 P2.x (I/O) I: 0; O: 1 0 X
TA0.1 Timer0_A2.TA1 1 1 X
(1) X = Don't care
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 35
XIN/P2.6/TA0.1
1
0
XOUT/P2.7
LF off
LFXT1CLK
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
To Module
From Module
PxOUT.y
DV
SS
DV
CC
1
Bus
Keeper
EN
1
0
PxIN.y
PxSEL.7
PxREN.y
1
0
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
PxSEL.7
0
1
from P2.6/XIN
MSP430G2x11
MSP430G2x01
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
www.ti.com
Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger - MSP430G2x01 and
MSP430G2x11
Table 19. Port P2 (P2.7) Pin Functions - MSP430G2x01 and MSP430G2x11
CONTROL BITS / SIGNALS
PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL.7
XOUT XOUT 1 1 1
7
P2.7 P2.x (I/O) I: 0; O: 1 0 0
36 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
MSP430G2x11
MSP430G2x01
www.ti.com
SLAS695G –FEBRUARY 2010–REVISED DECEMBER 2011
REVISION HISTORY
REVISION DESCRIPTION
SLAS695 Limited Product Preview release
Updated Product Preview
SLAS695A Changes throughout for sampling
SLAS695B Updated Product Preview
SLAS695C Production Data release
Table 14, Corrected P1DIR.x column for TA0.0 and TA0.1.
SLAS695D Table 18, Corrected FUNCTION column for TA0.1.
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger –MSP430G2x11, Corrected schematic.
Changed Storage temperature range limits in Absolute Maximum Ratings.
SLAS695E Table 15, Removed CAPD.y column.
Table 19, Corrected Control Bits/Signals.
Changed Tstg, Programmed device, to -55°C to 150°C in Absolute Maximum Ratings.
SLAS695F Changed fSYSTEM MAX at VCC = 1.8 V from 4.15 to 6 MHz in Recommended Operating Conditions.
SLAS695G Changed port schematics (added buffer after PxOUT.y mux) in APPLICATION INFORMATION
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 37
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430G2001IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM
MSP430G2001IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2001IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2001IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2001IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2101IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM
MSP430G2101IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2101IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2101IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2101IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2111IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM
MSP430G2111IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2111IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2111IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2111IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2201IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM
MSP430G2201IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2201IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2201IRSA16 OBSOLETE QFN RSA 16 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430G2201IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2201IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2211IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM
MSP430G2211IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2211IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
MSP430G2211IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MSP430G2211IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2001, MSP430G2101, MSP430G2111, MSP430G2201, MSP430G2211 :
•Automotive: MSP430G2001-Q1, MSP430G2101-Q1, MSP430G2111-Q1, MSP430G2201-Q1, MSP430G2211-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430G2001IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2001IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2001IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2101IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2101IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2101IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2111IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2111IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2111IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2201IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2201IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2201IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2211IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MSP430G2211IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
MSP430G2211IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430G2001IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2001IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2001IRSA16T QFN RSA 16 250 210.0 185.0 35.0
MSP430G2101IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2101IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2101IRSA16T QFN RSA 16 250 210.0 185.0 35.0
MSP430G2111IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2111IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2111IRSA16T QFN RSA 16 250 210.0 185.0 35.0
MSP430G2201IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2201IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2201IRSA16T QFN RSA 16 250 210.0 185.0 35.0
MSP430G2211IPW14R TSSOP PW 14 2000 367.0 367.0 35.0
MSP430G2211IRSA16R QFN RSA 16 3000 367.0 367.0 35.0
MSP430G2211IRSA16T QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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