MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 * * 2 * * * * Low Supply-Voltage Range: 1.8 V to 3.6 V Ultralow Power Consumption - Active Mode: 220 A at 1 MHz, 2.2 V - Standby Mode: 0.5 A - Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Ultrafast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations - Internal Frequencies up to 16 MHz With One Calibrated Frequency - Internal Very Low Power Low-Frequency (LF) Oscillator - 32-kHz Crystal - External Digital Clock Source * * * * * * * * 16-Bit Timer_A With Two Capture/Compare Registers Brownout Detector On-Chip Comparator for Analog Signal Compare Function or Slope A/D (See Table 1) Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface For Family Members Details, See Table 1 Available in a 14-Pin Plastic Small-Outline Thin Package (TSSOP) (PW), 14-Pin Plastic Dual Inline Package (PDIP) (N), and 16-Pin QFN (RSA) For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144) DESCRIPTION The Texas Instruments MSP430TM family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430G2x01/MSP430G2x11 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O pins. The MSP430G2x11 family members have a versatile analog comparator. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Table 1. Available Options (1) BSL EEM Flash (KB) RAM (B) Timer_A Comp_A+ Channel Clock I/O Package Type (2) MSP430G2211IRSA16 MSP430G2211IPW14 MSP430G2211IN14 - 1 2 128 1x TA2 8 LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2201IRSA16 MSP430G2201IPW14 MSP430G2201IN14 - 1 2 128 1x TA2 - LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2111IRSA16 MSP430G2111IPW14 MSP430G2111IN14 - 1 1 128 1x TA2 8 LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2101IRSA16 MSP430G2101IPW14 MSP430G2101IN14 - 1 1 128 1x TA2 - LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2001IRSA16 MSP430G2001IPW14 MSP430G2001IN14 - 1 0.5 128 1x TA2 - LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP Device (1) (2) 2 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Device Pinout, MSP430G2x01 N or PW PACKAGE (TOP VIEW) DVCC P1.0/TA0CLK/ACLK 1 14 2 13 P1.1/TA0.0 P1.2/TA0.1 P1.3 P1.4/SMCLK/TCK 3 12 4 11 5 10 6 9 P1.5/TA0.0/TMS 7 8 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/TDO/TDI P1.6/TA0.1/TDI/TCLK NOTE: See port schematics in Application Information for detailed I/O information. NC DVSS NC DVCC RSA PACKAGE (TOP VIEW) 2 11 XOUT/P2.7 P1.2/TA0.1 3 10 TEST/SBWTCK P1.3 4 9 RST/NMI/SBWTDIO 5 6 7 8 P1.7/TDO/TDI P1.1/TA0.0 P1.5/TA0.0/TMS 16 15 14 13 12 P1.6/TA0.1/TDI/TCLK 1 P1.4/SMCLK/TCK P1.0/TA0CLK/ACLK XIN/P2.6/TA0.1 NOTE: See port schematics in Application Information for detailed I/O information. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 3 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Device Pinout, MSP430G2x11 N or PW PACKAGE (TOP VIEW) DVCC P1.0/TA0CLK/ACLK/CA0 1 14 2 13 P1.1/TA0.0/CA1 P1.2/TA0.1/CA2 P1.3/CAOUT/CA3 P1.4/SMCLK/CA4/TCK 3 12 4 11 5 10 6 9 P1.5/TA0.0/CA5/TMS 7 8 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/CA7/TDO/TDI P1.6/TA0.1/CA6/TDI/TCLK NOTE: See port schematics in Application Information for detailed I/O information. NC DVSS NC DVCC RSA PACKAGE (TOP VIEW) 16 15 14 13 P1.1/TA0.0/CA1 2 11 XOUT/P2.7 P1.2/TA0.1/CA2 3 10 TEST/SBWTCK P1.3/CAOUT/CA3 4 9 RST/NMI/SBWTDIO 5 6 7 8 P1.6/TA0.1/CA6/TDI/TCLK XIN/P2.6/TA0.1 P1.7/CAOUT/CA7/TDO/TDI 12 P1.5/TA0.0/CA5/TMS 1 P1.4/SMCLK/CA4/TCK P1.0/TA0CLK/ACLK/CA0 NOTE: See port schematics in Application Information for detailed I/O information. 4 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Functional Block Diagram, MSP430G2x11 DVCC XOUT XIN DVSS P1.x P2.x 8 2 Port P1 Port P2 8 I/O Interrupt capability pullup/down resistors 2 I/O Interrupt capability pullup/down resistors ACLK Clock System SMCLK Flash 2KB 1KB MCLK 16MHz CPU MAB incl. 16 Registers MDB Emulation 2BP RAM 128B Comp_A+ Brownout Protection JTAG Interface 8 Channels Watchdog WDT+ 15-Bit Timer0_A2 2 CC Registers Spy-Bi Wire RST/NMI Functional Block Diagram, MSP430G2x01 XIN XOUT DVCC DVSS P1.x P2.x 8 2 Port P1 Port P2 8 I/O Interrupt capability pull-up/down resistors 2 I/O Interrupt capability pull-up/down resistors ACLK Clock System MCLK SMCLK Flash RAM 2KB 1KB 0.5KB 16MHz CPU MAB incl. 16 Registers MDB Emulation 2BP JTAG Interface Brownout Protection 128B Watchdog WDT+ 15-Bit Timer0_A2 2 CC Registers Spy-Bi Wire RST/NMI Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 5 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME 14 N, PW I/O DESCRIPTION 16 RSA P1.0/ General-purpose digital I/O pin TA0CLK/ 2 ACLK/ 1 I/O Timer0_A, clock signal TACLK input ACLK signal output Comparator_A+, CA0 input (1) CA0 P1.1/ General-purpose digital I/O pin TA0.0/ 3 2 I/O Timer0_A, capture: CCI0A input, compare: Out0 output CA1 Comparator_A+, CA1 input (1) P1.2/ General-purpose digital I/O pin TA0.1/ 4 3 I/O Timer0_A, capture: CCI1A input, compare: Out1 output Comparator_A+, CA2 input (1) CA2 P1.3/ General-purpose digital I/O pin CA3/ 5 4 I/O Comparator_A+, CA3 input (1) CAOUT Comparator_A+, output (1) P1.4/ General-purpose digital I/O pin SMCLK/ 6 CA4/ 5 I/O SMCLK signal output Comparator_A+, CA4 input (1) TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ 7 CA5/ 6 I/O Timer0_A, compare: Out0 output Comparator_A+, CA5 input (1) TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin TA0.1/ 8 CA6/ 7 I/O Timer0_A, compare: Out1 output Comparator_A+, CA6 input (1) TDI/TCLK JTAG test data input or test clock input during programming and test P1.7/ General-purpose digital I/O pin CA7/ 9 CAOUT/ TDO/TDI 8 I/O (2) CA7 input (1) Comparator_A+, output (1) JTAG test data output terminal or test data input during programming and test XIN/ Input terminal of crystal oscillator P2.6/ 13 12 I/O TA0.1 General-purpose digital I/O pin Timer0_A, compare: Out1 output XOUT/ P2.7 12 11 I/O 10 9 I RST/ Output terminal of crystal oscillator (3) General-purpose digital I/O pin Reset NMI/ SBWTDIO TEST/ Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. 11 10 I DVCC 1 16 NA Supply voltage DVSS 14 14 NA Ground reference NC - 15 NA Not connected QFN Pad - Pad NA QFN package pad connection to VSS recommended. SBWTCK (1) (2) (3) 6 Spy-Bi-Wire test clock input during programming and test MSP430G2x11 only TDO or TDI is selected via JTAG instruction. If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 3. Instruction Word Formats EXMPLE OPERATION Dual operands, source-destination INSTRUCTION FORMAT ADD R4,R5 R4 + R5 --> R5 Single operands, destination only CALL R8 PC ->(TOS), R8-> PC JNE Jump-on-equal bit = 0 Relative jump, un/conditional Table 4. Address Mode Descriptions (1) (1) ADDRESS MODE S D SYNTAX EXAMPLE Register MOV Rs,Rd MOV R10,R11 OPERATION R10 - -> R11 Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) - -> M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) - -> M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) - -> M(TCDAT) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) - -> M(Tab+R6) Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) - -> R11 R10 + 2- -> R10 Immediate MOV #X,TONI MOV #45,TONI #45 - -> M(TONI) S = source, D = destination Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 7 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Operating Modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: * Active mode (AM) - All clocks are active * Low-power mode 0 (LPM0) - CPU is disabled - ACLK and SMCLK remain active, MCLK is disabled * Low-power mode 1 (LPM1) - CPU is disabled - ACLK and SMCLK remain active, MCLK is disabled - DCO's dc generator is disabled if DCO not used in active mode * Low-power mode 2 (LPM2) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator remains enabled - ACLK remains active * Low-power mode 3 (LPM3) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - ACLK remains active * Low-power mode 4 (LPM4) - CPU is disabled - ACLK is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - Crystal oscillator is stopped 8 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go into LPM4 immediately after power-up. Table 5. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) PORIFG RSTIFG WDTIFG KEYV (2) NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (2) (3) Comparator_A+ CAIFG (4) (5) Watchdog Timer+ WDTIFG Timer_A2 Timer_A2 I/O Port P2 (two flags) I/O Port P1 (eight flags) See (1) (2) (3) (4) (5) (6) TACCR0 CCIFG (4) TACCR1 CCIFG, TAIFG (2) (4) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 31, highest (non)-maskable (non)-maskable (non)-maskable 0FFFCh 30 0FFFAh 29 0FFF8h 28 0FFF6h 27 maskable 0FFF4h 26 maskable 0FFF2h 25 maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 0FFEAh 21 0FFE8h 20 P2IFG.6 to P2IFG.7 (2) (4) maskable 0FFE6h 19 (2) (4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 0FFDEh to 0FFC0h 15 to 0, lowest P1IFG.0 to P1IFG.7 (6) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. Devices with Comparator_A+ only The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 9 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device. Table 6. Interrupt Enable Register 1 and 2 Address 7 6 00h WDTIE OFIE NMIIE ACCVIE Address 5 4 1 0 ACCVIE NMIIE 3 2 OFIE WDTIE rw-0 rw-0 rw-0 rw-0 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 3 2 1 0 01h Table 7. Interrupt Flag Register 1 and 2 Address 7 6 5 02h WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault. Power-On Reset interrupt flag. Set on VCC power-up. External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. Set via RST/NMI pin 7 6 5 4 3 2 1 0 03h 10 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Memory Organization Table 8. Memory Organization MSP430G2001 MSP430G2011 MSP430G2101 MSP430G2111 MSP430G2201 MSP430G2211 Size 512B 1kB 2kB Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 Main: code memory Flash 0xFFFF to 0xFE00 0xFFFF to 0xFC00 0xFFFF to 0xF800 Information memory Size 256 Byte 256 Byte 256 Byte Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h Memory RAM Peripherals Size 128B 128B 128B 027Fh to 0200h 027Fh to 0200h 027Fh to 0200h 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0Fh to 00h 0Fh to 00h 0Fh to 00h 8-bit SFR Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory. * Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 11 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1s. The basic clock module provides the following clock signals: * Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator. * Main clock (MCLK), the system clock used by the CPU. * Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. Table 9. DCO Calibration Data (Provided From Factory In Flash Information Memory Segment A) DCO FREQUENCY 1 MHz CALIBRATION REGISTER SIZE CALBC1_1MHZ byte 010FFh CALDCO_1MHZ byte 010FEh ADDRESS Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Digital I/O There is one 8-bit I/O port implemented--port P1--and two bits of I/O port P2: * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt condition is possible. * Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2. * Read/write access to port-control registers is supported by all instructions. * Each I/O has an individually programmable pullup/pulldown resistor. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. 12 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 10. Timer_A2 Signal Connections - Devices With No Analog INPUT PIN NUMBER PW, N RSA DEVICE INPUT SIGNAL 2 - P1.0 1 - P1.0 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER PW, N RSA 2 - P1.0 1 - P1.0 TACLK INCLK 3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1 ACLK (internal) CCI0B 7 - P1.5 6 - P1.5 VSS GND 4 - P1.2 3 - P1.2 CCR0 TA0 VCC VCC TA1 CCI1A 4 - P1.2 3 - P1.2 TA1 CCI1B 8 - P1.6 7 - P1.6 VSS GND 13 - P2.6 12 - P2.6 VCC VCC CCR1 TA1 Table 11. Timer_A2 Signal Connections - Devices With Comparator_A+ INPUT PIN NUMBER PW, N RSA DEVICE INPUT SIGNAL MODULE INPUT NAME 2 - P1.0 1 - P1.0 TACLK TACLK ACLK ACLK SMCLK SMCLK 2 - P1.0 1 - P1.0 TACLK INCLK 3 - P1.1 2 - P1.1 TA0 CCI0A ACLK (internal) CCI0B VSS GND VCC VCC 4 - P1.2 3 - P1.2 TA1 CCI1A CAOUT (internal) CCI1B VSS GND VCC VCC MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA CCR0 CCR1 TA0 TA1 OUTPUT PIN NUMBER PW, N RSA 3 - P1.1 2 - P1.1 7 - P1.5 6 - P1.5 4 - P1.2 3 - P1.2 8 - P1.6 7 - P1.6 13 - P2.6 12 - P2.6 Comparator_A+ (MSP430G2x11 Only) The primary function of the comparator_A+module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 13 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Peripheral File Map Table 12. Peripherals With Word Access MODULE Timer_A Flash Memory Watchdog Timer+ REGISTER NAME REGISTER DESCRIPTION OFFSET Capture/compare register TACCR1 0174h Capture/compare register TACCR0 0172h Timer_A register TAR 0170h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Watchdog/timer control WDTCTL 0120h Table 13. Peripherals With Byte Access MODULE Comparator_A+ (MSP430G2x11 only) Basic Clock System+ Port P2 Port P1 Special Function 14 Submit Documentation Feedback REGISTER DESCRIPTION REGISTER NAME OFFSET Comparator_A+ port disable CAPD 05Bh Comparator_A+ control 2 CACTL2 05Ah Comparator_A+ control 1 CACTL1 059h Basic clock system control 3 BCSCTL3 053h Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h Port P2 resistor enable P2REN 02Fh Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V 2 mA Diode current at any device pin Storage temperature range, Tstg (3) Unprogrammed device -55C to 150C Programmed device -55C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. (1) (2) (3) Recommended Operating Conditions MIN VCC Supply voltage VSS Supply voltage TA Operating free-air temperature (1) (2) MAX During program execution 1.8 3.6 During flash program/erase 2.2 3.6 0 Processor frequency (maximum MCLK frequency) (1) (2) fSYSTEM NOM UNIT V V I version -40 85 T version -40 105 VCC = 1.8 V, Duty cycle = 50% 10% dc 6 VCC = 2.7 V, Duty cycle = 50% 10% dc 12 VCC 3.3 V, Duty cycle = 50% 10% dc 16 C MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. Legend : System Frequency - MHz 16 MHz Supply voltage range, during flash memory programming 12 MHz Supply voltage range, during program execution 6 MHz 1.8 V Note: 2.7 V 2.2 V Supply Voltage - V 3.3 V 3.6 V Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Safe Operating Area Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 15 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER Active mode (AM) current (1 MHz) IAM,1MHz (1) (2) TEST CONDITIONS TA fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 32768 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 VCC MIN TYP 2.2 V 220 3V 300 MAX UNIT A 370 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Typical Characteristics - Active Mode Supply Current (Into VCC) 5.0 4.0 Active Mode Current - mA Active Mode Current - mA f DCO = 16 MHz 4.0 3.0 f DCO = 12 MHz 2.0 f DCO = 8 MHz 1.0 TA = 85 C 3.0 TA = 25 C VCC = 3 V 2.0 TA = 85 C TA = 25 C 1.0 f DCO = 1 MHz 0.0 1.5 2.0 2.5 3.0 3.5 VCC = 2.2 V 4.0 VCC - Supply Voltage - V Figure 2. Active Mode Current vs VCC, TA = 25C 16 Submit Documentation Feedback 0.0 0.0 4.0 8.0 12.0 16.0 f DCO - DCO Frequency - MHz Figure 3. Active Mode Current vs DCO Frequency Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 ILPM2 Low-power mode 2 (LPM2) current (4) fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 ILPM3,LFXT1 Low-power mode 3 (LPM3) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 ILPM3,VLO Low-power mode 3 current, (LPM3) (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 ILPM4 Low-power mode 4 (LPM4) current (5) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 ILPM0,1MHz (1) (2) (3) (4) (5) TA VCC 25C 2.2 V MIN (2) TYP MAX UNIT A 65 25C 22 2.2 V 105C 25C 2.2 V 105C 25C 2.2 V 105C 25C 85C A 31 2.2 V 105C 0.7 1.5 3 6 0.5 0.7 2 5 0.1 0.5 0.8 1.5 2 4 A A A All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Typical Characteristics Low-Power Mode Supply Currents 3.00 2.50 2.75 2.25 ILPM4 - Low-Power Mode Current - A ILPM3 - Low-Power Mode Current - A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 2.50 2.25 2.00 1.75 1.50 Vcc = 3.6 V 1.25 Vcc = 3 V 1.00 Vcc = 2.2 V 0.75 0.50 Vcc = 1.8 V 0.25 0.00 -40 -20 0 20 40 60 TA - Temperature - C Figure 4. LPM3 Current vs Temperature Copyright (c) 2010-2011, Texas Instruments Incorporated 80 2.00 1.75 1.50 1.25 Vcc = 3.6 V 1.00 Vcc = 3 V 0.75 Vcc = 2.2 V 0.50 0.25 0.00 -40 Vcc = 1.8 V -20 0 20 40 60 80 TA - Temperature - C Figure 5. LPM4 Current vs Temperature Submit Documentation Feedback 17 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Schmitt-Trigger Inputs - Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT-) VCC MIN RPull Pullup/pulldown resistor CI Input capacitance VIN = VSS or VCC MAX 0.45 VCC 0.75 VCC 1.35 2.25 3V For pullup: VIN = VSS For pulldown: VIN = VCC TYP UNIT V 0.25 VCC 0.55 VCC 3V 0.75 1.65 3V 0.3 1 V 3V 20 50 k 35 5 V pF Leakage Current - Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.x) (1) (2) TEST CONDITIONS VCC (1) (2) High-impedance leakage current MIN 3V MAX UNIT 50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Outputs - Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH High-level output voltage I(OHmax) = -6 mA (1) 3V VCC - 0.3 V VOL Low-level output voltage I(OLmax) = 6 mA (1) 3V VSS + 0.3 V (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified. Output Frequency - Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fPx.y Port output frequency (with load) Px.y, CL = 20 pF, RL = 1 k fPort_CLK Clock output frequency Px.y, CL = 20 pF (2) (1) (2) 18 (1) (2) VCC MIN TYP MAX UNIT 3V 12 MHz 3V 16 MHz A resistive divider with 2 x 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Typical Characteristics - Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 50 VCC = 2.2 V P1.7 TA = 25C 25 TA = 85C 20 15 10 5 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 30 0 VCC = 3 V P1.7 TA = 25C 40 TA = 85C 30 20 10 0 0 0.5 1 1.5 2 2.5 0 VOL - Low-Level Output Voltage - V 0.5 1 1.5 Figure 6. 2.5 3 3.5 3 3.5 Figure 7. 0 0 VCC = 2.2 V P1.7 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA 2 VOL - Low-Level Output Voltage - V -5 -10 -15 TA = 85C -20 TA = 25C -25 0 0.5 VCC = 3 V P1.7 -10 -20 -30 TA = 85C -40 TA = 25C -50 1 1.5 2 VOH - High-Level Output Voltage - V Figure 8. Copyright (c) 2010-2011, Texas Instruments Incorporated 2.5 0 0.5 1 1.5 2 2.5 VOH - High-Level Output Voltage - V Figure 9. Submit Documentation Feedback 19 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com POR/Brownout Reset (BOR) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 10 dVCC/dt 3 V/s 0.7 x V(B_IT-) V(B_IT-) See Figure 10 through Figure 12 dVCC/dt 3 V/s 1.35 V Vhys(B_IT-) See Figure 10 dVCC/dt 3 V/s 130 mV td(BOR) See Figure 10 t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (1) V 2000 2.2 V/3 V 2 s s The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-)is 1.8 V. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage 20 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Typical Characteristics - POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw - Pulse Width - s 1 ns t pw - Pulse Width - s Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 t f = tr 1 t pw - Pulse Width - s 1000 tf tr t pw - Pulse Width - s Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 21 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Main DCO Characteristics * * * All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 x fDCO(RSEL,DCO) x fDCO(RSEL,DCO+1) MOD x fDCO(RSEL,DCO) + (32 - MOD) x fDCO(RSEL,DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V RSELx = 14 2.2 3.6 V RSELx = 15 3 3.6 V 0.14 MHz fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3V fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3V 0.12 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3V 0.15 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3V 0.21 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3V 0.3 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3V 0.41 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3V 0.58 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3V 0.8 fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3V fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3V 1.6 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3V 2.3 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3V 3.4 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3V 4.25 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3V fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3V fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3V fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 15.25 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 21 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3V 1.35 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3V 1.08 ratio Duty cycle Measured at SMCLK output 3V 50 22 Submit Documentation Feedback 0.06 0.8 MHz 1.5 4.3 7.3 7.8 8.6 MHz MHz MHz 13.9 MHz % Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Calibrated DCO Frequencies - Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature (1) BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, calibrated at 30C and 3 V 0C to 85C -40C to 105C 3V -3 0.5 +3 % 1-MHz tolerance over VCC BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, calibrated at 30C and 3 V 30C 1.8 V to 3.6 V -3 2 +3 % 1-MHz tolerance overall BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz, calibrated at 30C and 3 V -40C to 85C -40C to 105C 1.8 V to 3.6 V -6 3 +6 % (1) This is the frequency change from the measured frequency at 30C over temperature. Wake-Up From Lower-Power Modes (LPM3/4) Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tDCO,LPM3/4 DCO clock wake-up time from LPM3/4 (1) tCPU,LPM3/4 CPU wake-up time from LPM3/4 (2) (1) (2) VCC BCSCTL1= CALBC1_1MHz, DCOCTL = CALDCO_1MHz MIN 3V TYP MAX UNIT 1.5 s 1/fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 DCO Wake Time - s 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency - MHz Figure 13. DCO Wake-Up Time From LPM3 vs DCO Frequency Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 23 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode OALF Oscillation allowance for LF crystals Integrated effective load capacitance, LF mode (2) CL,eff fFault,LF (1) (2) (3) (4) XTS = 0, LFXT1Sx = 0 or 1 VCC MIN TYP 1.8 V to 3.6 V 1.8 V to 3.6 V MAX 32768 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF 500 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF 200 UNIT Hz 50000 Hz k XTS = 0, XCAPx = 0 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Duty cycle, LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz 2.2 V 30 Oscillator fault frequency, LF mode (3) XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4) 2.2 V 10 50 pF 70 % 10000 Hz To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fVLO VLO frequency dfVLO/dT VLO frequency temperature drift TA -40C to 85C 105C dfVLO/dVCC VLO frequency supply voltage drift VCC MIN TYP MAX 4 12 20 3V I: -40C to 85C T: -40C to 105C 3V 25C 1.8 V to 3.6 V 22 UNIT kHz 0.5 %/C 4 %/V Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A input clock frequency Internal: SMCLK, ACLK External: TACLK, INCLK Duty cycle = 50% 10% tTA,cap Timer_A capture timing TA0, TA1 24 Submit Documentation Feedback VCC MIN TYP fSYSTEM 3V 20 MAX UNIT MHz ns Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Comparator_A+ (MSP430G2x11 only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT I(DD) CAON = 1, CARSEL = 0, CAREF = 0 3V 45 A I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at CA0 and CA1 3V 45 A V(IC) CAON = 1 3V Common-mode input voltage 0 VCC-1 V V(Ref025) Voltage @ 0.25 VCC node VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at CA0 and CA1 3V 0.24 V(Ref050) Voltage @ 0.5 VCC node VCC PCA0 = 1, CARSEL = 1, CAREF = 2, No load at CA0 and CA1 3V 0.48 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at CA0 and CA1, TA = 85C 3V 490 mV 3V 10 mV 3V 0.7 mV 120 ns 1.5 s V(RefVT) See Figure 14 and Figure 15 V(offset) Offset voltage (1) Vhys Input hysteresis t(response) (1) Response time (low-high and high-low) CAON = 1 TA = 25C, Overdrive 10 mV, Without filter: CAF = 0 TA = 25C, Overdrive 10 mV, With filter: CAF = 1 3V The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 25 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Typical Characteristics - Comparator_A+ 650 650 VCC = 2.2 V V(RefVT) - Reference Voltage - mV V(RefVT) - Reference Voltage - mV VCC = 3 V 600 Typical 550 500 450 400 -45 600 Typical 550 500 450 400 -25 -5 15 35 55 75 TA - Free-Air Temperature - C 95 -45 115 Figure 14. V(RefVT) vs Temperature, VCC = 3 V -25 -5 15 35 55 75 TA - Free-Air Temperature - C 95 115 Figure 15. V(RefVT) vs Temperature, VCC = 2.2 V Short Resistance - kW 100 VCC = 1.8 V VCC = 2.2 V VCC = 3 V 10 VCC = 3.6 V 1 0 0.2 0.4 0.6 0.8 1 VIN/VCC - Normalized Input Voltage - V/V Figure 16. Short Resistance vs VIN/VCC 26 Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA tCPT Cumulative program time (1) 2.2 V/3.6 V 10 ms tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 4 Program/erase endurance 10 ms 5 10 cycles tRetention Data retention duration TJ = 25C tWord Word or byte program time (2) 30 tFTG tBlock, 0 Block program time for first byte or word (2) 25 tFTG tBlock, 1-63 Block program time for each additional byte or word (2) 18 tFTG tBlock, End Block program end-sequence wait time (2) 6 tFTG tMass Erase Mass erase time (2) 10593 tFTG tSeg Erase Segment erase time (2) 4819 tFTG (1) (2) 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) CPU halted MIN MAX 1.6 UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 27 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V/3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V/3 V 0.025 15 s tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.2 V/3 V 1 s tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V/3 V 15 100 2.2 V 0 5 MHz 3V 0 10 MHz 2.2 V/3 V 25 90 k fTCK TCK input frequency (2) RInternal Internal pulldown resistance on TEST (1) (2) 60 s Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow IFB Supply current into TEST during fuse blow tFB Time to blow fuse (1) 28 TEST CONDITIONS TA = 25C MIN MAX 2.5 6 UNIT V 7 V 100 mA 1 ms Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x01 PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y DVSS 0 DVCC 1 1 0 1 From Timer P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3 PxIN.y To Module PxIE.y PxIRQ.y EN Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Table 14. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x01 PIN NAME (P1.x) x P1.0/ TA0CLK/ 0 FUNCTION P1DIR.x P1SEL.x P1.x (I/O) I: 0; O: 1 0 TA0CLK 0 1 ACLK ACLK P1.1/ P1.x (I/O) TA0.0 1 TA0.CCI0A TA0.0 P1.2/ TA0.1 P1.3 3 1 1 I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 TA0.CCI1A 0 1 TA0.1 1 1 I: 0; O: 1 0 P1.x (I/O) 2 CONTROL BITS/SIGNALS P1.x (I/O) Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 29 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x01 PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y 0 From Module 1 DVSS 0 DVCC 1 1 P1.4/SMCLK/TCK P1.5/TA0.0/TMS P1.6/TA0.1/TDI/TCLK P1.7/TDO/TDI PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y From JTAG To JTAG Table 15. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x01 PIN NAME (P1.x) x P1.4/ FUNCTION P1.x (I/O) SMCLK/ 4 SMCLK TCK TCK P1.5/ P1.x (I/O) TA0.0/ 5 TA0.0 TMS TMS P1.6/ P1.x (I/O) TA0.1/ 6 TDI/TCLK P1.7/ TDO/TDI (1) 30 7 CONTROL BITS / SIGNALS (1) P1DIR.x P1SEL.x JTAG Mode I: 0; O: 1 0 0 1 1 0 X X 1 I: 0; O: 1 0 0 1 1 0 X X 1 I: 0; O: 1 0 0 TA0.1 1 1 0 TDI/TCLK X X 1 P1.x (I/O) I: 0; O: 1 0 0 TDO/TDI X X 1 X = Don't care Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x11 To Comparator From Comparator CAPD.y PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y 0 ACLK 1 DVSS 0 DVCC 1 Bus Keeper EN 1 P1.0/TA0CLK/ACLK/CA0 P1.1/TA0.0/CA1 P1.2/TA0.1/CA2 P1.3/CAOUT/CA3 PxIN.y To Module PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 31 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Table 16. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x11 PIN NAME (P1.x) x FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x P1SEL.x CAPD.y P1.0/ P1.x (I/O) I: 0; O: 1 0 0 TA0CLK/ TA0.TACLK 0 1 0 ACLK 1 1 0 CA0 CA0 X X 1 (y = 0) P1.1/ P1.x (I/O) I: 0; O: 1 0 0 TA0.0/ TA0.0 1 1 0 TA0.CCI0A 0 1 0 ACLK/ 0 1 CA1 CA1 P1.2/ P1.x (I/O) TA0.1/ TA0.1 2 CA2 P1.3/ CA3 (1) 32 3 X 1 (y = 1) 0 0 1 1 0 TA0.CCI1A 0 1 0 CA2 X X 1 (y = 2) P1.x (I/O) CAOUT/ X I: 0; O: 1 I: 0; O: 1 0 0 CAOUT 1 1 0 CA3 X X 1 (y = 3) X = Don't care Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x11 To Comparator From Comparator CAPD.y PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y From Module DVSS 0 DV CC 1 1 0 1 P1.4/SMCLK/CA4/TCK P1.5/TA0.0/CA5/TMS P1.6/TA0.1/CA6/TDI/TCLK P1.7/CAOUT/CA7/TDO/TDI PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select From JTAG To JTAG Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 33 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Table 17. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x11 PIN NAME (P1.x) x FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x P1SEL.x JTAG Mode CAPD.y 0 P1.4/ P1.x (I/O) I: 0; O: 1 0 0 SMCLK/ SMCLK 1 1 0 0 CA4 X X 0 1 (y = 4) TCK TCK X X 1 0 P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0.0/ TA0.0 1 1 0 0 CA5 X X 0 1 (y = 5) CA4/ 4 5 CA5/ TMS TMS P1.6/ P1.x (I/O) TA0.1/ 6 CA6/ X X 1 0 I: 0; O: 1 0 0 0 TA0.1 1 1 0 0 CA6 X X 0 1 (y = 6) TDI/TCLK TDI/TCLK X X 1 0 P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 CAOUT/ CAOUT 1 1 0 0 CA7 X X 0 1 (y = 7) TDO/TDI X X 1 0 CA7/ TDO/TDI (1) 34 7 X = Don't care Submit Documentation Feedback Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger - MSP430G2x01 and MSP430G2x11 XOUT/P2.7 LF off PxSEL.6 PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK 0 1 PxSEL.6 PxDIR.y 1 0 Direction 0: Input 1: Output PxREN.y PxSEL.6 PxOUT.y 0 From Module 1 DV SS 0 DV CC 1 1 Bus Keeper EN XIN/P2.6/TA0.1 PxIN.y To Module PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Table 18. Port P2 (P2.6) Pin Functions - MSP430G2x01 and MSP430G2x11 PIN NAME (P2.x) x XIN XIN P2.6 TA0.1 (1) FUNCTION 6 P2.x (I/O) Timer0_A2.TA1 CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.6 P2SEL.7 0 1 1 I: 0; O: 1 0 X 1 1 X X = Don't care Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 35 MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger - MSP430G2x01 and MSP430G2x11 XIN/P2.6/TA0.1 LF off PxSEL.6 PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK 0 PxDIR.y 1 0 from P2.6/XIN 1 PxSEL.7 Direction 0: Input 1: Output PxREN.y PxSEL.7 PxOUT.y 0 From Module 1 DVSS 0 DV CC 1 1 Bus Keeper EN XOUT/P2.7 PxIN.y To Module PxIE.y EN PxIRQ.y Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Table 19. Port P2 (P2.7) Pin Functions - MSP430G2x01 and MSP430G2x11 PIN NAME (P2.x) XOUT P2.7 36 x 7 FUNCTION XOUT P2.x (I/O) Submit Documentation Feedback CONTROL BITS / SIGNALS P2DIR.x P2SEL.6 P2SEL.7 1 1 1 I: 0; O: 1 0 0 Copyright (c) 2010-2011, Texas Instruments Incorporated MSP430G2x11 MSP430G2x01 SLAS695G - FEBRUARY 2010 - REVISED DECEMBER 2011 www.ti.com REVISION HISTORY REVISION DESCRIPTION SLAS695 Limited Product Preview release SLAS695A Updated Product Preview Changes throughout for sampling SLAS695B Updated Product Preview SLAS695C Production Data release SLAS695D Table 14, Corrected P1DIR.x column for TA0.0 and TA0.1. Table 18, Corrected FUNCTION column for TA0.1. Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x11, Corrected schematic. SLAS695E Changed Storage temperature range limits in Absolute Maximum Ratings. Table 15, Removed CAPD.y column. Table 19, Corrected Control Bits/Signals. SLAS695F Changed Tstg, Programmed device, to -55C to 150C in Absolute Maximum Ratings. Changed fSYSTEM MAX at VCC = 1.8 V from 4.15 to 6 MHz in Recommended Operating Conditions. SLAS695G Changed port schematics (added buffer after PxOUT.y mux) in APPLICATION INFORMATION Copyright (c) 2010-2011, Texas Instruments Incorporated Submit Documentation Feedback 37 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) MSP430G2001IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2001IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2001IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2001IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2001IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2101IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2101IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2101IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2101IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2101IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2111IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2111IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2201IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IRSA16 OBSOLETE QFN RSA 16 TBD Addendum-Page 1 Call TI Samples Call TI PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 2-Apr-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2201IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2201IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2211IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2211IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2211IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2211IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2211IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSP430G2001, MSP430G2101, MSP430G2111, MSP430G2201, MSP430G2211 : * Automotive: MSP430G2001-Q1, MSP430G2101-Q1, MSP430G2111-Q1, MSP430G2201-Q1, MSP430G2211-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430G2001IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2001IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2001IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2101IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2101IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2101IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2111IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2111IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2111IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2201IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2201IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2201IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2211IPW14R TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 MSP430G2211IRSA16R QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 MSP430G2211IRSA16T QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430G2001IPW14R MSP430G2001IRSA16R TSSOP PW 14 2000 367.0 367.0 35.0 QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2001IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2101IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2101IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2101IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2111IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2111IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2111IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2201IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2201IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2201IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2211IPW14R TSSOP PW 14 2000 367.0 367.0 35.0 MSP430G2211IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2211IRSA16T QFN RSA 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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