LMZ14201H 1A SIMPLE SWITCHER Power Module for High Output Voltage Easy to use 7 pin package Performance Benefits High efficiency reduces system heat generation Low radiated EMI (EN 55022 Class B compliant) (Note 5) No compensation required Low package thermal resistance System Performance Efficiency VOUT = 12V 30135430 TO-PMOD 7 Pin Package 10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in) JA = 16C/W, JC = 1.9C/W RoHS Compliant 100 EFFICIENCY (%) 95 Electrical Specifications Up to 1A output current Input voltage range 6V to 42V Output voltage as low as 5V Efficiency up to 97% 90 85 80 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 75 70 0.0 Key Features Integrated shielded inductor Simple PCB layout Flexible startup sequencing using external soft-start and 1.0 30135407 Thermal Derating VOUT = 12V, JA = 16C/W 1.2 OUTPUT CURRENT (A) precision enable Protection against inrush currents Input UVLO and output short circuit protection - 40C to 125C junction temperature range Single exposed pad and standard pinout for easy mounting and manufacturing Low output voltage ripple Pin-to-pin compatible family: LMZ14203H/2H/1H (42V max 3A, 2A, 1A) LMZ14203/2/1 (42V max 3A, 2A, 1A) LMZ12003/2/1 (20V max 3A, 2A, 1A) Fully enabled for Webench(R) Power Designer 1.0 0.8 0.6 0.4 0.2 VIN = 15V VIN = 24V VIN = 42V 0.0 -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) 30135432 Radiated Emissions (EN 55022 Class B) Intermediate bus conversions to 12V and 24V rail Time critical projects Space constrained / high thermal requirement applications Negative output voltage applications RADIATED EMISSIONS (dBV/m) 80 Applications 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) Emissions (Evaluation Board) EN 55022 Limit (Class B) 70 60 50 40 30 20 10 0 0 200 400 600 800 FREQUENCY (MHz) 1000 30135425 SIMPLE SWITCHER(R) is a registered trademark of National Semiconductor Corporation PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 301354 SNVS690C Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Simplified Application Schematic 30135401 Connection Diagram 30135402 Top View 7-Lead TO-PMOD Ordering Information 2 Order Number Package Type NSC Package Drawing Supplied As LMZ14201HTZ TO-PMOD-7 TZA07A 250 Units on Tape and Reel LMZ14201HTZX TO-PMOD-7 TZA07A 500 Units on Tape and Reel LMZ14201HTZE TO-PMOD-7 TZA07A 45 Units in a Rail Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Pin Descriptions Pin Name Description 1 VIN Supply input -- Additional external input capacitance is required between this pin and the exposed pad (EP). 2 RON On time resistor -- An external resistor from VIN to this pin sets the on-time and frequency of the application. Typical values range from 100k to 700k ohms. 3 EN 4 GND 5 SS Soft-Start -- An internal 8 A current source charges an external capacitor to produce the soft-start function. 6 FB Feedback -- Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference point is 0.8V at this input pin. Connect the feedback resistor divider between the output and ground to set the output voltage. 7 EP Enable -- Input to the precision enable comparator. Rising threshold is 1.18V. Ground -- Reference point for all stated voltages. Must be externally connected to EP. VOUT Output Voltage -- Output from the internal inductor. Connect the output capacitor between this pin and the EP. EP Exposed Pad -- Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be electrically connected to pin 4 external to the package. Copyright (c) 1999-2012, Texas Instruments Incorporated 3 LMZ14201H Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN, RON to GND -0.3V to 43.5V EN, FB, SS to GND -0.3V to 7V Junction Temperature 150C Storage Temperature Range -65C to 150C ESD Susceptibility(Note 2) 2 kV Peak Reflow Case Temperature 245C (30 sec) For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c Operating Ratings (Note 1) VIN EN Operation Junction Temperature 6V to 42V 0V to 6.5V -40C to 125C Electrical Characteristics Limits in standard type are for TJ = 25C only; limits in boldface type apply over the junction temperature (TJ) range of -40C to +125C. Minimum and Maximum limits are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 24V, VOUT = 12V, RON = 249k Symbol Parameter Conditions Min (Note 3) Typ (Note 4) Max (Note 3) 1.10 1.18 1.25 Units SYSTEM PARAMETERS Enable Control VEN VEN-HYS EN threshold trip point VEN rising EN threshold hysteresis 90 V mV Soft-Start ISS ISS-DIS SS source current VSS = 0V 8 SS discharge current 10 15 -200 A A Current Limit ICL Current limit threshold DC average VINUVLO Input UVLO EN pin floating VIN rising 3.75 V VINUVLO-HYST Hysteresis EN pin floating VIN falling 130 mV ON timer minimum pulse width 150 ns OFF timer pulse width 260 ns 1.5 1.95 2.7 A VIN UVLO ON/OFF Timer tON-MIN tOFF Regulation and Over-Voltage Comparator VFB 4 In-regulation feedback voltage VIN = 24V, VOUT = 12V VSS >+ 0.8V TJ = -40C to 125C IOUT = 10mA to 1A 0.782 0.803 0.822 V VIN = 24V, VOUT = 12V VSS >+ 0.8V TJ = 25C IOUT = 10mA to 1A 0.786 0.803 0.818 V Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Symbol VFB VFB-OVP Min (Note 3) Typ (Note 4) Max (Note 3) Units VIN = 36V, VOUT = 24V VSS >+ 0.8V TJ = -40C to 125C IOUT = 10mA to 1A 0.780 0.803 0.823 V VIN = 36V, VOUT = 24V VSS >+ 0.8V TJ = 25C IOUT = 10mA to 1A 0.787 0.803 0.819 V Parameter Conditions In-regulation feedback voltage Feedback over-voltage protection threshold 0.92 V IFB Feedback input bias current 5 nA IQ Non Switching Input Current VFB= 0.86V 1 mA ISD Shut Down Quiescent Current VEN= 0V 25 A Rising 165 C 15 C 4 layer Printed Circuit Board, 7.62cm x 7.62cm (3in x 3in) area, 1 oz Copper, No air flow 16 C/W 4 layer Printed Circuit Board, 6.35cm x 6.35cm (2.5in x 2.5in) area, 1 oz Copper, No air flow 18.4 C/W No air flow 1.9 C/W 8 mV PP Thermal Characteristics TSD TSD-HYST JA JC Thermal Shutdown Thermal Shutdown Hysteresis Junction to Ambient Junction to Case PERFORMANCE PARAMETERS VOUT Output Voltage Ripple VOUT = 5V, COUT = 100F 6.3V X7R VOUT/VIN Line Regulation VIN = 16V to 42V, IOUT= 1A .01 % VOUT/IOUT Load Regulation VIN = 24V, IOUT= 0A to 1A 1.5 mV/A Efficiency VIN = 24V VOUT = 12V IOUT = 0.5A 94 % Efficiency VIN = 24V VOUT = 12V IOUT = 1A 92 % Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The human body model is a 100pF capacitor discharged through a 1.5 k resistor into each pin. Test method is per JESD-22-114. Note 3: Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National's Average Outgoing Quality Level (AOQL). Note 4: Typical numbers are at 25C and represent the most likely parametric norm. Note 5: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. Copyright (c) 1999-2012, Texas Instruments Incorporated 5 LMZ14201H Typical Performance Characteristics Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 47uF; TAMB = 25C. Efficiency VOUT = 5.0V TAMB = 25C Power Dissipation VOUT = 5.0V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.2 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135412 Efficiency VOUT = 12V TAMB = 25C 30135410 Power Dissipation VOUT = 12V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.2 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135407 Efficiency VOUT = 15V TAMB = 25C 30135416 Power Dissipation VOUT = 15V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 70 0.0 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135409 6 1.2 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135450 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Efficiency VOUT = 18V TAMB = 25C Power Dissipation VOUT = 18V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 70 0.0 1.2 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135449 Efficiency VOUT = 24V TAMB = 25C 30135448 Power Dissipation VOUT = 24V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 70 0.0 1.2 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135447 Efficiency VOUT = 30V TAMB = 25C 30135446 Power Dissipation VOUT = 30V TAMB = 25C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 34V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 0.9 0.6 0.3 0.0 1.0 30135440 Copyright (c) 1999-2012, Texas Instruments Incorporated 1.2 0.0 VIN = 34V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135439 7 LMZ14201H Efficiency VOUT = 5.0V TAMB = 85C Power Dissipation VOUT = 5.0V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.2 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135415 Efficiency VOUT = 12V TAMB = 85C 30135445 Power Dissipation VOUT = 12V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.2 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135414 Efficiency VOUT = 15V TAMB = 85C 30135413 Power Dissipation VOUT = 15V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 70 0.0 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135442 8 1.2 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135441 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Efficiency VOUT = 18V TAMB = 85C Power Dissipation VOUT = 18V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 70 0.0 1.2 VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135444 Efficiency VOUT = 24V TAMB = 85C 30135443 Power Dissipation VOUT = 24V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 70 0.0 1.2 VIN = 28V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135438 Efficiency VOUT = 30V TAMB = 85C 30135437 Power Dissipation VOUT = 30V TAMB = 85C 100 1.5 POWER DISSIPATION (W) EFFICIENCY (%) 95 90 85 80 75 70 0.0 VIN = 34V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 0.9 0.6 0.3 0.0 1.0 30135436 Copyright (c) 1999-2012, Texas Instruments Incorporated 1.2 0.0 VIN = 34V VIN = 36V VIN = 42V 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135435 9 LMZ14201H Thermal Derating VOUT = 12V, JA = 20C/W 1.2 1.2 1.0 1.0 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Thermal Derating VOUT = 12V, JA = 16C/W 0.8 0.6 0.4 0.2 0.0 -20 VIN = 15V VIN = 24V VIN = 42V 0.8 0.6 0.4 0.2 VIN = 15V VIN = 24V VIN = 42V 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) 30135432 Thermal Derating VOUT = 24V, JA = 20C/W 1.2 1.2 1.0 1.0 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Thermal Derating VOUT = 24V, JA = 16C/W 30135429 0.8 0.6 0.4 0.2 0.0 -20 VIN = 30V VIN = 36V VIN = 42V 0.8 0.6 0.4 0.2 VIN = 30V VIN = 36V VIN = 42V 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) -20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) 30135431 1.2 1.2 1.0 1.0 0.8 0.6 0.4 0.2 0.0 -20 VIN = 34V VIN = 36V VIN = 42V 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) 30135453 10 Thermal Derating VOUT = 30V, JA = 20C/W OUTPUT CURRENT (A) OUTPUT CURRENT (A) Thermal Derating VOUT = 30V, JA = 16C/W 30135428 -20 VIN = 34V VIN = 36V VIN = 42V 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (C) 30135454 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H THERMAL RESISTANCE JA (C/W) 40 0LFM (0m/s) air 225LFM (1.14m/s) air 500LFM (2.54m/s) air Evaluation Board Area 35 30 25 20 15 10 5 0 0 10 20 30 40 BOARD AREA (cm2) 50 Line and Load Regulation TAMB = 25C OUTPUT VOLTAGE REGULATION (%) Package Thermal Resistance JA 4 Layer Printed Circuit Board with 1oz Copper 60 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V -0.20 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135452 30135427 Output Ripple VIN = 12V, IOUT = 1A, Ceramic COUT, BW = 200 MHz 30135405 Load Transient Response VIN = 24V VOUT = 12V Load Step from 10% to 100% 30135403 Copyright (c) 1999-2012, Texas Instruments Incorporated Output Ripple VIN = 24V, IOUT = 1A, Polymer Electrolytic COUT, BW = 200 MHz 30135404 Load Transient Response VIN = 24V VOUT = 12V Load Step from 30% to 100% 30135406 11 LMZ14201H Current Limit vs. Input Voltage VOUT = 5V Switching Frequency vs. Power Dissipation VOUT = 5V 1.8 POWER DISSIPATION (W) DC CURRENT LIMIT LEVEL (A) 3.5 3.0 2.5 2.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 1.5 1.0 VIN = 12V VIN = 24V VIN = 36V VIN = 42V 1.5 1.2 0.9 0.6 0.3 0.0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 45 200 300 400 500 600 700 SWITCHING FREQUENCY (kHz) 30135421 Current Limit vs. Input Voltage VOUT = 12V 30135418 Switching Frequency vs. Power Dissipation VOUT = 12V 1.8 POWER DISSIPATION (W) DC CURRENT LIMIT LEVEL (A) 3.5 3.0 2.5 2.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 1.5 1.0 VIN = 15V VIN = 24V VIN = 36V VIN = 42V 1.5 1.2 0.9 0.6 0.3 0.0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 40 45 200 300 400 500 600 700 SWITCHING FREQUENCY (kHz) 30135422 Current Limit vs. Input Voltage VOUT = 24V Switching Frequency vs. Power Dissipation VOUT = 24V 1.8 1.6 POWER DISSIPATION (W) DC CURRENT LIMIT LEVEL (A) 800 30135419 3.5 3.0 2.5 2.0 Fsw = 250kHz Fsw = 400kHz Fsw = 600kHz 1.5 1.0 1.4 1.2 1.0 0.8 0.6 VIN = 30V VIN = 36V VIN = 42V 0.4 0.2 0.0 30 33 36 39 42 INPUT VOLTAGE (V) 45 30135423 12 800 200 300 400 500 600 700 SWITCHING FREQUENCY (kHz) 800 30135420 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Startup VIN = 24V IOUT = 1A Radiated EMI of Evaluation Board, VOUT = 12V RADIATED EMISSIONS (dBV/m) 80 Emissions (Evaluation Board) EN 55022 Limit (Class B) 70 60 50 40 30 20 10 0 0 30135457 200 400 600 800 FREQUENCY (MHz) 1000 30135425 Conducted EMI, VOUT = 12V Evaluation Board BOM and 3.3H 1F LC line filter CONDUCTED EMISSIONS (dBV) 80 70 Emissions CISPR 22 Quasi Peak CISPR 22 Average 60 50 40 30 20 10 0 0.1 1 10 FREQUENCY (MHz) 100 30135424 Copyright (c) 1999-2012, Texas Instruments Incorporated 13 LMZ14201H Application Block Diagram 30135408 COT Control Circuit Overview Constant On Time control is based on a comparator and an on-time one shot, with the output voltage feedback compared to an internal 0.8V reference. If the feedback voltage is below the reference, the high-side MOSFET is turned on for a fixed on-time determined by a programming resistor RON. RON is connected to VIN such that on-time is reduced with increasing input supply voltage. Following this on-time, the high-side MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the on-time cycle is repeated. Regulation is achieved in this manner. Design Steps for the LMZ14201H Application The LMZ14201H is fully supported by Webench(R) which offers the following: * Component selection * Electrical simulation * Thermal simulation * Build-it prototype board for a reduction in design time The following list of steps can be used to manually design the LMZ14201H application. * Select minimum operating VIN with enable divider resistors * Program VO with divider resistor selection * Program turn-on time with soft-start capacitor selection * Select CO * Select CIN * Set operating frequency with RON * Determine module dissipation * Layout PCB for required thermal performance ENABLE DIVIDER, RENT AND RENB SELECTION The enable input provides a precise 1.18V reference threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typ) of hysteresis resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5V. For applications where the midpoint of the enable divider exceeds 6.5V, a small zener can be added to limit this voltage. The function of the RENT and RENB divider shown in the Application Block Diagram is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turn-on of the supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14201H output rail. The two resistors should be chosen based on the following ratio: RENT / RENB = (VIN-ENABLE/ 1.18V) - 1 (1) 14 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H The EN pin is internally pulled up to VIN and can be left floating for always-on operation. However, it is good practice to use the enable divider and turn on the regulator when VIN is close to reaching its nominal value. This will guarantee smooth startup and will prevent overloading the input supply. OUTPUT VOLTAGE SELECTION Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an on-time cycle is initiated when the voltage on the FB pin falls below 0.8V. The high-side MOSFET on-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at FB is above 0.8V, on-time cycles will not occur. The regulated output voltage determined by the external divider resistors RFBT and RFBB is: VO = 0.8V x (1 + RFBT / RFBB) (2) Rearranging terms; the ratio of the feedback resistors for a desired output voltage is: RFBT / RFBB = (VO / 0.8V) - 1(3) These resistors should be chosen from values in the range of 1 k to 50 k. A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple. A table of values for RFBT , RFBB , and RON is included in the simplified applications schematic. SOFT-START CAPACITOR, CSS, SELECTION Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot. Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula: tSS = VREF x CSS / Iss = 0.8V x CSS / 8uA (4) This equation can be rearranged as follows: CSS = tSS x 8 A / 0.8V (5) Use of a 4700pF capacitor results in 0.5ms soft-start duration. This is a recommended value. Note that high values of CSS capacitance will cause more output voltage droop when a load transient goes across the DCM-CCM boundary. Use equation 18 below to find the DCM-CCM boundary load current for the specific operating condition. If a fast load transient response is desired for steps between DCM and CCM mode the softstart capacitor value should be less than 0.018F. Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 A current sink: * The enable input being "pulled low" * Thermal shutdown condition * Over-current fault * Internal VIN UVLO OUTPUT CAPACITOR, CO, SELECTION None of the required output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst case RMS current rating of 0.5 x ILR P-P, as calculated in equation (19). Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 F is generally required. Experimentation will be required if attempting to operate with a minimum value. Low ESR capacitors, such as ceramic and polymer electrolytic capacitors are recommended. CAPACITANCE: The following equation provides a good first pass approximation of CO for load transient requirements: COISTEP x VFB x L x VIN/ (4 x VO x (VIN -- VO) x VOUT-TRAN)(6) As an example, for 1A load step, VIN = 24V, VOUT = 12V, VOUT-TRAN = 50mV: CO 1A x 0.8V x 15H x 24V / (4 x 12V x ( 24V -- 12V) x 50mV) CO 10.05F ESR: The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger VOUT peak-to-peak ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the over-voltage protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired VOUT peak-to-peak ripple voltage and to avoid over-voltage protection during normal operation. The following equations can be used: ESRMAX-RIPPLE VOUT-RIPPLE / ILR P-P(7) where ILR P-P is calculated using equation (19) below. ESRMAX-OVP < (VFB-OVP - VFB) / (ILR P-P x AFB )(8) Copyright (c) 1999-2012, Texas Instruments Incorporated 15 LMZ14201H where AFB is the gain of the feedback network from VOUT to VFB at the switching frequency. As worst case, assume the gain of AFB with the CFF capacitor at the switching frequency is 1. The selected capacitor should have sufficient voltage and RMS current rating. The RMS current through the output capacitor is: I(COUT(RMS)) = ILR P-P / 12 (9) INPUT CAPACITOR, CIN, SELECTION The LMZ14201H module contains an internal 0.47 F input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance should be located as close as possible to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by the equation: I(CIN(RMS)) 1 / 2 x IO x (D / 1-D) (10) where D VO / VIN (As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when VIN = 2 x VO). Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. If the system design requires a certain maximum value of input ripple voltage VIN to be maintained then the following equation may be used. CIN IO x D x (1-D) / fSW-CCM x VIN(11) If VIN is 1% of VIN for a 24V input to 12V output application this equals 240 mV and fSW = 400 kHz. CIN 1A x 12V/24V x (1- 12V/24V) / (400000 x 0.240 V) CIN 2.6F Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. ON TIME, RON, RESISTOR SELECTION Many designs will begin with a desired switching frequency in mind. As seen in the Typical Performance Characteristics section, the best efficiency is achieved in the 300kHz-400kHz switching frequency range. The following equation can be used to calculate the RON value. fSW(CCM) VO / (1.3 x 10-10 x RON) (12) This can be rearranged as RON VO / (1.3 x 10 -10 x fSW(CCM) (13) The selection of RON and fSW(CCM) must be confined by limitations in the on-time and off-time for the COT control section. The on-time of the LMZ14201H timer is determined by the resistor RON and the input voltage VIN. It is calculated as follows: tON = (1.3 x 10-10 x RON) / VIN (14) The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should be selected such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by the following equation: fSW(MAX) = VO / (VIN(MAX) x 150 nsec) (15) This equation can be used to select RON if a certain operating frequency is desired so long as the minimum on-time of 150 ns is observed. The limit for RON can be calculated as follows: RON VIN(MAX) x 150 nsec / (1.3 x 10 -10) (16) If RON calculated in (13) is less than the minimum value determined in (16) a lower frequency should be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged. Additionally, the minimum off-time of 260 ns (typ) limits the maximum duty ratio. Larger RON (lower FSW) should be selected in any application requiring large duty ratio. Discontinuous Conduction and Continuous Conduction Modes At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to zero before the end of the off-time. Note that during the period of time that inductor current is zero, all load current is supplied by the output capacitor. The next on-time period starts when the voltage on the FB pin falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as compared to CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are reduced with the smaller load and lower switching frequency. Operating frequency in DCM can be calculated as follows: fSW(DCM)VO x (VIN-1) x 15H x 1.18 x 1020 x IO / (VIN-VO) x RON2 (17) 16 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the off-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using equation 12 above. The approximate formula for determining the DCM/CCM boundary is as follows: IDCBVOx (VIN-VO) / ( 2 x 15H x fSW(CCM) x VIN) (18) The inductor internal to the module is 15H. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated with: ILR P-P=VO x (VIN- VO) / (15H x fSW x VIN) (19) Where VIN is the maximum input voltage and fSW is determined from equation 12. If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. Be aware that the lower peak of ILR must be positive if CCM operation is required. POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS For a design case of VIN = 24V, VOUT = 12V, IOUT = 1A, TAMB (MAX) = 85C , and TJUNCTION = 125C, the device must see a maximum junction-to-ambient thermal resistance of: JA-MAX < (TJ-MAX - TAMB(MAX)) / PD This JA-MAX will ensure that the junction temperature of the regulator does not exceed TJ-MAX in the particular application ambient temperature. To calculate the required JA-MAX we need to get an estimate for the power losses in the IC. The following graph is taken form the Typical Performance Characteristics section and shows the power dissipation of the LMZ14201H for VOUT = 12V at 85C TAMB. Power Dissipation VOUT = 12V TAMB = 85C POWER DISSIPATION (W) 1.5 1.2 VIN = 15V VIN = 24V VIN = 30V VIN = 36V VIN = 42V 0.9 0.6 0.3 0.0 0.0 0.2 0.4 0.6 0.8 OUTPUT CURRENT (A) 1.0 30135413 Using the 85C TAMB power dissipation data as a conservative starting point, the power dissipation PD for VIN = 24V and VOUT = 12V is estimated to be 0.75W. The necessary JA-MAX can now be calculated. JA-MAX < (125C - 85C) / 0.75W JA-MAX < 53.3C/W To achieve this thermal resistance the PCB is required to dissipate the heat effectively. The area of the PCB will have a direct effect on the overall junction-to-ambient thermal resistance. In order to estimate the necessary copper area we can refer to the following Package Thermal Resistance graph. This graph is taken from the Typical Performance Characteristics section and shows how the JA varies with the PCB area. Copyright (c) 1999-2012, Texas Instruments Incorporated 17 LMZ14201H Package Thermal Resistance JA 4 Layer Printed Circuit Board with 1oz Copper THERMAL RESISTANCE JA (C/W) 40 0LFM (0m/s) air 225LFM (1.14m/s) air 500LFM (2.54m/s) air Evaluation Board Area 35 30 25 20 15 10 5 0 0 10 20 30 40 BOARD AREA (cm2) 50 60 30135427 For JA-MAX< 53.3C/W and only natural convection (i.e. no air flow), the PCB area can be smaller than 9cm2. This corresponds to a square board with 3cm x 3cm (1.18in x 1.18in) copper area, 4 layers, and 1oz copper thickness. Higher copper thickness will further improve the overall thermal performance. Note that thermal vias should be placed under the IC package to easily transfer heat from the top layer of the PCB to the inner layers and the bottom layer. For more guidelines and insight on PCB copper area, thermal vias placement, and general thermal design practices please refer to Application Note AN-2020 (http://www.national.com/an/AN/AN-2020.pdf). PC BOARD LAYOUT GUIDELINES PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 30135411 1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14201H. Therefore place CIN1 as close as possible to the LMZ14201H VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP). 2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP. 3. Minimize trace length to the FB pin. Both feedback resistors, R FBT and RFBB, and the feed forward capacitor CFF, should be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from RFBT, RFBB, and CFF should be routed away from the body of the LMZ14201H to minimize noise pickup. 4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy. 5. Provide adequate device heat-sinking. 18 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 m) thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125C. Additional Features OUTPUT OVER-VOLTAGE COMPARATOR The voltage at FB is compared to a 0.92V internal reference. If FB rises above 0.92V the on-time is immediately terminated. This condition is known as over-voltage protection (OVP). It can occur if the input voltage is increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top MOSFET on-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain on until inductor current falls to zero. CURRENT LIMIT Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET. Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds the ICL value, the current limit comparator disables the start of the next ontime period. The next switching cycle will occur only if the FB input is less than 0.8V and the inductor current has decreased below I CL. Inductor current is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds ICL, further on-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to the longer off-time. It should also be noted that DC current limit varies with duty cycle, switching frequency, and temperature. THERMAL PROTECTION The junction temperature of the LMZ14201H should not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165 C (typ) causing the device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back below 145 C (typ Hyst = 20 C) the SS pin is released, VO rises smoothly, and normal operation resumes. ZERO COIL CURRENT DETECTION The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM operating mode, which improves efficiency at light loads. PRE-BIASED STARTUP The LMZ14201H will properly start up into a pre-biased output. This startup situation is common in multiple rail logic applications where current paths may exist between different power rails during the startup sequence. The pre-bias level of the output voltage must be less than the input UVLO set point. This will prevent the output pre-bias from enabling the regulator through the high side MOSFET body diode. Copyright (c) 1999-2012, Texas Instruments Incorporated 19 LMZ14201H Physical Dimensions inches (millimeters) unless otherwise noted 7-Lead TZA Package NS Package Number TZA07A 20 Copyright (c) 1999-2012, Texas Instruments Incorporated LMZ14201H Notes Copyright (c) 1999-2012, Texas Instruments Incorporated 21 Notes Copyright (c) 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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