This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale Semiconductor
Advance Information
This ha rdware specification contains detailed information on the
power considerations, DC/AC electrical characteristics, and AC
timing spec ificat ions of the MPC853T. The MPC853T contains a
PowerPC™ proc essor core.
This hard wa re sp e cific a t io n d e s c r i be s per t inent e l e ctr i c al a n d
physi ca l charact er isti cs of the MPC8 53T. For t he functio nal
characteristics of the processor, refer to the MPC866
PowerQUICC™ Famil y User’s Manual (MPC866UM).
1Overview
The MPC853T P owerQUICC™ is a 0. 18-micron d erivati ve of the
MPC860 PowerQUICC family . It can operate at up to 100 MHz on
the MPC8xx core with a 66- MHz ext ernal bus. The MPC853T has
a 1. 8-V core and 3. 3-V I/O oper ation wit h 5-V TTL compatibi lity.
The MPC853T integrated communications controller is a versatile
one-chip integr ated microproc e ssor and periphe ral combinati on
that can be used in a variety of controller a pplications. I t
particularly excels in Ethernet control applications, including CPE
equipment, Ethernet routers a nd hubs, VoIP clients, and Wi-Fi
access points.
The MPC853T is a PowerPC architecture -based deri vative of
Freescale's M PC860 quad integrated communications controller
(PowerQUICC). The CPU on the MPC853T has a MPC8xx cor e,
a 32-bit microprocessor that implements the PowerPC architecture
MPC853TEC
Rev. 1, 12/2004
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum T olerated Ratings . . . . . . . . . . . . . . . . . . . 6
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
8. Power Supply and Power Sequencing . . . . . . . . . . . 11
9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 42
13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
14. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 63
15. Mechanical Data and O rderi ng I nfo r m ation . . . . . . . 67
16. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
17. Document Revision History . . . . . . . . . . . . . . . . . . . 84
MPC853T Hardware Specification
MPC853T Hardware Specification, Rev. 1
2Freescale Semiconductor
Features
and in corpora tes memory management units (MMUs), instr uction and data caches. The MPC853T is a subset of t his
family of devices and is the main foc us of this document.
2Features
The MPC853T is comprised of three modules tha t each us e the 3 2-b it intern a l bu s: a MPC 8xx core, a system
integrati on unit (SIU), and a communi cations processor module ( CPM). The MPC853T block dia gram is shown in
Figure 1.
The following list summarizes the key MPC853T feature s:
• Embedded MPC8xx core up to 100 MHz
• Maximum frequency operation of the external bus is 66 M Hz
— The 50-/66-MHz core frequenc ie s support both the 1:1 and 2:1 modes.
— The 80-/100-MHz core frequ encie s support 2:1 mode only.
• Single-iss ue, 32-bit core (comp atible with the PowerPC architecture definit ion) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch pr ediction with co nditional pref etch and without conditional execution .
— 4-K b yte data ca ch e an d 4-Kb yt e ins tru cti o n cach e
– Instruction cache is two-way, set-associative with 128 sets
– Data cache is two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches a re physically add ressed, implement a least re cently used (LRU) r eplacement algorit hm, and
are lockable on a cache block basis.
— MMUs with 32-entry translation look-aside buf fer (TLB), fully associa tive inst ruction, and data TLBs
— MMUs support multiple page size s of 4 Kbytes, 16 Kbyte s, 512 Kbytes, and 8 Mbytes; 16 virtua l
address spaces and 16 prote ction groups
• Up to 32-bit data bus (dynamic bus sizing f or 8, 1 6, an d 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complet e dynamic RAM (DRAM) controlle r
— Each b ank can be a chip sel ect or RA S to support a DRAM bank.
— Up to 30 wait states programmable per memory ba nk
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
— DRAM controller progra mmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select a vailable at reset ( options for 8-, 16- , or 32-bit memory)
— Variable block siz es (32 Kbytes–256 Mbytes)
— Selectable wri te protection
— On-chip bus arbitration logic
• Fa st Eth er n et Cont ro ll er (FEC)
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 3
Features
• General-purpose timers
— Two 16-bit timers or one 32-bit timer
— Gat e mo de can en abl e/d i sab le count i ng
— Interrupt can be masked on ref ere nce match and event captur e
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 11 49.1 te st access por t (JTAG)
• Interrupts
— Seven ex te rnal in terrupt request (I RQ) li ne s
— Seven port pins with interrupt capabi lity
— Eighteen interna l interr upt sources
— Programmable priority between SCCs
— Programmable highe st priority r equest
• Communications processor module (CPM)
— RISC controller
— Communicat ion-specific commands (for exam ple, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT)
— Supports contin uous mode transmiss ion and receptio n on all seri al channels
— 8-Kbytes of dual-port RAM
— Eight serial DMA (SDMA) channels
— Th ree para lle l I/O reg isters with ope n -d rain cap abi l ity
• Two baud-rate generators
— Independent (ca n be connecte d to any SCC3 /4 or SMC1)
— Allow changes during operation
— Autobaud support option
• Two SCCs (serial communication controlle rs)
— Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps opera tion
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area ne twork (LAN))
— Universal async hronous recei ver transmit ter (UART)
— To tally tran sparent (bit str e ams)
— To tally tran sparent (frame based with optional cyclic redund ancy chec k (CRC))
• SMC (serial management channels)
— UART
MPC853T Hardware Specification, Rev. 1
4Freescale Semiconductor
Features
• SPI (serial peri pheral inter f ace)
— Supports master and slave modes
— Supports multipl e-master ope ration on the same bus
• The MPC853T has a time-slot assigne r (TSA) that supports one TDM bus (TDMb)
— Allows SCCs and SMC to run in multiplexed and/or non-mu ltiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchron ization, and clocking
— Allows dynamic changes
— Ca n be inter na lly co nn ect ed to three se rial cha nne l s (two SCC s and one SMC )
• PCMCIA interface
— Master (socket) inte rface, rele ase 2.1 compliant
— Supports one independent PCMCIA socket, 8 m emory or I/O windows
• Debug interface
— Eight c omparat ors: f our opera te on instructi on address, two operate on data address , and two operate on
data
— Suppor ts c onditions: = ≠ < >
— Each watchpoint can generate a break point internally
• Normal high and normal low power modes to conserve power
• 1.8- V core and 3.3- V I/O operation with 5- V TTL compatib ility. Refer to Table 5 for a listing of the 5-V
tolerant pins .
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 5
Features
Figure 1. MPC853T Block Diagram
Bus
System Interface Unit (SIU)
Embedded
Parallel I/O
Memory Controller
2
Timers
Interrupt
Controllers
8-Kbyte
Dual-Port RAM
1 Virtual
System Functions
4-Kbyte
Instruction Cache
32-Entry ITLB
Instruction MMU
4-Kbyte
Data Cache
32-Entry DTLB
Data MMU
Instruction
Bus
Load/Store
Bus
Unified
Internal
Bus Interface
Unit
External
Bus Interface
Unit
Timers
32-Bit RISC Controller
and Program
ROM
MPC8xx
Processor
Core
DMAs
FIFOs
10/100
MII
BaseT
Media Access
Serial Interface (NMSI)
Control
Fast Ethernet
Controller
PCMCIA-ATA Interface
Generators
2 Baud Rate
IDMA
Channels
DMA
8 Serial
&
SCC3 SCC4 SMC1 SPI
Time-Slot Assigner
MPC853T Hardware Specification, Rev. 1
6Freescale Semiconductor
Maximum Tolerated Ratings
3 Maximum Tolerated Ratings
This se ction provides the maximum tolerated voltage and temperature ranges for the MPC853T. Table 1 pro vi d e s
the maximum ratings and the operating temperatur es.
This de vice contains c irc uitry prot ectin g agai nst damage c aused by high -st atic volt age or elect rical fiel ds; however,
it is advised that normal pr ecaution s be taken to avoid application of any voltages higher than maximum-rated
voltages to this high- impedance circuit. Relia bility of operation is enhance d if unused inputs are tied to an
appropriate logic voltage level (for example, either GND, VDDL, or V DDH).
Table 1. Maximum Tolerated Ratings
Rating Symbol Value Unit
Supply voltage 1
1
The power supply of the device must start its ramp from 0.0 V.
VDDL (core voltage) –0.3 to 3.4 V
VDDH (I/O voltage) –0.3 to 4 V
VDDSYN –0.3 to 3.4 V
Difference between VDDL
and VDDSYN
100 mV
Input voltage 2
2
Functional operating conditions are provided with the DC electrical specifications in Ta b le 5 . Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power
up and normal operation (that is, if the MPC853T is unpowered, a voltage greater than 2.5 V must not be applied to
its inputs).
Vin GND–0.3 to VDDH V
Storage temperature range Tstg –55 to +150 °C
Table 2. Operating Temperatures
Rating Symbol Value Unit
Temperature 1 (standard)
1
Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as
junction temperature, Tj.
TA(min) 0°C
Tj(max) 95 °C
Temperature (extended) TA(min) –40 °C
Tj(max) 100 °C
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 7
Thermal Characteristics
4 Thermal Characteristics
Table 3 shows the thermal c haracteristics for the MPC853T.
5 Power Dissipation
Table 4 provide s power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, a nd 2:1
mode, where CPU frequency is twice bus speed .
Table 3. MPC853T Thermal Resistance Data
Rating Environment Symbol Value Unit
Junction-to-ambient 1
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
Natural convection Single-layer board (1s) RθJA 2
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
49 °C/W
Four-layer board (2s2p) RθJMA 3
3
Per JEDEC JESD51-6 with the board horizontal.
32
Airflow (200 ft/min) Single-layer board (1s) RθJMA341
Four-layer board (2s2p) RθJMA329
Junction-to-board 4
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
RθJB 24
Junction-to-case 5
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
RθJC 13
Junction-to-package top 6
6
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
Natural convection ΨJT 3
Airflow (200 ft/min) ΨJT 2
MPC853T Hardware Specification, Rev. 1
8Freescale Semiconductor
DC Characteristics
6 DC Characteristics
Table 5 provide s the DC electrical chara cterist ics for the MPC853T.
Table 4. Power Dissipation (PD)
Die Revision Bus Mode Frequency (MHz) Typical 1
1
Typical power dissipation is measured at 1.9 V.
Maximum 2
2
Maximum power dissipation at VDDL and VDDSYN is at 1.9 V, and VDDH is at 3.465 V.
NOTE
Values in Table 4 represent VDDL-based power dissipation and do not
include I/O power dissi pation over VDDH. I/O power dissipation varies
widely by application due to buffer current, which depends on external
circuitry.
The VDDSYN power dissipation is negligible.
Unit
0
1:1
50 110 140 mW
66 150 180 mW
2:1
66 140 160 mW
80 170 200 mW
100 210 250 mW
Table 5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage VDDH 3.135 3.465 V
VDDL 1.7 1.9 V
VDDSYN 1.7 1.9 V
Difference between VDDL
and VDDSYN
—100mV
Input high voltage (all inputs except PA[0:3],
PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7],
PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST
,
TMS, MII_TXEN, MII_MDIO) 1
VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7 ×VDDH VDDH V
Input leakage current, Vin = 5.5 V (except the TMS,
TRST, DSCK, and DSDI pins) for 5-V tolerant pins 1
Iin — 100 µA
Input leakage current, Vin = VDDH (except TMS,
TRST, DSCK, and DSDI)
IIn —10µA
Input leakage current, Vin = 0 V (except the TMS,
TRST, DSCK, and DSDI)
IIn —10µA
Input capacitance 2 Cin —20pF
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 9
Thermal Calculation and Measurement
7 Thermal Calculation and Measurement
For the following discussions, PD= (VDDL ×IDDL) + PI/O, wh e re PI/O is the power dissipation of the I/O drivers.
NOTE
The VDDSYN power dissipa tion is neglig ible.
7.1 Estimation with Junction-to-Ambient Thermal Resistance
An estimation of the chip junc tion temperat ur e, TJ, in °C can be obtaine d from the fo llowing equation:
TJ = TA + (RθJA ×PD)
where:
TA = amb ien t tem pe ratu re ºC
RθJA = package junction-to- ambient thermal resi stance (ºC/W)
PD = power dissipation in package
The junction-to-ambient the rmal resi sta nce is an indust ry standard va lue that pr ovides a quick and easy estimation
of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor
of two (in the quantity TJ–T
A) are possible.
Output high voltage, IOH = –2.0 mA, VDDH = 3.0 V
(except XTAL and open-drain pins)
VOH 2.4 — V
Output low voltage
IOL = 2.0 mA (CLKOUT)
IOL = 3.2 mA 3
IOL = 5.3 mA 4
IOL = 7.0 mA (Txd1/pa14, txd2/pa12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET,
SRESET)
VOL —0.5V
1
The PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15, PD[3:15], TDI, TDO, TCK, TRST,
TMS, MII_TXEN, and MII_MDIO are 5-V tolerant pins.
2
Input capacitance is periodically sampled.
3
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IWP(0:1)/VFLS(0:1),
RXD3/PA11, TXD3/PA10, RXD4/PA9, TXD4/PA8, TIN3/BRGO3/CLK5/PA3, BRGCLK2/TOUT3/CLK6/PA2,
TIN4/BRGO4/CLK7/PA1, TOUT4/CLK8/PA0, SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29,
BRGO4/SPIMISO/PB28, SMTXD1/PB25, SMRXD1/PB24, BRGO3/PB15, RTS1/DREQ0/PC15, RTS3/PC13,
RTS4/PC12, CTS3/PC7, CD3/PC6, CTS4/SDACK1/PC5, CD4/PC4, MII-RXD3/PD15, MII-RXD2/PD14,
MII-RXD1/PD13, MII-MDC/PD12, MII-TXERR/RXD3/PD11, MII-RX0/TXD3/PD10, MII-TXD0/RXD4/PD9,
MII-RXCLK/TXD4/PD8, MII-TXD3/PD5, MII-RXDV/RTS4/PD6, MII-RXERR/RTS3/PD7, MII-TXD2/REJECT3/PD4,
MII-TXD1/REJECT4/PD3, MII_CRS, MII_MDIO, MII_TXEN, MII_COL
4
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6), CS(7), WE0/BS_B0/IORD, WE1/BS_B1/IOWR,
WE2/BS_B2/PCOE, WE3/ BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1),
OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
Table 5. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
MPC853T Hardware Specification, Rev. 1
10 Freescale Semiconductor
Thermal Calculation and Measurement
7.2 Estimation with Junction-to-Case Thermal Resistance
Histor ically , the therm al r esista nce has freque ntly been express ed as the sum of a junc tion-to-case ther mal re sistance
and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = ju n c t io n- t o-a mbient th erm al r esi st a n c e (º C/W )
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = cas e- to- am bien t ther ma l resi sta n ce (ºC /W )
RθJC is device related and can not be influe nced by the user. The user adj usts the therma l environment to affect the
case -t o-ambie nt therma l resi st an ce, RθCA. For instance, the user can change the airflow around the device, add a
heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipa tion on the
print ed c ircuit board surround ing the device. Thi s thermal model is most useful for cera mic p ackages with heat sin ks
where some 90% of the heat flows through the case and the heat sink to the ambient environ ment. For mo st
packages, a better model is required.
7.3 Estimation with Junction-to-Board Thermal Resistance
A simple pa ckage the rmal model which ha s demonst rated reasona ble accur acy (about 20%) is a two- resistor model
consi sting of a junctio n-to- board and a junction -to-ca se thermal resi stance. Th e junction- to-case t hermal resista nce
covers the situation where a heat sink is used or a substantial amount of heat is dissipated from the top of the package.
The junction-to-board thermal resistance de scribes the thermal performance whe n most of the hea t is c onducted to
the printe d circuit board. It has been observed tha t the thermal pe rformanc e of most plasti c packages, and especiall y
PBGA packages, is strongl y depende nt on the board temperature . If the boar d temper ature is known, an estimate of
the junction temperature in the environment can be made using the following equation :
TJ = TB + ( RθJB ×PD)
where:
RθJB = jun ction -to-board thermal resistance (ºC/ W)
TB = board temperature ºC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable
prediction s of junction temperature can be made. For this method to work, the board and board mounting must be
similar to the test board used to determine the junction-to- board therm al resistanc e , namel y a 2s2p (board with a
power and a ground plane) and vias attaching the thermal balls to the ground plane.
7.4 Estimation Using Simulation
When the bo ard temperature is n ot known, a th ermal s imulation of t he application i s needed. The si mple two resi stor
model can be used wi th the thermal sim ulatio n of th e application [2], or a more a ccurate and compl ex model of the
package can be used in the thermal simulation.
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 11
Power Supply and Power Sequencing
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal
char act erizat ion pa ram et er (ΨJT) can be used. It determines the junction temperat ure with a measurement of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT ×PD)
where:
ΨJT = thermal characterizat i on parameter
TT = th ermocouple tempera ture on top of package
PD = power dissipation in package
The ther mal cha racte rizati on parameter is mea sured per the JESD51-2 spec ification publi shed by JEDEC using a 40
gauge type T thermocouple epo xied to the top center of the package case. The thermocouple should be positioned
so that the thermocouple junction res ts on the pack age. A small a mount of epoxy is placed over the thermocouple
junct ion and ove r about 1 m m of wire extending f rom th e junction. The the rmocouple wir e is pl aced fl at ag ainst the
package case to avoid measure ment e rrors caused by cool ing effects of the thermocouple wire.
8 Power Supply and Power Sequencing
This se ction provides design considerations for the MPC853T power supply. The MPC853T has a core voltage
(VDDL) and PLL voltage (VDDSYN), which both operate at lower volta ges than the I/O volta ge VDDH. The I/O
section of the MPC853T is supplied with 3.3 V a cross VDDH and VSS (GND).
The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31] , PC[4:7], PC[12:13], PC15] PD[3:15] , TDI , TDO,
TCK, TRST , TMS, MII_TXEN, and MII_MDIO are 5-V toler ant. All in puts cannot be more than 2.5 V greater than
VDDH. In addition, 5-V tolera nt pins can not exceed 5.5 V, and rema ining input pins cannot exceed 3.465 V. This
restriction applies to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially ap plied, the voltage rails ramp up at
diffe rent rates . The rates depend on the nature of the power supply, the type of load on eac h power supply, and the
manner in which diff erent volt ages are derived. The following restriction s apply:
•V
DDL must not exceed VDDH during power up and power down.
•V
DDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V.
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge
(ESD) protection diode s are forward -biased, and excessive current can flow through the se diodes. If the syste m
power supply design does not cont rol the volta ge sequencing, the circuit shown in Figure 2 can be added to meet
these requir ements. The MUR420 Schottky diodes c ontrol the maximum potentia l difference bet ween the external
bus and core power supplies on power up and the 1N5820 diodes regu late the maximum potentia l difference on
power down.
MPC853T Hardware Specification, Rev. 1
12 Freescale Semiconductor
Mandatory Reset Configurations
Figure 2. Example Voltage Sequencing Circuit
9 Mandatory Reset Configurations
The MPC853T requires a mandatory conf iguration dur ing reset.
If hardwa re re set confi guration wor d (HRCW) is ena bled, t he HRCW[DBGC] value need s to be set to bina ry X1 in
HRCW, and th e SIUMCR[DBGC] should be programmed wit h th e same value in the boot code afte r re set. This ca n
be done by asserting the RSTCONF during HRESET assertion.
If HRCW is disabled, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset by
negating the RSTCONF during the HRESET assertion.
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR , PCPAR, and PCDIR registers need to be configure d
with the mandatory value in Table 6 in the boot code afte r the reset is negated.
Table 6. Mandatory Reset Configuration of MPC853T
Register/Configuration Field Value
(binary)
HRCW
(Hardware reset configuration word)
HRCW[DBGC] 0bx1
SIUMCR
(SIU module configuration register)
SIUMCR[DBGC] 0bx1
MBMR
(Machine B mode register)
MBMR[GPLB4DIS} 0
PAPAR
(Port A pin assignment register)
PAPAR [ 4: 7]
PAPAR[12:15]
0
PADIR
(Port A data direction register)
PADIR[4:7]
PADIR[12:15]
1
PBPAR
(Port B pin assignment register)
PBPAR[14]
PBPAR[16:23]
PBPAR[26:27]
0
PBDIR
(Port B Data direction register)
PBDIR[14]
PBDIR[16:23]
PBDIR[26:27]
1
VDDH VDDL
1N5820
MUR420
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 13
Layout Practices
10 Layout Practices
Each V DD pin on the MPC853T should be provided with a low-impedance path to the board’s supply. Each GND
pin should li ke wise be provided wit h a low-im pedance path to ground. The powe r supply pins drive dis tinct groups
of logic on ch ip. The VDD power supply should be bypass ed to ground using at least f our 0.1-µF bypass capa citors
located as close as possible to the four sides of the package. Each board designed should be characterized, and
additional app ropriat e decoupling capacitors shoul d be used if required. Capacitor leads and assoc iated pri nted
circuit tra ces connecti ng to chip VDD and GND should be kept to less than hal f an inch per capacitor lead. At a
minimum, a four-la yer board employing two inne r layers as VDD and GND planes should be used.
All output pins on the MPC853T have fast rise and fall tim es. Printed circuit (PC) tr ace interconnection length
should be minimized in order to mini mize undershoot and refle ctions caused by these fast outpu t switc hing times.
This r ecommendation particularly applies to the address a nd data busses. M aximum PC tr ace lengths of six inches
are recommended. Capaci tance calcula tions should consider all device loads, as well as parasitic capacita nces
cause d by the PC traces. Attention to pr oper PCB layout and bypassing becomes e speciall y criti cal in systems with
highe r capacitiv e loads because these loads cre ate higher transie nt curren ts in the VDD and GND circuit s. Pull up all
unused inputs or signa ls that will be inputs dur ing reset. Speci al care should be taken to mini mize the noise levels
on the PLL supply pins . For more inf ormation, pleas e refer to Sect ion 14.4.3, “Cloc k Synthesizer Power (VDDSYN,
VSSSYN, V SSSYN1)” in the MPC866 PowerQUICC Family User’s Manual.
11 Bus Signal Timing
The maximum bus speed supporte d by the MPC853T is 66 MHz. Table 7 shows the freque nc y ranges for standard
part f requencies in 1:1 bus mode.
Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode.
PCPAR
(Port C pin assignment register)
PCPAR[8:11]
PCDIR[14]
0
PCDIR
(Port C data direction register)
PCDIR[8:11]
PCDIR[14]
1
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency 50 MHz 66 MHz
Min Max Min Max
Core Frequency 40 50 40 66.67
Bus Frequency 40 50 40 66.67
Table 6. Mandatory Reset Configuration of MPC853T (continued)
Register/Configuration Field Value
(binary)
MPC853T Hardware Specification, Rev. 1
14 Freescale Semiconductor
Bus Signal Timing
Table 9 provide s the bus operation timi ng for the MPC853T at 33, 40, 50, and 66 MHz.
The timing for the MPC853T bus shown assumes a 50-pF load for maxi mum delays and a 0-p F load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay.
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Frequency 50 MHz 66 MHz 80 MHz 100 MHz
Min Max Min Max Min Max Min Max
Core Frequency 40 50 40 66.67 40 80 40 100
Bus Frequency 2:1 20 25 20 33.33 20 40 20 50
Table 9. Bus Operation Timings
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B1 Bus period (CLKOUT), see Ta b l e 7 ————————ns
B1a EXTCLK to CLKOUT phase skew - If
CLKOUT is an integer multiple of
EXTCLK, then the rising edge of
EXTCLK is aligned with the rising edge
of CLKOUT. For a non-integer multiple
of EXTCLK, this synchronization is lost,
and the rising edges of EXTCLK and
CLKOUT have a continuously varying
phase skew.
–2 +2 –2 +2 –2 +2 –2 +2 ns
B1b CLKOUT frequency jitter peak-to-peak — 1 — 1 — 1 — 1 ns
B1c Frequency jitter on EXTCLK 1 —0.50—0.50—0.50—0.50%
B1d CLKOUT phase jitter peak-to-peak
for OSCLK ≥ 15 MHz
—4—4—4—4ns
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
—5—5—5—5ns
B2 CLKOUT pulse width low
(MIN = 0.4 ×B1, MAX = 0.6 ×B1)
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
B3 CLKOUT pulse width high
(MIN = 0.4 ×B1, MAX = 0.6 ×B1)
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3)
output hold (MIN = 0.25 ×B1)
7.60 — 6.30 — 5.00 — 3.80 — ns
B7a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,
PTR output hold (MIN = 0.25 ×B1)
7.60 — 6.30 — 5.00 — 3.80 — ns
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 15
Bus Signal Timing
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS output
hold (MIN = 0.25 ×B1)
7.60 — 6.30 — 5.00 — 3.80 — ns
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31), DP(0:3) valid
(MAX = 0.25 ×B1 + 6.3)
— 13.80 — 12.50 — 11.30 — 10.00 ns
B8a CLKOUT to TSIZ(0:1), REG, RSV, BDIP,
PTR valid (MAX = 0.25 ×B1 + 6.3)
— 13.80 — 12.50 — 11.30 — 10.00 ns
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1), STS valid 3
(MAX = 0.25 ×B1 + 6.3)
— 13.80 — 12.50 — 11.30 — 10.00 ns
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, PTR High-Z
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B11 CLKOUT to TS, BB assertion
(MAX = 0.25 ×B1 + 6.0)
7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns
B11a CLKOUT to TA, BI assertion (when
driven by the memory controller or
PCMCIA interface)
(MAX = 0.00 ×B1 + 9.30 2)
2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns
B12 CLKOUT to TS, BB negation
(MAX = 0.25 ×B1 + 4.8)
7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns
B12a CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface)
(MAX = 0.00 ×B1 + 9.00)
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
B13 CLKOUT to TS, BB High-Z
(MIN = 0.25 ×B1)
7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
B13a CLKOUT to TA, BI High-Z (when driven
by the memory controller or PCMCIA
interface) (MIN = 0.00 ×B1 + 2.5)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B14 CLKOUT to TEA assertion
(MAX = 0.00 ×B1 + 9.00)
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
B15 CLKOUT to TEA High-Z
(MIN = 0.00 ×B1 + 2.50)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time)
(MIN = 0.00 ×B1 + 6.00)
6.00 — 6.00 — 6.00 — 6.00 — ns
B16a TEA, KR, RETRY, CR valid to CLKOUT
(setup time) (MIN = 0.00 ×B1 + 4.5)
4.50 — 4.50 — 4.50 — 4.50 — ns
B16b BB, BG, BR, valid to CLKOUT (setup
time) 3 (4MIN = 0.00 ×B1 + 0.00)
4.00 — 4.00 — 4.00 — 4.00 — ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
16 Freescale Semiconductor
Bus Signal Timing
B17 CLKOUT to TA, TEA, BI, BB, BG, BR
valid (hold time)
(MIN = 0.00 ×B1 + 1.00 4)
1.00 — 1.00 — 1.00 — 2.00 — ns
B17a CLKOUT to KR, RETRY, CR valid (hold
time) (MIN = 0.00 ×B1 + 2.00)
2.00 — 2.00 — 2.00 — 2.00 — ns
B18 D(0:31), DP(0:3) valid to CLKOUT rising
edge (setup time) 5
(MIN = 0.00 ×B1 + 6.00)
6.00 — 6.00 — 6.00 — 6.00 — ns
B19 CLKOUT rising edge to D(0:31), DP(0:3)
valid (hold time) 5
(MIN = 0.00 ×B1 + 1.00 6)
1.00 — 1.00 — 1.00 — 2.00 — ns
B20 D(0:31), DP(0:3) valid to CLKOUT falling
edge (setup time)
7(MIN = 0.00 ×B1 + 4.00)
4.00 — 4.00 — 4.00 — 4.00 — ns
B21 CLKOUT falling edge to D(0:31),
DP(0:3) valid (hold Time) 7
(MIN = 0.00 ×B1 + 2.00)
2.00 — 2.00 — 2.00 — 2.00 — ns
B22 CLKOUT rising edge to CS asserted
GPCM ACS = 00
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0
(MAX = 0.00 ×B1 + 8.00)
— 8.00 — 8.00 — 8.00 — 8.00 ns
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 ×B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 ×B1 + 6.6)
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
B23 CLKOUT rising edge to CS negated
GPCM read access, GPCM write access
ACS = 00, TRLX = 0 & CSNT = 0
(MAX = 0.00 ×B1 + 8.00)
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B25 CLKOUT rising edge to OE,
WE(0:3)/BS_B[0:3] asserted
(MAX = 0.00 ×B1 + 9.00)
— 9.00 9.00 9.00 9.00 ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 17
Bus Signal Timing
B26 CLKOUT rising edge to OE negated
(MAX = 0.00 ×B1 + 9.00)
2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 ×B1 – 2.00)
35.90 — 29.30 — 23.00 — 16.90 — ns
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
B28 CLKOUT rising edge to
WE(0:3)/BS_B[0:3] negated GPCM
write access CSNT = 0
(MAX = 0.00 ×B1 + 9.00)
— 9.00 — 9.00 — 9.00 — 9.00 ns
B28a CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negated GPCM
write access TRLX = 0,1 CSNT = 1,
EBDF = 0 (MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B28b CLKOUT falling edge to CS negated
GPCM write access TRLX = 0,1
CSNT = 1 ACS = 10 or ACS = 11,
EBDF = 0 (MAX = 0.25 ×B1 + 6.80)
— 14.30 — 13.00 — 11.80 — 10.50 ns
B28c CLKOUT falling edge to
WE(0:3)/BS_B[0:3] negated GPCM
write access TRLX = 0,1 CSNT = 1 write
access TRLX = 0,1 CSNT = 1,
EBDF = 1 (MAX = 0.375 ×B1 + 6.6)
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0,1
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1 (MAX = 0.375 ×B1 + 6.6)
— 18.00 — 18.00 — 14.30 — 12.30 ns
B29 WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access,
CSNT=0, EBDF=0
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B29a WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access,
TRLX=0, CSNT=1, EBDF=0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B29b CS negated to D(0:31), DP(0:3), High-Z
GPCM write access, ACS = 00,
TRLX = 0,1 & CSNT = 0
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
18 Freescale Semiconductor
Bus Signal Timing
B29c CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0,
CSNT = 1, ACS = 10, or ACS = 11
EBDF = 0 (MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B29d WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access,
TRLX=1, CSNT=1, EBDF=0
(MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
B29e CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1,
CSNT = 1, ACS = 10, or ACS = 11
EBDF = 0 (MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
B29f WE(0:3/BS_B[0:3]) negated to D(0:31),
DP(0:3) High-Z GPCM write access,
TRLX=0, CSNT=1, EBDF=1
(MIN = 0.375 ×B1 – 6.30)
5.00 — 3.00 — 1.10 — 0.00 — ns
B29g CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 0,
CSNT = 1 ACS = 10 or ACS = 11,
EBDF = 1 (MIN = 0.375 ×B1–6.30)
5.00 — 3.00 — 1.10 — 0.00 — ns
B29h WE(0:3)/BS_B[0:3] negated to D(0:31),
DP(0:3) High-Z GPCM write access,
TRLX=1, CSNT=1, EBDF=1
(MIN = 0.375 ×B1 – 3.30)
38.40 — 31.10 — 24.20 — 17.50 — ns
B29i CS negated to D(0:31), DP(0:3) High-Z
GPCM write access, TRLX = 1,
CSNT = 1, ACS = 10 or ACS = 11,
EBDF = 1 (MIN = 0.375 ×B1–3.30)
38.40 — 31.10 — 24.20 — 17.50 — ns
B30 CS, WE(0:3)/BS_B[0:3] negated to
A(0:31), BADDR(28:30) invalid GPCM
write access 8 (MIN = 0.25 ×B1–2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B30a WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 0, CSNT =1 ACS = 10,
or ACS == 11, EBDF = 0
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B30b WE(0:3)/BS_B[0:3] negated to A(0:31)
Invalid GPCM BADDR(28:30) invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS negated to A(0:31) invalid
GPCM write access TRLX = 1,
CSNT = 1, ACS = 10, or ACS == 11
EBDF = 0 (MIN = 1.50 ×B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 19
Bus Signal Timing
B30c WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS
negated to A(0:31) invalid GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1
(MIN = 0.375 ×B1 – 3.00)
8.40 — 6.40 — 4.50 — 2.70 — ns
B30d WE(0:3)/BS_B[0:3] negated to A(0:31),
BADDR(28:30) invalid GPCM write
access TRLX = 1, CSNT =1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10
or 11, EBDF = 1
38.67 — 31.38 — 24.50 — 17.83 — ns
B31 CLKOUT falling edge to CS valid, as
requested by control bit CST4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B31a CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B31b CLKOUT rising edge to CS valid, as
requested by control bit CST2 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
B31c CLKOUT rising edge to CS valid, as
requested by control bit CST3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.30)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM
EBDF = 1 (MAX = 0.375 ×B1 + 6.6)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B32 CLKOUT falling edge to BS valid, as
requested by control bit BST4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B32a CLKOUT falling edge to BS valid, as
requested by control bit BST1 in the
corresponding word in the UPM,
EBDF = 0 (MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32b CLKOUT rising edge to BS valid, as
requested by control bit BST2 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 8.00)
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
20 Freescale Semiconductor
Bus Signal Timing
B32c CLKOUT rising edge to BS valid, as
requested by control bit BST3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32d CLKOUT falling edge to BS valid, as
requested by control bit BST1 in the
corresponding word in the UPM,
EBDF = 1 (MAX = 0.375 ×B1 + 6.60)
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B33 CLKOUT falling edge to GPL valid, as
requested by control bit GxT4 in the
corresponding word in the UPM
(MAX = 0.00 ×B1 + 6.00)
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B33a CLKOUT rising edge to GPL valid, as
requested by control bit GxT3 in the
corresponding word in the UPM
(MAX = 0.25 ×B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B34 A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by control bit
CST4 in the corresponding word in the
UPM (MIN = 0.25 ×B1–2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B34a A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by control bit
CST1 in the corresponding word in the
UPM (MIN = 0.50 ×B1–2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B34b A(0:31), BADDR(28:30), and D(0:31) to
CS valid, as requested by CST2 in the
corresponding word in UPM
(MIN = 0.75 ×B1 – 2.00)
20.70 — 16.70 — 13.00 — 9.40 — ns
B35 A(0:31), BADDR(28:30) to CS valid, as
requested by control bit BST4 in the
corresponding word in the UPM
(MIN = 0.25 ×B1 – 2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
B35a A(0:31), BADDR(28:30), and D(0:31) to
BS valid, as requested by BST1 in the
corresponding word in the UPM
(MIN = 0.50 ×B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
B35b A(0:31), BADDR(28:30), and D(0:31) to
BS valid, as requested by control bit
BST2 in the corresponding word in the
UPM (MIN = 0.75 ×B1–2.00)
20.70 — 16.70 — 13.00 — 9.40 — ns
B36 A(0:31), BADDR(28:30), and D(0:31) to
GPL valid, as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 ×B1–2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 21
Bus Signal Timing
B37 UPWAIT valid to CLKOUT falling edge 9
(MIN = 0.00 ×B1 + 6.00)
6.00 — 6.00 — 6.00 — 6.00 — ns
B38 CLKOUT falling edge to UPWAIT valid 9
(MIN = 0.00 ×B1 + 1.00)
1.00 — 1.00 — 1.00 — 1.00 — ns
B39 AS valid to CLKOUT rising edge 10
(MIN = 0.00 ×B1 + 7.00)
7.00 — 7.00 — 7.00 — 7.00 — ns
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge
(MIN = 0.00 ×B1 + 7.00)
7.00 — 7.00 — 7.00 — 7.00 — ns
B41 TS valid to CLKOUT rising edge (setup
time) (MIN = 0.00 ×B1 + 7.00)
7.00 — 7.00 — 7.00 — 7.00 — ns
B42 CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00 ×B1 + 2.00)
2.00 — 2.00 — 2.00 — 2.00 — ns
B43 AS negation to memory controller
signals negation (MAX = TBD)
—TBD—TBD—TBD—TBDns
1
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time)
the maximum allowed jitter on EXTAL can be up to 2%.
2
For part speeds above 50 MHz, use 9.80 ns for B11a.
3
The timing required for BR input is relevant when the MPC853T is selected to work with the internal bus arbiter. The
timing for BG input is relevant when the MPC853T is selected to work with the external bus arbiter.
4
For part speeds above 50 MHz, use 2 ns for B17.
5
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
6
For part speeds above 50 MHz, use 2 ns for B19.
7
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18.
10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 21.
Table 9. Bus Operation Timings (continued)
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
MPC853T Hardware Specification, Rev. 1
22 Freescale Semiconductor
Bus Signal Timing
Figure 3 provides the contr ol timing dia gram.
Figure 3. Control Timing
Figure 4 provides the timing for the external clock.
Figure 4. External Clock Timing
CLKOUT
Outputs
A
B
2.0 V
0.8 V 0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
Outputs 2.0 V
0.8 V
2.0 V
0.8 V
B
A
Inputs 2.0 V
0.8 V
2.0 V
0.8 V
D
C
Inputs 2.0 V
0.8 V
2.0 V
0.8 V
C
D
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
CLKOUT
B1
B5
B3
B4
B1
B2
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 23
Bus Signal Timing
Figure 5 provides the timing for the synchronous output signa ls.
Figure 5. Synchronous Output Signals Timing
Figure 6 provides the timing for the synchronous active pull-up and open-drain output signals.
Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
CLKOUT
Output
Signals
Output
Signals
Output
Signals
B8
B7 B9
B8a
B9B7a
B8b
B7b
CLKOUT
TS, BB
TA , BI
TEA
B13
B12B11
B11a B12a
B13a
B15
B14
MPC853T Hardware Specification, Rev. 1
24 Freescale Semiconductor
Bus Signal Timing
Figure 7 provides the timing for the synchronous input signals.
Figure 7. Synchronous Input Signals Timing
Figure 8 provides normal ca se ti ming for input data. I t also appl ies to normal read ac cesses under the contro l of the
UPM in the memory controller.
Figure 8. Input Data Timing in Normal Case
CLKOUT
TA, BI
TEA, KR,
RETRY
, CR
BB, BG, BR
B16
B17
B16a
B17a
B16b
B17
CLKOUT
TA
D[0:31],
DP[0:3]
B16
B17
B19
B18
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 25
Bus Signal Timing
Figure 9 provides the timing for the input dat a controll ed by the UPM for data beats where DLT3 = 1 in th e UP M
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 9. Input Data Timing When Controlled by the UPM in the Memory Controller and DLT3 = 1
Figure 10 throug h Figure 13 provide the timing for the external bus read controlled by various GPCM factors.
Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28
MPC853T Hardware Specification, Rev. 1
26 Freescale Semiconductor
Bus Signal Timing
Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a B23
B26
B19B18
B25B24
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B22b
B8
B22c B23
B24a B25 B26
B19B18
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 27
Bus Signal Timing
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)
Figure 14 throug h Figure 16 provide the timing for the external bus write c ontrolled by various GPCM factors.
CLKOUT
A[0:31]
CSx
OE
TS
D[0:31],
DP[0:3]
B11 B12
B8
B22a
B27
B27a
B22b B22c B19B18
B26
B23
MPC853T Hardware Specification, Rev. 1
28 Freescale Semiconductor
Bus Signal Timing
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
CLKOUT
A[0:31]
CSx
WE[0:3]
OE
TS
D[0:31],
DP[0:3]
B11
B8
B22 B23
B12
B30
B28B25
B26
B8 B9
B29
B29b
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 29
Bus Signal Timing
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
B23
B30a B30c
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11
B8
B22
B12
B28b B28d
B25
B26
B8
B28a
B9
B28c
B29c B29g
B29a B29f
MPC853T Hardware Specification, Rev. 1
30 Freescale Semiconductor
Bus Signal Timing
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1)
B23B22
B8
B12B11
CLKOUT
A[0:31]
CSx
WE[0:3]
TS
OE
D[0:31],
DP[0:3]
B30dB30b
B28b B28d
B25 B29e B29i
B26 B29d B29h
B28a B28c B9B8
B29b
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 31
Bus Signal Timing
Figure 17 provid es the timing for the exter nal bus controll e d by the UPM.
Figure 17. External Bus Timing (UPM-Controlled Signals)
CLKOUT
CSx
B31d
B8
B31
B34
B32b
G
PL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
A[0:31]
B31c
B31b
B34a
B32
B32a B32d
B34b
B36
B35b
B35a
B35
B33
B32c
B33a
B31a
MPC853T Hardware Specification, Rev. 1
32 Freescale Semiconductor
Bus Signal Timing
Figure 18 provid es the timing for the asynchr onous asserted UPWAIT signal controlled by the UPM.
Figure 18. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing
Figure 19 provid es the timing for the asynchr onous negated UPWAIT signal controll ed by the UPM.
Figure 19. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing
CLKOUT
CSx
UPWAIT
G
PL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3]
B37
B38
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 33
Bus Signal Timing
Figure 20 provid es the timing for the synch ronous external master access co ntrolled by the GPCM.
Figure 20. Synchronous External Master Access Timing (GPCM Handled—ACS = 00)
Figure 21 provid es the timing for the asynchr onous external master memory access controlle d by the GPCM.
Figure 21. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 22 provid es the timing for the asynchr onous external master control signa ls negation.
Figure 22. Asynchronous External Master—Control Signals Negation Timing
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
CSx
B41 B42
B40
B22
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
MPC853T Hardware Specification, Rev. 1
34 Freescale Semiconductor
Bus Signal Timing
Table 10 provides interrupt timing for the MPC853T.
.
Figure 23 provides the interrupt detection timing for the external level-sensitive lines.
Figure 23. Interrupt Detection Timing for External Level-Sensitive Lines
Figure 24 provides the interrupt detection timing for the external edge-sensitive lines.
Figure 24. Interrupt Detection Timing for External Edge-Sensitive Lines
Table 10. Interrupt Timing
Num Characteristic 1
1
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC853T is able to support.
All Frequencies
Unit
Min Max
I39 IRQx valid to CLKOUT rising edge (setup time) 6.00 ns
I40 IRQx hold time after CLKOUT 2.00 ns
I41 IRQx pulse width low 3.00 ns
I42 IRQx pulse width high 3.00 ns
I43 IRQx edge-to-edge time 4 ×TCLOCKOUT —
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I41 I42
I43
I43
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 35
Bus Signal Timing
Table 11 shows the PCMCIA timing for the MPC853T.
Table 11. PCMCIA Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
J82 A(0:31), REG valid to PCMCIA strobe
asserted 1 (MIN = 0.75 ×B1–2.00)
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITA signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITA assertion will be effective only if it is detected two cycles before the PSL timer expiration.
See the Chapter 16, “PCMCIA Interface,” in the
MPC866 PowerQUICC Family User’s Manual
.
20.70 — 16.70 — 13.00 — 9.40 — ns
J83 A(0:31), REG valid to ALE negation1
(MIN = 1.00 ×B1 – 2.00)
28.30 — 23.00 — 18.00 — 13.20 — ns
J84 CLKOUT to REG valid
(MAX = 0.25 ×B1 + 8.00)
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J85 CLKOUT to REG invalid
(MIN = 0.25 ×B1 + 1.00)
8.60 — 7.30 — 6.00 — 4.80 — ns
J86 CLKOUT to CE1, CE2 asserted
(MAX = 0.25 ×B1 + 8.00)
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J87 CLKOUT to CE1, CE2 negated
(MAX = 0.25 ×B1 + 8.00)
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
J88
CLKOUT to PCOE, IORD, PCWE,
IOWR assert time
(MAX = 0.00 ×B1 + 11.00)
— 11.00 — 11.00 — 11.00 — 11.00 ns
J89
CLKOUT to PCOE, IORD, PCWE,
IOWR negate time
(MAX = 0.00 ×B1 + 11.00)
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
J90 CLKOUT to ALE assert time
(MAX = 0.25 ×B1 + 6.30)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
J91 CLKOUT to ALE negate time
(MAX = 0.25 ×B1 + 8.00)
— 15.60 — 14.30 — 13.00 — 11.80 ns
J92 PCWE, IOWR negated to D(0:31)
invalid1 (MIN = 0.25 ×B1–2.00)
5.60 — 4.30 — 3.00 — 1.80 — ns
J93 WAITA and WAITB valid to CLKOUT
rising edge1 (MIN = 0.00 ×B1 + 8.00)
8.00 — 8.00 — 8.00 — 8.00 — ns
J94
CLKOUT rising edge to WAITA and
WAITB invalid1
(MIN = 0.00 ×B1 + 2.00)
2.00 — 2.00 — 2.00 — 2.00 — ns
MPC853T Hardware Specification, Rev. 1
36 Freescale Semiconductor
Bus Signal Timing
Figure 25 provides the PCMCIA access cycle timing for the external bus read.
Figure 25. PCMCIA Access Cycles Timing External Bus Read
CLKOUT
A[0:31]
REG
CE1/CE2
PCOE, IORD
TS
D[0:31]
ALE
B19B18
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 37
Bus Signal Timing
Figure 26 provides the PCMCIA access cycle timing for the external bus write.
Figure 26. PCMCIA Access Cycles Timing External Bus Write
Figure 27 provid es the PCMCIA WAIT signals detection timing.
Figure 27. PCMCIA WAIT Signals Detection Timing
CLKOUT
A[0:31]
REG
CE1/CE2
PCWE, IOWR
TS
D[0:31]
ALE
B9B8
P53P52 P52
P51P50
P48 P49
P46 P45
P44
P47
P54
CLKOUT
WAITA
P55
P56
MPC853T Hardware Specification, Rev. 1
38 Freescale Semiconductor
Bus Signal Timing
Table 12 shows the PCMCIA port timing for the MPC853T.
Figure 28 provid es the PCMCIA output port timing for the MPC853T.
Figure 28. PCMCIA Output Port Timing
Figure 29 provid es the PCMCIA in put port timing for the MPC853T.
Figure 29. PCMCIA Input Port Timing
Table 12. PCMCIA Port Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
J95 CLKOUT to OPx valid
(MAX = 0.00 ×B1 + 19.00)
— 19.00 — 19.00 — 19.00 — 19.00 ns
J96 HRESET negated to OPx
drive 1(MIN = 0.75 ×B1 + 3.00)
1
OP2 and OP3 only.
25.70 — 21.70 — 18.00 — 14.40 — ns
J97 IP_Xx valid to CLKOUT rising edge
(MIN = 0.00 ×B1 + 5.00)
5.00 — 5.00 — 5.00 — 5.00 — ns
J98 CLKOUT rising edge to IP_Xx invalid
(MIN = 0.00 ×B1 + 1.00)
1.00 — 1.00 — 1.00 — 1.00 — ns
CLKOUT
HRESET
Output
Signals
OP2, OP3
P57
P58
CLKOUT
Input
Signals
P59
P60
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 39
Bus Signal Timing
Table 13 shows the debug port timing fo r the MPC853T.
Figure 30 provid es the input timing for the debug port clock.
Figure 30. Debug Port Clock Input Timing
Figure 31 provid es the timing for the debug port.
Figure 31. Debug Port Timings
Table 13. Debug Port Timing
Num Characteristic
All Frequencies
Unit
Min Max
J82 DSCK cycle time 3 ×TCLOCKOUT —
J83 DSCK clock pulse width 1.25 ×TCLOCKOUT —
J84 DSCK rise and fall times 0.00 3.00 ns
J85 DSDI input data setup time 8.00 ns
J86 DSDI data hold time 5.00 ns
J87 DSCK low to DSDO data valid 0.00 15.00 ns
J88 DSCK low to DSDO invalid 0.00 2.00 ns
DSCK
D61
D61
D63
D62
D62
D63
DSCK
DSDI
DSDO
D64
D65
D66
D67
MPC853T Hardware Specification, Rev. 1
40 Freescale Semiconductor
Bus Signal Timing
Table 14 shows the reset tim ing for the MPC853T.
Table 14. Reset Timing
Num Characteristic
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
J82
CLKOUT to HRESET high
impedance
(MAX = 0.00 ×B1 + 20.00)
— 20.00 — 20.00 — 20.00 — 20.00 ns
J83
CLKOUT to SRESET high
impedance
(MAX = 0.00 ×B1 + 20.00)
— 20.00 — 20.00 — 20.00 — 20.00 ns
J84 RSTCONF pulse width
(MIN = 17.00 ×B1)
515.20 — 425.00 — 340.00 — 257.60 — ns
J85 — —————————
J86
Configuration data to HRESET
rising edge setup time
(MIN = 15.00 ×B1 + 50.00)
504.50 — 425.00 — 350.00 — 277.30 — ns
J87
Configuration data to RSTCONF
rising edge setup time
(MIN = 0.00 ×B1 + 350.00)
350.00 — 350.00 — 350.00 — 350.00 — ns
J88
Configuration data hold time after
RSTCONF negation
(MIN = 0.00 ×B1 + 0.00)
0.00 — 0.00 — 0.00 — 0.00 — ns
J89
Configuration data hold time after
HRESET negation
(MIN = 0.00 ×B1 + 0.00)
0.00 — 0.00 — 0.00 — 0.00 — ns
J90
HRESET and RSTCONF
asserted to data out drive
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
J91
RSTCONF negated to data out
high impedance
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
J92
CLKOUT of last rising edge
before chip three-states
HRESET to data out high
impedance
(MAX = 0.00 ×B1 + 25.00)
— 25.00 — 25.00 — 25.00 — 25.00 ns
J93 DSDI, DSCK setup
(MIN = 3.00 ×B1)
90.90 — 75.00 — 60.00 — 45.50 — ns
J94 DSDI, DSCK hold time
(MIN = 0.00 ×B1 + 0.00)
0.00 — 0.00 — 0.00 — 0.00 — ns
J95
SRESET negated to CLKOUT
rising edge for DSDI and DSCK
sample (MIN = 8.00 ×B1)
242.40 — 200.00 — 160.00 — 121.20 — ns
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 41
Bus Signal Timing
Figure 32 shows the reset timing for the data bus configuration.
Figure 32. Reset Timing—Configuration from Data Bus
Figure 33 provid es the reset timing fo r the data bus weak drive during configuration.
Figure 33. Reset Timing—Data Bus Weak Drive During Configuration
HRESET
RSTCONF
D[0:31] (IN)
R71
R74
R73
R75
R76
CLKOUT
HRESET
D[0:31] (OUT)
(Weak)
RSTCONF
R69
R79
R77 R78
MPC853T Hardware Specification, Rev. 1
42 Freescale Semiconductor
IEEE 1149.1 Electrical Specifications
Figure 34 provid es the reset timing fo r the debug port configuration.
Figure 34. Reset Timing—Debug Port Configuration
12 IEEE 1149.1 Electrical Specifications
Table 15 provides the JTAG timi ngs for the MPC853T shown in Figure 35 to Figure 38.
Table 15. JTAG Timing
Num Characteristic
All Frequencies
Unit
Min Max
J82 TCK cycle time 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — ns
J86 TMS, TDI data hold time 25.00 — ns
J87 TCK low to TDO data valid — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 ns
J90 TRST assert time 100.00 — ns
J91 TRST setup time to TCK low 40.00 — ns
J92 TCK falling edge to output valid — 50.00 ns
J93 TCK falling edge to output valid out of high impedance — 50.00 ns
J94 TCK falling edge to output high impedance — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81 R81
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 43
IEEE 1149.1 Electrical Specifications
Figure 35. JTAG Test Clock Input Timing
Figure 36. JTAG Test Access Port Timing Diagram
Figure 37. JTAG TRST Timing Diagram
TCK
J82 J83
J82 J83v
J84 J84
TCK
T
MS, TDI
TDO
J85
J86
J87
J88 J89
TCK
TRST
J91
J90
MPC853T Hardware Specification, Rev. 1
44 Freescale Semiconductor
CPM Electrical Characteristics
Figure 38. Boundary Scan (JTAG) Timing Diagram
13 CPM Electrical Characteristics
This section provide s the AC and DC electr ic al sp ecifica tions for the co mmunications pr oc essor m odule (CPM) of
the MPC853T.
13.1 Port C Interrupt AC Electrical Specifications
Table 16 provides the tim ings for port C interrupts.
Figure 39 shows the port C interrupt detection timing.
Figure 39. Port C Interrupt Detection Timing
Table 16. Port C Interrupt Timing
Num Characteristic
33.34 MHz
Unit
Min Max
35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns
36 Port C interrupt minimum time between active edges 55 — ns
TCK
Output
Signals
Output
Signals
Output
Signals
J92 J94
J93
J95 J96
Port C
35
36
(Input)
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 45
CPM Electrical Characteristics
13.2 IDMA Controller AC Electrical Specifications
Table 17 provides the IDMA contro ller timing s as shown in Figure 40 to Figure 43.
Figure 40. IDMA External Requests Timing Diagram
Table 17. IDMA Controller Timing
Num Characteristic
All Frequencies
Unit
Min Max
40 DREQ setup time to clock high 7 — ns
41 DREQ hold time from clock high 1
1
Applies to high-to-low mode (EDM=1)
3—ns
42 SDACK assertion delay from clock high — 12 ns
43 SDACK negation delay from clock low — 12 ns
44 SDACK negation delay from TA low — 20 ns
45 SDACK negation delay from clock high — 15 ns
46 TA assertion to falling edge of the clock setup time (applies to external TA)7 —ns
41
40
DREQ
(Input)
CLKO
(Output)
MPC853T Hardware Specification, Rev. 1
46 Freescale Semiconductor
CPM Electrical Characteristics
Figure 41. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
Figure 42. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
DATA
42
46
43
CLKO
(Output)
TS
(Output)
R/W
(Output)
TA
(Input)
SDACK
DATA
42 44
CLKO
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 47
CPM Electrical Characteristics
Figure 43. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
13.3 Baud-Rate Generator AC Electrical Specifications
Table 18 provides the baud- rate genera tor timings as shown in Figure 44.
Figure 44. Baud Rate Generator Timing Diagram
Table 18. Baud Rate Generator Timing
Num Characteristic
All Frequencies
Unit
Min Max
50 BRGO rise and fall time — 10 ns
51 BRGO duty cycle 40 60 %
52 BRGO cycle 40 — ns
DATA
42 45
CLKO
(Output)
TS
(Output)
R/W
(Output)
TA
(Output)
SDACK
52
50
51
BRGOX
50
51
MPC853T Hardware Specification, Rev. 1
48 Freescale Semiconductor
CPM Electrical Characteristics
13.4 Timer AC Electrical Specifications
Table 19 provides the gene ral-purpose timer timings as shown in Figure 45.
Figure 45. CPM General-Purpose Timers Timing Diagram
13.5 Serial Interface AC Electrical Specifications
Table 20 provides the serial interface (SI) timings as shown in Figure 46 to Figure 50.
Table 19. Timer Timing
Num Characteristic
All Frequencies
Unit
Min Max
61 TIN/TGATE rise and fall time 10 — ns
62 TIN/TGATE low time 1 — CLK
63 TIN/TGATE high time 2 — CLK
64 TIN/TGATE cycle time 3 — CLK
65 CLKO low to TOUT valid 3 25 ns
Table 20. SI Timing
Num Characteristic
All Frequencies
Unit
Min Max
70 L1RCLKB, L1TCLKB frequency (DSC = 0) 1, 2 — SYNCCLK/2
.5
MHz
71 L1RCLKB, L1TCLKB width low (DSC = 0) 2P + 10 — ns
71a L1RCLKB, L1TCLKB width high (DSC = 0) 3 P + 10 — ns
72 L1TXDB, L1ST1 and L1ST2, L1RQ, L1CLKO rise/fall time — 15.00 ns
73 L1RSYNCB, L1TSYNCB valid to L1CLKB edge (SYNC setup time) 20.00 — ns
74 L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time) 35.00 — ns
CLKO
TIN/TGATE
(Input)
TOUT
(Output)
64
65
61
626361
60
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 49
CPM Electrical Characteristics
75 L1RSYNCB, L1TSYNCB rise/fall time — 15.00 ns
76 L1RXDB valid to L1CLKB edge (L1RXDB setup time) 17.00 — ns
77 L1CLKB edge to L1RXDB invalid (L1RXDB hold time) 13.00 — ns
78 L1CLKB edge to L1ST1 and L1ST2 valid 4 10.00 45.00 ns
78A L1SYNCB valid to L1ST1 and L1ST2 valid 10.00 45.00 ns
79 L1CLKB edge to L1ST1 and L1ST2 invalid 10.00 45.00 ns
80 L1CLKB edge to L1TXDB valid 10.00 55.00 ns
80A L1TSYNCB valid to L1TXDB valid 410.00 55.00 ns
81 L1CLKB edge to L1TXDB high impedance 0.00 42.00 ns
82 L1RCLKB, L1TCLKB frequency (DSC =1) — 16.00 or
SYNCCLK/2
MHz
83 L1RCLKB, L1TCLKB width low (DSC =1) P + 10 — ns
83a L1RCLKB, L1TCLKB width high (DSC = 1)3P + 10 — ns
84 L1CLKB edge to L1CLKOB valid (DSC = 1) — 30.00 ns
85 L1RQB valid before falling edge of L1TSYNCB41.00 — L1TC
LK
86 L1GRB setup time242.00 — ns
87 L1GRB hold time 42.00 — ns
88 L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
—0.00ns
1
The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLKB edge or L1SYNCB, whichever comes
later.
Table 20. SI Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
MPC853T Hardware Specification, Rev. 1
50 Freescale Semiconductor
CPM Electrical Characteristics
Figure 46. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
L1RXDB
(Input)
L1RCLKB
(FE=0, CE=0)
(Input)
L1RCLKB
(FE=1, CE=1)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
71
72
70 71a
RFSD=1
75
73
74 77
78
76
79
BIT0
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 51
CPM Electrical Characteristics
Figure 47. SI Receive Timing with Double-Speed Clocking (DSC = 1)
L1RXDB
(Input)
L1RCLKB
(FE=1, CE=1)
(Input)
L1RCLKB
(FE=0, CE=0)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
72
RFSD=1
75
73
74 77
78
76
79
83a
82
L1CLKOB
(Output)
84
BIT0
MPC853T Hardware Specification, Rev. 1
52 Freescale Semiconductor
CPM Electrical Characteristics
Figure 48. SI Transmit Timing Diagram (DSC = 0)
L1TXDB
(Output)
L1TCLKB
(FE=0, CE=0)
(Input)
L1TCLKB
(FE=1, CE=1)
(Input)
L1TSYNCB
(Input)
L1ST(2-1)
(Output)
71 70
72
73
75
74
80a
80
78
TFSD=0
81
79
BIT0
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 53
CPM Electrical Characteristics
Figure 49. SI Transmit Timing with Double Speed Clocking (DSC = 1)
L1TXDB
(Output)
L1RCLKB
(FE=0, CE=0)
(Input)
L1RCLKB
(FE=1, CE=1)
(Input)
L1RSYNCB
(Input)
L1ST(2-1)
(Output)
72
TFSD=0
75
73
74
78a
80
79
83a
82
L1CLKOB
(Output)
84
BIT0
78
81
MPC853T Hardware Specification, Rev. 1
54 Freescale Semiconductor
CPM Electrical Characteristics
Figure 50. IDL Timing
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
L1RXDB
(Input)
L1TXDB
(Output)
L1ST(2-1)
(Output)
L1RQB
(Output)
73
77
12345678910 11 12 13 14 15 16 17 18 19 20
74
80
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
71
71
L1GRB
(Input)
78
85
72
76
87
86
L1RSYNCB
(Input)
L1RCLKB
(Input)
81
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 55
CPM Electrical Characteristics
13.6 SCC in NMSI Mode Electrical Specifications
Table 21 provides the NMSI external clock timing.
Table 22 provides the NMSI interna l clock timin g.
Table 21. NMSI External Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLK3 and TCLK3 width high 1
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.
1/SYNCCLK — ns
101 RCLK3 and TCLK3 width low 1/SYNCCLK +5 — ns
102 RCLK3 and TCLK3 rise/fall time — 15.00 ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 50.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 50.00 ns
105 CTS3 setup time to TCLK3 rising edge 5.00 — ns
106 RXD3 setup time to RCLK3 rising edge 5.00 — ns
107 RXD3 hold time from RCLK3 rising edge 2
2
Also applies to CD and CTS hold time when they are used as external sync signals.
5.00 — ns
108 CD3 setup Time to RCLK3 rising edge 5.00 — ns
Table 22. NMSI Internal Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLK3 and TCLK3 frequency 1
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLK3 and TCLK3 rise/fall time — — ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns
104 RTS3 active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns
105 CTS3 setup time to TCLK3 rising edge 40.00 — ns
106 RXD3 setup time to RCLK3 rising edge 40.00 — ns
107 RXD3 hold time from RCLK3 rising edge 2
2
Also applies to CD and CTS hold time when they are used as external sync signals.
0.00 — ns
108 CD3 setup time to RCLK3 rising edge 40.00 — ns
MPC853T Hardware Specification, Rev. 1
56 Freescale Semiconductor
CPM Electrical Characteristics
Figure 51 throug h Figure 53 show the NMSI timings.
Figure 51. SCC NMSI Receive Timing Diagram
Figure 52. SCC NMSI Transmit Timing Diagram
RCLK3
CD3
(Input)
102
100
107
108
107
RxD3
(Input)
CD3
S
YNC Input)
102 101
106
TCLK3
CTS3
(Input)
102
100
104
107
TxD3
(Output)
CTS3
(SYNC Input)
102 101
RTS3
(Output)
105
103
104
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 57
CPM Electrical Characteristics
Figure 53. HDLC Bus Timing Diagram
13.7 Ethernet Electrical Specifications
Table 23 provides the Ether net timings as shown in Figure 54 to Figure 58.
Table 23. Ethernet Timing
Num Characteristic
All Frequencies
Unit
Min Max
120 CLSN width high 40 — ns
121 RCLK3 rise/fall time — 15 ns
122 RCLK3 width low 40 — ns
123 RCLK3 clock period 1 80 120 ns
124 RXD3 setup time 20 — ns
125 RXD3 hold time 5 — ns
126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns
127 RENA width low 100 — ns
128 TCLK3 rise/fall time — 15 ns
129 TCLK3 width low 40 — ns
130 TCLK3 clock period199 101 ns
131 TXD3 active delay (from TCLK3 rising edge) — 50 ns
132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns
133 TENA active delay (from TCLK3 rising edge) 10 50 ns
TCLK3
CTS3
(Echo Input)
102
100
104
TxD3
(Output)
102 101
RTS3
(Output)
103
104107
105
MPC853T Hardware Specification, Rev. 1
58 Freescale Semiconductor
CPM Electrical Characteristics
Figure 54. Ethernet Collision Timing Diagram
Figure 55. Ethernet Receive Timing Diagram
134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns
135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns
136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns
137 REJECT width low 1 — CLK
138 CLKO1 low to SDACK asserted 2 —20ns
139 CLKO1 low to SDACK negated 2—20ns
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 23. Ethernet Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124 123
127
126
Last Bit
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 59
CPM Electrical Characteristics
Figure 56. Ethernet Transmit Timing Diagram
Figure 57. CAM Interface Receive Start Timing Diagram
Figure 58. CAM Interface REJECT Timing Diagram
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133 134
132
131 121
129
(NOTE 2)
RCLK3
RxD3
(Input)
RSTRT
(Output)
0
136
125
1 1 BIT1 BIT2
Start Frame De-
REJECT
137
MPC853T Hardware Specification, Rev. 1
60 Freescale Semiconductor
CPM Electrical Characteristics
13.8 SPI Master AC Electrical Specifications
Table 24 provides the SPI maste r timings as shown in Figure 59 and Figure 60.
Figure 59. SPI Master (CP = 0) Timing Diagram
Table 24. SPI Master Timing
Num Characteristic
All Frequencies
Unit
Min Max
160 MASTER cycle time 4 1024 tcyc
161 MASTER clock (SCK) high or low time 2 512 tcyc
162 MASTER data setup time (inputs) 15 — ns
163 Master data hold time (inputs) 0 — ns
164 Master data valid (after SCK edge) — 10 ns
165 Master data hold time (outputs) 0 — ns
166 Rise time output — 15 ns
167 Fall time output — 15 ns
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 61
CPM Electrical Characteristics
Figure 60. SPI Master (CP = 1) Timing Diagram
13.9 SPI Slave AC Electrical Specifications
Table 25 provides the SPI sla ve timings as shown in Figure 61 and Figure 62.
Table 25. SPI Slave Timing
Num Characteristic
All Frequencies
Unit
Min Max
170 Slave cycle time 2 — tcyc
171 Slave enable lead time 15 — ns
172 Slave enable lag time 15 — ns
173 Slave clock (SPICLK) high or low time 1 — tcyc
174 Slave sequential transfer delay (does not require deselect) 1 — tcyc
175 Slave data setup time (inputs) 20 — ns
176 Slave data hold time (inputs) 20 — ns
177 Slave access time — 50 ns
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164
162
MPC853T Hardware Specification, Rev. 1
62 Freescale Semiconductor
CPM Electrical Characteristics
Figure 61. SPI Slave (CP = 0) Timing Diagram
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182173
173 170
msb lsb msb
181
177 182
175 179
SPISEL
(Input)
171172
174
Datamsb lsb msbUndef
181
178
176 182
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 63
FEC Electrical Characteristics
Figure 62. SPI Slave (CP = 1) Timing Diagram
14 FEC Electrical Characteristics
This se ction provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the tim ing
specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII
signals use TTL signal leve ls compatibl e with devices opera ting a t either 5.0 V or 3.3 V.
14.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The recei ver functions correctly up to a MII_RX_CLK maximum freque ncy of 25MHz + 1%. There is no minimum
frequency re quirement. In a ddition, the proc essor cl ock frequency must e xceed the M II_RX_CLK freq uency –1%.
Table 26 provides inf ormation on the MII recei ve sig nal timing.
Table 26. MII Receive Signal Timing
Num Characteristic Min Max Unit
M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns
M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns
M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period
M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period
SPIMOSI
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
SPIMISO
(Output)
180
Data
181182
msb lsb
181
177 182
175 179
SPISEL
(Input)
174
Data
msb lsbUndef
178
176 182
msb
msb
172
173
173
171 170
181
MPC853T Hardware Specification, Rev. 1
64 Freescale Semiconductor
FEC Electrical Characteristics
Figure 63 shows MII receive signal timing .
Figure 63. MII Receive Signal Timing Diagram
14.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter f unctions cor rectly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK
frequency –1%.
Table 27 provides inf ormation on the MII trans mit signal timin g.
Table 27. MII Transmit Signal Timing
Num Characteristic Min Max Unit
M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns
M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25
M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period
M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period
M1 M2
MII_RX_CLK (input)
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M3
M4
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 65
FEC Electrical Characteristics
Figure 64 shows the MII transmit signal timing dia gram.
Figure 64. MII Transmit Signal Timing Diagram
14.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 28 provides inf ormation on the MII async inpu ts signal timing.
Figure 65 shows the MII asynchronous inputs signal timing diagram.
Figure 65. MII Async Inputs Timing Diagram
14.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 29 provides inf ormation on the MII serial mana ge ment channel signal timing. The FEC functi ons correct ly
with a maximum MDC frequency in excess of 2. 5 MHz. The exact uppe r bound is under inve stigation.
Table 28. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period
Table 29. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0— ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns
M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns
M6
MII_TX_CLK (input)
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
MII_CRS, MII_COL
M9
MPC853T Hardware Specification, Rev. 1
66 Freescale Semiconductor
FEC Electrical Characteristics
Figure 66 shows the MII serial management channel tim ing diagram.
Figure 66. MII Serial Management Channel Timing Diagram
M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns
M14 MII_MDC pulse width high 40% 60% MII_MDC period
M15 MII_MDC pulse width low 40% 60% MII_MDC period
Table 29. MII Serial Management Channel Timing (continued)
Num Characteristic Min Max Unit
M11
MII_MDC (output)
MII_MDIO (output)
M12 M13
MII_MDIO (input)
M10
M14
MM15
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 67
Mechanical Data and Ordering Information
15 Mechanical Data and Ordering Information
Table 30 identifie s the packages and operating frequencie s orderable for the MPC853T.
15.1 Pin Assignments
The fol lowing sect ions give t he pinout and pi n l isti ng for the JEDEC Complia nt an d the n on-JEDEC versi ons of the
16 x 16 PBGA package.
15.1.1 The JEDEC Compliant Pinout
Figure 67 shows the JEDEC pinout of the PBGA package as viewed from the top sur face. For additional
info rm atio n, se e the MPC866 PowerQUICC Family User’s Manual.
Table 30. MPC853T Package/Frequency Orderable
Package Type Temperature (Tj) Frequency (MHz) Order Number
Plastic ball grid array
(VR and ZT suffix)
0°C to 95°C 50 MPC853TVR50
MPC853TZT50
66 MPC853TVR66
MPC853TZT66
80 MPC853TVR80
MPC853TZT80
100 MPC853TVR100
MPC853TZT100
Plastic ball grid array
(CVR suffix)
–40°C to 100°C 66 TBD
MPC853T Hardware Specification, Rev. 1
68 Freescale Semiconductor
Mechanical Data and Ordering Information
NOTE: This is the top view of the device.
Figure 67. Pinout of the PBGA Package - JEDEC Standard
Table 31 contains a list of the MPC853T input and output signals and shows multiplexing and pin
assignments.
Table 31. Pin Assignments - JEDEC Standard
Name Pin Number Type
A[0:31] B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12,
B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8,
B11, A8, B10, B9, D8
Bidirectional
Three-state (3.3V only)
TSIZ0
REG
E8 Bidirectional
Three-state (3.3V only)
TSIZ1 E7 Bidirectional
Three-state (3.3V only)
RD/WR B1 Bidirectional
Three-state (3.3V only)
N/C
WR
VDDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0 CE2_A GPL_A3 WE3
GPL_A0
GPL_A4 CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI CS2 OE
MII_CRS BS_A3 A22 A30
WE0 BS_A1 A24
TS TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29VDDL
A
B
C
D
E
MII_COL BB
VFLS_1 RSV BURST
DSCK VFLS_0
AS BADDR30
OP1 OP2
BADDR29 BADDR28
VDDL
XTAL EXTCLK WAIT_A
PORST VDDSYN VSSSYN1
PC12 PA11
TMS TRST
VDDL MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
VDDL PA0
PD12 PD14
N/C PD11
GND
K
L
VDDH
M
N
VDDL IP_A7 IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN
P
R
T
D30
1234567 891011
12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
VDDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 69
Mechanical Data and Ordering Information
BURST G3 Bidirectional
Three-state (3.3V only)
BDIP
GPL_B5
D1 Output
TS E2 Bidirectional
Active Pull-up (3.3V only)
TA F4 Bidirectional
Active Pull-up (3.3V only)
TEA E3 Open-drain
BI D2 Bidirectional
Active Pull-up (3.3V only)
IRQ2
RSV
G2 Bidirectional
Three-state (3.3V only)
IRQ4
KR
RETRY
SPKROUT
J1 Bidirectional
Three-state (3.3V only)
CR
IRQ3
F1 Input (3.3V only)
D[0:31] R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12,
R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6,
P6, T5, R5
Bidirectional
Three-state (3.3V only)
DP0
IRQ3
P4 Bidirectional
Three-state (3.3V only)
DP1
IRQ4
P5 Bidirectional
Three-state (3.3V only)
DP2
IRQ5
T4 Bidirectional
Three-state (3.3V only)
DP3
IRQ6
R4 Bidirectional
Three-state (3.3V only)
BR E1 Bidirectional (3.3V only)
BG G4 Bidirectional (3.3V only)
BB F3 Bidirectional
Active Pull-up (3.3V only)
FRZ
IRQ6
H4 Bidirectional (3.3V only)
IRQ0 P13 Input (3.3V only)
IRQ1 M11 Input (3.3V only)
M_TX_CLK
IRQ7
N12 Input (3.3V only)
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
70 Freescale Semiconductor
Mechanical Data and Ordering Information
CS[0:5] B2, A2, D3, C3, E6, C4 Output
CS6 D4 Output
CS7 A3 Output
WE0
BS_B0
IORD
D6 Output
WE1
BS_B1
IOWR
C6 Output
WE2
BS_B2
PCOE
A5 Output
WE3
BS_B3
PCWE
B5 Output
BS_A[0:3] A6, D7, C7, B7 Output
GPL_A0
GPL_B0
C5 Output
OE
GPL_A1
GPL_B1
D5 Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
A4, B4 Output
UPWAITA
GPL_A4
C2 Bidirectional (3.3V only)
GPL_A5 E4 Output
PORESET P1 Input (3.3V only)
RSTCONF K4 Input (3.3V only)
HRESET J4 Open-drain
SRESET M3 Open-drain
XTAL N1 Analog Output
EXTAL M1 Analog Input (1.8V only)
CLKOUT N6 Output
EXTCLK N2 Input (1.8V only)
ALE_A H1 Output
CE1_A E5 Output
CE2_A B3 Output
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 71
Mechanical Data and Ordering Information
WAIT_A N3 Input (3.3V only)
IP_A0 T2 Input (3.3V only)
IP_A1 M6 Input (3.3V only)
IP_A2
IOIS16_A
R3 Input (3.3V only)
IP_A3 M5 Input (3.3V only)
IP_A4 T3 Input (3.3V only)
IP_A5 N5 Input (3.3V only)
IP_A6 M7 Input (3.3V only)
IP_A7 R2 Input (3.3V only)
DSCK H2 Bidirectional
Three-state (3.3V only)
IWP[0:1]
VFLS[0:1]
H3, G1 Bidirectional (3.3V only)
OP0 K1 Bidirectional (3.3V only)
OP1 K2 Output
OP2
MODCK1
STS
K3 Bidirectional (3.3V only)
OP3
MODCK2
DSDO
L1 Bidirectional (3.3V only)
BADDR[28:29] L3, L2 Output
BADDR30
REG
J3 Output
AS J2 Input (3.3V only)
PA 1 1
RXD3
L1TXDB
E16 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PA 1 0
TXD3
L1RXDB
H15 Bidirectional
(5V tolerant)
PA 9
RXD4
J16 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PA 8
TXD4
J15 Bidirectional
(5V tolerant)
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
72 Freescale Semiconductor
Mechanical Data and Ordering Information
PA 3
CLK5
BRGO3
TIN3
K16 Bidirectional
(5V tolerant)
PA 2
CLK6
TOUT3
L1RCLKB
K14 Bidirectional
(5V tolerant)
PA 1
CLK7
BRGO4
TIN4
L15 Bidirectional
(5V tolerant)
PA 0
CLK8
TOUT4
L1TCLKB
M16 Bidirectional
(5V tolerant)
PB31
SPISEL
E13 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB30
SPICLK
F13 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB29
SPIMOSI
D15 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB28
SPIMISO
BRGO4
G13 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB25
SMTXD1
H14 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB24
SMRXD1
H16 Bidirectional
(Optional: Open-drain)
(5V tolerant)
PB15
BRGO3
L16 Bidirectional
(5V tolerant)
PC15
DREQ0
C16 Bidirectional
(5V tolerant)
PC13
RTS3
L1RQB
L1ST3
E14 Bidirectional
(5V tolerant)
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 73
Mechanical Data and Ordering Information
PC12
RTS4
L1ST4
E15 Bidirectional
(5V tolerant)
PC7
L1TSYNCB
CTS3
J14 Bidirectional
(5V tolerant)
PC6
L1RSYNCB
CD3
K15 Bidirectional
(5V tolerant)
PC5
CTS4
SDACK1
J13 Bidirectional
(5V tolerant)
PC4
CD4
L14 Bidirectional
(5V tolerant)
PD15
MII-RXD3
M14 Bidirectional
(5V tolerant)
PD14
MII-RXD2
N16 Bidirectional
(5V tolerant)
PD13
MII-RXD1
K13 Bidirectional
(5V tolerant)
PD12
MII-MDC
N15 Bidirectional
(5V tolerant)
PD11
RXD3
MII-TXERR
P16 Bidirectional
(5V tolerant)
PD10
TXD3
MII-RXD0
R15 Bidirectional
(5V tolerant)
PD9
RXD4
MII-TXD0
N14 Bidirectional
(5V tolerant)
PD8
TXD4
MII_RX_CLK
M13 Bidirectional
(5V tolerant)
PD7
RTS3
MII_RX_ER
T15 Bidirectional
(5V tolerant)
PD6
RTS4
MII_RX_DV
N13 Bidirectional
(5V tolerant)
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
74 Freescale Semiconductor
Mechanical Data and Ordering Information
15.1.2 The Non-JEDEC Pinout
Figure 68 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional
info rm atio n, se e the MPC866 PowerQUICC Family User’s Manual.
PD5
MII-TXD3
R14 Bidirectional
(5V tolerant)
PD4
MII-TXD2
P14 Bidirectional
(5V tolerant)
PD3
MII-TXD1
M12 Bidirectional
(5V tolerant)
TMS F15 Input
(5V tolerant)
TDI
DSDI
G14 Input
(5V tolerant)
TCK
DSCK
H13 Input
(5V tolerant)
TRST F16 Input
(5V tolerant)
TDO
DSDO
F14 Output
(5V tolerant)
MII_CRS B6 Input
MII_MDIO G16 Bidirectional
(5V tolerant)
MII_TXEN T14 Output
(5V tolerant)
MII_COL F2 Input
VSSSYN N4 PLL analog GND
VSSSYN1 P3 PLL analog GND
VDDSYN P2 PLL analog VDD
GND G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9,
J10, J11, K6, K7, K8, K9, K10, K11
Power
VDDL A7, C1, D16, G15, L4, M2, R1, M15, T8 Power
VDDH F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12,
K5, K12, L5, L6, L7, L8, L9, L10, L11, L12
Power
N/C A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 No-connect
Table 31. Pin Assignments - JEDEC Standard (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 75
Mechanical Data and Ordering Information
NOTE: This is the top view of the device.
Figure 68. Pinout of the PBGA Package—non-JEDEC
Table 32 contains a list of the MPC853T input and output signals and shows multiplexing and pin assignments.
Table 32. Pin Assignments—Non-JEDEC
Name Pin Number Type
A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13,
C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10,
D9, C12, B9, C11, C10, E9
Bidirectional
Three-state (3.3 V only)
TSIZ0
REG
F9 Bidirectional
Three-state (3.3 V only)
TSIZ1 F8 Bidirectional
Three-state (3.3 V only)
RD/WR C2 Bidirectional
Three-state (3.3 V only)
N/C
WR
VDDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0 CE2_A GPL_A3 WE3
GPL_A0
GPL_A4 CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI CS2 OE
MII_CRS BS_A3 A22 A30
WE0 BS_A1 A24
TS TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29VDDL
B
C
D
E
MII_COL BB
VFLS_1 RSV BURST
DSCK VFLS_0
AS BADDR30
OP1 OP2
BADDR29 BADDR28
VDDL
XTAL EXTCLK WAIT_A
PORST VDDSYN VSSSYN1
PC12 PA11
TMS TRST
VDDL MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
VDDL PA0
PD12 PD14
N/C PD11
GND
K
L
VDDH
M
N
VDDL IP_A7 IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN
P
R
T
D30
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
VDDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1
U
17
MPC853T Hardware Specification, Rev. 1
76 Freescale Semiconductor
Mechanical Data and Ordering Information
BURST H4 Bidirectional
Three-state (3.3 V only)
BDIP
GPL_B5
E2 Output
TS F3 Bidirectional
Active pull-up
(3.3 V only)
TA G5 Bidirectional
Active pull-up
(3.3 V only)
TEA F4 Open drain
BI E3 Bidirectional
Active pull-up
(3.3 V only)
IRQ2
RSV
H3 Bidirectional
Three-state (3.3 V only)
IRQ4
KR
RETRY
SPKROUT
K2 Bidirectional
Three-state (3.3 V only)
CR
IRQ3
G2 Input (3.3 V only)
D[0:31] T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13,
T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9,
T12, T7, R7, U6, T6
Bidirectional
Three-state (3.3 V only)
DP0
IRQ3
R5 Bidirectional
Three-state (3.3 V only)
DP1
IRQ4
R6 Bidirectional
Three-state (3.3 V only)
DP2
IRQ5
U5 Bidirectional
Three-state (3.3 V only)
DP3
IRQ6
T5 Bidirectional
Three-state (3.3 V only)
BR F2 Bidirectional (3.3 V only)
BG H5 Bidirectional (3.3 V only)
BB G4 Bidirectional
Active pull-up
(3.3 V only)
FRZ
IRQ6
J5 Bidirectional (3.3 V only)
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 77
Mechanical Data and Ordering Information
IRQ0 R14 Input (3.3 V only)
IRQ1 N12 Input (3.3 V only)
IRQ7
M_TX_CLK
P13 Input (3.3 V only)
CS[0:5] C3, B3, E4, D4, F7, D5 Output
CS6 E5 Output
CS7 B4 Output
WE0
BS_B0
IORD
E7 Output
WE1
BS_B1
IOWR
D7 Output
WE2
BS_B2
PCOE
B6 Output
WE3
BS_B3
PCWE
C6 Output
BS_A[0:3] B7, E8, D8, C8 Output
GPL_A0
GPL_B0
D6 Output
OE
GPL_A1
GPL_B1
E6 Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
B5, C5 Output
UPWAITA
GPL_A4
D3 Bidirectional (3.3 V only)
GPL_A5 F5 Output
PORESET R2 Input (3.3 V only)
RSTCONF L5 Input (3.3 V only)
HRESET K5 Open drain
SRESET N4 Open drain
XTAL P2 Analog output
EXTAL N2 Analog Input (3.3 V only)
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
78 Freescale Semiconductor
Mechanical Data and Ordering Information
CLKOUT P7 Output
EXTCLK P3 Input (3.3 V only)
ALE_A J2 Output
CE1_A F6 Output
CE2_A C4 Output
WAIT_A P4 Input (3.3 V only)
IP_A0 U3 Input (3.3 V only)
IP_A1 N7 Input (3.3 V only)
IP_A2
IOIS16_A
T4 Input (3.3 V only)
IP_A3 N6 Input (3.3 V only)
IP_A4 U4 Input (3.3 V only)
IP_A5 P6 Input (3.3 V only)
IP_A6 N8 Input (3.3 V only)
IP_A7 T3 Input (3.3 V only)
DSCK J3 Bidirectional
Three-state (3.3 V only)
IWP[0:1]
VFLS[0:1]
J4, H2 Bidirectional (3.3 V only)
OP0 L2 Bidirectional (3.3 V only)
OP1 L3 Output
OP2
MODCK1
STS
L4 Bidirectional (3.3 V only)
OP3
MODCK2
DSDO
M2 Bidirectional (3.3 V only)
BADDR[28:29] M4, M3 Output
BADDR30
REG
K4 Output
AS K3 Input (3.3 V only)
PA11
RXD3
L1TXDB
F17 Bidirectional
(Optional: open-drain)
(5-V tolerant)
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 79
Mechanical Data and Ordering Information
PA10
TXD3
L1RXDB
J16 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PA9
RXD4
K17 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PA8
TXD4
K16 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PA3
CLK5
BRGO3
TIN3
L17 Bidirectional
(5-V tolerant)
PA2
CLK6
TOUT3
L1RCLKB
L15 Bidirectional
(5-V tolerant)
PA1
CLK7
BRGO4
TIN4
M16 Bidirectional
(5-V tolerant)
PA0
CLK8
TOUT4
L1TCLKB
N17 Bidirectional
(5-V tolerant)
PB31
SPISEL
F14 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PB30
SPICLK
G14 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PB29
SPIMOSI
E16 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PB28
SPIMISO
BRGO4
H14 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PB25
SMTXD1
J15 Bidirectional
(Optional: open-drain)
(5-V tolerant)
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
80 Freescale Semiconductor
Mechanical Data and Ordering Information
PB24
SMRXD1
J17 Bidirectional
(Optional: open-drain)
(5-V tolerant)
PB15
BRGO3
M17 Bidirectional
(5-V tolerant)
PC15
DREQ0
D17 Bidirectional
(5-V tolerant)
PC13
RTS3
L1RQB
L1ST3
F15 Bidirectional
(5-V tolerant)
PC12
RTS4
L1ST4
F16 Bidirectional
(5-V tolerant)
PC7
L1TSYNCB
CTS3
K15 Bidirectional
(5-V tolerant)
PC6
L1RSYNCB
CD3
L16 Bidirectional
(5-V tolerant)
PC5
CTS4
SDACK1
K14 Bidirectional
(5-V tolerant)
PC4
CD4
M15 Bidirectional
(5-V tolerant)
PD15
MII_RXD3
N15 Bidirectional
(5-V tolerant)
PD14
MII_RXD2
P17 Bidirectional
(5-V tolerant)
PD13
MII_RXD1
L14 Bidirectional
(5-V tolerant)
PD12
MII_MDC
P16 Bidirectional
(5-V tolerant)
PD11
RXD3
MII_TX_ER
R17 Bidirectional
(5-V tolerant)
PD10
TXD3
MII_RXD0
T16 Bidirectional
(5-V tolerant)
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 81
Mechanical Data and Ordering Information
PD9
RXD4
MII_TXD0
P15 Bidirectional
(5-V tolerant)
PD8
TXD4
MII_RX_CLK
N14 Bidirectional
(5-V tolerant)
PD7
RTS3
MII_RX_ER
U16 Bidirectional
(5-V tolerant)
PD6
RTS4
MII_RX_DV
P14 Bidirectional
(5-V tolerant)
PD5
MII_TXD3
T15 Bidirectional
(5-V tolerant)
PD4
MII_TXD2
R15 Bidirectional
(5-V tolerant)
PD3
MII_TXD1
N13 Bidirectional
(5-V tolerant)
TMS G16 Input
(5-V tolerant)
TDI
DSDI
H15 Input
(5-V tolerant)
TCK
DSCK
J14 Input
(5-V tolerant)
TRST G17 Input
(5-V tolerant)
TDO
DSDO
G15 Output
(5-V tolerant)
MII_CRS C7 Input
MII_MDIO H17 Bidirectional
(5-V tolerant)
MII_TX_EN U15 Output
(5-V tolerant)
MII_COL G3 Input
VSSSYN P5 PLL analog GND
VSSSYN1 R4 PLL analog GND
VDDSYN R3 PLL analog VDD
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
82 Freescale Semiconductor
Mechanical Data and Ordering Information
GND H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9,
K10, K11, K12, L7, L8, L9, L10, L11, L12
Power
VDDL B8, D2, E17, H16, M5, N3, T2, N16, U9 Power
VDDH G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13,
L6, L13, M6, M7, M8, M9, M10, M11, M12, M13
Power
N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 No-connect
Table 32. Pin Assignments—Non-JEDEC (continued)
Name Pin Number Type
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 83
Mechanical Data and Ordering Information
15.2 Mechanical Dimensions of the PBGA Package
Figure 69 shows the mechanical dimensions of the PBGA package.
Figure 69. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC853TVRXXX
Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC853TZTXXX
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
NOTES:
MPC853T Hardware Specification, Rev. 1
84 Freescale Semiconductor
References
16 References
Semiconductor Equipme nt and Materials International (415) 964- 5111
805 East Middlefield Rd
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifi cations 800-854-717 9 or
(Avail able from Global Engineering Documents) 303-397-7956
JEDEC Specifications http://ww w.jedec.org
1. C.E. Triplett and B. Joine r, “An Experimental Characterizat ion of a 272 PBGA Within an Automotive Engine
Controller Module, ” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joine r and V. Adams, “ Measurement a nd Simulation of Junction to Board Thermal Resistance and Its
Application in Therm al Modeling,” Proceedings of SemiThe rm, San Die go, 1999, pp. 212-220.
17 Document Revision History
Table 33 lists significa nt change s between revi sions of this hardwar e specific ation.
Table 33. Document Revision History
Revision
Number Date Changes
0 10/2003 Initial release.
0.1 12/2003 Added overbars to signals CR (pin G2) and WAIT_A (pin P4) on Figure 62 on
page 63.
1.0 12/2004 • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment
for Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Broke the Section 15.1, “Pin Assignments” into 2 smaller sections for the
JEDEC and non-JEDEC pinouts.
MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 85
Document Revision History
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MPC853T Hardware Specification, Rev. 1
86 Freescale Semiconductor
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MPC853T Hardware Specification, Rev. 1
Freescale Semiconductor 87
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MPC853TEC
Rev. 1
12/2004
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