ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE FEATURES APPLICATIONS * 2.7-V to 5.5-V Analog Supply, Low Power: - 15.5 mW (1 MHz, +VA = 3 V, +VBD = 1.8 V) * 1-MHz Sampling Rate 3 V +VA 5.5 V, 900-kHz Sampling Rate 2.7 V +VA 3 V * Excellent DC Performance: 1.0 LSB Typ, 1.75 LSB Max INL 0.5 LSB Typ, 1 LSB Max DNL 16-Bit NMC Over Temperature 0.5 mV Max Offset Error at 3 V 1 mV Max Offset Error at 5 V * Excellent AC Performance at fI = 10 kHz with 93 dB SNR, 105 dB SFDR, -102 dB THD * Built-In Conversion Clock (CCLK) * 1.65 V to 5.5 V I/O Supply: SPI/DSP Compatible Serial SCLK up to 50 MHz * Comprehensive Power-Down Modes: Deep Power-Down Nap Power-Down Auto Nap Power-Down * Unipolar Input Range: 0 V to VREF * Software Reset * Global CONVST (Independent of CS) * Programmable Status/Polarity EOC/INT * 16-Pin 4 x 4 QFN and 16-Pin TSSOP Packages * Multi-Chip Daisy Chain Mode * Programmable TAG Bit Output * Auto/Manual Channel Select Mode (ADS8330) * * * * * * * 1 2 Communications Transducer Interface Medical Instruments Magnetometers Industrial Process Control Data Acquisition Systems Automatic Test Equipment DESCRIPTION The ADS8329 is a low-power, 16-bit, 1-MSPS analog-to-digital converter (ADC) with a unipolar input. The device includes a 16-bit capacitor-based SAR ADC with inherent sample-and-hold. The ADS8330 is based on the same core and includes a 2-to-1 input MUX with programmable option of TAG bit output. Both the ADS8329 and ADS8330 offer a high-speed, wide voltage serial interface and are capable of chain mode operation when multiple converters are used. These converters are available in 4 x 4 QFN and 16-pin TSSOP packages, and are fully specified for operation over the industrial -40C to +85C temperature range. Low Power, High-Speed SAR Converter Family Type/Speed 16-bit single-ended 14-bit single-ended 12-bit single ended ADS8330 ADS8329 +IN1 NC +IN0 COM +IN -IN REF+ REF- 1 MSPS ADS8327 ADS8329 Dual ADS8328 ADS8330 Single -- ADS7279 Dual -- ADS7280 Single -- ADS7229 Dual -- ADS7230 OUTPUT LATCH and 3-STATE DRIVER SAR + _ 500 kSPS Single SDO CDAC COMPARATOR OSC CONVERSION and CONTROL LOGIC FS/CS SCLK SDI CONVST EOC/INT/CDI 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2009, Texas Instruments Incorporated ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MAXIMUM INTEGRAL LINEARITY (LSB) MODEL ADS8329I 2.5 MAXIMUM DIFFERENTIAL LINEARITY (LSB) MAXIMUM OFFSET ERROR (mV) -1/+2 PACKAGE TYPE PACKAGE DESIGNATOR 4 x 4 QFN-16 RSA 0.8 4 x 4 QFN-16 1.75 1 -1/+2 1 Tube, 90 ADS8329IPWR Tape and reel, 2000 ADS8329IBRSAT Small tape and reel, 250 ADS8329IBRSAR Tape and reel, 3000 ADS8329IBPW Tube, 90 ADS8329IBPWR Tape and reel, 2000 ADS8330IRSAT Small tape and reel, 250 ADS8330IRSAR Tape and reel, 3000 PW RSA ADS8330IPW Tube, 90 ADS8330IPWR Tape and reel, 2000 ADS8330IBRSAT Small tape and reel, 250 ADS8330IBRSAR Tape and reel, 3000 PW RSA 0.5 -40C to +85C TSSOP-16 (1) Tape and reel, 3000 ADS8329IPW -40C to +85C 4 x 4 QFN-16 1.75 Small tape and reel, 250 RSA 0.8 TSSOP-16 ADS8330IB ADS8329IRSAT ADS8329IRSAR -40C to +85C 4 x 4 QFN-16 2.5 TRANSPORT MEDIA, QUANTITY PW 0.5 TSSOP-16 ADS8330I ORDERING INFORMATION -40C to +85C TSSOP-16 ADS8329IB TEMPERATURE RANGE ADS8330IBPW Tube, 90 ADS8330IBPWR Tape and reel, 2000 PW For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) UNIT Voltage Voltage range +IN to AGND -0.3 V to +VA + 0.3 V -IN to AGND -0.3 V to +VA + 0.3 V +VA to AGND -0.3 V to 7 V +REF to AGND -0.3 V to +VA + 0.3 V -REF to AGND -0.3 V to 0.3 V +VBD to BDGND -0.3 V to 7 V AGND to BDGND -0.3 V to 0.3 V Digital input voltage to BDGND -0.3 V to +VBD + 0.3 V Digital output voltage to BDGND -0.3 V to +VBD + 0.3 V TA Operating free-air temperature range -40C to +85C Tstg Storage temperature range -65C to +150C Junction temperature (TJ max) (1) 2 4 x 4 QFN-16 package Power dissipation TSSOP-16 package Power dissipation +150C (TJMax - TA)/JA JA thermal impedance +47C/W (TJMax - TA)/JA JA thermal impedance +86C/W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ELECTRICAL CHARACTERISTICS TA = -40C to 85C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 5 V, and fSAMPLE = 1 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) Absolute input voltage +IN - (-IN) or (+INx - COM) 0 +VREF +IN, +IN0, +IN1 AGND - 0.2 +VA + 0.2 -IN or COM AGND - 0.2 AGND + 0.2 Input capacitance Input leakage current Input channel isolation, ADS8330 only 40 No ongoing conversion, dc input -1 At dc 109 VI = 1.25 VPP at 50 kHz 101 V 45 pF 1 nA dB SYSTEM PERFORMANCE Resolution 16 No missing codes Bits 16 Bits INL Integral linearity ADS8329IB, ADS8330IB DNL Differential linearity ADS8329IB, ADS8330IB -1 0.4 1 ADS8329I, ADS8330I -1 0.5 2 EO Offset error (3) -1 0.27 1 -1.25 0.8 1.25 ADS8329I, ADS8330I ADS8329IB, ADS8330IB ADS8329I, ADS8330I Offset error drift EG -1.75 1.2 1.75 -2.5 1.5 2.5 FSR = 5 V Gain error +0.4 -0.25 Gain error drift CMRR Common-mode rejection ratio At dc 70 VI = 0.4 VPP at 1 MHz 50 Power-supply rejection ratio At FFFFh output code (3) LSB (2) mV ppm/C 0.25 +0.75 Noise PSRR -0.04 LSB (2) %FSR ppm/C dB 33 V RMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Acquisition time Manual trigger Auto trigger 3 Throughput rate (1) (2) (3) CCLK 3 1 MHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span; does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [+IN - (-IN)] of 4.096 V when +VA = 5 V. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 3 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = -40C to 85C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 5 V, and fSAMPLE = 1 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) SNR Signal-to-noise ratio VIN = 5 VPP at 10 kHz -102 VIN = 5 VPP at 100 kHz -95 VIN = 5 VPP at 10 kHz SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range VIN = 5 VPP at 100 kHz dB 93 ADS8329/30IB 90 ADS8329/30I 92 dB 90 VIN = 5 VPP at 10 kHz 92 VIN = 5 VPP at 100 kHz 90 VIN = 5 VPP at 10 kHz 105 VIN = 5 VPP at 100 kHz 97 -3dB small-signal bandwidth dB dB 30 MHz CLOCK Internal conversion clock frequency SCLK external serial clock 21 22.9 Used as I/O clock only 24.5 50 As I/O clock and conversion clock 1 42 0.3 +VA -0.1 0.1 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range VREF[(REF+) - (REF-)] 5.5 V +VA 4.5 V (REF-) - AGND Resistance (5) Reference input 40 V k DIGITAL INPUT/OUTPUT Logic family--CMOS VIH High-level input voltage 5.5 V +VBD 4.5 V 0.65 x (+VBD) +VBD + 0.3 V 0.35 x (+VBD) V 50 nA VIL Low-level input voltage 5.5 V +VBD 4.5 V -0.3 II Input current VI = +VBD or BDGND -50 CI Input capacitance 5 VOH High-level output voltage 5.5 V +VBD 4.5 V, IO = 100 A VOL Low-level output voltage 5.5 V +VBD 4.5 V, IO = 100 A CO Output capacitance CL Load capacitance pF +VBD - 0.6 +VBD V 0 0.4 V 5 pF 30 pF Data format--straight binary POWER-SUPPLY REQUIREMENTS Power-supply voltage +VBD 1.65 3.3 5.5 V 4.5 5 5.5 V 1-MHz Sample rate 7.0 7.8 NAP/Auto-NAP mode 0.3 0.5 4 50 +VA Supply current Deep power-down mode Buffer I/O supply current Power dissipation 1 MSPS 1.7 +VA = 5 V, +VBD = 5 V 44 48 +VA = 5 V, +VBD = 1.8 V 35 39.5 mA nA mA mW TEMPERATURE RANGE TA (4) (5) 4 Operating free-air temperature -40 +85 C Calculated on the first nine harmonics of the input frequency. Can vary 30%. Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ELECTRICAL CHARACTERISTICS TA = -40C to 85C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5x(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V +VA 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA 2.7 V using external clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) +IN - (-IN) or (+INx - COM) Absolute input voltage 0 +VREF +IN, +IN0, +IN1 AGND - 0.2 +VA + 0.2 -IN or COM AGND - 0.2 AGND + 0.2 Input capacitance 40 No ongoing conversion, DC Input Input leakage current Input channel isolation, ADS8330 only -1 At dc 108 VI = 1.25 VPP at 50 kHz 101 V 45 pF 1 nA dB SYSTEM PERFORMANCE Resolution 16 No missing codes INL Integral linearity ADS8329IB, ADS8330IB Differential linearity Offset error (3) EO 1 1.75 -2.5 1.5 2.5 ADS8329IB, ADS8330IB -1 0.5 1 ADS8329I, ADS8330I -1 0.8 2 ADS8329IB, ADS8330IB -0.5 0.05 0.5 ADS8329I, ADS8330I -0.8 0.2 0.8 -0.25 -0.04 Offset error drift EG FSR = 2.5 V +0.8 Gain error Gain error drift CMRR Common-mode rejection ratio At dc 70 VI = 0.4 VPP at 1 MHz 50 Power-supply rejection ratio At FFFFh output code (3) LSB (2) LSB (2) mV ppm/C 0.25 +0.5 Noise PSRR Bits -1.75 ADS8329I, ADS8330I DNL Bits 16 %FSR ppm/C dB 33 V RMS 78 dB 18 CCLK SAMPLING DYNAMICS tCONV tSAMPLE1 tSAMPLE2 Conversion time Manual trigger Acquisition time Auto trigger 3 Throughput rate (1) (2) (3) CCLK 3 1 MHz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns Ideal input span, does not include gain or offset error. LSB means least significant bit. Measured relative to an ideal full-scale input [+IN - (-IN)] of 2.5 V when +VA = 3 V. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 5 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = -40C to 85C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5x(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V +VA 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA 2.7 V using external clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS THD Total harmonic distortion (4) SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range VIN = 2.5 VPP at 10 kHz -102 VIN = 2.5 VPP at 100 kHz -93 VIN = 2.5 VPP at 10 kHz 89 VIN = 2.5 VPP at 100 kHz 88 VIN = 2.5 VPP at 10 kHz dB dB 88.5 VIN = 2.5 VPP at 100 kHz dB 88 VIN = 2.5 VPP at 10 kHz 104 VIN = 2.5 VPP at 100 kHz 94.2 -3dB small-signal bandwidth dB 30 MHz CLOCK Internal conversion clock frequency SCLK external serial clock 21 22.3 Used as I/O clock only 23.5 42 As I/O clock and conversion clock 1 42 fSAMPLE 500kSPS, 2.7 V +VA < 3V 0.3 2.525 fSAMPLE 500kSPS, 3 V +VA < 3.6V 0.3 3 fSAMPLE > 500kSPS, 2.7 V +VA < 3V 2.475 2.525 fSAMPLE > 500kSPS, 3 V +VA 3.6V 2.475 3 MHz MHz EXTERNAL VOLTAGE REFERENCE INPUT VREF Input reference range VREF[(REF+) - (REF-)] (REF-) - AGND Resistance (5) -0.1 Reference input V 0.1 40 k DIGITAL INPUT/OUTPUT Logic family--CMOS VIH High-level input voltage (+VA x 1.5) V +VBD 1.65 V 0.65 x (+VBD) +VBD + 0.3 VIL Low-level input voltage (+VA x 1.5) V +VBD 1.65 V -0.3 0.35 x (+VBD) V II Input current VI = +VBD or BDGND -50 50 nA CI Input capacitance 5 VOH High-level output voltage (+VA x 1.5) V +VBD 1.65 V, IO = 100 A VOL Low-level output voltage (+VA x 1.5) V +VBD 1.65 V, IO = 100 A CO Output capacitance CL Load capacitance V pF +VBD - 0.6 +VBD V 0 0.4 V 5 pF 30 pF Data format--straight binary (4) (5) 6 Calculated on the first nine harmonics of the input frequency. Can vary 30%. Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ELECTRICAL CHARACTERISTICS (continued) TA = -40C to 85C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5x(+VA), VREF = 2.5 V, fSAMPLE = 1 MHz for 3 V +VA 3.6 V, fSAMPLE = 900 kHz for 3 V < +VA 2.7 V using external clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.65 +VA 1.5 x (+VA) UNIT POWER-SUPPLY REQUIREMENTS +VBD Power-supply voltage fs 1 MHz +VA fs 900 kHz 3 3.6 2.7 3.6 1-MHz sample rate, 3 V +VA 3.6 V Supply current 5.1 Buffer I/O supply current 4.84 NAP/Auto-NAP mode 0.25 0.4 2 50 Power dissipation 1 MSPS, +VBD = 1.8 V 0.05 +VBD = 1.8 V, 3 V +VA 3.6 V 15.5 +VBD = 1.8 V, 2.7 V +VA 3 V 13.2 V 6.1 900-kHz sample rate, 2.7 V +VA 3 V Deep power-down mode V mA nA mA 19 mW TEMPERATURE RANGE TA Operating free-air temperature -40 Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 +85 Submit Documentation Feedback C 7 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS All specifications typical at -40C to 85C and +VA = +VBD = 5 V. (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal, fCCLK = 1/2 fSCLK 21 TYP MAX UNIT 21 MHz 22.9 24.5 tsu(CSF-EOC) Setup time, falling edge of CS to EOC th(CSF-EOC) Hold time, falling edge of CS to EOC twL(CONVST) Pulse duration, CONVST low tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tsu(CSF-SCLK1F) Setup time, falling edge of CS to first falling SCLK 5 ns twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) - 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) - 8 ns I/O Clock only Cycle time, SCLK CCLK 0 ns 40 ns 20 I/O and conversion clock tc(SCLK) 1 I/O Clock, chain mode I/O and conversion clock, chain mode 23.8 2000 ns 20 23.8 2000 td(SCLKF-SDOINVALID) Delay time, falling edge of SCLK to SDO invalid 10-pF Load td(SCLKF-SDOVALID) Delay time, falling edge of SCLK to SDO valid 10-pF Load 10 ns td(CSF-SDOVALID) Delay time, falling edge of CS to SDO valid, SDO MSB output 10-pF Load 8.5 ns tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns td(CSR-SDOZ) Delay time, rising edge of CS/FS to SDO 3-state tsu(16th SCLKF-CSR) Setup time, 16th falling edge of SCLK before rising edge of CS/FS td(SDO-CDI) Delay time, CDI high to SDO high in daisy chain mode (1) (2) 8 2 ns 5 10 10-pF Load, chain mode ns ns 16 ns All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 TIMING CHARACTERISTICS All specifications typical at -40C to 85C, +VA = 2.7 V, +VBD = 1.8 V (unless otherwise noted) PARAMETER fCCLK Frequency, conversion clock, CCLK (1) (2) MIN TYP MAX External, 3 V +VA 3.6 V, fCCLK = 1/2 fSCLK 0.5 21 External, 2.7 V +VA 3 V, fCCLK = 1/2 fSCLK 0.5 18.9 Internal, fCCLK = 1/2 fSCLK 20 22.3 UNIT MHz 23.5 tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns tsu(CSF-SCLK1F) Setup time, falling edge of CS to first falling SCLK 5 ns twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) - 8 ns twH(SCLK) Pulse duration, SCLK high ns tc(SCLK) Cycle time, SCLK 8 tc(SCLK) - 8 All modes, 3 V +VA 3.6 V 23.8 2000 All modes, 2.7 V +VA < 3 V 26.5 2000 ns td(SCLKF-SDOINVALID) Delay time, falling edge of SCLK to SDO invalid 10-pF Load td(SCLKF-SDOVALID) Delay time, falling edge of SCLK to SDO valid 10-pF Load 16 10-pF Load, 2.7 V +VA 3 V 13 td(CSF-SDOVALID) Delay time, falling edge of CS to SDO valid, SDO MSB output 10-pF Load, 3 V +VA 3.6 V 11 7.5 ns ns ns tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns td(CSR-SDOZ) Delay time, rising edge of CS/FS to SDO 3-state tsu(16th SCLKF-CSR) Setup time, 16th falling edge of SCLK before rising edge of CS/FS td(SDO-CDI) Delay time, CDI high to SDO high in daisy chain mode (1) (2) 8 10 10-pF Load, chain mode ns ns 23 ns All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 9 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com PIN ASSIGNMENTS ADS8329 RSA PACKAGE (TOP VIEW) AGND COM +IN0 15 14 13 2 11 +VA CONVST 3 10 +VBD EOC/INT/CDI 4 9 SCLK 8 NC BDGND SCLK +IN1 7 9 12 SDO 4 1 6 EOC/INT/CDI REF+ (REFIN) SDI +VBD REF- +IN 13 10 BDGND 3 8 CONVST 16 -IN 14 +VA 7 11 SDO 2 5 AGND 15 NC 6 RESERVED SDI 12 5 1 FS/CS REF+ (REFIN) FS/CS REF16 ADS8330 RSA PACKAGE (TOP VIEW) CAUTION: The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. ADS8329 PW PACKAGE (TOP VIEW) +VA RESERVED +IN -IN AGND REFREF+ (REFIN) NC ADS8330 PW PACKAGE (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 +VBD SCLK BDGND SDO SDI FS/CS EOC/INT/CDI CONVST +VA +IN1 +IN0 COM AGND REFREF+ (REFIN) NC 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 +VBD SCLK BDGND SDO SDI FS/CS EOC/INT/CDI CONVST NC = No internal connection 10 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ADS8329 Terminal Functions NO. QFN TSSOP I/O AGND NAME 15 5 -- Analog ground BDGND 8 14 -- Interface ground CONVST 3 9 I Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. EOC/ INT/ CDI DESCRIPTION 4 10 O 5 11 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave select (SS-). +IN 13 3 I Noninverting input -IN 14 4 I Inverting input, usually connected to ground NC 2 8 -- REF+ 1 7 I External reference input. REF- 16 6 I Connect to AGND through individual via. RESERVED 12 2 I Connect to AGND or +VA SCLK 9 15 I Clock for serial interface SDI 6 12 I Serial data in SDO 7 13 O Serial data out +VA 11 1 Analog supply, +2.7 V to +5.5 VDC. +VBD 10 16 Interface supply FS/CS No connection. ADS8330 Terminal Functions NO. NAME QFN TSSOP I/O 15 5 -- Analog ground BDGND 8 14 -- Interface ground COM 14 4 I Common inverting input, usually connected to ground CONVST 3 9 I Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. AGND EOC/ INT/ CDI DESCRIPTION 4 10 O 5 11 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface +IN1 12 2 I Second noninverting input. +IN0 13 3 I First noninverting input NC 2 8 -- REF+ 1 7 I External reference input. REF- 16 6 I Connect to AGND through individual via. SCLK 9 15 I Clock for serial interface SDI 6 12 I Serial data in (conversion start and reset possible) SDO 7 13 O Serial data out +VA 11 1 Analog supply, +2.7 V to +5.5 VDC. +VBD 10 16 Interface supply FS/CS No connection. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 11 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com MANUAL TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) Nth Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) tSAMPLE1 = 3 CCLKs min th(CSR-EOS) th(CSF-EOC) th(CSF-EOS) EOS twL(CONVST) EOC EOC (active low) EOS EOC CONVST th(CSF-EOC) tsu(CSF-EOC) tsu(CSF-EOS) CS/FS 1 SCLK 1 . . . . . . . . . . . . . . . . . . . . 16 SDO td(CSR-EOS) = 20 ns min Nth Nth-1st SDI 1101b 1101b READ Result READ Result Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while sampling) AUTO TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) tCONV = 18 CCLKs tSAMPLE2 = 3 CCLKs Nth tSAMPLE2 = 3 CCLKs tCONV = 18 CCLKs INT (active low) EOS EOC (active low) EOC EOS EOS EOC CONVST = 1 th(CSF-EOS) th(CSF-EOC) tsu(CSF-EOS) tsu(CSF-EOS) CS/FS SCLK SDO SDI 1 . . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . . .16 N - 2nd N - 1st 1110b. . . . . . . . . . . . . . CONFIGURE th(CSF-EOC) 1 Nth 1101b 1101b READ Result READ Result Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while sampling) 12 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 MANUAL TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) N - 1st Nth Nth EOC (active low) EOS EOC twL(CONVST) EOS CONVST tCONV = 18 CCLKs N + 1st tSAMPLE1 = 3 CCLKs min INT (active low) th(CSF-EOS) tsu(CSR-EOS) tsu(CSF-EOS) CS/FS tsu(CSF-EOC) th(CSF-EOC) SCLK 1 1 . . . . . . . . . . . . . . . . . . . .16 SDO N th N - 1st 1101b SDI 1101b READ Result READ Result Figure 3. Timing for Conversion and Acquisition Cycles for Manual Trigger (Read while converting) AUTO TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) tCONV = 18 CCLKs th(CSF-EOS) tsu(CSF-EOS) EOS tCONV = 18 CCLKs tSAMPLE2 = 3 CCLKs min tSAMPLE2 = 3 CCLKs min Nth INT (active low) N + 1st EOC EOC (active low) EOS EOS EOC CONVST = 1 th(CSR-EOS) tsu(CSR-EOS) th(CSF-EOS) CS/FS 1 . . . . . . . . . . . . . . . . . . 16 SCLK 1 . . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . . 16 ?? SDO N-2nd SDI 1110b . . . . . . . . . . . . . . . tsu(CSR-EOS) Nth N-1st 1101b CONFIGURE READ Result 1101b READ Result Figure 4. Timing for Conversion and Acquisition Cycles for Autotrigger (Read while converting) Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 13 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com 1 2 3 4 5 6 14 7 15 16 SCLK tsu(CSF-SCLK1F) tc(SCLK) twH(SCLK) twL(SCLK) CS/FS tsu(16thSCLK-CSR) td(SCLKF-SDOINVALID) td(CSR-SDOZ) td(SCLKF-SDOVALID) td(CSF-SDOVALID) SDO Hi-Z MSB-1 MSB-2 MSB-3 MSB-4 MSB MSB-5 MSB-6 LSB+2 LSB+1 LSB th(SDI-SCLKF) MSB SDI MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6 LSB+2 LSB+1 LSB tsu(SDI-SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use internal CCLK active high, EOC and INT active low, TAG enabled, auto channel select) Nth CH1 Nth CH0 CONVST twL(CONVST) EOS EOC (active low) EOC twL(CONVST) Nth CH0 Nth CH1 tCONV = 18 CCLKs tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) tsu(CSF-EOS) th(CSF-EOC) CS/FS SCLK 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 1 . . . . . . . . . . . . . . . . . . . . . . . 16 17 td(CSR-EOS) = 20 ns MIN SDO Hi-Z Nth CH0 N-1st CH1 TAG = 0 TAG = 1 SDI 1101b Hi-Z 1101b READ Result READ Result Figure 6. Simplified Dual Channel Timing 14 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 TYPICAL CHARACTERISTICS At -40C to 85C, VREF [REF+ - (REF-)] = 5 V when +VA = +VBD = 5 V or VREF [REF+ - (REF-)] = 2.5 V when +VA = +VBD = 3 V, fSCLK = 42 MHz, or VREF = 2.5 when +VA = +VBD = 2.7 V, fSCLK = 37.8 MHz, fI = dc for dc curves, fI = 100 kHz for ac curves with 5-V supply and fI = 10 kHz for ac curves with 3-V supply (unless otherwise noted). CROSSTALK vs FREQUENCY DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 110 1 105 0.8 INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 2 +VA = 5 V +VA = 5 V INL - LSB 95 DNL - LSB Crosstalk -dB 1.5 100 +VA = 3 V 0.6 +VA = 3 V 1 0.4 90 +VA = 5 V 0.5 0.2 85 +VA = 3 V 0 -40 -25 80 0 50 100 150 f - Frequency - kHz 200 5 20 35 50 65 0 -40 80 TA - Free-Air Temperature - C -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 80 Figure 7. Figure 8. Figure 9. DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY DIFFERENTIAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY 2 1 1 +VA = 5 V +VA = 5 V +VA = 3 V 1.5 1 INL - LSB 0.5 0 MIN MAX MAX 0.5 0.5 DNL - LSB MAX DNL - LSB -10 0 -0.5 MIN 0 MIN -1 -0.5 -0.5 -1.5 -1 0.1 1 10 External Clock Frequency - MHz -2 0.1 100 Figure 10. 10 1 External Clock Frequency - MHz 100 Figure 11. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 -1 0.1 1 10 External Clock Frequency - MHz 100 Figure 12. Submit Documentation Feedback 15 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 2 OFFSET VOLTAGE vs SUPPLY VOLTAGE 1 1 +VA = 3 V 1.5 MAX 0 MIN Offset Voltage - mV 0.5 -0.5 0.8 0.5 Offset Voltage - mV INL - LSB 1 +VA = 5 V 0 +VA = 3 V -0.5 -1 0.6 0.4 0.2 -1.5 -2 0.1 1 10 External Clock Frequency - MHz -1 -40 100 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 0 2.7 80 Figure 15. GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs SUPPLY VOLTAGE POWER-SUPPLY REJECTION RATIO vs SUPPLY RIPPLE FREQUENCY PSRR - Power Supply Rejection Ratio - dB 0.10 Gain Error - %FSR +VA = 3 V -0.06 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 3.2 3.7 4.2 4.7 -80 -78 -76 -74 +VA = 5 V -72 +VA = 3 V -70 5.2 0 20 +VA - Supply Voltage - V 40 60 f - Frequency - kHz 80 100 Figure 16. Figure 17. Figure 18. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SINAD - Signal-To-Noise and Distortion - dB SNR - Signal-To-Noise Ratio - dB -0.10 2.7 80 95 +VA = 5 V 91 +VA = 3 V 87 85 20 40 60 80 fi - Input Frequency - kHz 100 Figure 19. 16 0 -0.05 -0.08 0 0.05 Submit Documentation Feedback -90 95 THD - Total Harmonic Distortion - dB Gain Error - %FSR +VA = 5 V -0.04 89 5.2 Figure 14. -0.02 93 3.7 4.2 4.7 +VA - Supply Voltage - V Figure 13. 0 -0.10 -40 3.2 93 +VA = 5 V 91 89 +VA = 3 V 87 85 +VA = 3 V -95 +VA = 5 V -100 -105 -110 0 20 40 60 80 fi - Input Frequency - kHz 100 Figure 20. 0 20 40 60 80 fi - Input Frequency - kHz 100 Figure 21. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE RATIO vs FULL-SCALE RANGE 110 104 102 100 +VA = 5 V 98 96 +VA = 3 V 94 SINAD - Signal-To-Noise and Distortion - dB 106 fi = 10 kHz 95 90 +VA = 3 V +VA = 5 V 85 80 75 92 70 90 0 20 40 60 80 fi - Input Frequency - kHz 0 100 4 5 90 +VA = 3 V +VA = 5 V 85 80 75 70 0 1 3 2 Full Scale Range - V 4 5 Figure 24. TOTAL HARMONIC DISTORTION vs FULL-SCALE RANGE SPURIOUS-FREE DYNAMIC RANGE vs FULL-SCALE RANGE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE -90 -95 +VA = 5 V -100 +VA = 3 V -105 1 0 2 3 Full Scale Range - V 4 5 110 -90 fi = 10 kHz 105 THD - Total Harmonic Distortion - dB SFDR - Spurious Free Dynamic Range - dB -85 +VA = 3 V +VA = 5 V 100 95 90 85 80 0 1 2 3 Full Scale Range - V 4 +VA = 5 V -95 -100 +VA = 3 V -105 -110 -40 -25 5 -10 5 20 35 50 65 TA - Free-Air Temperature - C 80 Figure 25. Figure 26. Figure 27. SPURIOUS-FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE 105 +VA = 3 V 100 +VA = 5 V 95 90 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 93 Figure 28. +VA = 5 V 91 +VA = 3 V 89 87 85 -40 -25 80 SINAD - Signal-To-Noise and Distortion - dB 95 110 SNR - Signal-To-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB 2 3 Full Scale Range - V fi = 10 kHz 95 Figure 23. fi = 10 kHz -110 1 100 Figure 22. -80 THD - Total Harmonic Distortion - dB SIGNAL-TO-NOISE AND DISTORTION vs FULL-SCALE RANGE 100 108 SNR - Signal-To-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY -10 5 20 35 50 65 TA - Free-Air Temperature - C 80 Figure 29. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 95 93 91 +VA = 5 V 89 +VA = 3 V 87 85 -40 -25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - C Figure 30. Submit Documentation Feedback 17 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE 24 15.50 +VA = 5 V 15 +VA = 3 V 14.50 14 -40 -25 -10 5 20 35 50 65 24 23.5 Internal Clock Frequency - MHz Internal Clock Frequency - MHz 16 ENOB - Effective Number of Bits - Bits INTERNAL CLOCK FREQUENCY vs FREE-AIR TEMPERATURE 23 22.5 22 21.5 21 2.7 80 3.2 22 21.5 TA - Free-Air Temperature - C Figure 31. Figure 32. Figure 33. ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 6.5 6.0 5.5 5.0 3.2 360 320 280 240 200 2.7 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V PD Mode Analog Supply Current - nA 7.0 80 10 NAP Mode Analog Supply Current - mA Analog Supply Current - mA 22.5 21 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 5.2 400 4.5 2.7 23 3.7 4.2 4.7 +VA - Supply Voltage - V fs = 1 MSPS 7.5 23.5 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 8 6 4 2 0 2.7 5.2 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 34. Figure 35. Figure 36. ANALOG SUPPLY CURRENT vs SAMPLE RATE ANALOG SUPPLY CURRENT vs SAMPLE RATE ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 500 Auto NAP +VA = 5 V 4 +VA = 3 V 3 2 1 0 1 10 100 Sample Rate - kHz 1000 Figure 37. 18 Submit Documentation Feedback Analog Supply Current - mA 6 5 7.5 PD Mode Analog Supply Current - mA Analog Supply Current - mA 7 400 300 +VA = 5 V 200 +VA = 3 V 100 0 fs = 1 MSPS +VA = 5 V 7 6.5 6 5.5 +VA = 3 V 5 4.5 1 5 4 -40 Sample Rate - kHz -10 5 20 35 50 65 TA - Free-Air Temperature - C Figure 38. Figure 39. 9 13 17 -25 80 Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.4 Analog Supply Current - mA NAP Mode 0.36 +VA = 5 V 0.32 0.28 +VA = 3 V 0.24 0.2 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - C 80 Figure 40. INL 1.75 1.5 +VA = 5 V INL - Bits 1.0 0.5 0 -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 40000 50000 60000 40000 50000 60000 Code Figure 41. DNL 1 +VA = 5 V DNL - Bits 0.5 0 -0.5 -1 0 10000 20000 30000 Code Figure 42. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 19 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) INL 1.75 1.5 +VA = 3 V INL - Bits 1.0 0.5 0 -0.5 -1.0 -1.5 -1.75 0 10000 20000 30000 Code 40000 50000 60000 Figure 43. DNL 1 +VA = 3 V DNL - Bits 0.5 0 -0.5 -1 0 10000 20000 30000 Code 40000 50000 60000 Figure 44. FFT 0 5 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 45. 20 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 TYPICAL CHARACTERISTICS (continued) FFT 0 10 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 46. FFT 0 100 kHz Input, +VA = 3 V, fs = 1 MSPS, Vref = 2.5 V -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 47. FFT 0 5 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 48. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 21 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) FFT 20 0 10 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V Amplitude - dB -20 -40 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 f - Frequency - kHz Figure 49. FFT 0 100 kHz Input, +VA = 5 V, fs = 1 MSPS, Vref = 5 V -20 Amplitude - dB -40 -60 -80 -100 -120 -140 -160 0 100 200 f - Frequency - kHz 300 400 500 Figure 50. THEORY OF OPERATION The ADS8329/30 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8329/30 has an internal clock that is used to run the conversion but can also be programmed to run the conversion based on the external serial clock, SCLK. The ADS8329 has one analog input. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and -IN inputs are disconnected from any internal function. The ADS8330 has two inputs. Both inputs share the same common pin, COM. The negative input is the same as the -IN pin for the ADS8329. The ADS8330 can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and 1 automatically. ANALOG INPUT When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between AGND - 0.2 V and AGND + 0.2 V, allowing the input to reject small signals which are common to both the +IN and -IN inputs. The +IN input has a range of -0.2 V to VREF + 0.2 V. The input span [+IN - (-IN)] is limited to 0 V to VREF. 22 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the ADS8329/30 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the minimum acquisition time (120 ns). When the converter goes into hold mode, the input impedance is greater than 1 G. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and -IN inputs and the span [+IN - (-IN)] should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and -IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Device in Hold Mode 150 W +IN 4 pF 40 pF +VA AGND 4 pF 150 W -IN 40 pF AGND Figure 51. Input Equivalent Circuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20 and a capacitor of 470 pF are recommended. The input to the converter is a unipolar input voltage in the range 0 V to VREF. The minimum -3dB bandwidth of the driving operational amplifier can be calculated to: f3db = (ln(2) x(n+1))/(2 x tACQ) where n is equal to 16, the resolution of the ADC (in the case of the ADS8329/30). When tACQ = 120 ns (minimum acquisition time), the minimum bandwidth of the driving amplifier is 15.6 MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in the typical input drive configuration, Figure 52. For the ADS8330, a series resistor of 0 should be used on the COM pin (or no resistor at all). Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8329/30 within its rated operating voltage range. This configuration is also recommended when the ADS8329/30 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240 reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91 dB SNR and -96 dB THD at an input frequency of 10 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ADS8329/30 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 23 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com Input Signal (0 V to 4 V) 5V ADS8329 +VA THS4031 20 W +IN 470 pF 50 W -IN 20 W Figure 52. Unipolar Input Drive Configuration 5V ADS8329 1V DC +VA THS4031 600 W 20 W +IN 470 pF Input Signal (-2 V to 2 V) 600 W -IN 20 W Figure 53. Bipolar Input Drive Configuration REFERENCE The ADS8329/30 can operate with an external reference with a range from 0.3 V to 5 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 22-F ceramic decoupling capacitor is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as possible to the pins of the device. The REF- should be connected to its own via to the analog ground plane with the shortest possible distance. CONVERTER OPERATION The ADS8329/30 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 21 MHz minimum. The oscillator is always on unless the device is in the deep power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (this is equivalent to 120 ns at 24.5 MHz) and the conversion time takes 18 conversion clocks (CCLK) (780 ns) to complete one conversion. The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 42-MHz SCLK this provides a 21-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is relaxed. 24 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns. Since the ADS8329/30 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most 1 s (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8329/30. CFR_D10 Conversion Clock (CCLK) =1 OSC =0 Divider 1/2 SPI Serial Clock (SCLK) Figure 54. Converter Clock Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR). This cycle time can be as short as 4 serial clocks (SCLK). Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter, ADS8330, has a built-in 2-to-1 MUX. If the device is programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to 0. Start of a Conversion The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8329/30 switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8329/30 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK) after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1. Different Types of Conversion MODE SELECT CHANNEL START CONVERSION Auto Channel Select (1) Auto Trigger Automatic No need to write channel number to the CMR. Use internal sequencer for the ADS8330. Manual (1) Manual Channel Select Write the channel number to the CMR. Start a conversion based on the conversion clock CCLK. Manual Trigger Start a conversion with CONVST. Auto channel select should be used with auto trigger and also with the TAG bit enabled. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 25 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com Status Output EOC/INT When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has ended. The EOC output goes low for 3 conversion clocks (CCLK) after the previous rising edge of EOC, if auto trigger is programmed. This status pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can be used as INT. (CFR_D[7:6] = 1, 0) which is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either function (EOC or INT), is programmable through CFR_D7. Power-Down Modes The ADS8329/30 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance (EOC) puts the device into auto nap power-down. The beginning of sampling resumes operation of the converter. The contents of the configuration register is not affected by any of the power-down modes. Any ongoing conversion when nap or deep power-down is activated is aborted. +VA - Supply Current - mA 100 10 1 0.1 20 10020 20020 30020 40020 Settling Time - ns Figure 55. Typical Analog Supply Current Drop vs Time After Power-Down 26 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 7 mA to 4 nA in 100 ns. The wake-up time after a power-down is 1 s. When bit D2 in the configuration register is set to 0, the device is in deep power-down. Setting this bit to 1 or sending a wake-up command can resume the converter from the deep power-down state. Nap Mode In nap mode the ADS8329/230 turns off biasing of the comparator and the mid-volt buffer. In this mode supply current falls from 7 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up (resume) time from nap power-down mode is 3 CCLKs (120 ns with a 24.5-MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap power-down state. Auto Nap Mode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method to wake up the device. Configuration register bit D4 is only used to enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has finished, which means the end of conversion activates auto nap power-down mode. Supply current falls from 7 mA in normal mode to about 0.3 mA in 200 ns. A CONVST resumes the device and turns biasing on again in 3 CCLKs (120 ns with a 24.5-MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb, wake up command or the set default mode command 1111b can also wake up the device from auto nap power-down. NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does remove the device from either one of these power-down states, deep/nap/auto nap power-down. 2. Wake-up time is defined as the time between when the host processor tries to wake up the converter and when a convert start can occur. Table 2. Power-Down Mode Comparisons TYPE OF POWER-DOWN POWER CONSUMPTION: 5 V/3 V Normal operation 7 mA/5.1 mA Deep power-down 4 nA/2 nA Nap power-down Auto nap power-down 0.3 mA/0.25 mA ACTIVATED BY ACTIVATION TIME RESUME POWER BY Setting CFR 100 ns Woken up by command 1011b Setting CFR 200 ns Woken up by command 1011b to achieve 6.6 mA since (1.3 + 12)/2 = 6.6 EOC (end of conversion) 200 ns Woken up by CONVST, any channel select command, default command 1111b, or wake up command 1011b. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 RESUME TIME ENABLE 1 s Set CFR 3 CCLKs Set CFR 3 CCLKs Set CFR Submit Documentation Feedback 27 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com EOS EOC EOS Converter State N+1 Converter State EOC N CONVST N+1 -th Sampling N -th Conversion N+1 -th Conversion Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N-1 -th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N -th Result Figure 56. Read While Converting versus Read While Sampling (Manual Trigger) Manual Trigger Converter State Resume N -th Sampling >=3CCLK N -th Conversion Activation Resume =18 CCLK N+1 -th Sampling >=3CCLK EOC EOC EOS N+1 EOS N CONVST N+1 -th Conversion Activation =18 CCLK 20 ns MIN 20 ns MIN 1 CCLK MIN Read While Converting Read N-1 -th CS Read N -th Result Result 20 ns MIN 20 ns MIN Read While Sampling Read N-1 -th CS 20 ns MIN 0 ns MIN 20 ns MIN Read N -th Result Result 20 ns MIN 20 ns MIN Figure 57. Read While Converting versus Read While Sampling with Deep or Nap Power-Down 28 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 40 ns MIN Manual Trigger Case 1 N N+1 Converter State Resume N -th Sampling EOS POWERDOWN N -th Conversion >=3CCLK Resume =18 CCLK EOC EOS EOC (programmed Active Low) EOC CONVST N+1 -th Sampling N+1 -th Conversion >=3CCLK =18 CCLK 6 CCLKs POWERDOWN 6 CCLKs Read While Converting 20 ns MIN 20 ns MIN Read N -th Result Read N-1 -th Result CS 20 ns MIN 20 ns MIN 1 CCLK MIN Read While Sampling 1 CCLK MIN 0 ns MIN Read N -th Result Read N-1 -th Result CS 20 ns MIN 20 ns MIN 40 ns MIN Manual Trigger Case 2 (wake up by CONVST) N+1 Converter State N -th Sampling N -th Conversion >=3CCLK POWER DOWN Resume N+1 -th Sampling >=3CCLK =18 CCLK EOC EOS Resume EOS N EOC (programmed Active Low) EOC CONVST N+1 -th Conversion POWER DOWN =18 CCLK Read While Converting 20 ns MIN 20 ns MIN Read While Sampling 20 ns MIN 20 ns MIN CS 20 ns MIN Read N -th Result Read N-1 -th Result CS 0 ns MIN 20 ns MIN Read N -th Result Read N-1 -th Result 20 ns MIN 20 ns MIN Figure 58. Read While Converting versus Read While Sampling with Auto Nap Power-Down Total Acquisition + Conversion Cycle Time: Automatic: = 21 CCLKs Manual: 21 CCLKs Manual + deep power-down: 4SCLK + 100 s + 3 CCLK + 18 CCLK +16 SCLK + 1 s Manual + nap power-down: 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK Manual + auto nap power-down: 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume) Manual + auto nap power-down: 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume) Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 29 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com DIGITAL INTERFACE The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made available to the output register at the EOC presented on the SDO output pin at the falling edge of FS/CS. This is the MSB. Output data are valid at the falling edge of SCLK with td(SCLKF-SDOVALID) delay so that the host processor can read it at the falling edge. Serial data input is also read at the falling edge of SCLK. The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends 16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with CPOL = 0 , CPHA = 1 or CPOL = 1, CPHA = 0. This means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS. NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read mode combination. See Table 3 for details. Internal Register The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 3. Command Set Defined by Command Register (CMR) (1) D[15:12] HEX COMMAND D[11:0] (2) WAKE UP FROM AUTO NAP MINIMUM SCLKs REQUIRED R/W 0000b 0h Select analog input channel 0 Don't care Y 4 W 0001b 1h Select analog input channel 1 (2) Don't care Y 4 W 0010b 2h Reserved Reserved - - - 0011b 3h Reserved Reserved - - - 0100b 4h Reserved Reserved - - - 0101b 5h Reserved Reserved - - - 0110b 6h Reserved Reserved - - - 0111b 7h Reserved Reserved - - - 1000b 8h Reserved Reserved - - - 1001b 9h Reserved Reserved - - - 1010b Ah Reserved Reserved - - - 1011b Bh Wake up Don't care Y 4 W 1100b Ch Read CFR Don't care - 16 R 1101b Dh Read data Don't care - 16 R 1110 Eh Write CFR CFR value - 16 W 1111b Fh Default mode (load CFR with default value) Don't care Y 4 W (1) (2) When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are supplied) of the previous conversion result. These two commands apply to the ADS8330 only. WRITING TO THE CONVERTER There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 6 for exceptions that require more than 16 SCLKs). 30 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 Configuring the Converter and Default Mode The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of SCLK. CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8329 and is always read as a 0). The same default values apply for the CFR after a power-on reset (POR) and SW reset. READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table 4. Configuration Register (CFR) Map SDI BIT CFR - D[11 - 0] DEFINITION Channel select mode D11 default = 1 D10 default = 1 D9 default = 1 D8 default = 1 D7 default = 1 D6 default = 1 D5 default = 1 D4 default = 1 D3 default = 1 D2 default = 1 D1 default = 0: ADS8329 1: ADS8330 D0 default = 1 0: Manual channel select enabled. Use channel select commands to access a different channel. 1: Auto channel select enabled. All channels are sampled and converted sequentially until the cycle after this bit is set to 0. Conversion clock (CCLK) source select 0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored. 0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST Don't care Don't care Pin 10 polarity select when used as an output (EOC/INT) 0: EOC Active high / INT active high 1: EOC active low / INT active low Pin 10 function select when used as an output (EOC/INT) 0: Pin used as INT 1: Pin used as EOC Pin 10 I/O select for chain mode operation 0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/INT output Auto nap power-down enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0. 0: Auto nap power-down enabled (not activated) 1: Auto nap power-down disabled Nap power-down (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in nap power-down 1: Remove device from nap power-down (resume) Deep power-down. This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in deep power-down 1: Remove device from deep power-down (resume) TAG bit enable. This bit is ignored by the ADS8329 and is always read 0. 0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK. Reset 0: System reset 1: Normal operation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when manual trigger is used or the end of the 3rd conversion clock (CCLK) after EOC if auto trigger is used. Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 31 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com The falling edge of FS/CS should not be placed at the precise moment (minimum of at least one conversion clock (CCLK) delay) at the end of a conversion (by default when EOC goes high), otherwise the data is corrupt. If FS/CS is placed before the end of a conversion, the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion result is read. The conversion result is 16-bit data in straight binary format as shown in Table 4. Generally 16 SCLKs are necessary, but there are exceptions where more than 16 SCLKS are required (see Table 6). Data output from the serial output (SDO) is left adjusted MSB first. The trailing bits are filled with the TAG bit first (if enabled) plus all zeros. SDO remains low until FS/CS is brought high again. SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output. NOTE: Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is SDO outputs all 1s during the cycle immediately after any reset (POR or software reset). If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all 16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in auto nap mode). Table 5. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full-scale range VREF STRAIGHT BINARY Least significant bit (LSB) VREF/65536 Full-scale +VREF - 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF/2 1000 0000 0000 0000 8000 Midscale - 1 LSB VREF/2- 1 LSB 0111 1111 1111 1111 7FFF Zero 0V 0000 0000 0000 0000 0000 BINARY CODE HEX CODE TAG Mode The ADS8330 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the converted result. An address bit is added after the LSB read out from SDO indicating which channel the result came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because of the additional TAG bit. Chain Mode The ADS8329/30 can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is chain mode operation. A typical connection of three converters is shown in Figure 59. 32 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 Micro Controller INT GPIO1 GPIO2 SDI SCLK CONVST CS ADS8329 #1 SDO EOC/INT SDOSCLK GPIO3 SDI SCLK CONVST CS ADS8329 #3 CDI SDO SDI SCLK CONVST CS ADS8329 #2 CDI SDO Program device #1 CFR_D[7:5] = XX0b SDI Program device #2 and #3 CFR_D[7:5] = XX1b Figure 59. Multiple Converters Connected Using Chain Mode When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the CDI input data goes straight to the output register, therefore the serial input data passes through the converter with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for detailed timing. In this timing the conversion in each converters are done simultaneously. INT #3 (active low) Nth EOS EOC #1 (active low) EOC CONVST #1, CONVST #2, CONVST #3 EOS Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low, and INT active low) CS held low during the N times 16 bits transfer cycle. tSAMPLE1 = 3 CCLKs min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 SDO #1, CDI #2 1 . . . . . . . . . . . . . . . . . . 16 1 . . . . . . . . . . . . . . . . . . 16 1 . . . . . . . . . . . . . . . . . . 16 Hi-Z Hi-Z Nth from #1 td(CSR-EOS) = 20 ns min CS/FS #2, CS/FS #3 SDO #2, CDI #3 SDO #3 td(SDO-CDI) Hi-Z Hi-Z N - 1th from #2 Nth from #1 Nth from #1 td(SDO-CDI) Hi-Z Hi-Z Nth from #3 SDI #1, SDI #2, SDI #3 1110............ CONFIGURE N - 1th from #2 1101b READ Result Nth from #1 1101b READ Result Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 33 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal. Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example, the same data from the converter is going to be shown repeatedly. Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired result. INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #1, CONVST #2, CONVST #3 EOS Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT polarity programmed as active low) CS held low during the N times 16 bits transfer cycle. tSAMPLE1 = 3 CCLKs min td(EOS-CSF) = 20 ns min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 16 1 SDO #1, CDI #2 1 16 Nth from #1 CS/FS #2 SCLK #2, SDO #2, CDI #3 N - 1th from #2 CS/FS #3 1 16 Nth from #1 Nth from #1 td(EOS-CSF) = td(CSR-EOS) = 20 ns min 20 ns min Nth from #1 td(EOS-CSF) = 20 ns min Nth from #1 td(CSR-EOS) = 20 ns min SDO #3 SDI #1, SDI #2, SDI #3 Nth from #3 1110............ CONFIGURE N - 1th from #2 Nth from #1 1101b 1101b READ Result READ Result Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream. 34 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low and INT active low) CS held low during the N times 16 bits transfer cycle. Note : old data shown. INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #2 = 1 EOS CONVST #1, CONVST #3 tSAMPLE1 = 3 CCLKs min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . . . . . . . . . . . .16 Hi-Z SDO #1, CDI #2 Hi-Z Nth from #1 td(CSR-EOS) = 20 ns min CS/FS #2, CS/FS #3 td(SDO-CDI) SDO #2, CDI #3 Hi-Z SDO #3 Hi-Z Hi-Z Nth from #1 N - 1th from #2 td(SDO-CDI) SDI #1, SDI #2, SDI #3 Hi-Z N - 1th from #2 Nth from #3 1110............ CONFIGURE 1101b Nth from #1 1101b READ Result READ Result Figure 62. Simplified Cascade Timing (Separate CONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected (that is, auto channel select). This is listed in Table 6. Table 6. Required SCLKs For Different Read Out Mode Combinations CHAIN MODE AUTO CHANNEL ENABLED CFR.D5 SELECT CFR.D11 TAG ENABLED CFR.D1 NUMBER OF SCLK PER SPI READ TRAILING BITS 0 0 0 16 None 0 0 1 17 MSB is TAG bit plus zero(s) 0 1 0 16 None 0 1 1 17 TAG bit plus 7 zeros 1 0 0 16 None 1 0 1 24 TAG bit plus 7 zeros 1 1 0 16 None 1 1 1 24 TAG bit plus 7 zeros Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 35 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. ADS8329 # 3 CDI SDO Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Serial data output Logic Delay Plus PAD 8.3 ns Q CLK ADS8329 # 2 SDO CDI Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Logic Delay Plus PAD 8.3 ns Q CLK ADS8329 # 1 CDI Serial data input SDO Logic Delay Plus PAD 2.7 ns D Logic Delay < = 8 .3 ns Logic Delay Plus PAD 8.3 ns Q CLK SCLK input Figure 63. Typical Delay Through Converters Configured in Chain Mode RESET The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state machine is reset to the power-on state. SW RESET CDI POR SET SAR Shift Register Intermediate Latch Output Register Conversion Clock Latched by End Of Conversion SDO SCLK Latched by Falling Edge of CS CS EOC EOC Figure 64. Digital Output Under Reset Condition 36 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 When the device is powered up, the POR sets the device to default mode when AVDD reaches 1.5V. When the device is powered down, the POR circuit requires AVDD to remain below 125mV for at least 350ms to ensure proper discharging of internal capacitors and to correct the behavior of the ADC when powered up again. If AVDD drops below 400mV but remains above 125mV, the internal POR capacitor does not discharge fully and the device requires a software reset to perform correctly after the recovery of AVDD (this condition is shown as the undefined zone in Figure 65). AVDD (V) 5.500 5.000 Specified Supply Voltage Range 4.000 3.000 2.700 2.000 POR Trigger Level 1.500 1.000 0.400 0.125 Undefined Zone 0 0.350 t (s) Figure 65. Relevant Voltage Levels for POR Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 37 ADS8329 ADS8330 SLAS516C - DECEMBER 2006 - REVISED JULY 2009 ................................................................................................................................................... www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 mF AGND Ext Ref Input 22 mF Analog Input AGND +VA REF+ REF- AGND IN+ IN- Host Processor FS/CS SDO SDI SCLK Interface Supply +1.8 V ADS8329 BDGND CONVST 4.7 mF EOC/INT +VBD Figure 66. Typical Circuit Configuration Part Change Notification # 20071101001 The ADS8329 and ADS8330 devices underwent a silicon change under Texas Instruments Part Change Notification (PCN) number 20071101001. Details on this part change can be obtained from the Product Information Center at Texas Instruments or by contacting your local sales/distribution office. Devices with a date code of 82xx and higher are covered by this PCN. 38 Submit Documentation Feedback Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C - DECEMBER 2006 - REVISED JULY 2009 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2008) to Revision C .................................................................................................. Page * * * * * * * * * * * * * * * * * * * * * Added 12- and 14-bit rows to family table ............................................................................................................................. 1 Added +REF to AGND and -REF to AGND rows to the Voltage range parameter of the Absolute Maximum Ratings table ....................................................................................................................................................................................... 2 Changed conditions for 4.5-V Electrical Characteristics........................................................................................................ 3 Changed typ and max specifications for the VREF[(REF+) - (REF-)] parameter in the 4.5-V Electrical Characteristics ...... 4 Changed NAP/Auto-NAP and Deep power-down test conditions of the Supply Current parameter in the 4.5-V Electrical Characteristics........................................................................................................................................................ 4 Changed conditions for the 2.7-V Electrical Characteristics.................................................................................................. 5 Changed VREF[(REF+) - (REF-)] parameter in the 2.7-V Electrical Characteristics ............................................................. 6 Changed NAP/Auto-NAP and Deep power-down test conditions of the Supply Current parameter in the Power-Supply Requirements section of the 2.7-V Electrical Characteristics table................................................................ 7 Corrected typo in Figure 1 ................................................................................................................................................... 12 Changed SDO trace of Figure 2 .......................................................................................................................................... 12 Corrected typo in Figure 3 ................................................................................................................................................... 13 Changed SDO trace in Figure 4 .......................................................................................................................................... 13 Corrected typo in Figure 6 ................................................................................................................................................... 14 Added last sentence to Driver Amplifier Choice section...................................................................................................... 23 Updated Figure 52 ............................................................................................................................................................... 24 Updated Figure 53 ............................................................................................................................................................... 24 Changed fifth sentence of Deep Power-Down Mode section .............................................................................................. 27 Changed second sentence of Nap Mode section................................................................................................................ 27 Changed fifth sentence of Auto Nap Mode section ............................................................................................................. 27 Changed power consumption and activation time column values of Table 2...................................................................... 27 Added Figure 65 and corresponding paragraph to RESET section .................................................................................... 37 Changes from Revision A (March 2008) to Revision B .................................................................................................. Page * * * * * * * * Added 16-Pin TSSOP to Features bullet to indicate new package availability ..................................................................... 1 Added 16-Pin TSSOP to third Description paragraph bullet to indicate new package availability ........................................ 1 Changed the Ordering Information table to reflect TSSOP package availability................................................................... 2 Changed Absolute Maximum Ratings table to reflect TSSOP package availability .............................................................. 2 Added pinouts for PW package for both ADS8329 and ADS8330...................................................................................... 10 Added TSSOP column to the ADS8329 Terminal Functions table...................................................................................... 11 Added TSSOP column to the ADS8330 Terminal Functions table...................................................................................... 11 Changed the Part Change Notification section.................................................................................................................... 38 Copyright (c) 2006-2009, Texas Instruments Incorporated Product Folder Link(s): ADS8329 ADS8330 Submit Documentation Feedback 39 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8329IBPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBRSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBRSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBRSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IBRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IRSAR ACTIVE QFN RSA 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IRSARG4 ACTIVE QFN RSA 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IRSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8329IRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBRSAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBRSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBRSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IBRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8330IPWG4 ACTIVE TSSOP PW 16 ADS8330IPWR ACTIVE TSSOP PW ADS8330IPWRG4 ACTIVE TSSOP ADS8330IRSAR ACTIVE ADS8330IRSARG4 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IRSAT ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8330IRSATG4 ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8329IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8329IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IBRSAT QFN RSA 16 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8329IRSAR QFN RSA 16 2000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8329IRSAT QFN RSA 16 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8330IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IBRSAT QFN RSA 16 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8330IRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8330IRSAT QFN RSA 16 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8329IBPWR ADS8329IBRSAR TSSOP PW 16 2000 367.0 367.0 35.0 QFN RSA 16 3000 338.1 338.1 20.6 ADS8329IBRSAT QFN RSA 16 250 338.1 338.1 20.6 ADS8329IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8329IRSAR QFN RSA 16 2000 338.1 338.1 20.6 ADS8329IRSAT QFN RSA 16 250 338.1 338.1 20.6 ADS8330IBPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8330IBRSAR QFN RSA 16 3000 338.1 338.1 20.6 ADS8330IBRSAT QFN RSA 16 250 338.1 338.1 20.6 ADS8330IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8330IRSAR QFN RSA 16 3000 338.1 338.1 20.6 ADS8330IRSAT QFN RSA 16 250 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2012, Texas Instruments Incorporated