PIC18F2480-I/SPREL - Microchip Technology

PIC18F2480/2580/4480/4580

Data Sheet

28/40/44-Pin

Enhanced Flash Microcontrollers

with ECAN™ Technology, 10-Bit A/D

and nanoWatt Technology

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code hopping devices, Serial

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PIC18F2480/2580/4480/4580

Power-Managed Modes:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Idle mode Currents Down to 5.8 μA Typical

• Sleep mode Current Down to 0.1 μA Typical

• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V

• Watchdog Timer: 2.1 μA

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – Available for Crystal

and Internal Oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal Oscillator Block:

- 8 user-selectable frequencies, from 31 kHz to 8 MHz

- Provides a complete range of clock speeds,

from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features:

• C Compiler Optimized Architecture with Optional

Extended Instruction Set

• 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical

• 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical

• Flash/Data EEPROM Retention: > 40 Years

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s

• Single-Supply 5V In-Circuit Serial

Programming™ (ICSP™) via Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Wide Operating Voltage Range: 2.0V to 5.5V

Peripheral Highlights:

• High-Current Sink/Source 25 mA/25 mA

• Three External Interrupts

• One Capture/Compare/PWM (CCP) module

• Enhanced Capture/Compare/PWM (ECCP) module

(40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Master Synchronous Serial Port (MSSP) module

Supporting 3-Wire SPI (all 4 modes) and I2C™

Master and Slave modes

• Enhanced Addressable USART module

- Supports RS-485, RS-232 and LIN 1.3

- RS-232 operation using internal oscillator

block (no external crystal required)

- Auto-wake-up on Start bit

- Auto-Baud Detect

• 10-Bit, up to 11-Channel Analog-to-Digital

Converter (A/D) module, up to 100 ksps

- Auto-acquisition capability

- Conversion available during Sleep

• Dual Analog Comparators with Input Multiplexing

ECAN Technology Module Features:

• Message Bit Rates up to 1 Mbps

• Conforms to CAN 2.0B Active Specification

• Fully Backward Compatible with PIC18XXX8 CAN

modules

• Three Modes of Operation:

- Legacy, Enhanced Legacy, FIFO

• Three Dedicated Transmit Buffers with Prioritization

• Two Dedicated Receive Buffers

• Six Programmable Receive/Transmit Buffers

• Three Full 29-Bit Acceptance Masks

• 16 Full 29-Bit Acceptance Filters w/Dynamic

Association

• DeviceNet™ Data Byte Filter Support

• Automatic Remote Frame Handling

• Advanced Error Management Features

Device

Program Memory Data Memory

I/O 10-Bit

A/D (ch)

CCP/

ECCP

(PWM)

MSSP

EUSART

Comp. Timers

8/16-bit

Flash

(bytes)

# Single-Word

Instructions

SRAM

(bytes)

EEPROM

(bytes) SPI Master

I2C™

PIC18F2480 16K 8192 768 256 25 8 1/0 Y Y 1 0 1/3

PIC18F2580 32K 16384 1536 256 25 8 1/0 Y Y 1 0 1/3

PIC18F4480 16K 8192 768 256 36 11 1/1 Y Y 1 2 1/3

PIC18F4580 32K 16384 1536 256 36 11 1/1 Y Y 1 2 1/3

28/40/44-Pin Enhanced Flash Microcontrollers with

ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580

Pin Diagrams

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN9

RB3/CANRX

RB2/INT2/CANTX

RB1/INT1/AN8

RB0/INT0/FLT0/AN10

VDD

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4/ECCP1/P1A

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

MCLR/VPP/RE3

RA0/AN0/CVREF

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/HLVDIN

RE0/RD/AN5

RE1/WR/AN6/C1OUT

RE2/CS/AN7/C2OUT

VDD

VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0/C1IN+

RD1/PSP1/C1IN-

PIC18F4480

40-Pin PDIP

PIC18F4580

PIC18F2480

14 15

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/HLVDIN

VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN9

RB3/CANRX

RB2/INT2/CANTX

RB1/INT1/AN8

RB0/INT0/AN10

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

28-Pin SPDIP, SOIC

PIC18F2580

28-Pin QFN

10 11

12 13 14 15

232425262728

PIC18F2480

RC0/T1OSO/T13CKI

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN9

RB3/CANRX

RB2/INT2/CANTX

RB1/INT1/AN8

RB0/INT0/AN10

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

MCLR/VPP/RE3

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4/SS/HLVDIN

VSS

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

PIC18F2580

PIC18F2480/2580/4480/4580

Pin Diagrams (Continued)

PIC18F4480

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0/CVREF

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN9

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

RD1/PSP1/C1IN-

RD0/PSP0/C1IN+

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

RC0/T1OSO/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

VSS

VDD

RE2/CS/AN7/C2OUT

RE1/WR/AN6/C1OUT

RE0/RD/AN5

RA5/AN4/SS/HLVDIN

RA4/T0CKI

RC7/RX/DT

RD4/PSP4/ECCP1/P1A

RD5/PSP5/P1B

RD6/PSP6/P1C

VSS

VDD

RB0/INT0/FLT0/AN10

RB1/INT1/AN8

RB2/INT2/CANTX

RB3/CANRX

44-Pin TQFP

RD7/PSP7/P1D 5

44-Pin QFN

PIC18F4480

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0/CVREF

MCLR/VPP/RE3

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN9

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3/C2IN-

RD2/PSP2/C2IN+

RD1/PSP1/C1IN-

RD0/PSP0/C1IN+

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI

RC0/T1OSO/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

VSS

AVDD

RE2/CS/AN7/C2OUT

RE1/WR/AN6/C1OUT

RE0/RD/AN5

RA5/AN4/SS/HLVDIN

RA4/T0CKI

RC7/RX/DT

RD5/PSP5/P1B

RD6/PSP6/P1C

VSS

VDD

RB0/INT0/FLT0/AN10

RB1/INT1/AN8

RB2/INT2/CANTX

RB3/CANRX

RD7/PSP7/P1D 5

4AVSS

VDD

AVDD

PIC18F4580

RD4/PSP4/ECCP1/P1A

PIC18F2480/2580/4480/4580
DS39637C-page 4 Preliminary © 2007 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 33
4.0 Reset .......................................................................................................................................................................................... 41
5.0 Memory Organization ................................................................................................................................................................. 61
6.0 Flash Program Memory.............................................................................................................................................................. 95
7.0 Data EEPROM Memory ........................................................................................................................................................... 105
8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 111
9.0 Interrupts .................................................................................................................................................................................. 113
10.0 I/O Ports ................................................................................................................................................................................... 129
11.0 Timer0 Module ......................................................................................................................................................................... 147
12.0 Timer1 Module ......................................................................................................................................................................... 151
13.0 Timer2 Module ......................................................................................................................................................................... 157
14.0 Timer3 Module ......................................................................................................................................................................... 159
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 163
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 173
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 187
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 227
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 247
20.0 Comparator Module.................................................................................................................................................................. 257
21.0 Comparator Voltage Reference Module................................................................................................................................... 263
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 267
23.0 ECAN Module........................................................................................................................................................................... 273
24.0 Special Features of the CPU.................................................................................................................................................... 343
25.0 Instruction Set Summary .......................................................................................................................................................... 361
26.0 Development Support............................................................................................................................................................... 411
27.0 Electrical Characteristics .......................................................................................................................................................... 415
28.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 451
29.0 Packaging Information.............................................................................................................................................................. 453
Appendix A: Revision History............................................................................................................................................................. 461
Appendix B: Device Differences......................................................................................................................................................... 461
Appendix C: Conversion Considerations ........................................................................................................................................... 462
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 462
Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 463
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 463
Index .................................................................................................................................................................................................. 465
The Microchip Web Site ..................................................................................................................................................................... 477
Customer Change Notification Service .............................................................................................................................................. 477
Customer Support .............................................................................................................................................................................. 477
Reader Response .............................................................................................................................................................................. 478
PIC18F2480/2580/4480/4580 Product Identification System ............................................................................................................ 479

PIC18F2480/2580/4480/4580

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Customer Notification System

PIC18F2480/2580/4480/4580

NOTES:

PIC18F2480/2580/4480/4580

1.0 DEVICE OVERVIEW

This document contains device specific information for

the following devices:

• PIC18F2480

• PIC18F2580

• PIC18F4480

• PIC18F4580

This family of devices offers the advantages of all

PIC18 microcontrollers – namely, high computational

performance at an economical price – with the addition

of high-endurance, Enhanced Flash program

memory. In addition to these features, the

PIC18F2480/2580/4480/4580 family introduces design

enhancements that make these microcontrollers a

logical choice for many high-performance, power

sensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F2480/2580/4480/4580

family incorporate a range of features that can signifi-

cantly reduce power consumption during operation.

Key items include:

•Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-Fly Mode Switching: The

power-managed modes are invoked by user code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

•Lower Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer have been reduced by up to

80%, with typical values of 1.1 and 2.1 μA,

respectively.

•Extended Instruction Set: In addition to the

standard 75 instructions of the PIC18 instruction

set, PIC18F2480/2580/4480/4580 devices also

provide an optional extension to the core CPU

functionality. The added features include eight

additional instructions that augment indirect and

indexed addressing operations and the

implementation of Indexed Literal Offset

Addressing mode for many of the standard PIC18

instructions.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2480/2580/4480/4580

family offer ten different oscillator options, allowing

users a wide range of choices in developing application

hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC

source (approximately 31 kHz, stable over

temperature and VDD), as well as a range of

6 user selectable clock frequencies, between

125 kHz to 4 MHz, for a total of 8 clock

frequencies. This option frees the two oscillator

pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and

internal oscillator modes, which allows clock

speeds of up to 40 MHz. Used with the internal

oscillator, the PLL gives users a complete

selection of clock speeds, from 31 kHz to

32 MHz – all without using an external crystal or

clock circuit.

Besides its availability as a clock source, the internal

oscillator block provides a stable reference source that

gives the family additional features for robust

operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer-

ence signal provided by the internal oscillator. If a

clock failure occurs, the controller is switched to

the internal oscillator block, allowing for continued

low-speed operation or a safe application

shutdown.

•Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

PIC18F2480/2580/4480/4580

1.2 Other Special Features

•Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles – up to 100,000 for program memory and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 40 years.

•Self-Programmability: These devices can write

to their own program memory spaces under inter-

nal software control. By using a bootloader routine

located in the protected Boot Block at the top of

program memory, it becomes possible to create

an application that can update itself in the field.

•Extended Instruction Set: The

PIC18F2480/2580/4480/4580 family introduces

an optional extension to the PIC18 instruction set,

which adds 8 new instructions and an Indexed

Addressing mode. This extension, enabled as a

device configuration option, has been specifically

designed to optimize re-entrant application code

originally developed in high-level languages, such

as C.

•Enhanced CCP Module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other features include auto-shutdown, for

disabling PWM outputs on interrupt or other select

conditions and auto-restart, to reactivate outputs

once the condition has cleared.

•Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation and provides support for the LIN

bus protocol. Other enhancements include auto-

matic baud rate detection and a 16-bit Baud Rate

Generator for improved resolution. When the

microcontroller is using the internal oscillator

block, the EUSART provides stable operation for

applications that talk to the outside world without

using an external crystal (or its accompanying

power requirement).

•10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period and

thus, reduce code overhead.

•Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit prescaler,

allowing a time-out range from 4 ms to over

131 seconds, that is stable across operating

voltage and temperature.

1.3 Details on Individual Family

Members

Devices in the PIC18F2480/2580/4480/4580 family are

available in 28-pin (PIC18F2X80) and 40/44-pin

(PIC18F4X80) packages. Block diagrams for the two

groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in six

ways:

1. Flash program memory (16 Kbytes for

PIC18FX480 devices; 32 Kbytes for

PIC18FX580 devices).

2. A/D channels (8 for PIC18F2X80 devices; 11 for

PIC18F4X80 devices).

3. I/O ports (3 bidirectional ports and 1 input only

port on PIC18F2X80 devices; 5 bidirectional

ports on PIC18F4X80 devices).

4. CCP and Enhanced CCP implementation

(PIC18F2X80 devices have 1 standard CCP

module; PIC18F4X80 devices have one

standard CCP module and one ECCP module).

5. Parallel Slave Port (present only on

PIC18F4X80 devices).

6. PIC18F4X80 devices provide two comparators.

All other features for devices in this family are identical.

These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

Like all Microchip PIC18 devices, members of the

PIC18F2480/2580/4480/4580 family are available as

both standard and low-voltage devices. Standard

devices with Enhanced Flash memory, designated with

an “F” in the part number (such as PIC18F2580),

accommodate an operating VDD range of 4.2V to 5.5V.

Low-voltage parts, designated by “LF” (such as

PIC18LF2580), function over an extended VDD range

of 2.0V to 5.5V.

PIC18F2480/2580/4480/4580

TABLE 1-1: DEVICE FEATURES

Features PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 16384 32768 16384 32768

Program Memory (Instructions) 8192 16384 8192 16384

Data Memory (Bytes) 768 1536 768 1536

Data EEPROM Memory (Bytes) 256 256 256 256

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 1 1 1 1

Enhanced Capture/

Compare/PWM Modules

0011

ECAN Module 1 1 1 1

Serial Communications MSSP,

Enhanced USART

MSSP,

Enhanced USART

MSSP,

Enhanced USART

MSSP,

Enhanced USART

Parallel Communications (PSP) No No Yes Yes

10-Bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input Channels

Comparators 0 0 2 2

Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

POR, BOR,

RESET Instruction,

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

Programmable High/

Low-Voltage Detect

Yes Yes Ye s Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

83 with Extended

Instruction Set

Enabled

75 Instructions;

83 with Extended

Instruction Set

Enabled

75 Instructions;

83 with Extended

Instruction Set

Enabled

75 Instructions;

83 with Extended

Instruction Set

Enabled

Packages 28-pin SPDIP

28-pin SOIC

28-pin QFN

28-pin SPDIP

28-pin SOIC

28-pin QFN

40-pin PDIP

44-pin QFN

44-pin TQFP

40-pin PDIP

44-pin QFN

44-pin TQFP

PIC18F2480/2580/4480/4580

FIGURE 1-1: PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM

Instruction

Decode &

Control

PORTA

PORTB

PORTC

RA4/T0CKI

RA5/AN4/SS/HLVDIN

RB0/INT0/AN10

RC0/T1OSO/T13CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

RB1/INT1/AN8

Data Latch

Data Memory

(.7, 1.5 Kbytes)

Address Latch

Data Address<12>

Access

BSR

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

RB2/INT2/CANTX

RB3/CANRX

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

OSC2/CLKO/RA6

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

RB4/KBI0/AN9

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

EUSARTComparator MSSP 10-Bit

ADC

Timer2Timer1 Timer3Timer0

ECCP1

HLVD

CCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Reference

Band Gap

VSS

MCLR(1)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

OSC1/CLKI/RA7

ECAN

BITOP

FSR0

FSR1

FSR2

inc/dec

Address

Decode

logic

PIC18F2480/2580/4480/4580

FIGURE 1-2: PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM

Instruction

Decode &

Control

Data Address<12>

Access

BSR

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PORTD

RD0/PSP0

PCLATU

PCU

PORTE

MCLR/VPP/RE3(1)

RE2/CS/AN7/C2OUT

RE0/RD/AN5

RE1/WR/AN6/C1OUT

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

/C1IN+

EUSARTComparator MSSP 10-Bit

ADC

Timer2Timer1 Timer3Timer0

CCP1

HLVD

ECCP1

BOR Data

EEPROM

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1(2)

OSC2(2)

VDD,

Brown-out

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Reference

Band Gap

VSS

MCLR(1)

Block

INTRC

Oscillator

8 MHz

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

RD1/PSP1/C1IN-

RD2/PSP2/C2IN+

RD3/PSP3/C2IN-

PORTA

PORTB

PORTC

RA4/T0CKI

RA5/AN4/SS/HLVDIN

RB0/INT0/FLT0/AN10

RC0/T1OSO/T13CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0/CVREF

RB1/INT1/AN8

RB2/INT2/CANTX

RB3/CANRX

OSC2/CLKO/RA6

RB4/KBI0/AN9

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

OSC1/CLKI/RA7

ECAN

FSR0

FSR1

FSR2

inc/dec

Address

Decode

logic

Data Latch

Data Memory

(.7, 1.5 Kbytes)

Address Latch

RD4/PSP4/ECCP1/P1A

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

PIC18F2480/2580/4480/4580

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin

Type

Buffer

Type Description

SPDIP,

SOIC QFN

MCLR/VPP/RE3

MCLR

VPP

RE3

126

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

Programming voltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

I/O

CMOS

TTL

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode; CMOS otherwise.

External clock source input. Always associated with pin

function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

10 7

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4 the

frequency of OSC1 and denotes the instruction cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

227

I/O

TTL

Analog

Digital I/O.

Analog input 0.

RA1/AN1

RA1

AN1

328

I/O

TTL

Analog

Digital I/O.

Analog input 1.

RA2/AN2/VREF-

RA2

AN2

VREF-

I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI

RA4

T0CKI

I/O

TTL

Digital I/O.

Timer0 external clock input.

RA5/AN4/SS/

HLVDIN

RA5

AN4

HLVDIN

I/O

TTL

Analog

TTL

Analog

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

SPDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0/ AN10

RB0

INT0

AN10

21 18

I/O

TTL

Analog

Digital I/O.

External interrupt 0.

Analog input 10.

RB1/INT1/AN8

RB1

INT1

AN8

22 19

I/O

TTL

Analog

Digital I/O.

External interrupt 1.

Analog input 8.

RB2/INT2/CANTX

RB2

INT2

CANTX

23 20

I/O

TTL

Digital I/O.

External interrupt 2.

CAN bus TX.

RB3/CANRX

RB3

CANRX

24 21

I/O

TTL

Digital I/O.

CAN bus RX.

RB4/KBI0/AN9

RB4

KBI0

AN9

25 22

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog input 9.

RB5/KBI1/PGM

RB5

KBI1

PGM

26 23

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

27 24

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

28 25

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

SPDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

11 8

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI

RC1

T1OSI

12 9

I/O

CMOS

Digital I/O.

Timer1 oscillator input.

RC2/CCP1

RC2

CCP1

13 10

I/O

Digital I/O.

Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK/SCL

RC3

SCK

SCL

14 11

I/O

Digital I/O.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

RC4/SDI/SDA

RC4

SDI

SDA

15 12

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO

RC5

SDO

16 13

I/O

—

Digital I/O.

SPI data out.

RC6/TX/CK

RC6

17 14

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

18 15

I/O

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

RE3 — — — — See MCLR/VPP/RE3 pin.

VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

VDD 20 17 P — Positive supply for logic and I/O pins.

TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

SPDIP,

SOIC QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

MCLR/VPP/RE3

MCLR

VPP

RE3

11818

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an

active-low Reset to the device.

Programming voltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

13 32 30

I/O

CMOS

TTL

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode;

CMOS otherwise.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

14 33 31

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4

the frequency of OSC1 and denotes the instruction

cycle rate.

General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTA is a bidirectional I/O port.

RA0/AN0/CVREF

RA0

AN0

CVREF

21919

I/O

TTL

Analog

Digital I/O.

Analog input 0.

Analog comparator reference output.

RA1/AN1

RA1

AN1

32020

I/O

TTL

Analog

Digital I/O.

Analog input 1.

RA2/AN2/VREF-

RA2

AN2

VREF-

42121

I/O

TTL

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

52222

I/O

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI

RA4

T0CKI

62323

I/O

TTL

Digital I/O.

Timer0 external clock input.

RA5/AN4/SS/

HLVDIN

RA5

AN4

HLVDIN

72424

I/O

TTL

Analog

TTL

Analog

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTB is a bidirectional I/O port. PORTB can be

software programmed for internal weak pull-ups on all

inputs.

RB0/INT0/FLT0/

AN10

RB0

INT0

FLT0

AN10

33 9 8

I/O

TTL

Analog

Digital I/O.

External interrupt 0.

Enhanced PWM Fault input (ECCP1 module).

Analog input 10.

RB1/INT1/AN8

RB1

INT1

AN8

34 10 9

I/O

TTL

Analog

Digital I/O.

External interrupt 1.

Analog input 8.

RB2/INT2/CANTX

RB2

INT2

CANTX

35 11 10

I/O

TTL

Digital I/O.

External interrupt 2.

CAN bus TX.

RB3/CANRX

RB3

CANRX

36 12 11

I/O

TTL

Digital I/O.

CAN bus RX.

RB4/KBI0/AN9

RB4

KBI0

AN9

37 14 14

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog input 9.

RB5/KBI1/PGM

RB5

KBI1

PGM

38 15 15

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGC

RB6

KBI2

PGC

39 16 16

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

40 17 17

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

data pin.

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

15 34 32

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI

RC1

T1OSI

16 35 35

I/O

CMOS

Digital I/O.

Timer1 oscillator input.

RC2/CCP1

RC2

CCP1

17 36 36

I/O

Digital I/O.

Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK/SCL

RC3

SCK

SCL

18 37 37

I/O

Digital I/O.

Synchronous serial clock input/output for

SPI mode.

Synchronous serial clock input/output for

I2C™ mode.

RC4/SDI/SDA

RC4

SDI

SDA

23 42 42

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO

RC5

SDO

24 43 43

I/O

—

Digital I/O.

SPI data out.

RC6/TX/CK

RC6

25 44 44

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

26 1 1

I/O

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTD is a bidirectional I/O port or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when PSP module

is enabled.

RD0/PSP0/C1IN+

RD0

PSP0

C1IN+

19 38 38

I/O

TTL

Analog

Digital I/O.

Parallel Slave Port data.

Comparator 1 input (+).

RD1/PSP1/C1IN-

RD1

PSP1

C1IN-

20 39 39

I/O

TTL

Analog

Digital I/O.

Parallel Slave Port data.

Comparator 1 input (-)

RD2/PSP2/C2IN+

RD2

PSP2

C2IN+

21 40 40

I/O

TTL

Analog

Digital I/O.

Parallel Slave Port data.

Comparator 2 input (+).

RD3/PSP3/C2IN-

RD3

PSP3

C2IN-

22 41 41

I/O

TTL

Analog

Digital I/O.

Parallel Slave Port data.

Comparator 2 input (-).

RD4/PSP4/ECCP1/

P1A

RD4

PSP4

ECCP1

P1A

27 2 2

I/O

TTL

Digital I/O.

Parallel Slave Port data.

Capture 2 input/Compare 2 output/PWM2 output.

ECCP1 PWM output A.

RD5/PSP5/P1B

RD5

PSP5

P1B

28 3 3

I/O

TTL

Digital I/O.

Parallel Slave Port data.

ECCP1 PWM output B.

RD6/PSP6/P1C

RD6

PSP6

P1C

29 4 4

I/O

TTL

Digital I/O.

Parallel Slave Port data.

ECCP1 PWM output C.

RD7/PSP7/P1D

RD7

PSP7

P1D

30 5 5

I/O

TTL

Digital I/O.

Parallel Slave Port data.

ECCP1 PWM output D.

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

PORTE is a bidirectional I/O port.

RE0/RD/AN5

RE0

AN5

82525

I/O

TTL

Analog

Digital I/O.

Read control for Parallel Slave Port (see also WR

and CS pins).

Analog input 5.

RE1/WR/AN6/C1OUT

RE1

AN6

C1OUT

92626

I/O

TTL

Analog

TTL

Digital I/O.

Write control for Parallel Slave Port (see CS

and RD pins).

Analog input 6.

Comparator 1 output.

RE2/CS/AN7/C2OUT

RE2

AN7

C2OUT

10 27 27

I/O

TTL

Analog

TTL

Digital I/O.

Chip select control for Parallel Slave Port (see

related RD and WR).

Analog input 7.

Comparator 2 output.

RE3 — — — — — See MCLR/VPP/RE3 pin.

VSS 12,

6, 30,

6, 29 P — Ground reference for logic and I/O pins.

VDD 11,

7, 8,

28, 29

7, 28 P — Positive supply for logic and I/O pins.

NC — 13 12, 13,

33, 34

— — No connect.

TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type

Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

PIC18F2480/2580/4480/4580

NOTES:

PIC18F2480/2580/4480/4580

2.0 OSCILLATOR

CONFIGURATIONS

2.1 Oscillator Types

PIC18F2480/2580/4480/4580 devices can be operated

in ten different oscillator modes. The user can program

the Configuration bits, FOSC3:FOSC0, in Configuration

1. LP Low-Power Crystal

2. XT Crystal/Resonator

3. HS High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL Enabled

5. RC External Resistor/Capacitor with

FOSC/4 Output on RA6

6. RCIO External Resistor/Capacitor with I/O

on RA6

7. INTIO1 Internal Oscillator with FOSC/4 Output

on RA6 and I/O on RA7

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

9. EC External Clock with FOSC/4 Output

10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic

Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal or

ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections.

The oscillator design requires the use of a parallel cut

crystal.

FIGURE 2-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(XT, LP, HS OR HSPLL

CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Note: Use of a series cut crystal may give a

frequency out of the crystal manufacturer’s

specifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

56 pF

47 pF

33 pF

56 pF

47 pF

33 pF

HS 8.0 MHz

16.0 MHz

27 pF

22 pF

27 pF

22 pF

Capacitor values are for design guidance only.

These capacitors were tested with the resonators

listed below for basic start-up and operation. These

values are not optimized.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes on page 24 for additional information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

Note: When using resonators with frequencies

above 3.5 MHz, the use of HS mode,

rather than XT mode, is recommended.

HS mode may be used at any VDD for

which the controller is rated. If HS is

selected, it is possible that the gain of the

oscillator will overdrive the resonator.

Therefore, a series resistor should be

placed between the OSC2 pin and the

resonator. As a good starting point, the

recommended value of RS is 330Ω.

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

PIC18FXXXX

RS(2)

Internal

PIC18F2480/2580/4480/4580

TABLE 2-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 2-2.

FIGURE 2-2: EXTERNAL CLOCK

INPUT OPERATION

(HS OSCILLATOR

CONFIGURATION)

2.3 External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. There is

no oscillator start-up time required after a Power-on

Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

FIGURE 2-3: EXTERNAL CLOCK

INPUT OPERATION

(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional

general purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-4 shows the pin connections

for the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCK

INPUT OPERATION

(ECIO CONFIGURATION)

Osc Type Crystal

Freq

Typical Capacitor Values

Tested:

C1 C2

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed

below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use the

HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

5: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

OSC1

OSC2

Open

Clock from

Ext. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System PIC18FXXXX

OSC1/CLKI

I/O (OSC2)

RA6

Clock from

Ext. System PIC18FXXXX

PIC18F2480/2580/4480/4580

2.4 RC Oscillator

For timing insensitive applications, the “RC” and

“RCIO” device options offer additional cost savings.

The actual oscillator frequency is a function of several

factors:

• supply voltage

• values of the external resistor (REXT) and

capacitor (CEXT)

• operating temperature

Given the same device, operating voltage and tempera-

ture and component values, there will also be unit-to-unit

frequency variations. These are due to factors such as:

• normal manufacturing variation

• difference in lead frame capacitance between

package types (especially for low CEXT values)

• variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-5 shows how the R/C combination is

connected.

FIGURE 2-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 2-6) functions like

the RC mode, except that the OSC2 pin becomes an

additional general purpose I/O pin. The I/O pin

becomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

2.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals or users who require higher

clock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS mode oscillator

for frequencies up to 10 MHz. A PLL then multiplies the

oscillator output frequency by 4 to produce an internal

clock frequency up to 40 MHz.

The PLL is only available to the crystal oscillator when

the FOSC3:FOSC0 Configuration bits are programmed

for HSPLL mode (= 0110).

FIGURE 2-7: PLL BLOCK DIAGRAM

(HS MODE)

2.5.2 PLL AND INTOSC

The PLL is also available to the internal oscillator block

in selected oscillator modes. In this configuration, the

PLL is enabled in software and generates a clock

output of up to 32 MHz. The operation of INTOSC with

the PLL is described in Section 2.6.4 “PLL in INTOSC

Modes”.

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

CEXT

REXT

PIC18FXXXX

OSC1 Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

I/O (OSC2)

RA6

MUX

VCO

Loop

Filter

Crystal

Osc

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

HS Osc Enable

÷4

(from Configuration Register 1H)

HS Mode

PIC18F2480/2580/4480/4580
DS39637C-page 26 Preliminary © 2007 Microchip Technology Inc.
2.6 Internal Oscillator Block
The PIC18F2480/2580/4480/4580 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the micro-
controller’s clock source. This may eliminate the need
for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled: 
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4, 
while OSC1 functions as RA7 for digital input and 
output.
• In INTIO2 mode, OSC1 functions as RA7 and 
OSC2 functions as RA6, both for digital input and 
output.
2.6.2 INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz. 
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across volt-
age and temperature are not necessarily reflected by
changes in INTRC and vice versa.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”. 
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.
2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through soft-
ware. The control bit, PLLEN (OSCTUNE<6>), is used
to enable or disable its operation. 
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all other
modes, it is forced to ‘0’ and is effectively unavailable.
2.6.5 INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are
discussed in Section 2.6.5.1 “Compensating with
the EUSART”, Section 2.6.5.2 “Compensating with
the Timers” and Section 2.6.5.3 “Compensating
with the CCP Module in Capture Mode”, but other
techniques may be used.

PIC18F2480/2580/4480/4580

2.6.5.1 Compensating with the EUSART

An adjustment may be required when the EUSART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high. To

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low. To

compensate, increment OSCTUNE to increase the

clock frequency.

2.6.5.2 Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, then the internal oscillator

block is running too fast. To adjust for this, decrement

the OSCTUNE register.

2.6.5.3 Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the first event is subtracted from the time of the

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the

calculated time, the internal oscillator block is running

too fast. To compensate, decrement the OSCTUNE

calculated time, the internal oscillator block is running

too slow. To compensate, increment the OSCTUNE

R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)

0 = PLL disabled

bit 5 Unimplemented: Read as ‘0’

bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency

• •

00001

00000 = Center frequency. Oscillator module is running at the calibrated frequency.

11111

• •

10000 = Minimum frequency

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See

text for details.

PIC18F2480/2580/4480/4580

2.7 Clock Sources and Oscillator

Switching

Like previous PIC18 devices, the

PIC18F2480/2580/4480/4580 family includes a feature

that allows the device clock source to be switched from

the main oscillator to an alternate low-frequency clock

source. PIC18F2480/2580/4480/4580 devices offer

two alternate clock sources. When an alternate clock

source is enabled, the various power-managed

operating modes are available.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The primary oscillators include the external crystal

and resonator modes, the external RC modes, the

external clock modes and the internal oscillator block.

The particular mode is defined by the FOSC3:FOSC0

Configuration bits. The details of these modes are

covered earlier in this chapter.

The secondary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F2480/2580/4480/4580 devices offer the Timer1

oscillator as a secondary oscillator. This oscillator, in all

power-managed modes, is often the time base for

functions such as a Real-Time Clock (RTC).

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Like the LP Oscillator mode circuit, loading

capacitors are also connected from each pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 12.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal

oscillator block is available as a power-managed

mode clock source. The INTRC source is also used as

the clock source for several special features, such as

the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F2480/2580/4480/4580

devices are shown in Figure 2-8. See Section 24.0

“Special Features of the CPU” for Configuration

FIGURE 2-8: PIC18F2480/2580/4480/4580 CLOCK DIAGRAM

PIC18F2X80/4X80

4 x PLL

FOSC3:FOSC0

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for Other Modules

OSC1

OSC2

Sleep

Primary Oscillator

HSPLL, INTOSC/PLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC)

OSCTUNE<6>

OSCTUNE<7>

and Two-Speed Start-up

PIC18F2480/2580/4480/4580

2.7.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in

full-power operation and in power-managed modes.

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC3:FOSC0 Configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator block. The clock source changes

immediately after one or more of the bits is written to,

following a brief clock transition interval. The SCS bits

are cleared on all forms of Reset.

The Internal Oscillator Frequency Select bits,

IRCF2:IRCF0, select the frequency output of the

internal oscillator block to drive the device clock. The

choices are the INTRC source, the INTOSC source

(8 MHz) or one of the frequencies derived from the

INTOSC postscaler (31 kHz to 4 MHz). If the internal

oscillator block is supplying the device clock, changing

the states of these bits will have an immediate change

on the internal oscillator’s output. On device Resets,

the default output frequency of the internal oscillator

block is set at 1 MHz.

When an output frequency of 31 kHz is selected

(IRCF2:IRCF0 = 000), users may choose which inter-

nal oscillator acts as the source. This is done with the

INTSRC bit in the OSCTUNE register (OSCTUNE<7>).

Setting this bit selects INTOSC as a 31.25 kHz clock

source by enabling the divide-by-256 output of the

INTOSC postscaler. Clearing INTSRC selects INTRC

(nominally 31 kHz) as the clock source.

This option allows users to select the tunable and more

precise INTOSC as a clock source, while maintaining

power savings with a very low clock speed. Regardless

of the setting of INTSRC, INTRC always remains the

clock source for features such as the Watchdog Timer

and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock

source is currently providing the device clock. The

OSTS bit indicates that the Oscillator Start-up Timer

has timed out and the primary clock is providing the

device clock in primary clock modes. The IOFS bit indi-

cates when the internal oscillator block has stabilized

and is providing the device clock in RC Clock modes.

The T1RUN bit (T1CON<6>) indicates when the

Timer1 oscillator is providing the device clock in

secondary clock modes. In power-managed modes,

only one of these three bits will be set at any time. If

none of these bits are set, the INTRC is providing the

clock or the internal oscillator block has just started and

is not yet stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-Managed Modes”.

2.7.2 OSCILLATOR TRANSITIONS

PIC18F2480/2580/4480/4580 devices contain circuitry

to prevent clock “glitches” when switching between

clock sources. A short pause in the device clock occurs

during the clock switch. The length of this pause is the

sum of two cycles of the old clock source and three to

four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction, or a very

long delay may occur while the Timer1

oscillator starts.

PIC18F2480/2580/4480/4580

R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction

0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits

111 = 8 MHz (INTOSC drives clock directly)

110 = 4 MHz

101 = 2 MHz

100 = 1 MHz(3)

011 = 500 kHz

010 = 250 kHz

001 = 125 kHz

000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1)

1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running

0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes

0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits

1x = Internal oscillator block

01 = Timer1 oscillator

00 = Primary oscillator

Note 1: Depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.

3: Default output frequency of INTOSC on Reset.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 31
PIC18F2480/2580/4480/4580
2.8 Effects of Power-Managed Modes 
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating. 
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the
power-managed mode (see Section 24.2 “Watchdog
Timer (WDT)”,  Section 24.3 “Two-Speed Start-up”
and Section 24.4 “Fail-Safe Clock Monitor” for more
information on WDT, Two-Speed Start-up and Fail-Safe
Clock Monitor. The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock (RTC). Other features may be operat-
ing that do not require a device clock source (i.e.,
MSSP slave, PSP, INTx pins and others). Peripherals
that may add significant current consumption are listed
in  Section 27.2 “DC Characteristics: Power Down
and Supply Current”.
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circum-
stances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 27-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit. 
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval T
CSD (parameter 38,
Table 27-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
OSC Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent 
voltage level
Feedback inverter disabled at quiescent 
voltage level
Note: See Table 4-2 in Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset.

PIC18F2480/2580/4480/4580

NOTES:

PIC18F2480/2580/4480/4580

3.0 POWER-MANAGED MODES

PIC18F2480/2580/4480/4580 devices offer a total of

seven operating modes for more efficient power

management. These modes provide a variety of

options for selective power conservation in applications

where resources may be limited (i.e., battery-powered

devices).

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

These categories define which portions of the device

are clocked and sometimes, what speed. The Run and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block); the Sleep mode does not use a clock source.

The power-managed modes include several

power-saving features offered on previous PIC®

devices. One is the clock switching feature, offered in

other PIC18 devices, allowing the controller to use the

Timer1 oscillator in place of the primary oscillator. Also

included is the Sleep mode, offered by all PIC devices,

where all device clocks are stopped.

3.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and the

selection of a clock source. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS1:SCS0 bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock sources

and affected modules are summarized in Table 3-1.

3.1.1 CLOCK SOURCES

The SCS1:SCS0 bits allow the selection of one of three

clock sources for power-managed modes. They are:

• The primary clock, as defined by the

FOSC3:FOSC0 Configuration bits

• The secondary clock (the Timer1 oscillator)

• The internal oscillator block (for RC modes)

3.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS1:SCS0 bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator

select bits, or changing the IDLEN bit, prior to issuing a

SLEEP instruction. If the IDLEN bit is already

configured correctly, it may only be necessary to

perform a SLEEP instruction to switch to the desired

mode.

TABLE 3-1: POWER-MANAGED MODES

Mode

OSCCON<7,1:0> Module Clocking

Available Clock and Oscillator Source

IDLEN(1) SCS1:SCS0 CPU Peripherals

Sleep 0N/A Off Off None – All clocks are disabled

PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2):

This is the normal full-power execution mode.

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)

PRI_IDLE 100Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 11xOff Clocked Internal Oscillator Block(2)

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

PIC18F2480/2580/4480/4580

3.1.3 CLOCK TRANSITIONS AND

STATUS INDICATORS

The length of the transition between clock sources is

the sum of two cycles of the old clock source and three

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Three bits indicate the current clock source and its

status. They are:

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a

given power-managed mode. When the OSTS bit is

set, the primary clock is providing the device clock.

When the IOFS bit is set, the INTOSC output is provid-

ing a stable 8 MHz clock source to a divider that

actually drives the device clock. When the T1RUN bit is

set, the Timer1 oscillator is providing the clock. If none

of these bits are set, then either the INTRC clock

source is clocking the device, or the INTOSC source is

not yet stable.

If the internal oscillator block is configured as the

primary clock source by the FOSC3:FOSC0 Configura-

tion bits, then both the OSTS and IOFS bits may be set

when in PRI_RUN or PRI_IDLE modes. This indicates

that the primary clock (INTOSC output) is generating a

stable 8 MHz output. Entering another RC

power-managed mode at the same frequency would

clear the OSTS bit.

3.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-managed mode specified by IDLEN at

that time. If IDLEN has changed, the device will enter the

new power-managed mode specified by the new setting.

3.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

3.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full-power execution

mode of the microcontroller. This is also the default

mode upon a device Reset, unless Two-Speed Start-up

is enabled (see Section 24.3 “Two-Speed Start-up” for

details). In this mode, the OSTS bit is set. The IOFS bit

may be set if the internal oscillator block is the primary

clock source (see Section 2.7.1 “Oscillator Control

3.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of lower power consumption while still using a

high accuracy clock source.

SEC_RUN mode is entered by setting the SCS1:SCS0

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 3-1), the primary oscilla-

tor is shut down, the T1RUN bit (T1CON<6>) is set and

the OSTS bit is cleared.

Note 1: Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode, or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS1:SCS0 bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled but not yet

running, device clocks will be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

PIC18F2480/2580/4480/4580

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the Timer1 oscillator while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 3-2). When the clock switch is complete, the

T1RUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up; the Timer1

oscillator continues to run.

FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer; the primary clock is shut down.

When using the INTRC source, this mode provides the

best power conservation of all the Run modes, while

still executing code. It works well for user applications

which are not highly timing sensitive or do not require

high-speed clocks at all times.

If the primary clock source is the internal oscillator

block (either INTRC or INTOSC), there are no distin-

guishable differences between PRI_RUN and

RC_RUN modes during execution. However, a clock

switch delay will occur during entry to and exit from

RC_RUN mode. Therefore, if the primary clock source

is the internal oscillator block, the use of RC_RUN

mode is not recommended.

This mode is entered by setting SCS1 to ‘1’. Although

it is ignored, it is recommended that SCS0 also be

cleared; this is to maintain software compatibility with

future devices. When the clock source is switched to

the INTOSC multiplexer (see Figure 3-3), the primary

oscillator is shut down and the OSTS bit is cleared. The

IRCF bits may be modified at any time to immediately

change the clock speed.

Q4Q3Q2

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2PC

123

n-1

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS1:SCS0 Bits Changed

TOST(1) TPLL(1)

12 n-1n

Clock

OSTS Bit Set

Transition

Note: Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

PIC18F2480/2580/4480/4580

If the IRCF bits and the INTSRC bit are all clear, the

INTOSC output is not enabled and the IOFS bit will

remain clear; there will be no indication of the current

clock source. The INTRC source is providing the

device clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output) or if INTSRC is set, the

IOFS bit becomes set after the INTOSC output

becomes stable. Clocks to the device continue while

the INTOSC source stabilizes after an interval of

TIOBST.

If the IRCF bits were previously at a non-zero value or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multiplexer while the primary clock is started. When the

primary clock becomes ready, a clock switch to the

primary clock occurs (see Figure 3-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. The IDLEN and SCS bits are not affected by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTOSC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS1:SCS0 Bits Changed

TOST(1) TPLL(1)

12 n-1n

Clock

OSTS Bit Set

Transition

Multiplexer

PIC18F2480/2580/4480/4580

3.3 Sleep Mode

The power-managed Sleep mode in the

PIC18F2480/2580/4480/4580 devices is identical to

the legacy Sleep mode offered in all other PIC devices.

It is entered by clearing the IDLEN bit (the default state

on device Reset) and executing the SLEEP instruction.

This shuts down the selected oscillator (Figure 3-5). All

clock source status bits are cleared.

Entering the Sleep mode from any other mode does not

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS1:SCS0 bits

becomes ready (see Figure 3-6), or it will be clocked

from the internal oscillator block if either the

Two-Speed Start-up or the Fail-Safe Clock Monitor are

enabled (see Section 24.0 “Special Features of the

CPU”). In either case, the OSTS bit is set when the pri-

mary clock is providing the device clocks. The IDLEN

and SCS bits are not affected by the wake-up.

3.4 Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to ‘1’ when a SLEEP instruction is

executed, the peripherals will be clocked from the clock

source selected using the SCS1:SCS0 bits; however, the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instruction provides a quick method of switching from a

given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue

to operate. If the Timer1 oscillator is enabled, it will also

continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 27-10) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_RUN mode). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS1:SCS0 bits.

FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1) TPLL(1)

OSTS Bit Set

PC + 2

PIC18F2480/2580/4480/4580

3.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC3:FOSC0 Configuration bits. The OSTS

bit remains set (see Figure 3-7).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the

wake-up, the OSTS bit remains set. The IDLEN and

SCS bits are not affected by the wake-up (see

Figure 3-8).

3.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by set-

ting the IDLEN bit and executing a SLEEP instruction. If

the device is in another Run mode, set the IDLEN bit

first, then set the SCS1:SCS0 bits to ‘01’ and execute

SLEEP. When the clock source is switched to the

Timer1 oscillator, the primary oscillator is shut down,

the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-8).

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, the SLEEP

instruction will be ignored and entry to

SEC_IDLE mode will not occur. If the

Timer1 oscillator is enabled but not yet

running, peripheral clocks will be delayed

until the oscillator has started. In such

situations, initial oscillator operation is far

from stable and unpredictable operation

may result.

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 39
PIC18F2480/2580/4480/4580
3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency, by modifying the IRCF
bits, before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer,
the primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 27-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the INTOSC multiplexer.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”). 
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 24.2 “Watchdog
Timer (WDT)”). 
The WDT timer and postscaler are cleared by execut-
ing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5.3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead. 
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 24.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 24.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.

PIC18F2480/2580/4480/4580

3.5.4 EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode where the primary clock source

is not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

In these instances, the primary clock source either

does not require an oscillator start-up delay, since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC and INTIO

Oscillator modes). However, a fixed delay of interval,

TCSD, following the wake event is still required when

leaving Sleep and Idle modes to allow the CPU to

prepare for execution. Instruction execution resumes

on the first clock cycle following this delay.

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

Before Wake-up

Clock Source

After Wake-up Exit Delay Clock Ready Status

bit (OSCCON)

Primary Device Clock

(PRI_IDLE mode)

LP, XT, HS

TCSD(2)

OSTSHSPLL

EC, RC

INTRC(1) —

INTOSC(3) IOFS

T1OSC or INTRC(1)

LP, XT, HS TOST(4)

OSTS

HSPLL TOST + trc(4)

EC, RC TCSD(2)

INTRC(1) —

INTOSC(3) TIOBST(5) IOFS

INTOSC(3)

LP, XT, HS TOST(5)

OSTS

HSPLL TOST + trc(4)

EC, RC TCSD(2)

INTRC(1) —

INTOSC(3) None IOFS

None

(Sleep mode)

LP, XT, HS TOST(4)

OSTS

HSPLL TOST + trc(4)

EC, RC TCSD(2)

INTRC(1) —

INTOSC(3) TIOBST(5) IOFS

Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.

2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 “Idle Modes”).

3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is

also designated as TPLL.

5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 41
PIC18F2480/2580/4480/4580
4.0 RESET
The PIC18F2480/2580/4480/4580 devices differentiate
between various kinds of Reset: 
a) Power-on Reset (POR) 
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes 
d) Watchdog Timer (WDT) Reset (during 
execution)
e) Programmable Brown-out Reset (BOR) 
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT        
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC
(1)
POR Pulse
OST
10-Bit Ripple Counter
PWRT
Chip_Reset
11-Bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 μs
MCLRE

PIC18F2480/2580/4480/4580

R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0

IPEN SBOREN —RITO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit(1)

If BOREN1:BOREN0 = 01:

1 = BOR is enabled

0 = BOR is disabled

If BOREN1:BOREN0 = 00, 10 or 11:

Bit is disabled and reads as ‘0’.

bit 5 Unimplemented: Read as ‘0’

bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction

0 = Set by execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit(2)

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent

Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after a Power-on Reset).

PIC18F2480/2580/4480/4580

4.2 Master Clear Reset (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

holding the pin low. These devices have a noise filter in

the MCLR Reset path which detects and ignores small

pulses.

The MCLR pin is not driven low by any internal Resets,

including the WDT.

In PIC18F2480/2580/4480/4580 devices, the MCLR

input can be disabled with the MCLRE Configuration

bit. When MCLR is disabled, the pin becomes a digital

input. See Section 10.5 “PORTE, TRISE and LATE

Registers” for more information.

4.3 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 4-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

POR events are captured by the POR bit (RCON<1>).

The state of the bit is set to ‘0’ whenever a Power-on

Reset occurs; it does not change for any other Reset

event. POR is not reset to ‘1’ by any hardware event.

To capture multiple events, the user manually resets

the bit to ‘1’ in software following any Power-on Reset.

FIGURE 4-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR/VPP pin breakdown, due to Electro-

static Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

PIC18FXXXX

VDD

PIC18F2480/2580/4480/4580

4.4 Brown-out Reset (BOR)

PIC18F2480/2580/4480/4580 devices implement a

BOR circuit that provides the user with a number of

configuration and power-saving options. The BOR is

controlled by the BORV1:BORV0 and

BOREN1:BOREN0 Configuration bits. There are a

total of four BOR configurations which are summarized

in Table 4-1.

The BOR threshold is set by the BORV1:BORV0 bits. If

BOR is enabled (any values of BOREN1:BOREN0,

except ‘00’), any drop of VDD below VBOR (parameter

D005) for greater than TBOR (parameter 35) will reset

the device. A Reset may or may not occur if VDD falls

below VBOR for less than TBOR. The chip will remain in

Brown-out Reset until VDD rises above VBOR.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above VBOR; it then will keep the chip in

Reset for an additional time delay, TPWRT

(parameter 33). If VDD drops below VBOR while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be

initialized. Once VDD rises above VBOR, the Power-up

Timer will execute the additional time delay.

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling a Brown-out Reset

does not automatically enable the PWRT.

4.4.1 SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be

enabled or disabled by the user in software. This is

done with the control bit, SBOREN (RCON<6>).

Setting SBOREN enables the BOR to function as

previously described. Clearing SBOREN disables the

BOR entirely. The SBOREN bit operates only in this

mode; otherwise it is read as ‘0’.

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to its

environment without having to reprogram the device to

change BOR configuration. It also allows the user to

tailor device power consumption in software by elimi-

nating the incremental current that the BOR consumes.

While the BOR current is typically very small, it may

have some impact in low-power applications.

4.4.2 DETECTING BOR

When Brown-out Reset is enabled, the BOR bit always

resets to ‘0’ on any Brown-out Reset or Power-on

Reset event. This makes it difficult to determine if a

Brown-out Reset event has occurred just by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This assumes that the POR bit is reset to ‘1’ in software

immediately after any Power-on Reset event. IF BOR

is ‘0’ while POR is ‘1’, it can be reliably assumed that a

Brown-out Reset event has occurred.

4.4.3 DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains

under hardware control and operates as previously

described. Whenever the device enters Sleep mode,

however, the BOR is automatically disabled. When the

device returns to any other operating mode, BOR is

automatically re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it saves additional power in Sleep mode

by eliminating the small incremental BOR current.

TABLE 4-1: BOR CONFIGURATIONS

Note: Even when BOR is under software control,

the Brown-out Reset voltage level is still

set by the BORV1:BORV0 Configuration

bits. It cannot be changed in software.

BOR Configuration Status of

SBOREN

(RCON<6>)

BOR Operation

BOREN1 BOREN0

00Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.

01Available BOR enabled in software; operation controlled by SBOREN.

10Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep

mode.

11Unavailable BOR enabled in hardware; must be disabled by reprogramming the

Configuration bits.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 45
PIC18F2480/2580/4480/4580
4.5 Device Reset Timers
PIC18F2480/2580/4480/4580 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F2480/2580/
4480/4580 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs=65.6ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit. 
4.5.2 OSCILLATOR START-UP TIMER 
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT
time-out is invoked (if enabled). 
2. Then, the OST is activated. 
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS  
Oscillator
Configuration
Power-up(2) and Brown-out Exit from 
Power-Managed Mode
PWRTEN = 0PWRTEN = 1
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) ——
RC, RCIO 66 ms(1) ——
INTIO1, INTIO2 66 ms(1) ——
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.

PIC18F2480/2580/4480/4580

FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC18F2480/2580/4480/4580

FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V 1V

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

PIC18F2480/2580/4480/4580

4.6 Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on a Power-on Reset and unchanged by all

other Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

Reset situations, as indicated in Table 4-3. These bits

are used in software to determine the nature of the

Reset.

Table 4-4 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition Program

Counter

RCON Register STKPTR Register

SBOREN RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 1 11100 0 0

RESET instruction 0000h u(2) 0uuuu u u

Brown-out Reset 0000h u(2) 111u0 u u

MCLR Reset during

power-managed Run modes

0000h u(2) u1uuu u u

MCLR Reset during

power-managed Idle modes and

Sleep mode

0000h u(2) u10uu u u

WDT time-out during full power

or power-managed Run modes

0000h u(2) u0uuu u u

MCLR Reset during full-power

execution

0000h u(2) uuuuu u u

Stack Full Reset (STVREN = 1) 0000h u(2) uuuuu 1 u

Stack Underflow Reset

(STVREN = 1)

0000h u(2) uuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)

0000h u(2) uuuuu u 1

WDT Time-out during

power-managed Idle or Sleep

modes

PC + 2 u(2) u00uu u u

Interrupt exit from

power-managed modes

PC + 2 u(2) uu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

PIC18F2480/2580/4480/4580

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

TOSU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---0 uuuu(3)

TOSH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3)

TOSL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(3)

STKPTR 2480 2580 4480 4580 00-0 0000 uu-0 0000 uu-u uuuu(3)

PCLATU 2480 2580 4480 4580 ---0 0000 ---0 0000 ---u uuuu

PCLATH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

PCL 2480 2580 4480 4580 0000 0000 0000 0000 PC + 2(2)

TBLPTRU 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu

TBLPTRH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TBLPTRL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TABLAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

PRODH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON 2480 2580 4480 4580 0000 000x 0000 000u uuuu uuuu(1)

INTCON2 2480 2580 4480 4580 1111 -1-1 1111 -1-1 uuuu -u-u(1)

INTCON3 2480 2580 4480 4580 11-0 0-00 11-0 0-00 uu-u u-uu(1)

INDF0 2480 2580 4480 4580 N/A N/A N/A

POSTINC0 2480 2580 4480 4580 N/A N/A N/A

POSTDEC0 2480 2580 4480 4580 N/A N/A N/A

PREINC0 2480 2580 4480 4580 N/A N/A N/A

PLUSW0 2480 2580 4480 4580 N/A N/A N/A

FSR0H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu

FSR0L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

WREG 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 2480 2580 4480 4580 N/A N/A N/A

POSTINC1 2480 2580 4480 4580 N/A N/A N/A

POSTDEC1 2480 2580 4480 4580 N/A N/A N/A

PREINC1 2480 2580 4480 4580 N/A N/A N/A

PLUSW1 2480 2580 4480 4580 N/A N/A N/A

FSR1H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu

FSR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

BSR 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu

INDF2 2480 2580 4480 4580 N/A N/A N/A

POSTINC2 2480 2580 4480 4580 N/A N/A N/A

POSTDEC2 2480 2580 4480 4580 N/A N/A N/A

PREINC2 2480 2580 4480 4580 N/A N/A N/A

PLUSW2 2480 2580 4480 4580 N/A N/A N/A

FSR2H 2480 2580 4480 4580 ---- 0000 ---- 0000 ---- uuuu

FSR2L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS 2480 2580 4480 4580 ---x xxxx ---u uuuu ---u uuuu

TMR0H 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TMR0L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

OSCCON 2480 2580 4480 4580 0100 q000 0100 00q0 uuuu uuqu

HLVDCON 2480 2580 4480 4580 0-00 0101 0-00 0101 0-uu uuuu

WDTCON 2480 2580 4480 4580 ---- ---0 ---- ---0 ---- ---u

RCON(4) 2480 2580 4480 4580 0q-1 11q0 0q-q qquu uq-u qquu

TMR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 2480 2580 4480 4580 0000 0000 u0uu uuuu uuuu uuuu

TMR2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

PR2 2480 2580 4480 4580 1111 1111 1111 1111 1111 1111

T2CON 2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu

SSPBUF 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

SSPSTAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

SSPCON1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

SSPCON2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

ADRESH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu

ADCON1 2480 2580 4480 4580 --00 0qqq --00 0qqq --uu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

ADCON2 2480 2580 4480 4580 0-00 0000 0-00 0000 u-uu uuuu

CCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu

ECCPR1H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

ECCPR1L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

ECCP1CON 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

BAUDCON 2480 2580 4480 4580 01-0 0-00 01-0 0-00 --uu uuuu

ECCP1DEL 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

ECCP1AS 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

CVRCON 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

CMCON 2480 2580 4480 4580 0000 0111 0000 0111 uuuu uuuu

TMR3H 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON 2480 2580 4480 4580 0000 0000 uuuu uuuu uuuu uuuu

SPBRGH 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

SPBRG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RCREG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TXREG 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TXSTA 2480 2580 4480 4580 0000 0010 0000 0010 uuuu uuuu

RCSTA 2480 2580 4480 4580 0000 000x 0000 000x uuuu uuuu

EEADR 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

EEDATA 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

EECON2 2480 2580 4480 4580 0000 0000 0000 0000 0000 0000

EECON1 2480 2580 4480 4580 xx-0 x000 uu-0 u000 uu-0 u000

IPR3 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

PIR3 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

PIE3 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

IPR2 2480 2580 4480 4580 11-1 1111 11-1 1111 uu-u uuuu

2480 2580 4480 4580 1--1 111- 1--1 111- u--u uuu-

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

PIR2 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu(1)

2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu-(1)

PIE2 2480 2580 4480 4580 00-0 0000 00-0 0000 uu-u uuuu

2480 2580 4480 4580 0--0 000- 0--0 000- u--u uuu-

IPR1 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

2480 2580 4480 4580 -111 1111 -111 1111 -uuu uuuu

PIR1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu(1)

2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu

PIE1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

2480 2580 4480 4580 -000 0000 -000 0000 -uuu uuuu

OSCTUNE 2480 2580 4480 4580 --00 0000 --00 0000 --uu uuuu

TRISE 2480 2580 4480 4580 0000 -111 0000 -111 uuuu -uuu

TRISD 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

TRISC 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

TRISB 2480 2580 4480 4580 1111 1111 1111 1111 uuuu uuuu

TRISA(5) 2480 2580 4480 4580 1111 1111(5) 1111 1111(5) uuuu uuuu(5)

LATE 2480 2580 4480 4580 ---- -xxx ---- -uuu ---- -uuu

LATD 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

LATC 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

LATB 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5) 2480 2580 4480 4580 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)

PORTE 2480 2580 4480 4580 ---- x000 ---- x000 ---- uuuu

PORTD 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5) 2480 2580 4480 4580 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)

ECANCON 2480 2580 4480 4580 0001 0000 0001 0000 uuuu uuuu

TXERRCNT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXERRCNT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

COMSTAT 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

CIOCON 2480 2580 4480 4580 --00 ---- --00 ---- --uu ----

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

BRGCON3 2480 2580 4480 4580 00-- -000 00-- -000 uu-- -uuu

BRGCON2 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

BRGCON1 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

CANCON 2480 2580 4480 4580 1000 000- 1000 000- uuuu uuu-

CANSTAT 2480 2580 4480 4580 100- 000- 100- 000- uuu- uuu-

RXB0D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0DLC 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

RXB0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

RXB0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB0CON 2480 2580 4480 4580 000- 0000 000- 0000 uuu- uuuu

RXB1D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1DLC 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

RXB1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

RXB1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXB1CON 2480 2580 4480 4580 000- 0000 000- 0000 uuu- uuuu

TXB0D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu

TXB0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

TXB0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

TXB0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB0CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu

TXB1D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu

TXB1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- uu-u

TXB1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

TXB1CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu

TXB2D7 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

TXB2D6 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D5 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D4 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D3 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D2 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D1 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2D0 2480 2580 4480 4580 xxxx xxxx uuuu uuuu 0uuu uuuu

TXB2DLC 2480 2580 4480 4580 -x-- xxxx -u-- uuuu -u-- uuuu

TXB2EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB2EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TXB2SIDL 2480 2580 4480 4580 xxxx x-xx uuuu u-uu -uuu uuuu

TXB2SIDH 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

TXB2CON 2480 2580 4480 4580 0000 0-00 0000 0-00 uuuu u-uu

RXM1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXM1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXM1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXM1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXM0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXM0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXM0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXM0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF5EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF5EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF5SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF5SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF4EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF4EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF4SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF4SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF3EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF3EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

RXF3SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF3SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF2EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF2EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF2SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF2SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF1EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF1EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF1SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF1SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF0EIDL 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF0EIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF0SIDL 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF0SIDH 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

B5EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B5SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B5SIDH(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B5CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

B4D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

B4D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

B4EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B4SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B4CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

B3D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

B3EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B3SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B3CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

B2D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

B2D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

B2EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B2SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B2CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

B1D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

B1EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B1SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B1CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

B0D7(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D6(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D5(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D4(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D3(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D2(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D1(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0D0(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0DLC(6) 2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

B0EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0SIDL(6) 2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu

B0SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

B0CON(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

TXBIE(6) 2480 2580 4480 4580 ---0 00-- ---u uu-- ---u uu--

BIE0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

BSEL0(6) 2480 2580 4480 4580 0000 00-- 0000 00-- uuuu uu--

MSEL3(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

MSEL2(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

MSEL1(6) 2480 2580 4480 4580 0000 0101 0000 0101 uuuu uuuu

MSEL0(6) 2480 2580 4480 4580 0101 0000 0101 0000 uuuu uuuu

SDFLC(6) 2480 2580 4480 4580 ---0 0000 ---0 0000 -u-- uuuu

RXFCON1(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFCON0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON7(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON6(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON5(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON4(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON3(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXFBCON2(6) 2480 2580 4480 4580 0001 0001 0001 0001 uuuu uuuu

RXFBCON1(6) 2480 2580 4480 4580 0001 0001 0001 0001 uuuu uuuu

RXFBCON0(6) 2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu

RXF15EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF15EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF15SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF15SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF14EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF14EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF14SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF14SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

RXF13EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF13EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF13SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF13SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF12EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF12EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF12SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF12SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF11EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF11EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF11SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu uuu- u-uu

RXF11SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu

RXF10EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF10EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF10SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu

RXF10SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF9EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF9EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF9SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu

RXF9SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF8EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF8EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF8SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu

RXF8SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF7EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF7EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF7SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu

RXF7SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF6EIDL(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF6EIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

RXF6SIDL(6) 2480 2580 4480 4580 xxx- x-xx uuu- u-uu -uuu uuuu

RXF6SIDH(6) 2480 2580 4480 4580 xxxx xxxx uuuu uuuu -uuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F2480/2580/4480/4580

5.0 MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for con-

current access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is addressed and accessed

through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash Program Memory”. Data EEPROM is dis-

cussed separately in Section 7.0 “Data EEPROM

Memory”.

5.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

program memory space. Accessing a location between

upper boundary of the physically implemented memory

and the 2-Mbyte address will return all ‘0’s (a NOP

instruction).

The PIC18F2480 and PIC18F4480 each have

16 Kbytes of Flash memory and can store up to 8,192

single-word instructions. The PIC18F2580 and

PIC18F4580 each have 32 Kbytes of Flash memory

and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory maps for PIC18FX480 and

PIC18FX580 devices are shown in Figure 5-1.

FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR

PIC18F2480/2580/4480/4580 DEVICES

PC<20:0>

Stack Level 1

•

Stack Level 31

Reset Vector

Low-Priority Interrupt Vector

•

CALL,RCALL,RETURN

RETFIE,RETLW

0000h

0018h

On-Chip

Program Memory

High-Priority Interrupt Vector 0008h

User Memory Space

1FFFFFh

4000h

3FFFh

Read ‘0’

200000h

PC<20:0>

Stack Level 1

•

Stack Level 31

Reset Vector

Low-Priority Interrupt Vector

•

CALL,RCALL,RETURN

RETFIE,RETLW

0000h

0018h

80000h

7FFFh

On-Chip

Program Memory

High-Priority Interrupt Vector 0008h

User Memory Space

Read ‘0’

1FFFFFh

200000h

PIC18FX480 PIC18FX580

PIC18F2480/2580/4480/4580

5.1.1 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and writable. The high byte, or PCH register, contains

the PC<15:8> bits; it is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 5.1.4.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to

a value of ‘0’. The PC increments by 2 to address

sequential instructions in the program memory.

The CALL, RCALL and GOTO program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

5.1.2 RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALL or RCALL instruc-

tion is executed or an interrupt is Acknowledged. The

PC value is pulled off the stack on a RETURN, RETLW

or a RETFIE instruction. PCLATU and PCLATH are not

affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data space. The Stack Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the

top-of-stack Special File Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

A CALL type instruction causes a push onto the stack;

the Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURN type instruction causes

a pop from the stack; the contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Reset value. Status bits indicate if the stack is

full or has overflowed or has underflowed.

5.1.2.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is

readable and writable. A set of three registers,

TOSU:TOSH:TOSL, hold the contents of the stack loca-

tion pointed to by the STKPTR register (Figure 5-2). This

allows users to implement a software stack if necessary.

After a CALL, RCALL or interrupt, the software can read

the pushed value by reading the TOSU:TOSH:TOSL

registers. These values can be placed on a user defined

software stack. At return time, the software can return

these values to TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack <20:0>

To p - o f - St a c k

000D58h

TOSLTOSHTOSU

34h1Ah00h

STKPTR<4:0>

Top-of-Stack Registers Stack Pointer

PIC18F2480/2580/4480/4580

5.1.2.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register 5-1) contains the Stack

Pointer value, the STKFUL (Stack Full) status bit and

the STKUNF (Stack Underflow) status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System for return stack maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 24.1 “Configuration Bits” for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

5.1.2.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit(1)

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F2480/2580/4480/4580

5.1.2.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 4L. When STVREN is set, a full

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

5.1.3 FAST REGISTER STACK

A fast register stack is provided for the STATUS,

WREG and BSR registers, to provide a “fast return”

option for interrupts. Each stack is only one level deep

and is neither readable nor writable. It is loaded with the

current value of the corresponding register when the

processor vectors for an interrupt. All interrupt sources

will push values into the stack registers. The values in

the registers are then loaded back into their associated

registers, if the RETFIE, FAST instruction is used to

return from the interrupt.

If both low and high-priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low-priority interrupts. If a high-priority interrupt occurs

while servicing a low-priority interrupt, the Stack

be overwritten. In these cases, users must save the key

registers in software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the

fast register stack for returns from interrupt. If no inter-

rupts are used, the Fast Register Stack can be used to

restore the STATUS, WREG and BSR registers at the

end of a subroutine call. To use the fast register stack

for a subroutine call, a CALL label, FAST instruction

must be executed to save the STATUS, WREG and

BSR registers to the fast register stack. A

RETURN, FAST instruction is then executed to restore

these registers from the fast register stack.

Example 5-1 shows a source code example that uses

the fast register stack during a subroutine call and

return.

EXAMPLE 5-1: FAST REGISTER STACK

CODE EXAMPLE

5.1.4 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1 Computed GOTO

A computed GOTO is accomplished by adding an offset

to the program counter. An example is shown in

Example 5-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions, that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 5-2: COMPUTED GOTO USING

AN OFFSET VALUE

5.1.4.2 Table Reads and Table Writes

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

Look-up table data may be stored two bytes per

program word by using table reads and writes. The

Table Pointer (TBLPTR) register specifies the byte

address and the Table Latch (TABLAT) register con-

tains the data that is read from or written to program

memory. Data is transferred to or from program

memory one byte at a time.

Table read and table write operations are discussed

further in Section 6.1 “Table Reads and Table Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18F2480/2580/4480/4580

5.2 PIC18 Instruction Cycle

5.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an inter-

nal or external source, is internally divided by four to

generate four non-overlapping quadrature clocks (Q1,

Q2, Q3 and Q4). Internally, the Program Counter (PC)

is incremented on every Q1; the instruction is fetched

from the program memory and latched into the Instruc-

tion Register (IR) during Q4. The instruction is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 5-3.

5.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the

pipelining, each instruction effectively executes in one

cycle. If an instruction causes the program counter to

change (e.g., GOTO), then two cycles are required to

complete the instruction (Example 5-3).

A fetch cycle begins with the program counter

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 5-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

Note: All instructions are single cycle, except for any program branches. These take two cycles since the

fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then

executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC18F2480/2580/4480/4580

5.2.3 INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). To maintain alignment

with instruction boundaries, the PC increments in steps

of 2 and the LSB will always read ‘0’ (see Section 5.1.1

“Program Counter”).

Figure 5-4 shows an example of how instruction words

are stored in the program memory.

The CALL and GOTO instructions have the absolute pro-

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 5-4 shows how the

instruction GOTO 0006h is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions that the PC will be

offset by. Section 25.0 “Instruction Set Summary”

provides further details of the instruction set.

FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

5.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instructions always has

‘1111’ as its four Most Significant bits; the other 12 bits

are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction spec-

ifies a special form of NOP. If the instruction is executed

in proper sequence – immediately after the first word –

the data in the second word is accessed and used by

the instruction sequence. If the first word is skipped for

some reason and the second word is executed by itself,

a NOP is executed instead. This is necessary for cases

when the two-word instruction is preceded by a condi-

tional instruction that changes the PC. Example 5-4

shows how this works.

EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

Word Address

LSB = 1LSB = 0↓

Program Memory

Byte Locations →

000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Note: See Section 5.5 “Program Memory and

the Extended Instruction Set” for infor-

mation on two-word instructions in the

extended instruction set.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F2480/2580/4480/4580

5.3 Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each;

PIC18F2480/2580/4480/4580 devices implement all

16 banks. Figure 5-6 shows the data memory

organization for the PIC18F2480/2580/4480/4580

devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s appli-

cation. Any read of an unimplemented location will read

as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle, PIC18

devices implement an Access Bank. This is a 256-byte

memory space that provides fast access to SFRs and

the lower portion of GPR Bank 0 without using the

BSR. Section 5.3.2 “Access Bank” provides a

detailed description of the Access RAM.

5.3.1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR3:BSR0). The upper four

bits are unused; they will always read ‘0’ and cannot be

written to. The BSR can be loaded directly by using the

MOVLB instruction.

The value of the BSR indicates the bank in data mem-

ory; the 8 bits in the instruction show the location in the

bank and can be thought of as an offset from the bank’s

lower boundary. The relationship between the BSR’s

value and the bank division in data memory is shown in

Figure 5-7.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an 8-bit address of F9h, while the BSR

is 0Fh will end up resetting the Program Counter.

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 5-6 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the

BSR completely when it executes. All other instructions

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their target registers.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 5.6 “Data Memory and the

Extended Instruction Set” for more

information.

PIC18F2480/2580/4480/4580

FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2480/4480 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When a = 0:

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

general purpose RAM

(from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

When a = 1:

The BSR specifies the Bank

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

CAN SFRs

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

CAN SFRs

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unimplemented

Read as ‘0’

PIC18F2480/2580/4480/4580

FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2580/4580 DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

00h

5Fh

60h

FFh

Access Bank

When a = 0:

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

general purpose RAM

(from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

When a = 1:

The BSR specifies the Bank

used by the instruction.

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

CAN SFRs

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

CAN SFRs

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unimplemented

Read as ‘0’

PIC18F2480/2580/4480/4580

FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

5.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data memory, it also means that the user must always

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation, but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

To streamline access for the most commonly used data

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 128 bytes of

memory (00h-7Fh) in Bank 0 and the last 128 bytes of

memory (80h-FFh) in Block 15. The lower half is known

as the “Access RAM” and is composed of GPRs. The

upper half is where the device’s SFRs are mapped.

These two areas are mapped contiguously in the

Access Bank and can be addressed in a linear fashion

by an 8-bit address (Figure 5-6).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the instruction

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle, without

updating the BSR first. For 8-bit addresses of 80h and

above, this means that users can evaluate and operate

on SFRs more efficiently. The Access RAM below 80h

is a good place for data values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail

in Section 5.6.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

5.3.3 GENERAL PURPOSE

PIC18 devices may have banked memory in the GPR

area. This is data RAM, which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom

of the SFR area. GPRs are not initialized by a

Power-on Reset and are unchanged on all other

Resets.

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0011 11111111

BSR(1)

PIC18F2480/2580/4480/4580

5.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

the top half of Bank 15 (F80h to FFFh). A list of these

registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The reset and interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this

section. Registers related to the operation of a

peripheral feature are described in the chapter for that

peripheral.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(3) FBFh ECCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2(3) FBEh ECCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H(1) F9Ch —

FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L(1) F9Bh OSCTUNE

FFAh PCLATH FDAh FSR2H FBAh ECCP1CON(1) F9Ah —

FF9h PCL FD9h FSR2L FB9h — F99h —

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h —

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(1) F96h TRISE(1)

FF5h TABLAT FD5h T0CON FB5h CVRCON(1) F95h TRISD(1)

FF4h PRODH FD4h — FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —

FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh —

FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh —

FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(1)

FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(1)

FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh —F8AhLATB

FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA

FE8h WREG FC8h SSPADD FA8h EEDATA F88h —

FE7h INDF1(3) FC7h SSPSTAT FA7h EECON2(3) F87h —

FE6h POSTINC1(3) FC6h SSPCON1 FA6h EECON1 F86h —

FE5h POSTDEC1(3) FC5h SSPCON2 FA5h IPR3 F85h —

FE4h PREINC1(3) FC4h ADRESH FA4h PIR3 F84h PORTE

FE3h PLUSW1(3) FC3h ADRESL FA3h PIE3 F83h PORTD(1)

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

PIC18F2480/2580/4480/4580

Address Name Address Name Address Name Address Name

F7Fh — F5Fh CANCON_RO0 F3Fh CANCON_RO2 F1Fh RXM1EIDL

F7Eh — F5Eh CANSTAT_RO0 F3Eh CANSTAT_RO2 F1Eh RXM1EIDH

F7Dh — F5Dh RXB1D7 F3Dh TXB1D7 F1Dh RXM1SIDL

F7Ch — F5Ch RXB1D6 F3Ch TXB1D6 F1Ch RXM1SIDH

F7Bh — F5Bh RXB1D5 F3Bh TXB1D5 F1Bh RXM0EIDL

F7Ah — F5Ah RXB1D4 F3Ah TXB1D4 F1Ah RXM0EIDH

F79h — F59h RXB1D3 F39h TXB1D3 F19h RXM0SIDL

F78h — F58h RXB1D2 F38h TXB1D2 F18h RXM0SIDH

F77h ECANCON F57h RXB1D1 F37h TXB1D1 F17h RXF5EIDL

F76h TXERRCNT F56h RXB1D0 F36h TXB1D0 F16h RXF5EIDH

F75h RXERRCNT F55h RXB1DLC F35h TXB1DLC F15h RXF5SIDL

F74h COMSTAT F54h RXB1EIDL F34h TXB1EIDL F14h RXF5SIDH

F73h CIOCON F53h RXB1EIDH F33h TXB1EIDH F13h RXF4EIDL

F72h BRGCON3 F52h RXB1SIDL F32h TXB1SIDL F12h RXF4EIDH

F71h BRGCON2 F51h RXB1SIDH F31h TXB1SIDH F11h RXF4SIDL

F70h BRGCON1 F50h RXB1CON F30h TXB1CON F10h RXF4SIDH

F6Fh CANCON F4Fh CANCON_RO1 F2Fh CANCON_RO3 F0Fh RXF3EIDL

F6Eh CANSTAT F4Eh CANSTAT_RO1 F2Eh CANSTAT_RO3 F0Eh RXF3EIDH

F6Dh RXB0D7 F4DH TXB0D7 F2Dh TXB2D7 F0Dh RXF3SIDL

F6Ch RXB0D6 F4Ch TXB0D6 F2Ch TXB2D6 F0Ch RXF3SIDH

F6Bh RXB0D5 F4Bh TXB0D5 F2Bh TXB2D5 F0Bh RXF2EIDL

F6Ah RXB0D4 F4Ah TXB0D4 F2Ah TXB2D4 F0Ah RXF2EIDH

F69h RXB0D3 F49h TXB0D3 F29h TXB2D3 F09h RXF2SIDL

F68h RXB0D2 F48h TXB0D2 F28h TXB2D2 F08h RXF2SIDH

F67h RXB0D1 F47h TXB0D1 F27h TXB2D1 F07h RXF1EIDL

F66h RXB0D0 F46h TXB0D0 F26h TXB2D0 F06h RXF1EIDH

F65h RXB0DLC F45h TXB0DLC F25h TXB2DLC F05h RXF1SIDL

F64h RXB0EIDL F44h TXB0EIDL F24h TXB2EIDL F04h RXF1SIDH

F63h RXB0EIDH F43h TXB0EIDH F23h TXB2EIDH F03h RXF0EIDL

F62h RXB0SIDL F42h TXB0SIDL F22h TXB2SIDL F02h RXF0EIDH

F61h RXB0SIDH F41h TXB0SIDH F21h TXB2SIDH F01h RXF0SIDL

F60h RXB0CON F40h TXB0CON F20h TXB2CON F00h RXF0SIDH

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES (CONTINUED)

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

PIC18F2480/2580/4480/4580

Address Name Address Name Address Name Address Name

EFFh —EDFh—EBFh—E9Fh—

EFEh —EDEh—EBEh—E9Eh—

EFDh —EDDh—EBDh—E9Dh—

EFCh —EDCh—EBCh—E9Ch—

EFBh —EDBh—EBBh—E9Bh—

EFAh —EDAh—EBAh—E9Ah—

EF9h —ED9h—EB9h— E99h —

EF8h —ED8h—EB8h— E98h —

EF7h —ED7h—EB7h— E97h —

EF6h —ED6h—EB6h— E96h —

EF5h —ED5h—EB5h— E95h —

EF4h —ED4h—EB4h— E94h —

EF3h —ED3h—EB3h— E93h —

EF2h —ED2h—EB2h— E92h —

EF1h —ED1h—EB1h— E91h —

EF0h —ED0h—EB0h— E90h —

EEFh —ECFh—EAFh—E8Fh—

EEEh —ECEh—EAEh—E8Eh—

EEDh —ECDh—EADh—E8Dh—

EECh —ECCh—EACh—E8Ch—

EEBh —ECBh—EABh—E8Bh—

EEAh —ECAh—EAAh—E8Ah—

EE9h —EC9h—EA9h— E89h —

EE8h —EC8h—EA8h— E88h —

EE7h —EC7h—EA7h— E87h —

EE6h —EC6h—EA6h— E86h —

EE5h —EC5h—EA5h— E85h —

EE4h —EC4h—EA4h— E84h —

EE3h —EC3h—EA3h— E83h —

EE2h —EC2h—EA2h— E82h —

EE1h —EC1h—EA1h— E81h —

EE0h —EC0h—EA0h— E80h —

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES (CONTINUED)

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

PIC18F2480/2580/4480/4580

Address Name Address Name Address Name Address Name

E7Fh CANCON_RO4 E6Fh CANCON_RO5 E5Fh CANCON_RO6 E4Fh CANCON_RO7

E7Eh CANSTAT_RO4 E6Eh CANSTAT_RO5 E5Eh CANSTAT_RO6 E4Eh CANSTAT_RO7

E7Dh B5D7(2) E6Dh B4D7(2) E5Dh B3D7(2) E4Dh B2D7(2)

E7Ch B5D6(2) E6Ch B4D6(2) E5Ch B3D6(2) E4Ch B2D6(2)

E7Bh B5D5(2) E6Bh B4D5(2) E5Bh B3D5(2) E4Bh B2D5(2)

E7Ah B5D4(2) E6Ah B4D4(2) E5Ah B3D4(2) E4Ah B2D4(2)

E79h B5D3(2) E69h B4D3(2) E59h B3D3(2) E49h B2D3(2)

E78h B5D2(2) E68h B4D2(2) E58h B3D2(2) E48h B2D2(2)

E77h B5D1(2) E67h B4D1(2) E57h B3D1(2) E47h B2D1(2)

E76h B5D0(2) E66h B4D0(2) E56h B3D0(2) E46h B2D0(2)

E75h B5DLC(2) E65h B4DLC(2) E55h B3DLC(2) E45h B2DLC(2)

E74h B5EIDL(2) E64h B4EIDL(2) E54h B3EIDL(2) E44h B2EIDL(2)

E73h B5EIDH(2) E63h B4EIDH(2) E53h B3EIDH(2) E43h B2EIDH(2)

E72h B5SIDL(2) E62h B4SIDL(2) E52h B3SIDL(2) E42h B2SIDL(2)

E71h B5SIDH(2) E61h B4SIDH(2) E51h B3SIDH(2) E41h B2SIDH(2)

E70h B5CON (2) E60h B4CON(2) E50h B3CON(2) E40h B2CON(2)

E3Fh CANCON_RO8 E2Fh CANCON_RO9 E1Fh —E0Fh—

E3Eh CANSTAT_RO8 E2Eh CANSTAT_RO9 E1Eh —E0Eh—

E3Dh B1D7(2) E2Dh B0D7(2) E1Dh —E0Dh—

E3Ch B1D6(2) E2Ch B0D6(2) E1Ch —E0Ch—

E3Bh B1D5(2) E2Bh B0D5(2) E1Bh —E0Bh—

E3Ah B1D4(2) E2Ah B0D4(2) E1Ah —E0Ah—

E39h B1D3(2) E29h B0D3(2) E19h — E09h —

E38h B1D2(2) E28h B0D2(2) E18h — E08h —

E37h B1D1(2) E27h B0D1(2) E17h — E07h —

E36h B1D0(2) E26h B0D0(2) E16h — E06h —

E35h B1DLC(2) E25h B0DLC(2) E15h — E05h —

E34h B1EIDL(2) E24h B0EIDL(2) E14h — E04h —

E33h B1EIDH(2) E23h B0EIDH(2) E13h — E03h —

E32h B1SIDL(2) E22h B0SIDL(2) E12h — E02h —

E31h B1SIDH(2) E21h B0SIDH(2) E11h — E01h —

E30h B1CON(2) E20h B0CON(2) E10h — E00h —

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES (CONTINUED)

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

PIC18F2480/2580/4480/4580

Address Name Address Name Address Name Address Name

DFFh — DDFh —DBFh—D9Fh—

DFEh — DDEh —DBEh—D9Eh—

DFDh —DDDh—DBDh—D9Dh—

DFCh TXBIE DDCh —DBCh—D9Ch—

DFBh — DDBh —DBBh—D9Bh—

DFAh BIE0 DDAh —DBAh—D9Ah—

DF9h —DD9h—DB9h— D99h —

DF8h BSEL0 DD8h SDFLC DB8h — D98h —

DF7h —DD7h—DB7h— D97h —

DF6h —DD6h—DB6h— D96h —

DF5h — DD5h RXFCON1 DB5h — D95h —

DF4h — DD4h RXFCON0 DB4h — D94h —

DF3h MSEL3 DD3h —DB3h— D93h RXF15EIDL

DF2h MSEL2 DD2h —DB2h— D92h RXF15EIDH

DF1h MSEL1 DD1h —DB1h— D91h RXF15SIDL

DF0h MSEL0 DD0h —DB0h— D90h RXF15SIDH

DEFh — DCFh —DAFh—D8Fh—

DEEh — DCEh —DAEh—D8Eh—

DEDh —DCDh—DADh—D8Dh—

DECh —DCCh—DACh—D8Ch—

DEBh — DCBh —DABh—D8BhRXF14EIDL

DEAh — DCAh —DAAh— D8Ah RXF14EIDH

DE9h —DC9h—DA9h— D89h RXF14SIDL

DE8h —DC8h—DA8h— D88h RXF14SIDH

DE7h RXFBCON7 DC7h —DA7h— D87h RXF13EIDL

DE6h RXFBCON6 DC6h —DA6h— D86h RXF13EIDH

DE5h RXFBCON5 DC5h —DA5h— D85h RXF13SIDL

DE4h RXFBCON4 DC4h —DA4h— D84h RXF13SIDH

DE3h RXFBCON3 DC3h —DA3h— D83h RXF12EIDL

DE2h RXFBCON2 DC2h —DA2h— D82h RXF12EIDH

DE1h RXFBCON1 DC1h —DA1h— D81h RXF12SIDL

DE0h RXFBCON0 DC0h —DA0h— D80h RXF12SIDH

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES (CONTINUED)

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

PIC18F2480/2580/4480/4580

Address Name

D7Fh —

D7Eh —

D7Dh —

D7Ch —

D7Bh RXF11EIDL

D7Ah RXF11EIDH

D79h RXF11SIDL

D78h RXF11SIDH

D77h RXF10EIDL

D76h RXF10EIDH

D75h RXF10SIDL

D74h RXF10SIDH

D73h RXF9EIDL

D72h RXF9EIDH

D71h RXF9SIDL

D70h RXF9SIDH

D6Fh —

D6Eh —

D6Dh —

D6Ch —

D6Bh RXF8EIDL

D6Ah RXF8EIDH

D69h RXF8SIDL

D68h RXF8SIDH

D67h RXF7EIDL

D66h RXF7EIDH

D65h RXF7SIDL

D64h RXF7SIDH

D63h RXF6EIDL

D62h RXF6EIDH

D61h RXF6SIDL

D60h RXF6SIDH

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR

PIC18F2480/2580/4480/4580 DEVICES (CONTINUED)

Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.

2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.

3: This is not a physical register.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 77
PIC18F2480/2580/4480/4580
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 62
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 49, 62
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 49, 62
STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 49, 63
PCLATU ——bit 21
(1) Holding Register for PC<20:16> ---0 0000 49, 62
PCLATH Holding Register for PC<15:8> 0000 0000 49, 62
PCL PC Low Byte (PC<7:0>) 0000 0000 49, 62
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 103
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 49, 103
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 49, 103
TABLAT Program Memory Table Latch 0000 0000 49, 103
PRODH Product Register High Byte xxxx xxxx 49, 111
PRODL Product Register Low Byte xxxx xxxx 49, 111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 115
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 49, 116
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 117
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 90
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 91
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 91
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 91
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), value of 
FSR0 offset by W
N/A 49, 91
FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 49, 90
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 49, 90
WREG Working Register xxxx xxxx 49
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 90
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 91
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 91
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 91
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register), value of 
FSR1 offset by W
N/A 49, 91
FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- xxxx 49, 90
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 49, 90
BSR — — — — Bank Select Register ---- 0000 50, 67
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 90
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 91
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 91
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 91
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register), value of 
FSR2 offset by W
N/A 50, 91
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

PIC18F2480/2580/4480/4580
DS39637C-page 78 Preliminary © 2007 Microchip Technology Inc.
FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- xxxx 50, 90
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50, 90
STATUS — — —NOV Z DC C---x xxxx 50, 88
TMR0H Timer0 Register High Byte 0000 0000 50, 149
TMR0L Timer0 Register Low Byte xxxx xxxx 50, 149
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 149
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 30, 50
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 267
WDTCON — — — — — — —SWDTEN--- ---0 50, 353
RCON IPEN SBOREN(2) —RITO PD POR BOR 0q-1 11q0 50, 127
TMR1H Timer1 Register High Byte xxxx xxxx 50, 155
TMR1L Timer1 Register Low Byte 0000 0000 50, 155
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 151
TMR2 Timer2 Register 1111 1111 50, 158
PR2 Timer2 Period Register -000 0000 50, 155
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 157
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 50, 195
SSPADD MSSP Address Register in I2C Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 50, 195
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 50, 197
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 198
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 199
ADRESH A/D Result Register High Byte xxxx xxxx 50, 256
ADRESL A/D Result Register Low Byte xxxx xxxx 50, 256
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 50, 247
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 50, 248
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 249
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 51, 168
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 51, 168
CCP1CON  —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 51, 163
ECCPR1H(9) Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 51, 167
ECCPR1L(9) Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 51, 167
ECCP1CON(9) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 0000 0000 51, 168
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0000 51, 230
ECCP1DEL(9) PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 51, 182
ECCP1AS(9) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 51, 183
CVRCON(9) CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 263
CMCON(9) C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 51, 257
TMR3H Timer3 Register High Byte xxxx xxxx 51, 161
TMR3L Timer3 Register Low Byte xxxx xxxx 51, 161
T3CON RD16 T3ECCP1(9) T3CKPS1 T3CKPS0 T3CCP1(9) T3SYNC TMR3CS TMR3ON 0000 0000 51, 161
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 79
PIC18F2480/2580/4480/4580
SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 51, 231
SPBRG EUSART Baud Rate Generator 0000 0000 51, 231
RCREG EUSART Receive Register 0000 0000 51, 238
TXREG EUSART Transmit Register 0000 0000 51, 236
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 237
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 237
EEADR EEPROM Address Register 0000 0000 51, 105
EEDATA EEPROM Data Register 0000 0000 51, 105
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 105
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 105
IPR3
Mode 0
IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP 1111 1111 51, 126
IPR3
Mode 1, 2
IRXIP WAKIP ERRIP TXBnIP TXB1IP(8) TXB0IP(8) RXBnIP FIFOWMIP 1111 1111 51, 126
PIR3
Mode 0
IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF 0000 0000 51, 120
PIR3
Mode 1, 2
IRXIF WAKIF ERRIF TXBnIF TXB1IF(8) TXB0IF(8) RXBnIF FIFOWMIF 0000 0000 51, 120
PIE3
Mode 0
IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE 0000 0000 51, 123
PIE3
Mode 1, 2
IRXIE WAKIE ERRIE TXBnIE TXB1IE(8) TXB0IE(8) RXBnIE FIFOMWIE 0000 0000 51, 123
IPR2 OSCFIP CMIP(9) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(9) 11-1 1111 51, 125
PIR2 OSCFIF CMIF(9) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(9) 00-0 0000 52, 119
PIE2 OSCFIE CMIE(9) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(9) 00-0 0000 52, 122
IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 124
PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 118
PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 121
OSCTUNE INTSRC PLLEN(4) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52
TRISE(3) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 141
TRISD(3) PORTD Data Direction Register 1111 1111 52, 138
TRISC PORTC Data Direction Register 1111 1111 52, 135
TRISB PORTB Data Direction Register 1111 1111 52, 132
TRISA TRISA7(6) TRISA6(6) PORTA Data Direction Register 1111 1111 52, 129
LATE(3) — — — — —LATE2LATE1LATE0---- -xxx 52, 141
LATD(3) LATD Output Latch Register xxxx xxxx 52, 138
LATC LATC Output Latch Register xxxx xxxx 52, 135
LATB LATB Output Latch Register xxxx xxxx 52, 132
LATA LATA7 (6) LATA6(6) LATA Output Latch Register xxxx xxxx 52, 129
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

PIC18F2480/2580/4480/4580
DS39637C-page 80 Preliminary © 2007 Microchip Technology Inc.
PORTE(3) — — — —RE3
(5) RE2(3) RE1(3) RE0(3) ---- xxxx 52, 145
PORTD(3) PORTD Data Direction Register xxxx xxxx 52, 138
PORTC PORTC Data Direction Register xxxx xxxx 52, 135
PORTB PORTB Data Direction Register xxxx xxxx 52, 132
PORTA RA7(6) RA6(6) PORTA Data Direction Register xx00 0000 52, 129
ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 0001 000 52, 280
TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 52, 285
RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 52, 293
COMSTAT
Mode 0
RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281
COMSTAT
Mode 1
— RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 52, 281
COMSTAT
Mode 2
FIFOEMPTY RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281
CIOCON —— ENDRHI CANCAP — — — — --00 ---- 52, 314
BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 53, 313
BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 53, 312
BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 53, 311
CANCON
Mode 0
REQOP2 REQOP1 REQOP0 ABAT WIN2(7) WIN1(7) WIN0(7) —(7) 1000 000- 53, 276
CANCON
Mode 1
REQOP2 REQOP1 REQOP0 ABAT —(7) —(7) —(7) —(7) 1000 ---- 53, 276
CANCON
Mode 2
REQOP2 REQOP1 REQOP0 ABAT FP3(7) FP2(7) FP1(7) FP0(7) 1000 0000 53, 276
CANSTAT
Mode 0
OPMODE2 OPMODE1 OPMODE0 —(7) ICODE3(7) ICODE2(7) ICODE1(7) —(7) 000- 0000 53, 277
CANSTAT
Modes 1, 2
OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7) EICODE2(7) EICODE1(7) EICODE0(7) 0000 0000 53, 277
RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 53, 292
RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 53, 292
RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx 53, 292
RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 53, 292
RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 53, 292
RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 53, 292
RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 53, 292
RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 53, 292
RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 53, 292
RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 53, 291
RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 53, 291
RXB0SIDL SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 53, 291
RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 53, 290
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 81
PIC18F2480/2580/4480/4580
RXB0CON
Mode 0
RXFUL RXM1 RXM0(7) —(7) RXRTRRO(7) RXBODBEN(7) JTOFF(7) FILHIT0(7) 000- 0000 53, 287
RXB0CON
Mode 1, 2
RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 53, 287
RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 53, 292
RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 53, 292
RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52 RXB1D51 RXB1D50 xxxx xxxx 53, 292
RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42 RXB1D41 RXB1D40 xxxx xxxx 53, 292
RXB1D3 RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32 RXB1D31 RXB1D30 xxxx xxxx 53, 292
RXB1D2 RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22 RXB1D21 RXB1D20 xxxx xxxx 53, 292
RXB1D1 RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12 RXB1D11 RXB1D10 xxxx xxxx 53, 292
RXB1D0 RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02 RXB1D01 RXB1D00 xxxx xxxx 53, 292
RXB1DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 53, 292
RXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 53, 291
RXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 53, 291
RXB1SIDL SID2 SID1 SID0 SRR EXID —EID17EID16xxxx xxxx 53, 291
RXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 290
RXB1CON
Mode 0
RXFUL RXM1 RXM0(7) —(7) RXRTRRO(7) FILHIT2(7) FILHIT1(7) FILHIT0(7) 000- 0000 54, 287
RXB1CON
Mode 1, 2
RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 54, 287
TXB0D7 TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72 TXB0D71 TXB0D70 xxxx xxxx 54, 284
TXB0D6 TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62 TXB0D61 TXB0D60 xxxx xxxx 54, 284
TXB0D5 TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52 TXB0D51 TXB0D50 xxxx xxxx 54, 284
TXB0D4 TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42 TXB0D41 TXB0D40 xxxx xxxx 54, 284
TXB0D3 TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32 TXB0D31 TXB0D30 xxxx xxxx 54, 284
TXB0D2 TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22 TXB0D21 TXB0D20 xxxx xxxx 54, 284
TXB0D1 TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12 TXB0D11 TXB0D10 xxxx xxxx 54, 284
TXB0D0 TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02 TXB0D01 TXB0D00 xxxx xxxx 54, 284
TXB0DLC —TXRTR—— DLC3 DLC2 DLC1 DLC0 -x-- xxxx 54, 285
TXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 54, 284
TXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 54, 283
TXB0SIDL SID2 SID1 SID0 —EXIDE —EID17EID16xxx- x-xx 54, 283
TXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 283
TXB0CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 54, 282
TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 54, 284
TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 54, 284
TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 54, 284
TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 54, 284
TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 54, 284
TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 54, 284
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

PIC18F2480/2580/4480/4580
DS39637C-page 82 Preliminary © 2007 Microchip Technology Inc.
TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 54, 284
TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 54, 284
TXB1DLC —TXRTR—— DLC3 DLC2 DLC1 DLC0 -x-- xxxx 54, 285
TXB1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 54, 284
TXB1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 54, 283
TXB1SIDL SID2 SID1 SID0 —EXIDE —EID17EID16xxx- x-xx 54, 283
TXB1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 54, 283
TXB1CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 54, 282
TXB2D7 TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 54, 284
TXB2D6 TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 55, 284
TXB2D5 TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 55, 284
TXB2D4 TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 55, 284
TXB2D3 TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 55, 284
TXB2D2 TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 55, 284
TXB2D1 TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 55, 284
TXB2D0 TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 55, 284
TXB2DLC —TXRTR—— DLC3 DLC2 DLC1 DLC0 -x-- xxxx 55, 285
TXB2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 284
TXB2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 283
TXB2SIDL SID2 SID1 SID0 —EXIDE —EID17EID16xxxx x-xx 55, 283
TXB2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxx- x-xx 55, 283
TXB2CON TXBIF TXABT TXLARB TXERR TXREQ — TXPRI1 TXPRI0 0000 0-00 55, 282
RXM1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 304
RXM1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 304
RXM1SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 55, 304
RXM1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 304
RXM0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 304
RXM0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 304
RXM0SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 55, 304
RXM0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 303
RXF5EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 303
RXF5EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 303
RXF5SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 55, 302
RXF5SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 302
RXF4EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 303
RXF4EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 303
RXF4SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 55, 302
RXF4SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 55, 302
RXF3EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 55, 303
RXF3EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 55, 303
RXF3SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 56, 302
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.

© 2007 Microchip Technology Inc. Preliminary DS39637C-page 83
PIC18F2480/2580/4480/4580
RXF3SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 302
RXF2EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 303
RXF2EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 303
RXF2SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 56, 302
RXF2SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 302
RXF1EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 303
RXF1EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 303
RXF1SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 56, 302
RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 302
RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 303
RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 303
RXF0SIDL SID2 SID1 SID0 — EXIDEN —EID17EID16xxx- x-xx 56, 302
RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 302
B5D7(8) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 56, 299
B5D6(8) B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 xxxx xxxx 56, 299
B5D5(8) B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 xxxx xxxx 56, 299
B5D4(8) B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 xxxx xxxx 56, 299
B5D3(8) B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 xxxx xxxx 56, 299
B5D2(8) B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 xxxx xxxx 56, 299
B5D1(8) B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 xxxx xxxx 56, 299
B5D0(8) B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 xxxx xxxx 56, 299
B5DLC(8) 
Receive mode
— RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301
B5DLC(8) 
Transmit mode
—TXRTR—— DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 301
B5EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 299
B5EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 298
B5SIDL(8) 
Receive mode
SID2 SID1 SID0 SRR EXID —EID17EID16xxxx x-xx 56, 297
B5SIDL(8) 
Transmit mode
SID2 SID1 SID0 —EXIDE —EID17EID16xxx- x-xx 56, 297
B5SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx x-xx 56, 296
B5CON(8) 
Receive mode
RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 56, 295
B5CON(8) 
Transmit mode
TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 56, 295
B4D7(8) B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 xxxx xxxx 56, 299
B4D6(8) B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 xxxx xxxx 56, 299
B4D5(8) B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 xxxx xxxx 56, 299
B4D4(8) B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 xxxx xxxx 57, 299
B4D3(8) B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 xxxx xxxx 57, 299
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on 
POR, BOR
Details on 
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices; 
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC 
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When 
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.