MC6802NS - Motorola / Freescale Semiconductor

●

MICROPROCESSOR WITH CLOCK AND OPTIONAL RAM

The MC6802 is amonolithic 8-bit microprocessor that contains all the

registers and accumulators of the present MC68~ plus an internal clock

oscillator and dtiver on the same chip, In addition, the MC8802 has 128

bytes of on-board RAM located at hex addresses $0000 to $O07F. The

first 32 bytes of RAM, at hex addresses $~0 to $001 F, maybe retained

in alow power mode by utilizing VCC standby; thus, facilitating

memory retention during apower-down situation.

The MC6802 is completely software compatible with’ the MC68W as

well as the entire M68~ family of parts. Hence, the MC6802 is expand-

able to ~K words,

The MC~02NS is identical to the MC6802 without standby RAM

feature. The MC~08 is identical to the MC6802 without on-board

RAM.

0On-Chip Clock Circuit

——

m+’~ Cso -VMA VMA —-~

HA.LT

.>..+,. t:.

*\i?,},*

~,,s.\t:.-{~\,.,.

‘::;/,. Clock

2kBytes ROM E

RIF RE -

.;+ 10 1/0 Lines —

Parallel 3Unes Timer R‘w MC6802 ml -

MPU ~A -

1/0 DO-D7 DO-D7 DO-D7 EXTAL ~

Control {CP2 AO-A1O,

CP1 Csl AO-A15 AO-A15 XTAL -

This block diagram shows atvpical cost effective microcomputer. The MPU is

the center of the microcomputersystem and is shown in aminimum svstem inter-

facing with aROM combination chip, It is not intended that this system be

limited to this function but that it be expandable with other parts in the M6800

Microcomputer family.

PIN ASSIGNMENT

-n

Vss 1 g 40 RESET

HALT 23g EXTAL

MR 338 XTAL

FQ [437 E

VMA[ 536 ]RE*’

NMI[ 635 JVCC Standby’

BA[ ?wJR/~

Vcc[ 833 ]DO

AO~932 ]Dl

Al [10 31 ]D2

A2 [11 30 ~D3

A3 [12 29 ]D4

A4 [13 28 ]D5

A5 [14 27 ]D6

A6 [15 26 ]D7

A7 [16 25 ]A15

A8 [77 24 1 A14

A9 [18 23 ]A13

A1O [19 22 ]A12

All[ 20 21 IVss

●pifl 35 mUSt be tied to 5von the 6802NS

●*Pin 36 must be tied to around for the 6808

MOTOROLAINC., 19S1 Ds-9al&R2

●

OPERATING TEMPERATURE RANGE

Device Speed Symbol Value Unit

MC6802P, L(1.0 MHz)

MC6802CP,CL TA Oto +70

(1.0 MHz) –40to +85 ‘c

MC68A02P, L(1.5 MHz) Oto +70

MC68A02CP,CL (1.5 MHz) TA –40to +85 ‘c

MC68B02P,L (2.0 MHz) Oto +70 “?.

MC68802CP,CL (2.0 MHz) TA _@to +85 ,;$$>,g,

MC6802NSP, L(1.0 MHz) TA oto +7q~’’:i:~>,“w

MC6808P, L(1.0 MHz) ,\ .,., $;.

l;,<:$,{,.>:,..$,.,,,

MC68A08P, L(1.5 MHz) TA ot$,;~z{px Oc

MC68808P,L (2.0 MHz) ..,,.

~,~.,.,.l\:..\’

‘~s.~.,>.+’

,\,:>.,~e::$,

*+.:.t.~\\,*\?{v

.:!!;.::,“~~:

..\ ,Y.

“t~cl

.+.?.

,,,\I~$, tg ~

DC ELECTRICAL CHARACTERISTICS (Vcc= 5.o Vdc +5%, VSS =0, TA=O to 700C, unl*+&~,~?wise noted)

,:,,\ *:.~$?,.

Characteristic sy.@ol “$ r

I--, ,+u; ”h \/-l.--- Looic. EXTAL I‘:a+tJi>* Iv<<+ 2.0 I

,, ,

Logic, EXTAL, w~ ~,$~[L Vs

,,, -,., -- -- ,.. ..’:’

Min ITyp Max Unit

,t,p”, ,,,~,,v“l Lagc -wi’P%:$t Iv:; +4.0 :Vcc

Vcc v

Input Low Voltage S–0,3 –VSS+O.8 v

lnpu~ LeaKage Lurrent (Vi” =Uto 5.25 V, Vcc= max) L&Mc IIi” I–1.0 2.5 VA

uutput Hlgn voltage .....+

,!$~-,**,.:.

(iLOad= –205pA, VCC= rein] ,~<?a~h‘>’QO-D7 VSS+2.4 – –

(lLoad= –145pA, VCC= rein) AO-A~5>@l~j VMA, EvOH VSS+2.4 –.- V

(lLoad=–100PA, VCC=min) ..,,.,!-’

,+~.,

‘J)y>>,,,

,>,<3,,\\,, BA VSS+2.4 –—

,,,,,.

Output Low Voltage .(lLoad= 1.6 mA, VCC= rein} *.:$?~..-

‘.~ vOL –—VSS+O.4 v

Internal Power Dissipation (Meas!jred at TA=n“f I,,*,, D,. ,T 0.600 1,0 w

t:il .,4*

In power-down mode, maximu~~*$~issipation is less than 42 mW.

#Capacitances are periodically s&p’l@ rather than 100% tested,

.,,+~~.’.

~..~,:,,<,t~!

e!.$,~~.~\,>h

\\/::, >,,

.\,::;.e,.,$>

CONTROL TIM ING,$$@gc=<&o V+5%, VSS =0, TA= TL to TH, unless otherwise noted)

,,!.:,$,.,~~

.:,:,,,,)i ~;r’

.:\.*,,:~’ MC6B02NS,

r.:\, ,.

.>~i.,.,

.. \’\,l,.,,7J Characteristics Symbol MC6B08

,.,‘J)!*. ~..il.~

~~,i,t%>.t~~ Min Max

Frequenc$~?@eration f. 0.1 1.0

Cryst~ Fr~kncy fXTAL 1.0 4.0

cillator Frequencv 4xfo 0.4 4.0

tr~ 100 –

RE, RESET, ~~) tpcs 200 –

Processor Control Rise and Fall Time tPCr, _

(Does Not Applv to RESET) tPcf 100

MC6BA02 McmBo2

0.1 1.5 I0.1 2.0 MHz

1.0 I6.0 I1.0 8.0 IMHz

0.4 6.0 0.4 8.0 MHz

100 –100 – ms

140 –110 – ns

—100 –100 ns

II I I

@MOTOROLA Semiconductor Products

Inc.

●

FIGURE 3 – BUS TIMING TEST LOAD

4,75 v

C=130 pF for DO-D7, E

=90 PF for AO-A15, R/~, and VMA ‘estpointti~~~~

=30 pF for BA

R= I1.7 kQ for DO-D7, E

=16.5 kQ for AO-A15, RI=, and VMA

=24 k~ for BA

FIGURE 4 – TYPICAL DATA BUS OUTPUT DELAY

versus CAPACITIVE LOADING

600 [I I I

-lo H=-205@max@2.4V

10 L=l.6mAmax@0.4V

500 -VCC=5,0V

-TA =25°C

~400

F 300

~/ ‘

: 200 / ‘

// ‘

100 I

CLincludes stray capacitance

o0,

100 200 300 400 500 600

Stack

Pointer ~

Index

32 BVtes 35 VCC StandbV

—————

96 Bytes ~_ Not Available

Jon MC6808

L—— —__ _

Program

Counter L

[“7

Instruction Accumulator

Co;:jon

VCC= Pin 8

[

Data

VCC =Pin 35 for MC6802NS Buffer ALU

VSS= Pins 1, 21

Vss =Pin 36 for MCW08 $#t!#$

26 27 28 29 30 31 32 33

D7 D6 D5 D4 D3 D2 D1 DO

@MOTOROLA Semiconductor Products Inc.

... . . .. . . .. . ,, ...... ...... ,.7:..... . ,.

,,,.-y..,,>-..;,;,.-.-.;.:::.,.,-~.

;-.,-’~,;, ... .. . . .

,:. : :,. : :., ,. :,. , ,,, : .,., ., ,, .-: ,.,, .,

!,-.

,,- ,’– ‘: MPU REGISTERS

,,:, ,

Ageneral block diagram of the MC6802is shown in Figure ,read/w;te memory that may have any location (address)

6. As shown, the number and configuration of the registers that is convenient. -In those applications that require storage

are the same as for the MC68~. The 128x 8-bit ”RAM* has of information in the stack when power is lost, the stack

Juco IIU, LIIavc ui I-uuaI u

-“,,-. ..!. —,,.- -The MPU contains two 8-bit accumul~lb~~l~at are used to

PROGRAM COUNTER ‘,. ,The condition code r~~x;<$hdicates the results of an

The program c,ounter is atwo”byte (16-bit) register that’ Arithmetic Logic Unit~w#~on: Negative (N), Zero [Z),

Overflow (V), Carr&~rn%t 7(C), and Half Carry from bit 3

points to the current program address. (H). These bits ofj:&&&,Qndition Code Register are used as

testable condj$$&h~~r the conditional branch instructions.

STACK POINTER Bit 4is the ~~t~;[.y~{ mask bit (1).The unused bits of the Con-

The stack pointer is atwo byte register that contains the dition Cod$J~eg&ter (b6 and b7) are ones.

address of the next available location in an external push- Fig&@ 8mows the order of saving the microprocessor

down/pop-up stack. This stack is normally arandom access stat~$’’~~~{hinthe stack.

,wt. +

,@ ~

i>.~t*,. Ji

●If programs are not executed from on-board RAM,’ TAVI applies. If.pro~ra~%”ko be stored and executed from on-board RAM, TAV2 ap-

plies. For normal data storage in the on-board RAM,, this extended dela~wsot applv. Programs cannot be executed from on-board RAM

when using Aand Bparts (M C68A02, MC68A08, MC68B02, and MC68B&}. On-board RAM can be used for data storage with all parts.

,:.,$>

,1:::. .

>+:,,

!ji‘.yl:>

<./(. t,~.,”

-F,,,,~$ft

FIGURE7 – PROG;A@W#~DEL OF THE MICROPROCESSINGUNIT

,~ltt..,3. ~,>

*,}‘q$+s+

~F,>:$3~

.tJ3,Ny::+*b

‘..~:~ ~7

‘*Y m‘ccum”’atorA

,*:**y ,~>

~,yst<~k.b$

,. e>< m‘ccumu’a’OrB ~

“$a.?. .. n

.!.?.,,,,, .\- Ix IIndex Register

.~,:::{&F

~,+:is>.

.?l.,}$’ 15 0

*?:\\‘~.~~ ,h.:~,

~i>. ‘s~~~r’ Pc Program Counter

.\)$,., s{} .

<!, QS+:”tf:!,

4:,,,%’e 15 0.

,,,,i\.*6+,.

‘:\*. ~.$$

~~”~,~,,, SP

.+:k.ty:i-?.,,* Stack Pointer

..,.t.{~~~\.:<.

,.$ ~J’*. 7.

*t *} o

.:,:>. ?*’- ,@

~,, ‘$$ Condition Codes

.,+\l.,.,.,,

‘*)*:.>\!~\.A\.....t. Register

,3*,%,,,>(4+;.

*) ‘*:&%;i

~$:~:i{:’,) Carry (From eit 7)

Overflow

ZirO

Negative

Interrupt

Half Carry (From Bit 3)

,@”.. MOTOROLA Semiconductor Products Inc.

,’,.,, 6

“

FIGURE 8 – SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK

SP =Stack Pointer

CC= Condition Codes (Almcalled the Processor Status Byte)

ACCB =Accumulator B

ACCA =Accumulator A

IXH =Index Register, Higher Order 8❑its

IXL=Index Register, Lower Order 8Bits

PCH =Program Counter, Higher ord~~ 8~it~

PCL =Program Counter, Lower Order 8Bits m-2

m-1

m+l

m+z

m-9

m-8 B

the state of the processor. These control and timing signals,t~

are similar to those of the MC6800 except that TSC,$$~8E,

@l, @2 input, and two unused pins have been eli~!n~k~d,

and the following signal and timing lines have b~~,’~ded:

RAM Enable (RE) .f,~“~.:.:,..:“,~A‘

,,.:?,

~i.’,it?

Crystal Connections EXTAL and XTAL ~>~~i~.,#”

Memory Ready (MR) J,h>.,:.:>.*:.)

$,.1s. ~

,,,kj..,,.t.,.

*~.~,,‘~a

VCC Standby **,\

.-k,x,‘,.*>--~’

\.\ .>.,

Enable 42 Output (E) .+.,*,. ,\,~:

.>..:,,.~i,l,..,

*,=*’!. -,,;$+:

The following is asummary of~he~~PU signals:

:’J*~y:?’

ADDRESS BUS (AO-AI 5) .,~3fi+,J{;~

Sixteen pins are used ~~t’~ address bus. The outputs are

capable of driving o,~e,sta$mrd TTL load and 90 pF. These

lines do not have+~t&-yate capability.

.:,+

DATA ~“~ (&:~&

~+.y,‘$%ix

Eight piq~%qa’hsed for the data bus. It is bidirectional,

transf@~~Xta to and from the memory and peripheral

dev~~4Y~:,~~also has three-state output buffers capable of

drwln~i~ne standard TTL load and 130 pF.

~~+~~ bus will be in the output mode when the internal

~~~ is accessed and RE will be high. This prohibits external

d5ta entering the MPU. It should be noted that the internal

RAM is fully decoded from $0000 to $O07F. External RAM at

$0000 to $O07F must be disabled when internal RAM is ac-

cessed.

HALT

When this input is in the low state, all activity in the

machine will be halted. This input is level sensitive. In the

HALT mode, the machine will stop at the end of an instruc-

.,.,~,.,

Proper operation of the MPU requires that certain control .tt {}’~~ri bus available will be at ahigh state, valid memory ad-

and timing signals be provided to accomplish specific func- ~~ dress will be at alow state. The address bus will dis~lav the

:J5:,.:\i..~*\

tions and that other signal lines be monitored to determine “Rs+~’J’

‘,~:

address of the next instruction.

To ensure single instruction operation, transition of the

_line must occur tpcs before the falling edge of Eand

the HALT line must go high for one clock cycle.

HALT should be tied high if not used. This is good

engineering design practice in general and necessary to en-

sure proper operation of the part.

READ/WRITE (R/~)

This TTL-compatible output signals the peripherals and

memory devices whether the MPU is in aread (high) or write

(low) state. The normal standby state of this signal is read

(high). When the processor is halted, it will be in the read

state. This output is capable of driving one standard TTL

load and 90 pF.

VALID MEMORY ADDRESS (VMA)

This output indicates to peripheral devices that there is a

valid address on the address bus, In normal operation, this

signal should be utilized for enabling peripheral interfaces

such as the PIA and AC IA. This signal is not three-state. One

standard TTL load and 90 pF may be directly driven by this

active high signal.

BUS AVAILABLE (BA) –The bus available sianal will nor-

mally be in the low state; when activated, it ~ill go to the

high state indicating that the microprocessor has stopped

and that the address bus is available (but not in athree-state

condition). This will occur if the HALT line is in the low state

or the processor is in the WAIT state as aresult of the execu-

tion of aWAIT instruction. At such time, all three-state out-

put drivers will go to their off-state and other outputs to their

normally inactive level. The processor is removed from the

Semiconductor Products Inc.

.... ... ,...,,. ..e,.:, ~..,..

,7. ~:_ . .,

m....T,,...:.. ,:.,

,==....... ... . ,.... ,. .

..;,,

,, ~.,:,.:

’,::..,. {,,. ,:, : h. :,(: :”-!

,.,,.:,.,,,i, ,::,.i ,+~, ,.: ,,,,,. .; .,.; ,::.,:.,‘:’ ‘:. ,,.,-: -,. . . . ,: ,“”” :.

~‘, ‘., .,.. ,.,

●:O ●:0: ●:$

,., .:, :. .’,;

., .;,: -.- ....’

,,, , .. -., ,.

,,.

WAIT ‘state by the occurrence of a‘m’askable (rnask.bitl =“0) ‘“tion of aroutine to initialize’the processor from its reset con-

or nonmaskable interrupt. This output is capable of. dtiving” ,’ dition.’All”the higher order address lines will be forced high.

one standard TTL” load and 30 pF. ‘For the restart, the last two ($FFFE, $FFFF) locations in

.. .. memory will, be. used to load the program that is addressed

INTERRUPT REQUEST (~Q) ;‘: ,;’ f‘“ ,‘”: by the program counter. During the restart routine, the inter-

Alow level on this input requests ‘that an interrupt se- rupt mask bit is set and must be reset before the MPU can be

quence be ‘generated within the machine. The processor will ~interrupted by ~Q. Power-up. and reset timing and power-

down sequences are shown in Figures 9 and 10, respectiv~y,

wait until it completes the current instruction ttiat is being .,

excuted before it recognizes the request. At that time, if the ,,RESET, when brought low, must be held low at least ~*,:

interrupt mask bit in the’ condition code register is not: set; clock cycles, This allows adequate time to respond @~[E@%y

the machine will begin an interrupt sequence. The index :.- to the reset. This is independent of the trc p~,~’a/~&set

~$~?>“’.*,?

code register are stored away on the stack. Next the MPU >+,‘.+&b@..~J

When RESET is released it must go t~:,~hk%e low-to-

“will respond to. the interrupt. request by setting the interrupt high threshold without bouncing, osc~J%\~~#~r otherwise

mask bit high so that no further interrupts may occur. At the causing an erroneous reset (less tha~\Jh&e” clock cycles).

end of the cycle, a16-bit’vectoring address which is’located This may cause improper MPU op&~~tio~.&ntil the next valid

in memory locations $FFF8’ and $FFF9 is loaded which reset. .Ji~.*>%,,,!

causes the MPU to branch to an interrupt routine in memory.. “.%~<$~$s

‘+;,”’’:k{,tt:$t;t

The HALT line must be in the high “state for interrupts to NON-MASKABLE lNTERR,@3@~@)

be serviced. Interrupts will be latched internally while HALT

—Alow-going edge q~~~~~wput requests that anon-

is low. ,,, , ::. maskable’ interrupt sequ~$~ be generated within the pro-

Anominal 3k~ pull up resistor to ,VCC should be used for cessor. As with tw]’%terrupt request signal, the processor

wire-OR and optimum control of interrupts: ~Q may be tied ,*.K.,*?:C*I..:...

will complete t~~~,mretit Instruction that is being executed

directly to VCC if not used. .,. before it rec~~~:e~the NM Isig’nal. The interrupt mask bit in

the condi~~~jcb~ register has no effect on ~.

RESET ,’ ,.. The ,J?de%$egister, program counter, accumulators, and

This input is used to reset and start theMPU from aconti$?~~:code registers are stored away on the stack. At the

power-down condition,. ,resulting from apower’ failure or ,ap ‘“< .tR# cycle, a16-bit vectoting address which is located

:p ~$+

initial start-up of the processor. When _thisline is’ low, the .,,,~;~g@ory locations $FFFC and $FFFD is loaded causing the

MPU is inactive and the information ‘in theregisters will be *~J&~~~ to branch to an interrupt service routine in memory,

lost. If ahigh level is detected on the. input, this will signal ~Anominal 3k~ pullup resistor to VCC should be used for

the MPU to begin the restart sequence. This will start exec~<~~> ‘“$s, wire-OR and optimum control of interrupts. ml may be tied

“*.:$*$,

.,:’ ~..:,$,,

$;h

~FIGURE ‘9 –l~Q\~~iyUP AND RESET TIMING”

4.75 v

.,’

,,.

,“

tr~ +

RESET

:,*$!) Option 1

,., ,’ (See Note 8elow)

.Option 2

~,. (See Figure 10 for

,. Power-down Condition)

NOTE: If option 1is chosen, ~and RE pins can be tied together.

,. ,,,

@~~

MOTOHO~~ Semiconductor Pioducts /nc.

,. ...,, .,. ,

,’,

,;,,

;

.,>., .,. ,8.

directly to VCC if not used, FIGURE 10 – POWER-DOWN SEQUENCE

Inputs ~Q and ~are hardware interrupt lines that are

sampled when Eis high and will start the interrupt routine on

alow Efollowing the completion of an instruction.

Figure 11 is aflowchart describing the major decision

paths and interrupt vectors of the microprocessor, Table 1‘CC7

gives the memory map for interrupt vectors, I

TABLE 1 – MEMORY MAP FOR

INTERRUPT VECTORS

Vector

6AcIlc Description Itpcft:Hiw

,“, ”IL- I

$FFFE $FFFF Rests rt

$FFFC I$FFFD Non-Maskable Interrupt

$FFFA $FFFB Software lnterru Dt

,,.

$FFF8 I$FFF9 Interrupt Request

Fetch Instruction Execute

Interrupt Routine

I I

4+v

Execute *

Instruction NMI ~Q

$FFFC $FFF8

$FFFD $FFF9

[7+*

@MO~OROLA Semiconductor Products Inc.

●

FIGURE 14 – MEMORY READY SYNCHRONIWTION

4xfo

Oscillator

EXTA

XTA’

MC6802

The Eclock will resume normal operation at the end of the kcycle during which MR assertion meets the tpcs setup time. The tpcs setup time

is referenced to transitions of Ewere it not stretched, If tpcs setup time is not met, Ewill fall at the second possible transition time after MR is

asserted. There is no direct means of determining when the tpcs references occur, unless the synchronizing circuit of Figure 14 is used.

mMOTOROLA Semiconductor Products Inc.

The instruction set has 72 different instructions. Included

are binary and decimal arithmetic, logical, shift, rotate, load,

itional or unconditional branch, interrupt and

~lation instructions (Tables 2through 6). The in-

*—

@teaddressing,’ the operand is contained in the

of the instruction except LDS and LDX which

erand in the second’ and third bytes of the in-

~e MPU addresses this location when it fetches

Ite instruction for execution. These are two- or

lstructions.

~’::~

~..i.i’:+?;,

,.,~’*$:*\ DIRECT ADDRESSING

l~,s:~t- ‘~’ In direct addressing, the address of the operand is Contain-

ed in the second byte of the instruction. Direct addressing

allows the user to directly address the lowest 256 bytes in the

!., locations-zero through 255. Enhanced execu-

“eachieved by storing data in these locations. In

ost configurations, it should be a random-access memory,

jtructions.

;ING

In extended addressing, the address contained in the se-

:the instruction is used as the higher eight bits of

This pin supplies the@~$k fo~h- ..... ---------------- of the operand. The third byte of the instruction

system. This is asing~~~~$%, TTL-cornpatible clock, TI elower eight bits of the address for the operand,

clock may be con~~w$d,by,a me,,. -,, ____ -.=,, -,. ,,.- ~is is an absolute address in memory. These are three-byte

equivalent to 42/~~~~QeM,C6800. This output is capable of ‘instructions.

driving one st&$SM. ~TL load anc

**:a~’*:&,l ,‘DDRESSING

~addressing, the address contained in the se-

fthe instruction is added to the index register’s

,. Thus, :lowest &ght bits in the MPU. The carry is then added to the

tier-up; higher order eight bits of the index register, This result is

3ximum. then used to address memory, The modified address is held

irv address resister so there is no change to the

current drain at VSB maximum ii

this pin must be connected to VC

Semiconductor Products Inc. —

●

IMPLIED ADDRESSING

In the implied addressing mode, the instruction gives the

address (i. e., stack pointer, index register, etc.). These are

one-byte instructions.

RELATIVE ADDRESSING

In relative addressing, the address contained in the second

byte of the instruction is added to the program counter’s

lowest eight bits plus two, The carry or borrow is then added

to the high eight bits. This allows the user to address data

within arange of – 125 to +129 bytes of the present instruc-

tion. These are two-byte instructions.

ABA

ADC

ADD

AND

ASL

ASR

BCC

Bcs

BEQ

BGE

BGT

BHI

BIT

BLE

BLS

BLT

BMI

BNE

BPL

BRA

BSR

BVC

BVS

CBA

CLC

CLI

Add Accumulators

Add with Car~

Add

Logical And

Arithmeti Shti Left

Arithmeti Shift Right

Branch if Car~ Clear

Branch if Carry Set

Branch if Equal to Zero

Branch if Greater or Equa zero

Branch if Greater than zero

CLR

CLV

CMP

COM

CPX

DAA

DEC

DES

DEX

EOR

Clear

Clear Overflow

Compare

Complement

Compare Index Register

Decimal Adjust

Decrement

Decrement Stack Pointer

Decrement index Register

Exclusive OR

Branch if Higher INC Increment .,,\ ~!i$t,

STA

Bit Test INS ,,”%...

Increment Stack Poi,ntBP~~.. STS

Branch if Lessor Equal INX increment Index ~’g~~ “w

Branch if Lower or Same ‘,

Branch if Less than Zero JMP Jump “.?.,..,

~‘$.::~,:N*.

Branch if Minus JSR Jump to suti@*\\.\\

Branch if Not ‘Equ4 to Zero LDA Load Accu~labr

Branch if Pfus LDS Loa~~@tackpointer

Bramh Always LDX Lq@]~ex Register

Branch to Subroutine LSR

Bramh if Overflow Clear ,~~~,d Shift Right

.~ft\.,~!,,,,~..

Branch if Overflow Set NEG ~,.s~x,~~a~e

NO~%,&*+& Operation

Compare Accumulators !$+.$)~J....>....

Clear Carrv ~QJ~t’t;?.’YInclusive OR Accumulator

MOTOROLA Semiconductor

STX

SUB

Swl

TAB

TAP

TBA

TPA

TST

TSX

Txs

WAI

Set Interrupt Mask

Set Overflow

Store Accumulator

Store Stack Register

Store Index Register

Subtract

Software Interrupt

Transfer Accumulators

Transfer Accumulators to Condition Code Reg.

Transfer Accumulators

Transfer Condition C&e Reg. toAccumulator

Test

Transfer Stack Pointer to Index Register

Transfer Itiex Register to Stack Pointer

Wait for Interrupt

Products \nc.

,. .. . . .. ...... ,:.:...

-.--7:7 T_... r;-7:7

T_. . .-, ----- . . . . . . . . . . . . ,.. .:_ . . . . ..-, ,. , . . . . . . .- ;. . . .... . .. ..

;,,,,.:,.; ,,... .

:.,,,.;.’ ‘...!. .,”,

,., {., :,

,, -, ..7,-.. ,,, .,”., ,

.,.,: ,.

TABLE 3- ACCUMULATOR AND MEMORY INSTRUCTIONS

,.. ,

,{, ,.

,, ADO RESSINGMOOE5” BOOLEAN/lRITHMETIC OPERATION CONO. COOEREG

,,”- IMMEO “OIRECT INOEX EXTNO’ IMPLIEO (All register labels 543210

OPERATIONS MNEMONIC OP== .OP. =Op-= Op, .=OP-= refer tO contentsl HINzvc

Add AODA 8B 2 2 9B32 AB 5 2 BB -4 3 A+ M-A

AODB, !●ttJI

C8 2‘2 OB32 EB52 FB’ 4 3 B+ M--B

Add Acmltrs t●t1t1

ABA IB21

Addw!lh Carry AOCA A+ B-A t●J1f f

8922 9932 A952 B943 A+ M+ C-A .

AOCB’ t●tIt1

C9 2 2 0932 E9 .5 zF943 B+ M+ C--B

A“d ANDA t●t$tj

84 2 2 .9J 3. 2A4 52B443 A.M:A ● ● t t R.

ANDB C4 220432 E4 52F443

Bit Test B. M.. B●. t t R.

BITA ,B5 22 9532 A552 B5q3 AM ● ● ttR.

81TB C5,2 2 0532 E5 52F543

Clear CLR EM

6F 7 2 7F, 6 3 ●. t t R’ ‘&<

004M

CLR,A ● ● R.+?~., .~,

4F21 00-. A

CLRB ~,“ ● ● \& .RS)’* *

Compare 5F21 00- B

CMPA ●e* >R*is a: 8

B122 9132 Al’ 5 2 B143 A-M ●,*3 p~t$

CMPB C122 D1 3, 2E152 Flq3 B-M ,$$)$ )$,, .$: .? tj

“7,\ .

Co,npare Acmltrs CBA 1121 A-B

Complement, 1’s dt1t1

COM 6372 1363 M-M .<-<,,.,,,

$:,

COMA ‘N; ,* I f Rs

43 2, 1fi-A >\:$,>~$;,

COMB ‘● ● t1Rs

5321 *$:’*: :!~~+ . . , ~Rs

~4B ‘!,.

Complement, 2’s NEG ~k,;.t>i}<tt

6072 7063

(Negate) 00 -M-M ,>\+., xi ..:,1,, ● ● rt@ @

NEGA ,’ 4021 ~.,:!:r~,,...>

00 -A-A

NEGB ..,~t,!$$~’ ,i~ ● ● t t @ @

Oecimal Adjust, A5021 00 -B-.6 ,‘a$>k’$;iw:~ ● ● t t @ @

OAA ,1921 Converts Binarv$~~ti:~&O Characters ● ● [ t I @

Oecrement into BCD ~grmat “’>*F

OEC 6A72 7A ‘6 3“,’.+..h

M-I,,,*M b● ● t t 4●

DECK .}. .t/.t,:>?<~\*.s

4A21 A+>1, ‘+;), ● ● {1 4 ●

OECB

Exclusi”e OR EORA 5A21 #?’l**B’* ●*[ ! 4●

BB22 9632 A852 BB43 .~y WM 3A ● ● t t R●

EORB C8 2.2 DB32 EB”5 2F843 &, ,:.B@#: B● ● tiR.

Incremel,t INC 6C72 7C63 “P{ ~M+ l-M ●. t 1@.

INCA ‘“ 4&:@’%2 1:A+I-. A

INCB 29’6 3 2 A; 5 2 B6 ,4 #,:?~ ‘

● ● t1@.

6+1-B

Load Acmltr LOAA. ● ● tr@.

B6 2~~+~>

,. ~“%.. M--A ● ● t1R.

LOAB C6 2 2 0632 E652 F64$ :.’ M-B

Or, Inclusi”e ORAA 8A 2● ● 1tR.

29A32 AA 52BA ~~~ .,:+$

s.)! i’!. A+ M-A

ORAB CA 2● ● ]rR.

20A32 EA52 F#/.>Lf,,;:+~; 6+ M-. B●9t I R.

Push Onta PSHA *&’ 4+,

.’,.,ia>:, 3641 A‘- MsP, SP -1 --SP

PSHB ● ● ● . . .

.31 “4 IB-. Msp, SP-l .SP

Pull Data PULA ,’ ,’ ,i;#> 9 9 ● ● ● ●

~., 3241

PULB SP+l--SP, MSP-A ● ● . . . .

,.{#$:$

Rotare Left ROL q; tt~$ 7963 334’ ~+1 -. SP, Msp -8 ●. . . . .

ROLA *lb “’’’’”J

● ● ] t @t

‘flOLB *+, ~;}..\. }%. 4921 A-

~.’tt-.~~’ ●*t t @I

,’ ,.:. t?:, 5921 Bc

RoIste Right b7 -bO

ROR ●*t t @t

.i$/“*4. W72 7683

RORA

}b “’’’’:’4

M~~ ●. t t @\

~{’,+~ws+~~~>.

-~ ~>, c46 2’ 1A

~:$;~}, %:3::>.: ~~ . . 1 1 @i

RORB C-b7 —bO

Shalt Left, Arilhme;tc .‘v&!. 56 2 1 B

ASL ,,, -.>$y$k”~ . . j:@1

.)”!.?+ 68’ 72 7863 M

ASLA 1-.. ~-

. . 1 1 @I

w.{.)i *+.:t. r4B21 A

ASLB ❑-~- o

~t:.,t .. ● ● t t @I

5821 B

Shalt Right, Arlthmet!c ASR ~F** ‘~~%kiv $’ ● ● 1\@t

6/72 77 6!3

ASRA .

}

:&o-;

9●1t@j

~~:, “:$ ~721 **t1 6 f

,+p ~**% b,

ASRB ,.\y .,. .%4..,$,*V 5721 Bb7

Shalt flight, log!c ●*t t @1

LS~$ ,:$* 6472 7463 M

,.&bq&?i& t.

}

● ● R1@~

4421 Ao-~ -0

‘$*{:? ● ● R[6]

5421 Bb7 bO C

Slore Aclnllr. >..> .$- e●Rt@t

9742 A762 B7.5 3

,*k\. STAB A.. M

07 q ● ● tiR.

.}*.t+,*$’$’~ ,, 2E7 6 2 F753

Subtract BM. . t \ R.

>+*. ,,& su~A

.~,*::&y BO 22 90 3, 2A052 BOq3

~.s. AM-A

C022 003’2 E052 F043 ● ● 1trt

sub,,, cl A&;l;~%@* ~By B- M-B ● ● ] [ ] t

,!.. -q.,.. 1021 A-B. A

Subtr. w~\~8q\k SBCA 82 2 . . 1[\t

2 9232 A2 52 8243 A–M– C.A . . ] [ ] I

?:<, ,,.\:.:\:*> SBCB C2 2

“>’’~cml$fs 2 02 3 2E2 52F2q3 B- M-C-.8

,t~sw$fe%:,, TAB ..!II1

1621 A--B ..t1R.

<. .. TBA

,<.~v ~~~$l:~~ro or Minus 1721 8 .A ..\1R.

TST .“ 60 7 2 7063

,:$y .... TSTA M-OO .. [1R R

!.>,,..

\., ,:~:.~.,:<*<t,4021

TSTB A-00 ● ● itR R

..p,;,.

,,,,,.:,,.<.~x\ 5021 B-00 ●. t 1R R

t~,$~ii

,,N.:** .,. ~

;(t::.: .$$ H1Nz v c

!~~. LEGENO: CO NOITION COOE SVMBOLS

OP Operalton Code (Hexadecimal); ,+ Boolean Inclusive OR;

.Number of MPU CVcles; @Boolean Excl”si.e OR; HHalf.c~rri from b,t 3;

Nu!nber of Program Bvtes; uComplement 01 M; IInterrupt mask

+Arithmetic Plus: Transfer Into; NNegative (tign bitl

Arithmetic Minus: oBlt=Zero; zZero (bvte)

Boolea!l ANO; 00 Byte =Zero; vOwedlow, 2’s complement

Msp Conlents of memorv Iocatlon pointed to be Slack Pointer: cCarrv from bit 7

RReset Alwavs

Note -Accumulator addressing mode instructions are included 10the column for IMPLIED addressing sSe! Alwavs

1Test and se! if true, cleared otherwise

●Not Affected

@MOTOROLA Semiconductor Products Inc.

~, 14

TABLE 4 – INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS

CO ND. COO EREG,

IMMEO IOlEl

—

Ifi

—

Lll

—

151413/21110

—

—I

39C

3OE

39E

BOOLEAN/ARITHMETIC OPERATION H] II NIZIVIC

MNEMONIC

CPX

DEX

OES

INX

INS

LOX

LOS

STX

STS

TXS

TSX

POINTER OPERATIONS

Compare Index ttag

Oecrement Index Reg

Oecrement Stack Pntr

Increment Index Reg

Increment Stack Pntr

Load Index Reg

Load Slack Pnlr

Store Index Reg

StoreStackPntr

Indx Reg -Stack Pntr

Stack Pntr -Indx Reg

[G.

—

(

●

—

●

RELATIVE INOEX EXTNO -IE

—

\,,

-\*.

—

BRA

8CC

BCS

BEO

BGE

BGT

BHI

BLE

BLS

BLT

BMI

BNE

8VC

BVS

BPL

BSR

JMP

JSR

NOP

C=o

C=l

Z=l

N@V=O

Z+(N@V)=O

C+z=o

Z+(N@V)=l

C+z=l

N@V=l

N=l

Z=o

V=o

V=l

N=o

}See Special Operations

(Figure 16)

Advances Prog. Cntr. Only —

}See Special Uperallons

(Figure 16)

@Semiconductor Products Inc. -

●

TABLE 7 – INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES

(Times in Mechine Cycle)

ABA

ADC

ADD

AND

ASL

ASR

BCC

BCS

BEA

BGE

BGT

BHI

BIT

BLE

BLS

BLT

BMI

BNE

BPL

BRA

BSR

BVC

BVS

CBA

CLC

CLI

CLR

CLV

CM P

COM

CPX

DAA

DEC

DES

DEX

EOR

NOTE

●☛☛☛ 2.

X* 234 tee

X* 2345e.

Xe 2345. .

2..67..

2..67.,

O**eee 4

****** 4

●a***. 4

●****e 4

●*oa*e 4

000 00 4

x- 23 :5*.

●.**.. 4

●*@*.* 4

●ee **@ 4

**seem 4

*****e 4

*****9 4

●***e* 4

●ma **e 6

INC

●e*9 10

***O 5

●eee 2

2345.

eeee 2

9*Q* 2

*oBe 2

e456.

0 567e

0567.

2345

eee, 192

..ee 2

baee 2

Oeoe 2

.0.8 2

ne 67.

00oe 4

●eee 4

**O* 9

@MOTOROLA Semiconductor Products Inc.

●

TABLE 8 – OPERATIONS SUMMARY (CONCLUDED)

Address Mode Cycle VMA R/fl

and instructions Cycles #Line Line Data Bus

INHERENT (Continued)

WA I1

Swl

Address Bus

Op Code Address

Op Code Address+ 1

Stack Pointer

Stack Pointer – 1

Stack Pointer – 2

Stack Pointer – 3

Stack Pointer – 4

Stack Pointer – 5

Stack Pointer – 6

Op Code Address

Op Code Address+ 1

Stack Pointer

Stack Pointer t1

Stack Pointer t2

Stack Pointer t3

Stack Pointer +4

Sta~k Poster – 2

~’a~iPointer – 3

~$~~k Pointer —4

%tack Pointer – 5

Stack Pointer – 6

Stack Pointer – 7

Vector Address FFFA (Hex)

Vector Address FFFB (Hax)

Op Code Address

Op Code Address +1

Op Code Address +2

Branch Address

Op Code Address

Op Code Address t1

Return Address of Main Program

Stack Pointer

Stack Pointer – 1

Stack Pointer – 2

Return Address of Main Program

Subroutine Address (Note 4)

Op Code

Op Code of Naxt Instruction

Return Address (Low Order Byte)

Return Address (High Order Byte)

Index Register {Low Order Byte)

Index Register (High Order B~~e)

.J,>... ‘~~\:.

Contents of AccumulatorJ~~~R>

Contants of Accumula4&r&~~ “::”

.,y Ji\

Contents of Con~~,.$~~W/gister

Op Code :s .Jl::*\&,\.1

~+,i,:t,~+,,*

~~ntents of Accumulator Afrom Stack

~~t~ Register from Stack (High Order

Index Register from Stack (Low Order

BVte)

Next Instruction Address from Stack

(High Order Byte)

Next Instruction Address from Stack

(Low Order Bvte)

Op Code

Irrelevant Data (Note 1)

Return Address (Low Order BVte)

Return Address (High Order .Bvte)

Index Registar (Low Order BVte)

Index Register (High Order Byte)

Contents of Accumulator A

Cqntents of Accumulator B

Contents of Cond. Code Register

Irrelevant Data (Note 1)

Address of Subroutine (High Order

BVte)

Address of Subroutine (Low Order

Bvte}

Op Code

Branch Offset

Irrelevant Data (Note 1)

Op Coda

Branch Offset

Irrelevant Data (Note 1)

Return Address (Low Order BVte)

Return Address (High Order Byte)

Irrelevant Data (Note 1)

OTES:

1. If device which is addressed during this cvcle uses VMA, then the Data Bus will go to the high-impedance three-state condition.

Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.

2. Data is ignored by the MPU.

3, For TST, VMA=O and Operand data does not change.

4. MS Byte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address.

~@ MOTOROLA Semiconductor Products Inc.

ORDERING INFORMATION

11 d+’ ,.;:;,,,“s

‘n :

DIM MIN MAX MIN MAX

A50,29 5!.31 1,980 2.020

J!uilllllllll II lli JU--~.Jjp’~:+”’ -; l% 1:: ~f:: ~;~ NOTES:

HdLD ‘EAT’NGPLAN:JL

.;~:&~’M+ ~: Rtti p~: fi:

1. LEAOS, TRUE POSITIONED WITHIN O.25mm

10.O1O)OIA (AT SEATING PLANE), AT MAX

MA~L CONOITION.

,. ,:.:,,.‘::.:{:,), G

“s?; 2.5ASSC O.lw Bsc

..l?l,>-2. OIMENSION “~ TO CENTER OF LEAOS

H0.76 1.78 O.mo 0.070

~~Yt. ~WHEN FORMEO PARALLEL.

‘*,>1:>>.,

~?$ J0.20 0.33 0.008 0.01s

,,$,,1:..~~~..$,,.h,?.~~’

..; K2.54 4,19 0.100 0.165

.99 15.49 0.590 0.610

‘t.’; q

*.,4.$?*,.~tj!i$? Ml- )00 -j~

..*.t..

~.\* N1,02 1,52 0.040 O.mo

pL4yi{{AG

V&A -----–----ic~-L’-q

$,,

.’, ,:.

“..:.. ~.;.

,.~ ~\Lt, ,, ,L -\ ::j(a~l ‘; :!;‘~;~‘$~ NOTES:

l~.:,~* ~G~ ~-F D\“~~.M

1. POSITIONAL TOLERANCE OF LEADS (0),

c3.94 5.08 0.155 0.200 SHALL BE WITHIN 0.25 mm(0.010) AT

‘f.*“SEfiT!NG o0.36 ~0.014 0.022 MAXIMUM MATERIAL CONOITION, IN

PLANE F1.02 1.52 0.040 0.060 RELATION TO SEATING PLANE ANO

~i~. G2.s Bsc 0.100BSC EACH OTHER.

H1,65 2.16 0.065 i0.085 2. OIMENSION LTO CENTER OF LEAOS

J0,20 0.36 0.00B I0.015 -WHEN FORMEO PARALLEL.

K2.92 3.43 0.1151 0.135 -3. OIMENSION BOOES NOT INCLUOE

L15,246SC 0.600 BSC MOLO FLASH.

M00 159 OQ 150

N0.51 I1,02 0.020 I0.040

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume anv Iiabilitvarising

out of the application or uae of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

@MOTOROLA Semiconductor Producfs Inc.

3501 ED BLUESTEIN BLVD., AUSTIN, THAS 78721 ●ASUBSIDIARY OF MOTOROLA INC. —