QS74LCX2H540, 2H541
MDSL-00178-02 QUALITY SEMICONDUCTOR, INC. 1
FEBRUARY 10, 1998
Now an Company
Y0(18)A0(2)
Y1(17)A1(3)
Y2(16)A2(4)
Y3(15)A3(5)
OE1
OE2
Y4(14)A4(6)
Y5(13)A5(7)
Y6(12)A6(8)
Y7(11)A7(9)
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
Y0(18)A0(2)
Y1(17)A1(3)
Y2(16)A2(4)
Y3(15)A3(5)
OE1
OE2
Y4(14)A4(6)
Y5(13)A5(7)
Y6(12)A6(8)
Y7(11)A7(9)
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
25Ω
LCX2H540
FEATURES/BENEFITS
• 5V tolerant inputs and outputs
• Bus Hold feature holds last active state during
3-state operation
•25Ω series resistor for low switching noise
•10µA ICCQ quiescent power supply current
• Hot insertable
• 2.0V-3.6V VCC supply operation
•±12mA balanced output drive
• Power down high impedance inputs and outputs
• Meets or exceeds JEDEC 36 specifications
•t
PD = 6.5ns
• Input hysteresis for noise immunity
• Operating temperature range:
–40°C to 85°C
• Latch-up performance exceeds 400mA
• ESD performance:
Human body model > 2000V
Machine model > 200V
• Packages available:
20-pin QSOP, 20-pin SOIC
LCX2H541
DESCRIPTION
The LCX2H540 and LCX2H541 are 8-bit buffers/
line drivers with three-state outputs that are ideal for
driving high capacitance loads such as memory
address and data buses. The 3.3V LCXPlus family
features low power, low switching noise, and fast
switching speeds for low power portable applica-
tions as well as high-end, advanced workstation
applications. 5V tolerant inputs and outputs allow
these LCXPlus products to be used in mixed 5V and
3.3V applications. The LCX2H540 and LCX2H541
with integrated output resistor are ideally suited for
low noise environments where reduced ouput over-
shoot and undershoot are critical requirements.
Active Bus Hold feature retains the last valid logic
state at unused or floating inputs, thus eliminating
the need for external pull-up resistors. To accomodate
hot-plug or live insertion applications, these prod-
ucts are designed not to load an active bus when
VCC is removed.
Figure 1. Functional Block Diagram
High-Speed 3.3V
CMOS 8-Bit
Buffer/Line Driver with
Bus Hold and Output Resistor
QS74LCX2H540
QS74LCX2H541
Q
Q
UALITY
S
EMICONDUCTOR,
I
NC.
Q
QS74LCX2H540, 2H541
2QUALITY SEMICONDUCTOR, INC. MDSL-00178-02
FEBRUARY 10, 1998
Now an Company
2H540 2H541
OE1OE1
OE1OE1
OE1 OE2OE2
OE2OE2
OE2 Input A Output Y Output Y Function
H X X Hi-Z Hi-Z Disable Outputs
X H X Hi-Z Hi-Z
L L L H L Enable Outputs
LLH L H
Figure 2. Pin Configurations
(All Pins Top View)
SOIC, QSOP
Table 1. Pin Description
Name I/O Description
A7-A0 I Data Inputs (Bus Hold Inputs)
Y7-Y0 O Data Outputs
OE1, OE2 I Three-State Output Enable
Table 2. Function Table
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
V
CC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
QS74LCX2H540, 2H541
MDSL-00178-02 QUALITY SEMICONDUCTOR, INC. 3
FEBRUARY 10, 1998
Now an Company
Note: Stresses greater than
those listed under ABSOLUTE
MAXIMUM RATINGS may
cause permanent damage to
QSI devices that result in func-
tional or reliability type failures.
Table 5. Recommended Operating Conditions
Table 4. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VCC Supply Voltage, Operating 2.0 3.6 V
Suppply Voltage, Data Retention Only 1.5 3.6
VIN Input Voltage 0 5.5 V
VOUT Output Voltage in Active State 0 VCC V
VOUT Output Voltage in "OFF" State 0 5.5 V
IOH/IOL Output Current VCC = 3.0 – 3.6V — ±12 mA
VCC = 2.7V — ±6
∆t/∆v Input Transition Slew Rate — 10 ns/V
TAOperating Free Air Temperature –40 85 °C
Supply Voltage to Ground................................................. –0.5V to 7.0V
DC Output Voltage VOUT
Outputs HIGH-Z.............................................................. –0.5V to 7.0V
Outputs Active ......................................................–0.5V to VCC + 0.5V
DC Input Voltage VIN.........................................................–0.5V to 7.0V
DC Input Diode Current with VIN < 0 ........................................... –50mA
DC Output Diode Current
VO < 0....................................................................................... –50mA
VO > VCC .................................................................................... 50mA
DC Output Source/Sink Current (IOH/IOL) ..................................... ±50mA
DC Supply Current per Supply Pin ........................................... ±100mA
DC Ground Current per Ground Pin ......................................... ±100mA
TSTG Storage Temperature.............................................–65°C to 150°C
Symbol Pins Typ Unit Conditions
CIN Input Capacitance 7.0 pF VIN = 0V, VOUT = 0V, f = 1MHz
CI/O I/O Capacitance 8.0 pF VIN = 0V, VOUT = 0V, f = 1MHz
CPD Power Dissipation 20 pF VCC = 3.3V, VIN = 0V, or VCC
Capacitance f = 10MHz
Note: Capacitance is characterized but not production tested.
Table 3. Capacitance
QS74LCX2H540, 2H541
4QUALITY SEMICONDUCTOR, INC. MDSL-00178-02
FEBRUARY 10, 1998
Now an Company
Table 6. DC Electrical Characteristics Over Operating Range
Industrial Temperature Range, TA = –40°C to 85°C.
Symbol Parameter Test Conditions(1) Min Typ(2) Max Unit
VIH Input HIGH Voltage Logic HIGH for All Inputs 2.0 — — V
VIL Input LOW Voltage Logic LOW for All Inputs — — 0.8 V
VOH Output HIGH Voltage VCC = 2.7V, IOH = –100µA VCC– 0.2 — — V
VCC = 3.0V, IOH = –12mA 2.4 — —
VCC = 3.0V, IOH = –18mA 2.2 — —
VOL Output LOW Voltage VCC = 2.7V, IOL = 100µA — — 0.2 V
VCC = 3.0V, IOL = 12mA — — 0.55
VCC = 3.0V, IOL = 18mA — — 0.8
∆VTInput Hysteresis(3) VTLH – VTHL for All Inputs — 150 — mV
| IOZ | Off-State Output VCC = 3.6V, VO = 0V, — — 1.0 µA
Current (Hi-Z) VO = 5.5V
IOS Short Circuit Current(3,4) VCC = 3.6V, V OUT = G N D –60 — –200 mA
IOR Current Drive(3) VCC = 3.6V, VOUT = 2.0V 40 — — mA
VIK Input Clamp Voltage VCC = 2.7V, IIN = –18mA — –0.7 –1.2 V
IIInput Leakage Current VI = 0V, VI = 5.5V, — — ±1.0 µA
VCC = 3.6V
ROUT Output Resistance VCC = 3.0V, IOL = 12mA — 28 — Ω
| IBH | Input Current VCC = 3.6V, VIN = 0V or — — 50 µA
Input HIGH or LOW VIN = VCC
Bus Hold Inputs(3,5) VCC = 3.6V, 0.8 < VIN < 2.0V — — 500(6) µA
IBHH Bus Hold Sustaining VCC = 3.0V VIN = 2.0V –75 — — µA
Current
IBHL Bus Hold Inputs VIN = 0.8V 75 — — µA
IOFF Power Off Leakage VCC = 0V, VI or VO = 5.5V — — 10 µA
Notes:
1. For conditions shown as Min. or Max. use appropriate value specified under Recommended Operating Conditions
for the applicable device type.
2. Typical values are at VCC = 3.3V and TA = 25°C.
3. These parameters are guaranteed by characterization, but not production tested.
4. Not more than one output should be tested at one time. Duration of test should not exceed one second.
5. Pins with Bus Hold are identified in the Pin Description.
6. An external driver must provide at least | IBH | during transition to guarantee that the Bus Hold input will
change state.
QS74LCX2H540, 2H541
MDSL-00178-02 QUALITY SEMICONDUCTOR, INC. 5
FEBRUARY 10, 1998
Now an Company
VCC TA = 25°C
Symbol Parameter Conditions (V) Typical Units
VOLP Quiet Output Dynamic Peak VOL CL = 30pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V
VOLV Quiet Output Dynamic Valley VOL CL = 30pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V
Table 8. Dynamic Switching Characteristics(1)
Note:
1. Characterized but not production tested.
Symbol Parameter Test Conditions(1) Typ(2) Max Unit
ICC Quiescent Power VCC = Max., Freq = 0 0.1 10 µA
Supply Current VIN = GND or VCC
∆ICC Supply Current per VCC = Max. Control Inputs 2.0 30 µA
Input @ TTL HIGH(3) VIN = VCC–0.6V, Freq = 0 Bus Hold Inputs — 500 µA
ICCD Supply Current per VCC = Max., Outputs Open 50 75 µA/
Input per MHz(4) One Bit Toggling @ 50% Duty Cycle MHz
OEx = GND
ICTotal Power VCC = Max., Outputs Open VIN = VCC–0.6V 0.5(5) 1.0(5) mA
Supply Current(6) One Bit Toggling VIN = GND
@ 50% Duty Cycle
OEx = GND, f = 10MHz
VCC = Max., Outputs Open VIN = VCC–0.6V 1.0(5) 3.5(5) mA
Sixteen Bits Toggling VIN = GND
@ 50% Duty Cycle
OEx = GND, f = 2.5MHz
Notes:
1. For conditions shown as Min. or Max., use the appropriate values specified under Recommended Operating Conditions
for applicable device type.
2. Typical values are at VCC = 3.3V, 25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in total power supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed by design but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC.
IC = ICCQ + ∆ICC DHNT + ICCD fNO.
ICCQ = Quiescent Current (ICCL, ICCH, and ICCZ).
∆ICC = Power Supply Current for a TTL-High Input (VIN = VCC-0.6V).
DH = Duty Cycle for TTL High Inputs.
NT = Number of TTL High Inputs.
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL).
f = Average Switching Frequency per Output.
NO = Number of Outputs Switching.
Table 7. Power Supply Characteristics
QS74LCX2H540, 2H541
6QUALITY SEMICONDUCTOR, INC. MDSL-00178-02
FEBRUARY 10, 1998
Now an Company
VCC = 3.3 ±0.3V VCC = 2.7V(2)
Symbol Description(1) Min Max Min Max Unit
tPHL Propagation Delay 1.5 6.5 1.5 7.5 ns
tPLH Ai to Yi
tPZH Output Enable Time 1.5 8.5 1.5 9.5 ns
tPZL OEx to Yi
tPHZ Output Disable Time(2) 1.5 7.5 1.5 8.5 ns
tPLZ OEx to Yi
tSK(O) Output Skew(3) — 0.5 — — ns
Table 9. Switching Characteristics Over Operating Range
Industrial Temperature Range, TA = –40°C to 85°C.
CLOAD = 30pF, RLOAD = 500Ω unless otherwise noted.
Notes:
1. Minimums guaranteed but not production tested. See test circuit and waveforms.
2. Guaranteed by characterization.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaran-
teed by characterization but not production tested.
QS74LCX2H540, 2H541
MDSL-00178-02 QUALITY SEMICONDUCTOR, INC. 7
FEBRUARY 10, 1998
Now an Company
TEST CIRCUIT AND WAVEFORMS
Figure 3. Test Circuit
500Ω
30pF 500Ω
6.0V
DUT
V
CC
V
IN
V
OUT
Pulse
Generator
Test
Open Drain
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
All Other Inputs
Switch
6V
GND
Open
R
T
C
L
DEFINITIONS:
C
L
= Load capacitance: includes jig
and probe capacitance.
R
T
= Termination resistance: should be
equal to Z
OUT
of the Pulse Generator.
SWITCH POSITION
Figure 4. Setup, Hold, and Release
Timing
tSU tH
0V
1.5V
3V
0V
1.5V
3V
0V
1.5V
3V
0V
1.5V
3V
tREM
tREM tH
Data
Input
Timing
Input
Asychronous Control
Preset, Clear, Etc.
Sychronous Control
Preset, Clear,
Clock Enable, Etc.
Figure 5. Enable and Disable Timing
3V
0V
1.5V
3.0V
0V
V
OL
V
OH
t
PZL
3.0V
0.3V
1.5V
t
PZL
0V
0.3V
1.5V
Control
Input
Output
Normally
Low
Output
Normally
High
Switch
Open
Switch
Closed
Figure 6. Pulse Width
1.5V
tW
1.5V
Low-High-Low
Pulse
High-Low-High
Pulse
1.5V
Same Phase
Input Transition
Output
Opposite Phase
Input Transition
3V
0V
1.5V
V
OH
V
OL
1.5V
3V
0V
t
PLH
t
PLH
t
PHL
t
PHL
Figure 7. Propagation Delay
Notes:
1. Input Control Enable = LOW and Input Control
Disable = HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz;
ZOUT ≤ 50Ω; tF, tR ≤ 2.5ns.
