QS74LCX2H540, 2H541 Q QUALITY SEMICONDUCTOR, INC. High-Speed 3.3V CMOS 8-Bit Buffer/Line Driver with Bus Hold and Output Resistor QS74LCX2H540 QS74LCX2H541 FEATURES/BENEFITS DESCRIPTION * 5V tolerant inputs and outputs * Bus Hold feature holds last active state during 3-state operation * 25 series resistor for low switching noise * 10A ICCQ quiescent power supply current * Hot insertable * 2.0V-3.6V VCC supply operation * 12mA balanced output drive * Power down high impedance inputs and outputs * Meets or exceeds JEDEC 36 specifications * tPD = 6.5ns * Input hysteresis for noise immunity * Operating temperature range: -40C to 85C * Latch-up performance exceeds 400mA * ESD performance: Human body model > 2000V Machine model > 200V * Packages available: 20-pin QSOP, 20-pin SOIC The LCX2H540 and LCX2H541 are 8-bit buffers/ line drivers with three-state outputs that are ideal for driving high capacitance loads such as memory address and data buses. The 3.3V LCXPlus family features low power, low switching noise, and fast switching speeds for low power portable applications as well as high-end, advanced workstation applications. 5V tolerant inputs and outputs allow these LCXPlus products to be used in mixed 5V and 3.3V applications. The LCX2H540 and LCX2H541 with integrated output resistor are ideally suited for low noise environments where reduced ouput overshoot and undershoot are critical requirements. Active Bus Hold feature retains the last valid logic state at unused or floating inputs, thus eliminating the need for external pull-up resistors. To accomodate hot-plug or live insertion applications, these products are designed not to load an active bus when VCC is removed. n a w o N y n pa m o C Figure 1. Functional Block Diagram LCX2H540 OE1 OE2 25 A0(2) 25 Y0(18) A4(6) 25 A1(3) Y1(17) A5(7) 25 A2(4) Y5(13) 25 Y2(16) A6(8) 25 A3(5) Y4(14) 25 Y6(12) 25 Y3(15) A7(9) Y7(11) LCX2H541 OE1 OE2 25 A0(2) 25 Y0(18) A4(6) 25 A1(3) Y1(17) A5(7) 25 A2(4) MDSL-00178-02 FEBRUARY 10, 1998 Y5(13) 25 Y2(16) A6(8) 25 A3(5) Y4(14) 25 Y6(12) 25 Y3(15) A7(9) QUALITY SEMICONDUCTOR, INC. Y7(11) 1 QS74LCX2H540, 2H541 Figure 2. Pin Configurations (All Pins Top View) SOIC, QSOP OE1 A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 y n pa m o C Table 1. Pin Description Name I/O Description A7-A0 I Data Inputs (Bus Hold Inputs) Y7-Y0 O Data Outputs OE1, OE2 I Three-State Output Enable n a w o N Table 2. Function Table 2 OE1 OE2 Input A 2H540 Output Y 2H541 Output Y H X X H X X Hi-Z Hi-Z Hi-Z Hi-Z Disable Outputs L L L L L H H L L H Enable Outputs Function QUALITY SEMICONDUCTOR, INC. MDSL-00178-02 FEBRUARY 10, 1998 QS74LCX2H540, 2H541 Table 3. Capacitance Symbol Pins Typ Unit Conditions CIN Input Capacitance 7.0 pF VIN = 0V, VOUT = 0V, f = 1MHz CI/O I/O Capacitance 8.0 pF VIN = 0V, VOUT = 0V, f = 1MHz CPD Power Dissipation Capacitance 20 pF VCC = 3.3V, VIN = 0V, or VCC f = 10MHz Note: Capacitance is characterized but not production tested. Table 4. Absolute Maximum Ratings Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to QSI devices that result in functional or reliability type failures. Supply Voltage to Ground ................................................. -0.5V to 7.0V DC Output Voltage VOUT Outputs HIGH-Z .............................................................. -0.5V to 7.0V Outputs Active ...................................................... -0.5V to VCC + 0.5V DC Input Voltage VIN ......................................................... -0.5V to 7.0V DC Input Diode Current with VIN < 0 ........................................... -50mA DC Output Diode Current VO < 0 ....................................................................................... -50mA VO > VCC .................................................................................... 50mA DC Output Source/Sink Current (IOH/IOL) ..................................... 50mA DC Supply Current per Supply Pin ........................................... 100mA DC Ground Current per Ground Pin ......................................... 100mA TSTG Storage Temperature ............................................. -65C to 150C y n pa m o C n a w o N Table 5. Recommended Operating Conditions Symbol Parameter Min Max Unit VCC Supply Voltage, Operating Suppply Voltage, Data Retention Only 2.0 1.5 3.6 3.6 V VIN Input Voltage 0 5.5 V VOUT Output Voltage in Active State 0 VCC V VOUT Output Voltage in "OFF" State 0 5.5 V Output Current VCC = 3.0 - 3.6V -- 12 mA VCC = 2.7V -- 6 -- 10 ns/V -40 85 C IOH/IOL t/v TA MDSL-00178-02 FEBRUARY 10, 1998 Input Transition Slew Rate Operating Free Air Temperature QUALITY SEMICONDUCTOR, INC. 3 QS74LCX2H540, 2H541 Table 6. DC Electrical Characteristics Over Operating Range Industrial Temperature Range, TA = -40C to 85C. Symbol Parameter Test Conditions(1) Min Typ(2) Max Unit VIH Input HIGH Voltage Logic HIGH for All Inputs 2.0 -- -- V VIL Input LOW Voltage Logic LOW for All Inputs -- -- 0.8 V VOH Output HIGH Voltage Output LOW Voltage VT Input Hysteresis(3) VCC- 0.2 2.4 2.2 -- -- -- -- -- -- -- -- -- -- 150 -- -- -- 0.2 0.55 0.8 -- V VOL VCC = 2.7V, IOH = -100A VCC = 3.0V, IOH = -12mA VCC = 3.0V, IOH = -18mA VCC = 2.7V, IOL = 100A VCC = 3.0V, IOL = 12mA VCC = 3.0V, IOL = 18mA VTLH - VTHL for All Inputs mV Off-State Output Current (Hi-Z) VCC = 3.6V, VO = 0V, VO = 5.5V -- -- 1.0 A IOS Short Circuit Current (3,4) VCC = 3.6V, VOUT = GND -60 -- -200 mA IOR Current Drive VCC = 3.6V, VOUT = 2.0V 40 -- -- mA VIK Input Clamp Voltage VCC = 2.7V, IIN = -18mA -- -0.7 -1.2 V Input Leakage Current VI = 0V, VI = 5.5V, VCC = 3.6V -- -- 1.0 A ROUT Output Resistance VCC = 3.0V, IOL = 12mA -- 28 -- | IBH | Input Current Input HIGH or LOW Bus Hold Inputs(3,5) VCC = 3.6V, VIN = 0V or VIN = VCC VCC = 3.6V, 0.8 < VIN < 2.0V -- -- 50 A -- -- 500(6) A VIN = 2.0V -75 -- -- A VIN = 0.8V 75 -- -- A -- -- 10 A | IOZ | (3) II IBHH IBHL IOFF an Bus Hold Sustaining Current Bus Hold Inputs VCC = 3.0V Power Off Leakage VCC = 0V, VI or VO = 5.5V w o N V y n pa m o C Notes: 1. For conditions shown as Min. or Max. use appropriate value specified under Recommended Operating Conditions for the applicable device type. 2. Typical values are at VCC = 3.3V and TA = 25C. 3. These parameters are guaranteed by characterization, but not production tested. 4. Not more than one output should be tested at one time. Duration of test should not exceed one second. 5. Pins with Bus Hold are identified in the Pin Description. 6. An external driver must provide at least | IBH | during transition to guarantee that the Bus Hold input will change state. 4 QUALITY SEMICONDUCTOR, INC. MDSL-00178-02 FEBRUARY 10, 1998 QS74LCX2H540, 2H541 Table 7. Power Supply Characteristics Symbol Parameter Test Conditions(1) Quiescent Power Supply Current VCC = Max., Freq = 0 VIN = GND or VCC ICC Supply Current per Input @ TTL HIGH (3) VCC = Max. VIN = VCC-0.6V, Freq = 0 ICCD Supply Current per Input per MHz(4) VCC = Max., Outputs Open One Bit Toggling @ 50% Duty Cycle OEx = GND Total Power Supply Current(6) VCC = Max., Outputs Open One Bit Toggling @ 50% Duty Cycle OEx = GND, f = 10MHz VCC = Max., Outputs Open Sixteen Bits Toggling @ 50% Duty Cycle OEx = GND, f = 2.5MHz ICC IC Typ(2) Max Unit 0.1 10 A Control Inputs 2.0 Bus Hold Inputs -- 30 500 A A 75 A/ MHz VIN = VCC-0.6V 0.5(5) VIN = GND 1.0(5) mA VIN = VCC-0.6V 1.0(5) VIN = GND 3.5(5) mA 50 y n pa m o C Notes: 1. For conditions shown as Min. or Max., use the appropriate values specified under Recommended Operating Conditions for applicable device type. 2. Typical values are at VCC = 3.3V, 25C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in total power supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed by design but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC. IC = ICCQ + ICC DHNT + ICCD fNO. ICCQ = Quiescent Current (ICCL, ICCH, and ICCZ). ICC = Power Supply Current for a TTL-High Input (VIN = VCC-0.6V). DH = Duty Cycle for TTL High Inputs. NT = Number of TTL High Inputs. ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL). f = Average Switching Frequency per Output. NO = Number of Outputs Switching. n a w o N Table 8. Dynamic Switching Characteristics(1) VCC TA = 25C Symbol Parameter Conditions (V) Typical Units VOLP Quiet Output Dynamic Peak VOL CL = 30pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V VOLV Quiet Output Dynamic Valley VOL CL = 30pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V Note: 1. Characterized but not production tested. MDSL-00178-02 FEBRUARY 10, 1998 QUALITY SEMICONDUCTOR, INC. 5 QS74LCX2H540, 2H541 Table 9. Switching Characteristics Over Operating Range Industrial Temperature Range, TA = -40C to 85C. CLOAD = 30pF, RLOAD = 500 unless otherwise noted. VCC = 3.3 0.3V Symbol VCC = 2.7V(2) Description(1) Min Max Min Max Unit tPHL tPLH Propagation Delay Ai to Yi 1.5 6.5 1.5 7.5 ns tPZH tPZL Output Enable Time OEx to Yi 1.5 8.5 1.5 9.5 ns tPHZ tPLZ Output Disable Time(2) OEx to Yi 1.5 7.5 1.5 8.5 ns tSK(O) Output Skew (3) -- 0.5 -- -- ns Notes: 1. Minimums guaranteed but not production tested. See test circuit and waveforms. 2. Guaranteed by characterization. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by characterization but not production tested. y n pa m o C n a w o N 6 QUALITY SEMICONDUCTOR, INC. MDSL-00178-02 FEBRUARY 10, 1998 QS74LCX2H540, 2H541 TEST CIRCUIT AND WAVEFORMS SWITCH POSITION Figure 3. Test Circuit 500 VCC 6.0V VIN Pulse Generator VOUT DUT RT 30pF CL 500 Test Open Drain Disable LOW Enable LOW Disable HIGH Enable HIGH All Other Inputs Switch 6V GND Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Figure 6. Pulse Width Figure 4. Setup, Hold, and Release Timing Data Input tREM tH Timing Input tREM 3V 1.5V 0V Low-High-Low Pulse 3V 1.5V 0V High-Low-High Pulse Asychronous Control Preset, Clear, Etc. 3V 1.5V 0V Sychronous Control Preset, Clear, Clock Enable, Etc. 3V 1.5V 0V tSU tH n a w o N Figure 5. Enable and Disable Timing 1.5V tW y n pa m o C Figure 7. Propagation Delay 3V Control Input 3V 1.5V 0V Same Phase Input Transition tPLH tPHL Output Normally Low 1.5V 0V VOH tPZL 1.5V 3.0V Switch Closed Switch Open 3.0V Output VOL Opposite Phase Input Transition tPLH 1.5V 0.3V tPZL Output Normally High 1.5V 0.3V VOH VOL tPHL 3V 1.5V 0V 1.5V 0V 0V Notes: 1. Input Control Enable = LOW and Input Control Disable = HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; ZOUT 50; tF, tR 2.5ns. MDSL-00178-02 FEBRUARY 10, 1998 QUALITY SEMICONDUCTOR, INC. 7