\ ov 24 wm: 80188 High Integration 8-Bit Microprocessor iAPX86 Family DISTINCTIVE CHARACTERISTICS @ integrated feature set Enhanced 10 MHz 8088-1 CPU Clock generator Two independent, high-speed OMA channels Programmable interrupt controller Three programmable 16-bit timers Programmable memory and peripheral chip-select jogic Programmable wait state generator Local bus controller @ Ejight-bit data bus interface, 16-bit internal architectur e @ Available in 10 MHz (80188-10), 8 MHz (80188) @ High-performance processor Two times the performance of the standard 8088 2.25 Mbyte/sec bus bandwidth interface @ Direct addressing capability to 1 Mbyte of memory @ Completely object code compatible with all existing iAPX 86, 88 software Ten new instruction types Compatible with 29843/45, 29833/63, 8284, and 8288 bu s support components @ Optional numeric processor extension e@ Available in 68-pin Plastic Leaded Chip Carrier (PLCC), Ceramic Leadless Chip Carrier (LCC), and Pin Grid Array (PGA) packages. GENERAL DESCRIPTION The 80188 is a highly-integrated microprocessor with an 8-bit data bus interface and a 16-bit internal architecture for high performance. It effectively combines 15-20 of the most common iAPX 86 system components onto one. The 8 MHz 80188 provides two times greater throughput than the standard 5 MHz 8088. The 80188 is upward compatible with 8086 and 8088 software and adds 10 new instruction types to the existing set. The 80188 comes in a 68-pin package and requires a single +5 V power supply. BLOCK DIAGRAM INTSAINTAT INT2ZINTAG CLKOUT Vcc GNO wht TMROUT1 TMROUTO TMA IN TMR IN 40h nmi INTO 1 t 0 | | | ~ = +14 PROGRAMMABLE EXECUTION UNIT: ' ana % % ! o 1 2 16-BIT 1 MAX COUNT | ALU 1 PROGRAMMABLE REGISTEAB INTERRUPT MAX COUNT loenenaton ear ; CONTROLLER REGISTER & GENERAL I CONTROL REGISTERS PURPOSE | CONTROL REGISTERS _I REGISTERS COUNT REGISTER f if INTERNAL 8US r- ORO {pT ORO? PROGRAMMABLE $-3 OMA UNIT $0-$2 6 1 CHIP-SELECT 20-81T SADY UNIT ISOURCE POINTERS| ARDY BUS INTERFACE 20-817 Test iT seer DESTINATION Unt HOLD AEGISTERS POINTERS HLDA BYTE PROGRAMMABLE 16-817 : col it RES PREFETCH REGISTERS TRANSFER COUNT Reser QUEUE CONTROL | L REGISTERS. RR aa + __DEN watt S$ PCSEIAZ Lock RO Ada AIBS3- vy ces | | ecssas AD? AY om 7 AB-Al5 _Y_ McSO-3 PCSO-4 BD003561 Reprinted by permission of Intel Corp. copyright 1983. Publication # Hev. Amendment 06878 B /0 Issue Date: January 1989 pat sstoe S2DdIAQq OIDIW P2DUPAPYTop CONNECTION DIAGRAMS Leadless Chip Carrier (LCC*) HLDA HOLD a a wn SO Wj: Wa nN WZ CMS _ o Pins Facing Up 25 S 3 = = ao 5 = 3 2 = 4 = 4 = a = a = 2 za = 5 = = = = 2 3 4 a 4 ot oy BERR j= |= Aiea ar rae Ar Ae Ar we ar we aw ar awe ae PIN NO. 1 MARK *LCC package placed in socket top down. Pin Grid Array (PGA) Pins Facing Down GD010511 @ O@ O O O@ OOO QOHYOO O@ @ @ OOOOOOOOOO OOOQOOOQOOD / \ ( @O@@O@OHOOO@O ) f @ @OQLOHOOOLHO O@ @ @ Q@ OO XO O@ @@ @@ OO @ @ @ @ @ @ @ @ @ @a @ @@ @@QGOQBHOQQOOOO O L O0000000 , Poe CD010521CONNECTION DIAGRAMS (Coni'd.) Plastic Leaded Chip Carrier (PLCC**) CD01G530 **PLCC package placed in socket top up. (PLCC pin-out same as LCC.) LOGIC SYMBOL Aie/S3-Aig/SB x [) * AgAis Jexrour P >] TMR in 1 AD,-AD, <_TMR out 1 = >] TMR in 0 ~~< | TMR out 0 ALE[/-->- 1 sRDY AD] > ARDY wal >| TEST s,| nM a <>| INT3/INTAT O- 2) $$$ INT27NTAO BEN ->- qInTs DT/R -> _-+ INTO COCK +}> RES RESET >_> +~_j UTS HULDA -> rn WCE. HOLD k#___ DRQO}_ ~ ts DRQ1-e#- < PCS0-4 +___| PCS5/A1 ~+-_ | PCS6A2 LS001970ORDERING INFORMATION Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type c. Device Number d. Speed Option e. Optional Processing R 80188 B | e. OPTIONAL PROCESSING B = Burn-in d. SPEED OPTION Blank = 8 MHz -10=10 MHz c. DEVICE NUMBER/DESCRIPTION 80188 High Integration 8-Bit Microprocessor b. PACKAGE TYPE R =68-Pin Ceramic Leadiess Chip Carrier (CA2068) N = 68-Pin Plastic Leaded Chip Carrier (PL 068) A=68-Pin Grid Array (CGX068) a. TEMPERATURE RANGE* Blank = Commercial (0 to + 70C) |= Industrial (40 to +85C) Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid Valid Combinations ARN 80188 combinations, to check on newly released valid i 80188-10 combinations, and to obtain additional data on AMD's A, R, IA, IA 80188B standard military grade products. *This device is also available in Military temperature range. See MOS Micro-processors and Peripherals Handbook (Order #09275A/0) for electrical performance characteristics.PIN DESCRIPTION Active State Name vo Description Voc. Voc System Power: +5 volt power supply. Vss, Vss ( System Ground. Active HIGH RESET o Reset Output indicates that the 801B8 CPU is being reset; and can be used as a system reset. It is active HIGH, synchronized with the processor clock, and lasts an integer number of clock periods corresponding to the length of the RES signal. X14, X2 | Crystal inputs, X1 and X2, provide an external connection for a fundamental mode parailel resonant crystal for the internal crystal oscillator. X1 can interface to an externat clock instead of a crystal. The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT). CLKOUT Clock Output provides the system with a 50% duty cycle waveform. All device pin timings are specified relative to CLKOUT. CLKOUT has sufficient MOS drive capabilities for a numeric processor extension. Active LOW AES | System Reset causes the 80188 to immediately terminate its present activity, clear the internal logic, and enter a dormant state. This signal may be asynchronous to the 80188 clack. The 80188 begins fetching instructions approximately 7 clock cycles after RES is returned HIGH. RES is required to be LOW for greater than 4 clock cycles and is internally synchronized. For proper initialization, the LOW-to- HIGH transition of RES must occur no sooner than 50 microseconds after power up. This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network. When RES occurs, the 80189 will drive the status lines to an inactive level for one clock, and then tri-state them. Active LOW TEST 1 TEST is examined by the WAIT instruction. If the TEST input is HIGH when "WAIT" execution begins, instruction execution will suspend. TEST will be resampled until it goes LOW, at which time execution will resume. If interrupts are enabled while the 80188 is waiting for TEST, interrupts will be serviced. This input is synchronized internally. Active HIGH TMR in 0, I Timer inputs are used either as clock or control signals, depending upon the programmed timer mode. TMR IN1 | These inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized. Active HIGH TMR OUT 0, oO Timer outputs are used to provide single pulse or continuous waveform generation, depending upon the TMR OUT 1 oO timer mode selected. Active HIGH DRQO | DMA Request is driven HiGH by an external device when it desires that a DMA channel (Channel 0 or 1) DRQ1 | pertorm a transfer. These signals are active HIGH, level-triggered, and internally synchronized. Active HIGH NMI | Non-Maskable Interrupt is an edge-triggered input which causes a type 2 interrupt. NMI is not maskable internally. A transition from a LOW to HIGH initiates the interrupt at the next instruction boundary. NMI is latched internally. An NMI duration of one clock or more will guarantee service. This input is internally synchronized. Active HIGH INTO, INT1 | Maskable Interrupt Requests can be requested by strobing one of these pins. When configured as or INT2/INTAO vO inputs, these pins are active HIGH. Interrupt Requests are synchronized intemally. INT2 and INT3 may LOW INT3/INTAt VO be configured via software to provide active-LOW interrupt-acknowledge output signals. All interrupt inputs may be configured via software to be either edge- or level-triggereed. To ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. When iRMX mode is selected, the function of these pins changes (see Interrupt Controller section of this data sheet). Active HIGH At9/S6, Oo Address Bus Outputs (16-19) and Bus Cycle Status (3-6) reflect the four most significant address bits A18/S5, oO during T1. These signals are active HIGH. During To, T3, Tw, and Ty, status information is available on A17/S4, O these fines as encoded below: A16/S3 oO Low High S6 Processor Cycle DMA Cycie $3, $4, and S5 are defined as LOW during To-Ty. Active HIGH AD?7-ADO 1/0 Address/Data Bus (0-7) signals constitute the time muitiplexed memory or I/O address (T1) and data (Ta, Tg. Tw, and Ta) bus. Active HIGH A15-A8 Address-only Bus (8-15), containing valid address from 14-T4. Active HIGH $7 3 This signal is always HIGH to indicate that the 80188 has an 8-bit data bus and is tri-state OFF during bus hold. Active HIGH ALE/QS0 oO Address Latch Enable/Queue Status 0 is provided by the 60188 to latch the address into the 8282/ 8283 address latches. Addresses are guaranteed to be valid on the trailing edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT immediately preceding T; of the associated bus cycle, effectively one-half clock cycle earlier than in the standard 8088. The trailing edge is generated off the CLKOUT rising edge in T; as in the 8088. Note that ALE is never floated.PIN DESCRIPTION (Cont.) Active State Name 1/0 Description Active LOW WR/QS1 Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a memory or an I/O device. WR is active for Tz, T3, and Ty of any write cycle. Floats during 'HOLD." It is driven HIGH for one clock during Reset, and then floated. When the 80188 is in queue status mode, the ALE/QSO and WR/QS1 pins provide information about processor/instruction queue interaction. Qs1 aso Queue Operation No queue operation First opcode byte fetched from the queve Subsequent byte fetched from the queue Empty the queue 0 0 1 1 Olas); o Active LOW RD/OQSMD Read Strobe indicates that the 80188 is performing a memory or I/O read cycle. AD is active LOW for Ta, Tg, and Ty of any read cycle. It is guaranteed not to. go LOW in T2 until after the Address Bus is floated. RD is active LOW, and floats during "HOLD." RD is driven HIGH for one clock during Reset, and then the output driver is floated. A weak internal pull-up mechanism on the RD line holds it HIGH when the lina is not driven. During RESET the pin is sampled to determine whether the 80188 should provide ALE, WR, and RD, or if the Queue-Status should be provided. RD should be connected to GND to provide Queue-Status data. Active HIGH ARDY Asynchronous Ready informs the 801B8 that the addressed memory space or I/O device will complete a data transfer. The ARDY input pin will accept an asynchronous input, and is active HIGH. Only the rising edge is internally synchronized by the 80188. This means that the falling edge of ARDY must be synchronized to the 80188 clock. If connected to Vcc, no WAIT states are inserted. Asynchronous teady (ARDY) or synchronous ready (SRDY) /ust be active to terminate a bus cycle. If line is unused, it may remain connected to Vcc of it may be connected to Vsg {in which case the programmer must initialize the part to inhibit the external pins). Active HIGH SRDY Synchronous Ready must be synchronized externally te the 80188. The use of SRDY provides a relaxed system-timing specification on the Ready input. This is accomplished by eliminating the one-half clock cycle which is required for internally resolving the signal level when using the ARDY input. This line is active HIGH. If this line is connected to Vcc no WAIT states are inserted. Asynchronous ready {ARDY) or synchronous ready (SRDY) must be active before a bus cycle is terminated. If line is unused, it may remain connected to Vcc or it may be connected to Vss (in which case the programmer must initialize the part to inhibit the external pins). Active LOW LOCK LOCK output indicates that other system bus masters are not to gain control of the system bus while LOGK is active LOW. The COCK signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction following the LOCK prefix. It remains active until the completion of the instruction following the LOCK prefix. No prefetches will occur while LOCK is asserted. When executing more than one LOCK instruction, there must be six bytes of code between the end of the first LOCK instruction and the start of the second LOCK instruction. LOCK is active LOW, is driven HIGH for one clock during RESET, and then floated. Bus cycle status 50-52 are encoded to provide bus-transaction information: 80188 Bus Cycle Status Information SO. Bus Cycle Initiated interrupt Acknowledge Read 1/0 Write 1/0 Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (no bus cycle) ala|-/-;alclo]/ of si 0 0 1 1 0 0 1 1 =jol=lo]=/o/=/o]g The status pins float during HOLD." _ _ 52 may be used as a logical M/IO indicator, and S1 as a DT/R indicator. The status lines are driven HIGH for one clock during Reset, and then floated until a bus cycle begins. Active HIGH HOLD (input) HiDA (output) HOLD indicates that another bus master is requesting the local bus. Tha HOLD input is active HIGH. HOLD may be asynchronous with respect to the 80188 clock. The 80188 will issue a HLDA in response to a HOLD request at the end of T4 or T; Simultaneous with the issuance of HLDA, the 80188 will float the local bus and control lines. After HOLD is detected as being LOW, the 80188 will lower HLDA. When the 80188 needs to run another bus cycle, it will again drive the local bus and control lines. Active LOW Al Upper Memory Chip Select is an active LOW output whenever a memory reference is made to the defined upper portion (1K-=256K block) of memory. This line is not floated during bus HOLD. The address range activating UCS is software programmable. Active LOW Al Lower Memory Chip Select is active LOW whenever a memory referance is made to the defined lower portion (1K-256K) of memary. This line is not floated during bus HOLD. The address range activating LCS is software programmable. Active LOW Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the defined mid-range portion of memory (8K-512K). These lines are not floated during bus HOLD. The address ranges activating MCS0-3 are software programmable. Active LOW oo Peripheral Chip Select signals 0-4 are active LOW when a reference is made to the defined peripheral area (65K byte I/O space). These lines are not floated during bus HOLD. The address ranges activating PCS0-4 are software programmable.PIN DESCRIPTION (Cont.) Active State Name Vo Description Active LOW Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth peripheral chip select, or or to provide an internally latched A1 signal. The address range activating PCS5 is software HIGH programmable. When programmed to provide latched A1, rather than PCSS5, this pin will retain the previously fatched value of A1 during a bus HOLD. Active LOW PCS6/A2 Peripheral Chip Select 6 or Latched A2 may be programmed to provide a seventh peripheral chip select, or or to provide an internally latched A2 signal. The address range activating BCSE is software HIGH programmable. When programmed to provide latched A2, rather than PCS6, this pin will retain the previously latched value of A2 during a bus HOLD. DT/R 3 Data Transmit/Receive contrals the direction of data flow through the external 2946/47 data bus transceiver. When LOW, data is transferred to the 80188. When HIGH the 80188 places write data on the data bus. Active LOW EN Oo Data Enable is provided as a 2946/47 data bus transceiver output enable. DEN is active LOW during each memory and 1/O access. DEN is HIGH whenever DT/R changes state. FUNCTIONAL DESCRIPTION Introduction The following Functional Description describes the base archi- tecture of the 80188. The architecture is common to the 8086, 8088, and 80286 microprocessor families as well. The 80188 is a very high integration 8-bit microprocessor. It combines 15-20 of the mast common microprocessor system components onto one chip while providing twice the performance of the standard 8088. The 80188 is object code compatible with the 8086, 8088 microprocessors and adds 10 new instruction types to the existing 8086, 8088 instruction set. 80188 BASE ARCHITECTURE The 8086, 8088, 80188, 80186 and 80286 family all contain the same basic set of registers, instructions, and addressing modes. The 80188 processor is upward compatible with the 8086, 8088, 80186 and 80286 CPUs. Register Set The 80188 base architecture has fourteen registers as shown in Figures 1 and 2. These registers are grouped into the following categories. General Registers Eight 16-bit general purpose registers used to contain arithme- tic and logical operands. Four of these (AX, BX, CX, and DX) can be used as 16-bit registers or split into pairs of separate 8-bit registers. Segment Registers Four 16-bit special purpose registers select, at any given time, the segments of memory that are immediately addressable for code, stack, and data. (For usage, refer to Memory Organiza- tion.) Base and Index Registers Four of the general purpose registers may also be used to determine offset addresses of operands in memory. These registers may contain base addresses or indexes to particular locations within a segment. The addressing mode selects the specific registers for operand and address calculations. Status and Control Registers Two 16-bit special purpose registers record or alter certain aspects of the 80188 processor state. These are the instruc- tion Pointer Register, which contains the offset address of the next sequential instruction to be executed, and the Status Word Register, which contains status and control flag bits (see Figures 1 and 2). Status Word Description The Status Word records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7, and 11) and controls the operation of the 80188 within a given operating mode (bits 8, 9, and 10). The Status Word Register is 16-bits wide. The function of the Status Word bits is shown in Table 2. 16-BIT SPECIAL REGISTER REGISTER NAME FUNCTIONS 7 7 a QYTE AX MULTIPLY/OIVIDE ADDRESSABLE VO INSTRUCTIONS (8-BiT Ox REGISTER NAMES cx LOOP/SHIF T/REPEAT/COUNT SHOWN) 8x BASE REGISTERS 6P ) INOEX REGISTERS o . sp STACK POINTER GENERAL REGISTERS CODE SEGMENT SELECTOR DATA SEGMENT SELECTOR STACK SEGMENT SELECTOR EXTRA SEGMENT SELECTOR SEGMENT REGISTERS s F STATUS WORD ie INSTRUCTION POINTER: STATUS AND CONTROL REGISTERS. TBOGO04S Figure 1. 80188 General Purpose Register SetSTATUS FLAGS: CARRY PARITY AUXILIARY CARRY ZERO SIGN OVERFLOW 4 3 12 W 1s 10 9 8 v7 6 5 v3 fz ro starus woro: [\\\\\A\\\Y\\AY oF | . | . A EAEAN EAN EAN ES RESERVED CONTROL FLAGS: TRAP FLAG INTERRUPT ENABLE DIRECTION FLAG DFO002910 Figure 2. Status Word Format Table 2. Status Word Bit Function Bit Position | Name Function Carry Flag Set on high-order bit carry or borrow; cleared otherwise. Parity Flag Set if low-order 8 bits or result contain an even number of 1-bits; cleared otherwise. Set on carry from or borrow to the low order four bits of AL; cleared otherwise. Zero Flag Set if result is zero; cleared otherwise. Sign Flag Set equal to high-order bit of result (0 if positive, 1 if negative). Single Step Flag Once set, a single step interrupt occurs after the next in- struction executes. TF is cleared by the single step interrupt. Interrupt-enable Flag-- When set, maskable interrupts will cause the CPU to transfer control to an interrupt vector specified location. Direction Flag Causes string instruc- tions to auto decrement the appropriate index register when set. Clearing DF 10 OF causes auto increment. Overflow Flag Set if the signed result cannot be expressed within the number of bits in the destination operand; 1 OF | cleared otherwise. Instruction Set The instruction set is divided into seven categories: data transfer, arithmetic, shift/rotate/logical, string manipulation, control transfer, high-level instructions, and processor control. These categories are summarized in Figure 3. An 80188 instruction can reference anywhere from zero to several operands. An operand can reside in a register, in the instruction itself, or in memory. Specific operand addressing modes are discussed later in this data sheet. Memory Organization Memory is organized in sets of segments. Each segment is a linear contiguous sequence of up to 64K (2! ) 8-bit bytes. Memory is addressed using a two-component address (a pointer) that consists of a 16-bit base segment and a 16-bit offset. The 16-bit base values are contained i one of four internal segment registers (code, data, stack, extra). The physical address is calculated by shifting the base value LEFT by four bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 4). This allows for a 1 MByte physical address size. All instructions that address operands in memory must specifiy the base segment and the 16-bit offset value. For speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see Table 3). These rules follow the way programs are written (see Figure 5) as independent modules that require areas for code and data, a stack, and access to external data areas. Special segment override instruction prefixes allow the implicit segment register selection rules to be overridden for special cases. The stack, data, and extra segments may coincide for simple programs.GENERAL PURPOSE INS Input bytes or word string MOV Move byte or word OUTS Output bytes or word string PUSH Push word onto stack CMPS Compare byte or word string POP Pop word off stack SCAS Scan byte or word string PUSHA Push all registers on stack LODS Load byte or word string POPA Pop all registers from stack STOS Store byte or word string XCHG Exchange byte or word REP Repeat XLAT Translate byte AED Repeat while equal/zero INPUT/OUTPUT IN Input byte or word EONS Repeat while not equal/not zero OUT Output byte or word ADDRESS OBJECT LOGICALS LEA Load effective address NOT Not' byte or word LDS Load pointer using DS AND "And" byte or word LES Load pointer using ES OR "Inclusive or" byte or word FLAG TRANSFER XOR Exclusive or byte or word LAHF Load AH register from flags TEST "Test" byte or word SAHF Store AH register in flags SHIFTS PUSHF Push flags onto stack SHL/SAL Shift logical/arithmetic left byte or word POPF Pop flags off stack SHR Shift logical right byte or word SAR Shift arithmetic right byte or word ADDITION ROTATES ADD Add byte or word ROL Rotate left byte or word ADC Add byte or word with carry ROR Rotate right byte or word INC Increment byte or word by 1 RCL Rotate through carry left byte or word AAA ASCII adjust for addition RCR Rotate through carry right byte or word DAA Decimal adjust for addition SUBTRACTION FLAG OPERATIONS suB Subtract byte or word STC Set carry flag S6B Subtract byte or word with borrow CLC Clear carry fiag DEC Decrement byte or word by 1 CMC Complement carry flag NEG Negate byte or word STD Set direction flag CMP Compare byte or word CLD Clear direction flag AAS ASCII adjust for subtraction STI Set interrupt enable flag DAS Decimal adjust for subtraction cu Clear interrupt enable flag MULTIPLICATION EXTERNAL SYNCHRONIZATION MUL Multiply byte or word unsigned HLT Halt until interrupt or reset IMUL Integer multiply byte or word WAIT Wait for TEST pin active AAM ASCII adjust for multiply ESC Escape to extension processor DIVISION LOCK Lock bus during next instruction DIV Divide byte or word unsigned NO OPERATION IDIV Integer divide byte or word NOP No operation AAD ASCII adjust for division HIGH LEVEL INSTRUCTIONS CBW Convert byte to word ENTER Format stack for procedure entry CwD Convert word to doubleword LEAVE Restore stack for procedure exit MOVS Move byte or word string BOUND Detects values outside prescribed range Figure 3. 80188 Instruction Set All mnemonics copyright Intel Corp.CONDITIONAL TRANSFERS UNCONDITIONAL TRANSFERS JA/JNBE Jump if above/not below nor equal CALL Call procedure JAE/JNB Jump if above or equal/not below RET Return from procedure JB/JNAE Jump if below/not above nor equal JMP Jump JBE/JNA Jump if below or equal/not above Jc Jump if carry ITERATION CONTROLS JE/IZ Jump if equal/zero JG/JNLE Jump if greater/not less nor equal LOOP Loop JGE/JNL Jump if greater or equal/not less LOOPE/LOOPZ Loop if equat/zero JL/JNGE Jump if less/not greater nor equal LOOPNE/LOOPNZ Loop if not equal/not zero JLE/JNG Jump if less or equal/not greater JCXZ Jump if register CX = 0 JNG Jump if not carry JNE/JNZ Jump if not equal/not zero INTERRUPTS JNO Jump if not overflow JNP/JPO Jump if not parity/parity odd INT Interrupt JNS Jump if not sign INTO Interrupt if overflow JO Jump if overflow IRET Interrupt return JP/JPE Jump if parity/parity even JS Jump if sign Figure 3. 80188 Instruction All mnemonics copyright Intel Corp. Set (continued) Ta access operands that do not reside in one of the four immediately available segments, a full 32-bit pointer can be used to reload both the base (segment) and offset values. SHIFT LEFT 4 BITS segnes ; = PHYSICAL ADDRESS w 0 TOMEMORY LOGICAL ADDAESS DF002920 Figure 4. Two Component Address Table 3. Segment Register Selection Rule Memory Segment Reference Register implicit Segment Needed Used Selection Rule Instructions Code (CS) | Instruction prefetch and im- mediate data. Stack Stack (SS) | Alt stack pushes and pops; any memory references which use BP Register as a base register. External Extra (ES) | All string instruction refer- Data ences which use the DI reg- (Global) ister as an index. Local Data Data (DS) All other data references. cr77 7 ; ' CODE MODULE A DATA I ' I i cove CPU MOOULE B | DATA CODE t i l DATA ! I STACK PROCESS STACK r EXTRA SEGMENT REGISTERS I i ' ! PROCESS DATA BLOCK 1 4 ! i I PROCESS DATA BLOCK 2 4 I | MEMORY DF002930 Figure 5. Segmented Memory Helps Structure SoftwareAddressing Modes The 80188 provides eight categories of addressing modes to specify operands. Two addressing modes are provided for instructions that operate on register or immediate operands: @ Register Operand Mode: The operand is located in one of the 8- or 16-bit general registers. immediate Operand Mode: The operand is included in the instruction. Six modes are provided to specify the location of an operand in a memory segment. A memory operand address consists of two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either implicity chosen by the addressing mode or explicitly chosen by a segment override prefix. The offset, also called the effective address, is calculated by summing any combination of the following three address elements: the displacement (an 8- or 16-bit immediate value con- tained in the instruction); the base (contents of either the BX or BP base registers); and @ the index (contents of either the SI or Dt index registers) Any carry out from the 16-bit addition is ignored. Eight-bit displacements are sign extended to 16-bit values. Combinations of these three address elements define the six memory addressing modes, described below. @ Direct Mode: The operand's offset is contained in the instruction as an 8- or 16-bit displacement element. Register Indirect Mode:The operands offset is in one of the registers SI, DI, BX, or BP. @ Based Mode: The operand's offset is the sum of an 8- or 16-bit displacement and the contents of a base register (BX or BP). @ indexed Mode: The operand's offset is the sum of an 8- or 16-bit displacement and the contents of an index register (St or DI). @ Based Indexed Mode: The operand's offset is the sum of the contents of a base register and an index register. @ Based Indexed Mode with Displacement: The operand's offset is the sum of a base register's contents, an index register's contents, and an 8- or 16-bit displacement. Data Types The 80188 directly supports the following data types: @ Integer: A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a two's complement representation. Signed 32 and 64 bit integers are supported using a numeric data processor. @ Ordinal: An unsigned binary numeric value contained in an 8-bit byte or a 16-bit word. @ Pointer: A 16- or 32-bit quantity, composed of a 16-bit offset component or a 16-bit segment base component in addition to a 16-bit offset component. @ String: A contiguous sequence of bytes or words. A string may contain from 1K to 64K bytes. @ ASCil: A byte representation of alphanumeric and control characters using the ASCII standard of character represen- tation. @ BCD: A byte (unpacked) representation of the decimal digits 0-9. @ Packed BCD: A byte (packed) representation of two deci- mal digits (0-9). One digit is stored in each nibble (4-bits) of the byte. Floating Point: A signed 32-, 64-, or 80-bit real number representation. (Floating point operands are supported using a numeric data processor configuration.) In general, individual data elements must fit within defined segment limits. Figure 6 graphically represents the data types supported by the 80188. 7 oO SIGNEO BYTE SIGN BIT 4 5 MAGNITUDE 7 0 UNSIGNED OYTE Luss MAGNITUDE wu tt p77 0 96 SIGNED WORD SIGN BIT-| CMSB J MAGNITUDE SIGNED 31 +3 +2 gas 7? 0 DOUBLE WORD SIGN BIT4 CMSB j +7 +6 +5 +4 +3 +2 +1 SIGNED 63 a? 1 16.18 Quad waro SIGN BIT + MSB MAGNITUDE 3 +! o 6 UNSIGNEO WORD cMsa_ ly MAGNITUDE +N +1 o pinany 7 0 07 DECHIAL (aco) BCD DIGIT N 7 *N oo ? asen [TT] vee asct CHARACTER, 7 tN 9 7 *1 97 % a PACKED 8 Tm} Ld OWIT 1 DIGIT oO mosT Least SIGNIFICANT O1GIT SIGNIFICANT DIGIT rs *N 9 ms 107 0 0 STRING eee BYTEWORD N BYTE/WORD 1 BYTE/WORD 0 n +3 +2 1615 +t POWTER SELECTOR OFFSET raro +8 +7 +6 +5 +4 +30 = +2~+1 0 nome TT TLLLLLL SIGN BIT =, I EXPONENT MAGNITUDE DF002940 NOTE: *SUPPORTED BY 80188 WITH A NUMERIC DATA PROCESSOR Figure 6. 80188 Supported Data TypesI/O Space The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions address the '/O space with either an 8- bit port address, specified in the instruction, or a 16-bit port address in the DX register, 8-bit port addresses are zero extended such that A15-Ag are LOW. I/O port addresses OOF8(H) through OOFF(H) are reserved. Interrupts An interrupt transfers execution to a new program location. The old program address (CS:IP)} and machine state (Status Word) are saved on the stack to allow resumption of the interrupted program. Interrupts fall into three classes: hard- ware initiated, INT instructions, and instruction exceptions. Hardware initiated interrupts occur in response to an externa! input and are classified as non-maskable or maskable. Programs may cause an interrupt with an INT instruction. Instruction exceptions occur when an unusual condition, which prevents further instruction processing, is detected while attempting to execute an instruction. If the exception was caused by executing an ESC instruction with the ESC trap bit set in the relocation register, the return instruction will point to the ESC instruction, or to the segment override prefix immedi- ately preceding the ESC instruction if the prefix was present. In ail other cases, the return address from an exception will point at the instruction immediately following the instruction causing the exception. A table containing up to 256 pointers defines the proper interrupt service routine for each interrupt. Interrupts 0-31, some of which are used for instruction exceptions, are reserved. Table 4 shows the 80188 predefined types and default priority levels. For each interrupt, an 8-bit vector must be supplied to the 80188 which identifies the appropriate table entry. Exceptions supply the interrupt vector internally. In addition, internal peripherals and noncascaded external inter- tupts will generate their own vectors through the internal interrupt controller. INT instructions contain or imply the vector and allow access to all 256 interrupts. Maskable hardware initiated interrupts supply the 8-bit vector to the CPU during an interrupt acknowledge bus sequence. Non-maskable hard- ware interrupts use a predefined internally supplied vector. Interrupt Sources The 80188 can service interrupts generated by software or hardware. The software interrupts are generated by specific instructions (INT, ESC, unused OP, etc.) or the results of conditions specified by instructions (array bounds check, INTO, DIV, IDIV, etc.) All interrupt sources are serviced by an indirect call through an element of a vector table. This vector table is indexed by using the interrupt vector type (Table 4), multiplied by four. All hardware-generated interrupts are sam- pled at the end of each instruction. Thus, the software interrupts will begin service first. Once the service routine is entered and interupts are enabled, any hardware source of sufficient priority can interrupt the service routine in progress. The software generated 80188 interrupts are described below. DIVIDE ERROR EXCEPTION (TYPE 0) Generated when a DIV or IDIV instuction quotient cannot be expressed in the number of bits in the destination. Table 4. 80188 Interrupt Vectors Vector! Default Related Interrupt Name Type | Priority Instructions Divide Error 0 "| DIV, IDIV Exception Single Step 1 12**2 All Interrupt NMI 2 1 All Breakpoint 3 "4 (INT Interrupt INTO Detected 4 "4 INTO Overflow Exception Array Bounds 5 4 BOUND Exception Unused-Opcode 6 "4 Undefined Exception Opcodes ESC Opcode 7 ye** ESC Opcodes Exception Timer 0 Interrupt 8 2A**** Timer 1 Interrupt 18 2B**** Timer 2 Interrupt 19 2Cc**** Reserved 9 3 DMA 0 Interrupt 10 4 DMA 1 Interrupt 14 5 INTO Interrupt 12 6 INT1 interrupt 13 7 INT2 Interrupt +4 8 INT3. Interrupt 5 9 NOTES: *1. These are generated as the result of an instruction execution. **2. This is handied as in the 8088. ****3_ All three timers constitute one source of request to the interrupt controller. The Timer interrupts all have the same default priority level with respect to all other interrupt sources. However, they have a defined priority ordering amongst themselves. (Priority 2A is higher priority than 2B.) Each Timer interrupt has a separate vector type number. 4. Default priorities for the interrupt sources are used only if the user does not program each source into a unique priority level. An escape opcode will cause a trap only if the proper bit is set in the peripheral control block relocation register. bial) SINGLE-STEP INTERRUPT (TYPE 1) Generated after most instructions if the TF flag is set. Interrupts will not be generated after prefix instructions (e.g., REP), instructions which modify segment registers (e.g., POP DS), or the WAIT instruction. NON-MASKABLE INTERRUPT-NMI (TYPE 2) An external interrupt source which cannot be masked. BREAKPOINT INTERRUPT (TYPE 3) A one-byte version of the INT instruction. It uses 12 as an index into the service routine address table (because it is a type 3 interrupt).INTO DETECTED OVERFLOW EXCEPTION (TYPE 4) Generated during an INTO instruction if the OF bit is set. ARRAY BOUNDS EXCEPTION (TYPE 5) Generated during a BOUND instruction if the array index is outside the array bounds. The array bounds are located in memory at a location indicated by one of the instruction operands. The other operand indicates the value of the index to be checked. UNUSED OPCODE EXCEPTION (TYPE 6) Generated if execution is attempted on undefined opcodes. ESCAPE OPCODE EXCEPTION {TYPE 7) Generated if execution is attempted of ESC opcodes (D8H- DFH). This exception will only be generated if a bit in the relocation register is set. The return address of this exception will point to the ESC instruction causing the exception. If a segment override prefix preceded the ESC instruction, the return address will point to the segment override prefix. Hardware-generated interrupts are divided into two groups: maskable interupts and non-maskable interrupts. The 80188 provides maskable hardware interrupt request pins INTO- INT3. In addition, maskable interrupts may be generated by the 80188 integrated DMA controller and the integrated timer unit. The vector types for these interrupts is shown in Table 4. Software enables these inputs by setting the interrupt flag bit (IF) in the Status Word. The interrupt controller is discussed in the peripheral section of this data sheet. Further maskabie interrupts are disabled while servicing an interrupt because the IF bit is reset as part of the response to an interrupt or exception. The saved Status Word will reflect the enable status of the processor prior to the interrupt. The interrupt flag will remain zero unless specifically set. The interrupt return instruction restores the Status Word, thereby restoring the original status of IF bit. If the interrupt return re- enables interrupts, and another interrupt is pending, the 80188 will immediately service the highest-priority interrupt pending, i.e., no instructions of the main line program will be executed. Non-Maskable Interrupt Request (NMI) A non-maskable interrupt (NMI) is also provided. This interrupt is serviced regardless of the state of the fF bit. A typical use of NMI would be to activate a power failure routine. The activation of this input causes an interrupt with an internally supplied vector value of 2. No external interrupt acknowledge sequence is performed. The IF bit is cleared at the beginning of an NMI interrupt to prevent maskable interrupts from being serviced. Single-Step Interrupt The 80188 has an internal interrupt that allows programs to execute one instruction at a time. It is called the single-step interrupt and is controlled by the single-step flag bit (TF) in the Status Word. Once this bit is set, an internal single-step interrupt will occur after the next instruction has been execut- ed. The interrupt clears the TF bit and uses an internally supplied vector of 1. The IRET instruction is used to set the TF bit and transfer controi to the next instruction to be single- stepped. Initialization and Processor Reset Processor initialization or startup is accomplished by driving the RES input pin LOW. RES forces the 80188 to terminate all execution and local bus activity. No instruction or bus activity will occur as long as RES is active. After RES becomes inactive and an internal processing interval elapses, the 80188 begins execution with the instruction at physical location FFFFO(H). RES also sets some registers to predefined values as shown in Table 5. Table 5. 80188 Initial Register State after RESET Status Word FO002(H) Instruction Pointer 0000(H) Code Segment FFFF(H) Data Segment 0Q000(H) Extra Segment 0000(H) Stack Segment 0000(H) Relocation Register 20FF(H) UMCS FFFB(H) THE 80188 COMPARED TO THE 80186 The 80188 CPU is an 8-bit processor designed around the 80186 internal structure. Most internal functions of the 80188 are identical to the equivalent 80186 functions. The 80188 handles the external bus the same way the 80186 does with the distinction of handling only 8 bits at a time. Sixteen bit operands are fetched or written in two consecutive bus cycles. Both processors will appear identical to the software engineer, with the exception of execution time. The internal register structure is identical and all instructions have the same end result. The differences between the 80188 and 80186 are outlined below. internally, there are three differences between the 80188 and the 80186. All changes are related to the 8-bit bus interface. e@ The queue length is 4 bytes in the 80188, whereas the 80186 queue contains 6 bytes, or three words. The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions. This was required because of the additional time necessary to fetch instructions 8 bits at a time. @ To further optimize the queue, the prefetching algorithm was changed. The 80188 BIU will fetch a new instruction to load into the queue each time there is a 1-byte hole (space available) in the queue. The 80186 waits until a 2-byte space is available. @ The internal execution time of the instruction is affected by the 8-bit interface. All 16-bit fetches and writes from/to memory take an additional four clock cycles. The CPU may also be limited by the speed of instruction fetches when a series of simple operations occurs. When the more sophis- ticated instructions of the 80188 are being used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow. The 80188 and 80186 are completely software compatibie by virtue of their identical execution units. Software that is system dependent may not be completely transferable, but software that is not system dependent will operate equally weil on an 80188 or an 80186. The hardware interface of the 80188 contains the major differences between the two CPUs. The pin assignments are nearly identical, however, with the following functional changes. @ A8-A15These pins are only address outputs on the 80188. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines. @ BHE has no meaning on the 80188 and has been eliminated. 4380188 CLOCK GENERATOR The 80188 provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide-by-two counter, synchro- nous and asynchronous ready inputs, and reset circuitry. Oscillator The oscillator circuit of the 80188 is designed to be used with a parallel resonant fundamental mode crystal. This is used as the time base for the 80188. The crystal frequency selected will be double the CPU clock frequency. Use of an LC or RC circuit is not recommended with this oscillator. If an external oscialltor is used, it can be connected directly to input pin X1 in lieu of a crystal. The output of the oscillator is not directly available outside the 80188. The recommended crystal contig- uration is shown in Figure 7. + 20 pF x, = C X MHz CRYSTAL X 80188 = 20 pF TC001852 X= 20 for 10 MHz (80188-1) X= 16 for 8 MHz (801B8-3) X = 12 for 6 MHz (801B8-6) Figure 7. Recommended 80188 Crystal Configuration Clock Generator The 80188 clock generator provides the 50% duty cycle processor clock for the 80188. It does this by dividing the oscillator output by 2 forming the symmetrical clock. If an external oscillator is used, the state of the clock generator will change on the falling edge of the oscillator signal. The CLKOUT pin provides the processor clock signal for use outside the 80188. This may be used to drive other system components. All timings are referenced to the output clock. READY Synchronization The 80188 provides both synchronous and asynchronous ready inputs. Asynchronous ready synchronization is accom- plished by circuitry which samples ARDY in the middle of To, Tg and again in the middle of each Ty until ARDY is sampled HIGH. One-half CLKOUT cycle of resolution time is used. Full synchronization is performed only on the rising edge of ARDY, i.e., the falling edge of ARDY must be synchronized to the CLKOUT signal if it will occur during To or Tw. HIGH-to-LOW transitions of ARDY must be performed synchronously to the CPU clock. A second ready input (SRDY) is provided to interface with externally synchronized ready signals. This input is sampled at the end of Ta and again at the end of each Tw until it is sampled HIGH. By using this input rather than the asynchro- nous ready input, the half-clock cycle resolution time penalty is eliminated. This input must satisfy set-up and hold times to guarantee proper operation of the circuit. In addition, the 80188, as part of the integrated chip-select logic, has the capability to program WAIT states for memory and peripheral blocks. This is discussed in the Chip Select/ Ready Logic description. RESET Logic The 80188 provides both a RES input pin and a synchronized RESET pin for use with other system components. The RES input pin on the 80188 is provided with hysteresis in order to facilitate power-on Reset generation via an RC network. RESET is guaranteed to remain active for at least five clocks given a RES input of at least six clocks. RESET may be delayed up to two and one-half clocks behind RES. Multiple 80188 processors may be synchronized through the RES input pin, since this input resets both the processor and divide-by-two internal counter in the clock generator. In order to insure that the divide-by-two counters all begin counting at the same time, the active going edge of RES must satisfy a 25 ns setup time before the failing edge of the 80188 clock input. In addition, in order to insure that all CPUs begin executing in the same clock cycle, the reset must satisfy a 25 ns setup time before the rising edge of the CLKOUT signal of all the processors. LOCAL BUS CONTROLLER The 80188 provides a local bus controller to generate the local bus control signals. In addition, it employs a HOLD/HLDA protocol for relinquishing the local bus to other bus masters. It also provides control lines that can be used to enable external buffers and to direct the flow of data on and off the local bus. Memory/Peripheral Control The 80188 provides ALE, RD, and WR bus control signals. The RD and WR signals are used to strobe data from memory to the 80188 or to strobe data from the 80188 to memory. The ALE line provides a strobe to address latches for the multi- plexed address/data bus. The 80188 local bus controller does not provide a memory/I/O signal. If this is required, the user will have to use the $2 signal (which will require external latching), make the memory and I/O spaces nonoverlapping, or use only the integrated chip-select circuitry. Transceiver Control The 80188 generates two control signals to be connected to 2946/2947 transceiver chips. This capability allows the addi- tion of transceivers for extra buffering without adding external logic. These control lines, DT/R and DEN, are generated to control the flow of data through the transceivers. The opera- tion of these signals is shown in Table 6. Table 6. Transceiver Control Signals Description Pin Name Function EN (Data Enable) Enables the output drivers of the transceivers. It is active LOW during memory, I/O, or INTA cycles, Determines the direction of trav- el through the transceivers. A HIGH level directs data away from the processor during write operations, while a LOW level directs data toward the proces- sor during a read operation. OT/R (Data Transmit/ Receive) 14Local Bus Arbitration The B0188 uses a HOLD/HLDA system of local bus ex- change. This provides an asynchronous bus exchange mecha- nism. This means multiple masters utilizing the same bus can operate at separate clock frequencies. The 80188 provides a single HOLD/HLDA pari through which all other bus masters may gain cotnrol of the local bus. This requires external circuitry to arbitrate whcih external device will gain control of the bus from the 80188 when there is more than one alternate local bus master. When the 80188 relinquishes control of the A19, S7 and DT/R to allow another master to drive these lines directly. The 80188 HOLD latency time, i.e., the time between HOLD request and HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is re- ceived. A HOLD request is the highest-priority activity request which the processor may receive: higher than instruction fetching or internal DMA cycles. However, if a DMA cycle is in progress, the 80188 will complete the transfer before relin- quishing the bus. This implies that if a HOLD request is received just as a DMA transfer begins, the HOLD latency time can be as great as 4 bus cycles. This will occur if a OMA word transfer operation is taking place from an odd address to an odd address. This is a total of 16 clocks or more, if WAIT states are required. In addition, if locked transfers are per- formed, the HOLD latency time will be increased by the length of the locked transfer. Local Bus Controller and Reset Upon receipt of a RESET pulse from the RES input, the local bus controller will perform the following actions: @ Drive DEN, RD, and WR HIGH for one clock cycle, then float. NOTE: RE is also provided with an internal pull-up de- vice to prevent the processor from inadvertently enter- ing Queue Status mode during reset. Drive SO-S2 to the passive state (all HIGH) and then float. Drive LOCK HIGH and then float. Tristate ADO-AD7, A8-A19, S7, DT/R @ Drive ALE LOW (ALE is never floated). @ Drive HLDA LOW. INTERNAL PERIPHERAL INTERFACE All the 80188 integrated peripherals are controiled via 16-bit registers contained within an internal 256-byte contro! block. This control block may be mapped into either memory or 1/O space. Internal logic will recognize the address and respond to the bus cycle. During bus cycles to internal registers, the bus controller will signal the operation externally (e., the RD, WR, status, address, data, etc., lines will be driven as in a normal bus cycle), but D7.9, SRDY, and ARDY will be ignored. The base address of the control block must be on an even 256- byte boundary (i.e., the lower 8 bits of the base address are all zeros). All of the defined registers within this control block may be read or written by the 80186 CPU at any time. The location of any register contained within the 256-byte control block is determined by the current base address of the control block. The control block base address is programmed via a 16-bit relocation register contained within the control block at offset FEH from the base address of the control block (see Figure 8). It provides the upper 12 bits of the base address of the control block. Note that mapping the control register block into an address range corresponding to a chip-select range is not recommended (the chip select circuitry is discussed later in this date sheet). In addition, bit 12 of this register determines whether the control block will be mapped into 1/O or memory space. If this bit is 1, the contro! block will be located in memory space, whereas if the bit is 0, the control block will be located in I/O space. If the control register block is mapped into 1/O space, the upper 4 bits of the base address must be programmed as 0 (since I/O addresses are only 16 bits wide). In addition to providing relocation information for the control block, the relocation register contains bits which place the interrupt controller into IRMX mode, and cause the CPU to interrupt upon encountering ESC instructions. At RESET, the relocation register is set to 20FFH. This causes the control black to start at FFOOH in I/O space. An offset map of the 256- byte contro! register block is shown in Figure 9. The integrated 80188 peripherals operate semiautonomously from the CPU. Access to them for the most part is via software read/write of the control and data locations in the control block. Most of these registers can be both read and written. A few dedicated lines, such as interrupts and DMA request provide real-time communication between the CPU and pe- ripherals as in a more conventional system utilizing discrete peripheral blocks. The overall interaction and function of the peripheral blocks has not substantially changed. CHIP-SELECT/READY GENERATION LOGIC The 80188 contains logic which provides programmable chip- select generation for both memories and peripherals. In addition, it can be programmed to provide READY (or WAIT state) generation. It can also provide latched address bits At and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they be generated by the CPU or by the integrated DMA unit. Memory Chip Selects The 80188 provides 6 memory chip select outputs for 3 address areas: upper memory, lower memory, and midrange memory. One each is provided for upper memory and lower memory, while four are provided for midrange memory. The range for each chip select is user-programmable and can be set to 2K, 4K, 8K, 16K, 32K, 64K, 128K (plus 1K and 256K for upper and lower chip selects). In addition, the beginning or base address of the midrange memory chip select may also be selected. Only one chip select may be programmed to be active for any memory location at a time. All chip select sizes are in bytes, whereas 80188 memory is arranged in words. This means that if, for example, 16 64K x 1 memories are used, the memory block size will be 128K, not 64K. 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 OFFSET: FEH| ET [RMX| | M/IO| ET =ESC Trap/No ESC Trap (1/0) Relocation Address Bits R19 - R& M/IO = Register block located in Memory / I/O Space (1/0) RMX = Normal Interrupt Controller mode / IRMX compatible Interrupt Controller mode (0/1)Figure 8. Relocation Register OFFSET Relocation Register FEH : DAH DMA Descriptors Channel 1 DOH . CAH DMA Descriptors Channel 0 COH . . A8H Chip-Select Control Registers AOH : . 66H Timer 2 Control Registers 60H . . 5EH Timer 1 Control Registers 58H : : 56H Timer 0 Control Registers 50H : 3EH Interrupt Controller Registers 20H Figure 9. Internal Register Map Upper Memory CS The 80188 provides a chip select, called UCS, for the top of memory. The top of memory is usually used as the system memory because after reset the 80188 begins executing at memory location FFFFOH. The upper limit of memory defined by this chip select is always FFFFFH, while the lower limit is programmable. By program- ming the lower limit, the size of the select block is also defined. Table 7 shows the relationship between the base address selected and the size of the memory block obtained. Table 7. UMCS Programming Values Starting Address Memory UMCS Value (Base Block (Assuming Address) Size RO = R1= R2 = 0) FFCOO 1K FFFBH FF800 2K FFB8H FFOOO 4k FF38H FEOoo 8K FE38H FCooo 16K FC38H Fs8000 32K F838H Foooo 64K F038H E0000 128K E03BH coo000 256K C038H The lower limit of this memory block is defined in the UMCS register (see Figure 10). This register is at offset AOH in the internal control block. The legal values for bits 6-13 and the resulting starting address and memory block sizes are given in Table 7. Any combination of bits 6-13 not shown in Table 7 will result in undefined operation. After reset, the UMCS register is programmed for a 1K area. It must be reprogrammed if a larger upper memory area is desired. Any internally generally 20-bit address whase upper 16-bits are greater than or equal to UMCS (with bits 0-5 ''0"') will cause UCS to be activated. UMCS bits R2-RO are used to specify READY mode for the area of memory defined by this chip-select register, as explained below. Lower Memory CS The 80188 provides a chip select for low memory called LCS. The bottom of memory contains the interrupt vector table, starting at location O0000H. The lower limit of memory defined by this chip select is always 0H, while the upper limit is programmable. By programming the upper limit, the size of the memory block is also defined. Table 8 shows the relationship between the upper address selected and the size of the memory block obtained. Table 8 LMCS Programming Values Memory LMCS Value Upper Block (Assuming Address Size RO =R1= R2=0) O003FFH 1K 0038H 007FFH 2K 0078H OOFFFH 4K OOF8H 0O1FFFH 8K 01F8H O3FFFH 16K 03F8H 07FFFH 32K 07F8H OFFFFH 64K OFF8H 1FFFFH 128K 1FF8H 3FFFFH 256K SFF8H The upper limit of this memory block is defined in the LMCS register (see Figure 11). This register is at offset A2H in the internal control block. The legal values for bits 6-15 and the resulting upper address and memory block sizes are given in Table 8. Any combination of bits 6-15 not shown in Table 8 will result in undefined operation. After reset, the LMCS register value is undefined. However, the LCS chip-select line will not become active until the LMCS register is accessed. Any internally generated 20-bit address whose upper 16 bits are jess than or equal to LMCS (with bits 0-5 ''1"') will cause UCS to be active. LMCS register bits R2-RO are used to specify the READY mode for the area of memory defined by this chip-select register. Mid-Range Memory CS The 80188 provides four MCS lines which are active within a user-locatable memory block. This block can be located anywhere within the 80188 1M byte memory address space exclusive of the areas defined by UCS and LCS. Both the base address and size of this memory block are programmable. The size of the memory block defined by the midrange select lines, as shown in Table 9, is determined by bits 8-14 of the MPCS register (see Figure 12). This register is at location ASH in the internal control block. One and only one of bits 8-14 must be set at a time. Unpredictable operation of the MCS lines will otherwise occur. Each of the four chip-select lines is active for one of the four equal contiguous divisions of the mid- range block. Thus, if the total block size is 23K, each chip select is active for 8K of memory with MCSO being active for the first range and MCS3 being active for the last range. The EX and MS in MPCS relate to peripheral functionally as described in a later section.Table 9. MMCS Programming Values The base address of the mid-range memory block is defined by bits 15-9 of the MMCS register (see Figure 13). This register is at offset AGH in the internal contro! block. These bits correspond to bits A19-A13 of the 20-bit memory address. Bits A12-A0 of the base address area always 0. The base address may be set at any integer multiple of the size of the total memory block selected. For example, if the midrange block size is 32K (or the size of the block for which each MCS line is active is 8K), the block could be located at 10000H or 18000H, but not at 14000H, since the first few integer multiples of a 32K memory block are 0H, 8000H, 10000H, 18000H, etc. After reset, the contents of both of these registers is undefined. However, none of the MGS lines will be active until both the MMCS and MPCS registers are accessed. Total Block Individual MNCS Bits Size Select Size 14-8 8K 2K 0000001B 16K 4K 00000108 32K 8K 0000100B 64K 16K 0001000B 128K 32K 00100008 256K 64K 0100000B 512K 128K 10000008 15 14 13 12 af] 10 9 8 7 6 5 4 3 2 1 0 orrset: aoH[ i [1 [utulufuftufujut{uj{ili] = [ R2 | Ri | RO | AI9 Att Figure 10. UMCS Register 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 orrset:aeHf oo ]ofTululutlui[utufufu[+[i]i [retro | A19 Att Figure 11. LMCS Register 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET: A8H | 1 [ me | ms | m4 | ms | m2 | m1 | Mo | ex | Ms | 1 [1 | _ [ R2 | Rt | Ro | Figure 12. MPCS Register 15 9 3 0 orrser: acH[u]u[ul[ulu[u[u]1[+][1]1][4] 14 [re]ar| ro] A19 A13 Figure 13. MMCS Register MMCS bits A2-RO specify READY mode of operation for all mid-range chip selects. All devices in mid-range memory must use the same number of WAIT states. The 512K block size for the mid-range memory chip selects is a special case. When using 512K, the base address would have to be at either locations OO000H or 80000H. if it were to be programmed at O00000H when the LCS line was pro- grammed, there would be an internal conflict between the tts ready generation logic and the MCS ready generation logic. Likewise, if the base address were programmed at 80000H, there would be a conflict with the UCS ready generation logic. Since the LCS chip-select line does not become active until programmed, while the UCS line is active at reset, the memory base can be set only at OOOOOH. If this base address is selected, however, the LCS range must not be programmed. Peripheral Chip Selects The 80188 can generate chip selects for up to seven peripheral devices. These chip selects are active for seven contiguous blocks of 128 bytes above a programmable base address. This base address may be located in either memory or I/O space. Seven CS lines called PCS0-6 are generated by the 80188. The base address is user-programmable; however it can only be a multiple of 1K bytes, i.e., the least significant 10 bits of the starting address are always 0. PCS5 and PCS6 can also be programmed to provide latched address bits A1, A2. If so programmed, they cannot be used as peripheral selects. These outputs can be connected directly to the AO, A1 pins used for selecting internal registers of 8-bit peripheral chips. This scheme simplifies the hardware interface because the 8-bit registers of peripherals are simply 17treated as 16-bit registers located on even boundaries in I/O space or memory space where only the lower 8-bits of the register are significant: the upper 8-bits are 'don't cares. The starting address of the peripheral chip-select block is defined by the PACS register (see Figure 14). This register is located at offset A4H in the internal control block. Bits 15-6 of this register correspond to bits 19-10 of the 20-bit Programma- ble Base Address (PBA) of the peripheral chip-select block. Bits 9-0 of the PBA of the peripheral chip-select block are all zeros. if the chip-select block is located in I/O space, bits 12- 15 must be programmed zero, since the I/O address is only 16 bits wide. Table 10 shows the address range of each peripheral chip select with respect to the PBA contained in PACS register. 15 6 5 3 0 orrset: aH{ u | ufufululututuflufu]fifi1]1 [rej ar| ao] A19 A10 Figure 14. PACS Register The user should program bits 15-6 to correspond to the desired peripheral base location. PACS bits 0-2 are used to specify READY mode for PCS0-PCS3. Table 10. PCS Address Ranges READY control consists of 3 bits for each CS line or group of lines generated by the 80188. The interpretation of the ready bits is shown in Table 12. Table 12. READY Bits Programming PCS Line Active between Locations R2|RA1) RO Number of WAIT States Generated PCSO PBA PBA + 127 0o;o {0 0 wait states, external RDY also used. PCS1 PBA + 128 PBA + 255 o;o;71 1 wait state inserted, external RDY also PCS2 PBA + 256 PBA + 383 used. PCS3 PBA + 384 PBA + 511 Oo; 1,0 2 wait states inserted, external RDY also PCS4 PBA + 512 PBA + 639 used. PCSs5 PBA + 640 PBA + 767 Oo;4)1 3 wait states inserted, external ARDY also PGS6 PBA + 768 PBA + 895 used. 1; 0; 0 0 wait states, external RDY ignored. The mode of operation of the peripheral chip selects is defined 1/0 }1 1 wait state inserted, external RDY by the MPCS register (which is also used to set the size of the ignored. mid-range memory chip-select block, see Figure 15). This 1/11/90 2 wait states inserted, external RDY ig- register is located at offset A8H in the internal control block. nored. Bit 7 is used to select the function of PCS5 and PCS6, while bit 1) 1]1 3 wait states inserted, external RDY ig- 6 is used to select whether the peripheral chip selects are nored. mapped into memory or I/O space. Table 11 describes the programming of these bits. After reset, the contents of both the MPCS and the PACS registers are undefined, however none of the PCS lines will be active until both of the MPCS and PACS registers are accessed. Table 11. MS, EX Programming Values Bit Description MS 1 = Peripherals mapped into memory space. 0 = Peripherals mapped into I/O space. Ex 0=5 PCS lines. Ai, A2 provided. 1=7 PCS lines. A1, A2 are not provided. MPCS bits 0-2 are used to specify READY mode for PCS4- PCS6 as outlined below. READY Generation Logic The 80188 can generate a 'READY"' signal internally for each of the memory or peripheral CS fines. The number of WAIT states to be inserted for each peripheral or memory is programmable to provide 0-3 wait states for all accesses to the area for which the chip select is active. In addition, the 80188 may be programmed to either ignore external READY for each chip- select range individually or to factor external READY with the integrated ready generator. The internal ready generator operates in parallel with external READY, not in series if the external READY is used (R2 = 0). This means, for example, if the internal generator is set to insert two wait states, but activity on the external READY lines will insert four wait states, the processor will only insert four wait states, not six. This is because the two wait states generated by the internal generator overlapped the first two wait states generated by the external ready signal. Note that the external ARDY and SRDY lines are always ignored during cycles accessing internal peripherals. R2-RO of each control word specifies the READY mode for the corresponding block, with the exception of the peripheral chip selects: R2-RO of PACS set the PCSO-3 READY mode, R2-R0 of MPCS set the PCS4-6 READY made. Chip Select/Ready Logic and Reset Upon reset, the Chip-Select/Ready Logic will perform the following actions: All chip-select outputs will be driven HIGH. Upon leaving RESET, the UCS line will be programmed to provide chip selects to a 1K block with the accompanying READY control bits set at 011 to allow the maximum number of internal wait states in conjunction with external Ready consideration (i.e. UMCS resets to FFFBH).15 14 1312 444*10:'i ke iB OTCUGLCUCBC KB OFFSET: asH| 1 | Me] M5 |M4[m3[m2]Mi[mol[ex[ ms] 1] 1] 1 | R2| At | Ro | Figure 15. MPCS Register @ No other chip select or READY control registers have any consist of a 20-bit Source pointer (2 words), a 20-bit Destina- predefined values after RESET. They will not become tion pointer (2 words), a 16-bit Transfer Counter, and a 16-bit active until the CPU accesses their control registers. Both Control Word. The format of the DMA Control Blocks is shown the PACS and MPCS registers must be accessed before in Table 13. The Transfer Count Register (TC) specifies the the PCS lines will become active. number of DMA transfers to be performed. Up to 64K byte or word transfers can be performed with automatic termination. DMA CHANNELS The Control Word defines the channel's operation (see Figure 17). All registers may be modified or altered during any DMA activity. Anyi changes made to these registers will be reflected immediately in DMA operation. The 80188 DMA controller provides two independent high- speed DMA channels. Data transfers can occur between memory and i/O spaces (e.g., Memory to |/O) or within the same space (e.g., Memory to Memory or I/O to I/O). Data can be transferred either in bytes (8 bits) or in words (16 bits) to or from even or odd addresses. Each DMA channel maintains Table 13. DMA Control Block Format both a 20-bit source and destination pointer which can be optionally incremented or decremented after each data trans- Register Address fer (by one or two depending on byte or word transfers). Each Register Name Ch. 0 | Ch. 1 data transfer consumes two bus cycles (a minimum of eight Control Word CAH DAH clocks), one cycle to fetch data and the other to store data. Transfer Count C8H D8H This provides a maximum data transfer rate of one Mword/sec Destination Painter (upper 4 bits) C6H D6H or 2 MBytes/sec. Destination Pointer C4H D4H . Source Pointer (upper 4 bits) G2H D2H DMA Operation Source Pointer COH DOH Each channel has six registers in the control block which define each channel's specific operation. The control registers 20 BIT ADDER/SUBTRACTOR ADDER CONTROL LOGIC TIMER REQUEST ora1 ry REQUEST SELECTION | TRANSFER COUNTER CH. 1 Loic ry DEST. ADRS. POINTER CH. 1 SRC. ADRS. POINTER CH. 1 DMA CONTROL | TRANSFER COUNTER CH. 0 toaie DEST. ADRS. POINTER CH. 0 SRC. ADRS. POINTER CH. 0 it CHANNEL CONTROL WORD 1 CHANNEL CONTROL WORD 0 < INTERNAL ADDRESS/DATA BUS BD003570 Figure 16. DMA Unit Block Diagram 1918 14 13 421+2C*YAstiatiBHCCCU CK 1 0 T M/ DESTINATION| M/ SOURCE D cues | stv | 8/ jo DEC INC| lO Dec inc | TC |INT] SYN | P| 2 | X |NocHG] STOP | w Q X= DON'T CARE Figure 17. DMA Control Register DMA Channel Control Word Register Each DMA Channel Control Word determines the mode of operation for the particular 80188 DMA channel. This register specifies: @ the mode of synchronization, @ whether bytes or words will be transferred; @ whether interrupts will be generated after the last transfer; whether DMA activity will cease after a programmed number of DMA cycles; the relative priority of the DMA channel with respect to the other DMA channel; whether the source pointer will be incremented, decrement- ed, or maintained constant after each transfer; whether the source pointer addresses memory or I/O space; whether the destination pointer will be incremented, dec- remented, or maintained constant after each transfer; and whether the destination pointer will address memory or I/O space. The DMA channel control registers may be changed while the channel is operating. However, any changes made during operation will affect the current DMA transfer. DMA Control Word Bit Descriptions BW: ST/STOP: CHG/NOCHG: Byte/Word (0/1) Transfers. Start/stop (1/0) Channel. Change/Do not change (1/0) ST/ STOP bit. If this bit is set when writing to the control word, the ST/STOP bit will be programmed by the write to the control word. If this bit is cleared when writing the control word, the ST/STOP bit will not be altered. This bit is not stored; it will always be a 0 on read. Enable Interrupts to CPU on byte count termination. INT: TC: lf set, DMA will terminate when the contents of the Transfer Count register reach zero. The ST/STOP bit will also be reset at this point if TC is set. If this bit is cleared, the DMA unit will decrement the transfer count register for each DMA cycle, but the DMA transfer will not stop when the contents of the TC register reach zero. SYN: (2 bits) 00 No synchronization NOTE: The ST bit will be cleared automatically when the contents of the TC register reach zero re gardless of the state of the bit. 01 Source synchronization. 10 Destination synchronization. 11 Unused. SOURCE: INC Increment source pointer by 1 or 2 (depends on B/W) after each transfer. M/10 Source pointer is in M/IO space (1/ 0). Decrement source pointer by 1 or 2 (depends on B/W) after each transfer. DEC DEST: INC Increment destination pointer by 1 or 2 (B/W) after each transfer. Destination pointer is in M/IO space (1/0). Decrement destination pointer by 1 or 2 (depending on B/W) after each transfer. DEC Channe! priority-relative to other channel. 0 low priority. 1 high priority. Channels will alternate cycles if both set at same priority level. TDRQ 0: Disable DMA requests from timer 2. 1: Enable DMA requests from timer 2. Bit 3 Bit 3 is not used. If both INC and DEC are specified for the same pointer, the pointer will remain constant after each cycle. DMA Destination and Source Pointer Registers Each DMA channel maintains a 20-bit source and a 20-bit destination pointer. Each of these pointers takes up two full 16-bit registers in the peripheral control block. The lower four bits of the upper register contain the upper four bits of the 20- bit physical address (see Figure 18). These pointers may be individually incremented or decremented after each transfer. If word transfers are performed the pointer is incremented or decremented by two. Each pointer may point into either memory or I/O space. Since the DMA channels can perform transfers to or from odd addresses, there is no restriction on values for the pointer registers. Higher transfer rates can be obtained if all word transfers are performed to even ad- 20dresses, since this will allow data to be accessed in a single memory access. DMA Transfer Count Register Each DMA channel! maintains a 16-bit transfer count register (TC). This register is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA Control Register. If the TC bit in the DMA control word is set, however, DMA activity will terminate when the transfer count register reaches zero. DMA Requests Data transfers may be either source or destination synchro- nized, that is either the source of the data or the destination of the data may request the data transfer. In addition, DMA transfers may be unsynchronized; that is, the transfer will take place continually until the correct number of transfers has occurred. When source or unsynchronized transfers are per- formed, the DMA channel may begin another transfer immedi- ately after the end of a previous DMA transfer. This allows complete transfer to take place every 2 bus cycles or eight clock cycles (assuming no wait states). No prefetching occurs when destination synchronization is performed, however. Data will not be fetched from the source address until the destina- tion device signatls that it is ready to receive it. When destination synchronized transfers are requested, the DMA controller will relinquish control of the bus after every transfer. lf no other bus activity is initiated, another DMA cycle will begin after two processor clocks. This is done to allow the destination device time to remove its request if another transfer is not desired. Since the DMA controller will relinquish the bus, the CPU can initiate a bus cycle. As a result, a complete bus cycle will often be inserted between destination synchronized transfers. These lead to the maximum DMA transfer rates shown in Table 14. Table 14. Maximum DMA Transfer Rates with 8 MHz 80188 Type of Synchronization CPU Running CPU Halted Selected Unsynchronized 1 Mbytes/sec 1 Mbytes/sec Source Synch 1 Mbytes/sec 1 Mbytes/sec Destination Synch .65 Mbytes/sec | .75 Mbytes/sec HIGHER REGISTER ADDRESS XXX XXX XXX A19-A16 LOWER REGISTER ADDRESS A15-A12 A11-A8 A7-A4 A3- AO 15 XXX = DON'T CARE Figure 18. DMA Memory Pointer Register Format DMA Acknowledge No explicit DMA acknowledge pulse is provided. Since both source and destination pointers are maintained, a read from a requesting source, or a write to a requesting destination, should be used as the DMA acknowledge signal. Since the chip-select lines can be programmed to be active for a given block of memory or 1/O space, and the DMA pointers can be programmed to point to the same given block, a chip-select line could be used to indicate a DMA acknowledge. DMA Priority The DMA channels may be programmed such that one channel is always given priority over the other, or they may be programmed such as to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles except between locked memory accesses or word accesses the odd memory locations; however, an external bus hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA opera- tion and the CPU cannot access memory during a DMA cycle, interrupt latency time will suffer during sequences of continu- ous DMA cycles. An NMI request, however, will cause all internal DMA activity to hait. This aliows the CPU to quickly respond to the NMI request. DMA Programming DMA cycles will occur whenever the ST/STOP bit of the Control Register is set. If synchronized transfers are programmed, a DRQ must aiso have been generated. Therefore, the source and destination transfer pointers, and the transfer count register (if used) must be programmed before this bit is set. Each DMA register may be modified while the channel is operating. If the CHG/NOCHG bit is cleared when the control register is written, the ST/STOP bit of the control register will not be modified by the write. If multiple channel registers are modified, it is recommended that a LOCKED string transfer be used to prevent a DMA transfer fram occurring between updates to the channel registers. DMA Channels and Reset Upon RESET, the DMA channels will perform the following actions: @ The Start/Stop bit for each channel will be rest to STOP. @ Any transfer in progress is aborted. TIMERS The 80188 provides three internal 16-bit programmable timers (see Figure 19). Two of these are highly flexible and are connected to four external pins (2 per timer). They can be used to count external events, time external events, generate nonrepetitive waveforms, etc. The third timer is not connected to any external pins, and is usefut for real-time coding and time delay applications. In addition, this third timer can be used as a prescaler to the other two, or as a DMA request source. 21@ @ TINY 11 DMA Nee Saget] IN UT, REQ. To Tt T2 INT. > INT. INT. REQ. REQ. REQ. 12 OUT TIMER 0 TIMER 1 MAX COUNT VALUE | MAX COUNT VALUE TIMER 2 A A CLOCK MAX counT VALUE MAX counr VALUE MAX COUNT VALUE MODE/CONTROL MODE/CONTROL MODE/CONTROL WORD WORD WORD > INTERNAL ADDRESS/DATA BUS ALL 16 SIT REGISTERS 8D003580 Figure 19. Timer Block Diagram Timer Operation The timers are controlled by 11 16-bit registers in the internal peripheral controt block. The configuration of these registers is shown in Table 15. The count register contains the current value of the timer. It can be read or written at any time independent of whether the timer is running or not. The value of this register will be incremented for each timer event. Each of the timers is equipped with a MAX COUNT register, which defines the maximum count the timer will reach. After reaching the MAX COUNT register value, the timer count value will reset to zero during that same clock, i.e., the maximum count value is never stored in the count register itself. Timers 0 and 1 are, in addition, equipped with a second MAX COUNT register, which enables the timers to alternate their count between two different MAX COUNT values programmed by the user. If a single MAX COUNT register is used, the timer output pin will switch LOW for a single clock, two clocks after the maximum count value has been reached. In the dual MAX COUNT register mode, the output pin will indicate which MAX COUNT register is currently in use, thus allowing nearly complete freedom in selecting waveform duty cycles. For the timers with two MAX COUNT registers, the RIU bit in the control register determines which is used for the comparison. Since the count registers and the maximum count registers are all 16-bits wide, 16 bits of resolution are provided. Any Read or Write access to the timers will add one wait state to the minimum four-clock bus cycle. However, this is needed to synchronize and coordinate the internal data flows between the internal timers and the internal bus. The timers have several programmable options. @ All three timers can be set to halt or continue on a terminal count. @ Timers 0 and 1 can select between internal and external clocks, alternate between MAX COUNT registers and be set to retrigger on external events. @ The timers may be programmed to cause an interrupt on terminal count. These options are selectable via the timer mode/control word. Timer Mode/Control Register The mode/control register (see Figure 20) allows the user to program the specific mode of operation or check the current programmed status for any of the three integrated timers. Table 15. Timer Control Block format Each timer gets serviced every fourth CPU-clock cycle, and ji thus can operate at speeds up to one-quarter the internal Register Offset clock frequency (one-eighth the crystal rate). External clocking Register Name Tmr. 0) Tmr. 1 Tmr. 2 of the timers may be done at up to a rate of one-quarter of the internal CPU-clock rate (2 MHz for an 8 MHz CPU clock). Due Mode eo Word oon cen not Or ent to internal synchronization and pipelining of the timer circuitry, Max Count A 52H 5AH bon a timer output may take up to six clocks to respond to any Count Redister 50H 58H 60H individual clock or gate input. g 15 14 13 42 1 5 4 3 2 1 0 [en [inh [ nt [ru] o |... | mc | RTG| P | ext | ALT [cont] Figure 20. Timer Mode/Control Register 22ALT: The ALT bit determines which of two MAX COUNT registers is used for count comparison. If ALT = 0, register A for that timer is always used, while if ALT = 1, the comparison will alternate between register A and register B when each maximum count is reached. This alternation allows the user to change one MAX COUNT register while the other is being used, and thus provides a method of generating nonrepetitive waveforms. Square waves and pulse outputs of any duty cycle are a subset of available signals obtained by not changing the final count registers. The ALT bit also determines the function of the timer output pin. If ALT is zero, the output pin will go LOW for one clock, the clock after the maximum count is reached, If ALT is one, the output pin will reflect the current MAX COUNT register being used (0/1 for B/A). CONT: Setting the CONT bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon maximum count. lf CONT = 0 and ALT = 1, the timer will count to the MAX COUNT register A value, reset, count to the register B value, reset, and halt. EXT: The external bit selects between internat and external clocking for the timer. The external signal may be asynchronous with respect to the 80188 clock. If this bit is set, the timer will count LOW-to-HIGH transitions on the input pin. If cleared, it will count an internal clock while using the input pin for control. In this mode, the function of the external pin is defined by the RTG bit. The maximum input to output transition latency time may be as much as 6 clocks. However, clock inputs may be pipelined as closely together as every four clocks without losing clock pulses. P: The prescaler bit is ignored unless internal clocking has been selected (EXT = 0). If the P bit is a zero, the timer will count at one-fourth the internal CPU clock rate. If the P bit is a one, the output of timer 2 will be used as a clock for the timer. Note that the user must initialize and start timer 2 to obtain the prescaled clock. RTG: Retrigger bit is only active for internal clocking (EXT = 0). In this case it determines the control function provided by the input pin. lf RTG = 0, the input level gates the internal clock on and off. if the input pin is HIGH, the timer will count; if the input pin is LOW, the timer will hold its value. As indicated previously, the input signal may be asynchronous with respect to the B0188 clock. When RTG = 1, the input pin detects LOW-to-HIGH transi- tions. The first such transition starts the timer running, clearing the timer value to zero on the first clock, and then increment- ing thereafter. Further transitions on the input pin will again reset the timer to zero, from which it will start counting up again. If CONT = 0, when the timer has reached maximum count, the EN bit will be cleared, inhibiting further timer activity. EN: The enable bit provides programmer control over the timer's RUN/HALT status. When set, the timer is enabled to incre- ment subject to the input pin constraints in the internal clock mode (discussed previously). When cleared, the timer will be inhibited from counting. All input pin transitions during the time EN is zero will be ignored. if CONT is zero, the EN bit is automatically cleared upon maximum count. INH: The inhibit bit allows for selective updating of the enable (EN} bit. If INH is a one during the write to the mode/control word, then the state of the EN bit will be modified by the write. If INH is a zero during the write, the EN bit will be unaffected by the operation. This bit is not stored; it will always be a 0 on a read. INT: When set, the INT bit enables interrupts from the timer, which will be generated on every terminal count. {f the timer is configured in dual MAX COUNT register mode, an interrupt will be generated each time the value in MAX GOUNT register A is reached, and each time the value in MAX COUNT register B is reached. If this enable bit is cleared after the interrupt request has been generated, but before a pending interrupt is ser- viced, the interrupt request will still be in force. (The request is latched in the Interrupt Controller.) MC: The Maximum Count bit is set whenever the timer reaches its final maximum count value. If the timer is configured in dual MAX COUNT register mode, this bit will be set each time the value in MAX COUNT register A is reached, and each time the value in MAX COUNT register B is reached. This bit is set regardless of the timer's interrupt-enable bit. The MC bit gives the user the ability to monitor timer status through software instead of through interrupts. RIU: The Register In Use bit indicates which MAX COUNT register is currently being used for comparison to the timer count value. A zero value indicates register A. The RIU bit cannot be written, i.e., its value is not affected when the control register is written. It is always cleared when the ALT bit is zero. Not all mode bits are provided for timer 2. Certain bits are hardwired as indicated below: ALT =0, EXT=0, P=0, ATG=0, RIU=0 Count Registers Each of the three timers has a 16-bit count register. The current contents of this register may be read or written by the processor at any time. if the register is written into while the timer is counting, the new value will take effect in the current count cycle. Max Count Registers Timers 0 and 1 have two MAX COUNT registers, while timer 2 has a single MAX COUNT register. These contain the number of events the timer will count. In timers 0 and 1, the MAX COUNT register used can alternate between the two max count values whenever the current maximum count is reached. The condition which causes a timer to reset is equivalent between the current count value and the max count being used. This means that if the count is changed to be above the max count value, or if the max count value is changed to be below the current value, the timer will not reset to zero, but rather will count to its maximum value, wrap around to zero, then count until the max count is reached. Timers and Reset Upon RESET, the Timers will perform the following actions: All EN (Enable) bits are reset preventing timer counting. All SEL (Select) bits are reset to zero. This selects MAX COUNT register A, resulting in the Timer Out pins going HIGH upon RESET. 23INTERRUPT CONTROLLER The 80188 can receive interrupts fram a number of sources, both internal and external. The internal interrupt controller serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources (Timers and DMA channels) can be disabled by their own contral registers or by mask bits within the interrupt controller. The 80188 interrupt controller has its own control registers that set the mode of operation for the controller. The interrupt controller will resolve priority among requests that are pending simultaneously. Nesting is provided so interrupt service routines for lower priority interrupts may themselves be interrupted by higher priority interrupts. A block diagram of the interrupt controller is shown in Figure 21. The interrupt controller has a special iRMX 86 compatibility mode that allows the use of the 80188 within the IRMX 86 operating system interrupt structure. The controller is set in this mode by setting bit 14 in the peripheral control block relocation register (see iRMX 86 Compatibility Mode section). In this mode, the internal 80188 interrupt controller functions as a "'slave" controiler to an external "master' controller. Special initialization software must be included to properly set up the 80188 interrupt controller in iIRMX 86 mode. MASTER (NON-iRMX) MODE OPERATION Interrupt Controller External Interface For external interrupt sources, five dedicated pins are provid- ed. One of these pins is dedicated to NMI, non-maskable interrupt. This is typically used for power-fail interrupts, etc. The other four pins may function either as four interrupt input lines with internally generated interrupt vectors, as an interrupt line and an interrupt acknowledge line (called the "cascade mode") along with two other input lines with internally generat- ed interrupt vectors, or as two interrupt input lines and two dedicated interrupt acknowledge ouput lines. When the inter- rupt lines are configured in cascade mode, the 80188 interrupt controller will not generate internal interrupt vectors. External sources in the cascade mode use externally generat- ed interrupt vectors. When an interrupt is acknowledged, two INTA cycles are initiated and the vector is read into the 80188 on the second cycle. The capability to interface to external 8259A programmable interrupt controllers is thus provided when the inputs are configured in cascade mode. Interrupt Controller Modes of Operation The basic modes of operation of the interrupt controller in non- iRMX mode are similar to the 8259A. The interrupt controller responds identically to internal interrupts in all three modes: the difference is only in the interpretation of function of the four external interrupt pins. The interrupt controller is set into one of these three modes by programming the correct bits in the INTO and INT1 control registers. The modes of interrupt controtler operation are as follows: Fully Nested Mode When in the fully nested mode four pins are used as direct interrupt requests. The vectors for these four inputs are generated internally. An in-service bit is provided for every interrupt source. If a lower-priority device requests an interrupt while the in-service bit (IS) is set, no interrupt will be generated by the interrupt controller. In addition, if another interrupt request occurs from the same interrupt source while the inservice bit is set, no interrupt will be generated by the interrupt controller. This allows interrupt service routines to operate with interrupts enabled without being themselves interrupted by lower-priority interrupts. Since interrupts are enabled, higher-priority interrupts will be serviced. When a service routine is completed, the proper |S bit must be reset by writing the proper pattern to the EOI register. This is required ta allow subsequent interrupts from this interrupt source and to allow servicing of tower-priority interrupts. An EOI command is issued at the end of the service routine just before the issuance of the return from interrupt instruction. If the fully nested structure has been upheld, the next highest- priority source with its IS bit set is then serviced. Cascade Mode The 80188 has four interrupt pins and two of them have dual functions. In the fully nested mode the four pins are used as direct interrupt inputs and the corresponding vectors are generated internally. In the cascade mode, the four pins are configured into interrupt input-dedicated acknowledge signal pairs. The interconnection is shown in Figure 22. INTO is an interrupt input interfaced to an 8259A, while INT2/INTAO serves as the dedicated interrupt acknowledge signal to that peripheral. The same is true for INT1 and INT3/INTA1. Each pair can selectively be placed in the cascade or non-cascade mode by programming the proper value into INTO and INT1 control registers. The use of the dedicated acknowledge signals eliminates the need for the use of external logic to generate INTA and device select signals. The primary cascade mode allows the capability to serve up to 128 external interrupt sources through the use of external master and slave 8259As. Three levels of priority are created, requiring priority resolution in the 80188 interrupt controller, the master 8259As, and the slave 8259As. If an external interrupt is serviced, one IS bit is set at each of these levels. When the interrupt service routine is completed, up to three end-of-interrupt commands must be issued by the program- mer. 24TIMER TIMER TIMER DMA DMA 0 1 2 ~=OttaSt*stNTCO. INT. INT2 NT3 NMI l | TIMER INTERRUPT CONTROL REG. REQUEST REG. DMAO INTERRUPT CONTROL REG. - MASK REG. DMA 1 | INSERVICE CONTROL REG. or REG. EXT. INPUT 0 J ator PRIOR. LEV. CONTROL REG. RreorveR MASK REG. EXT. INPUT 1 INTERRUPT CONTROL REG. STATUS REG. EXT. INPUT 2 VECTOR CONTROL REG. GENERA- EXT. INPUT 3 TION CONTROL REG. LOGIC INTERRUPT REQUEST TO PROCESSOR \Z < INTERNAL ADDRESS/DATA BUS BD003590 Figure 21. Interrupt Controller Block Diagram Special Fully Nested Mode This mode is entered by setting the SFNM bit in INTO or INT1 control register. It enables complete nestability with external 8259A masters. Normally, an interrupt request from an inter- rupt source will not be recognized unless the in-service bit for that source is reset. If more than one interrupt source is connected to an external interrupt controller, all of the interrupts will be funneled through the same 80188 interrupt request pin. As a result, if the external interrupt controller receives a higher-priority interrupt, its interrupt will not be recognized by the 80188 controller until the 80188 in-service bit is reset. In special fully nested mode, the 80188 interrupt controller will allow interrupts from an external pin regardless of the state of the in-service bit for an interrupt source in order to allow multiple interrupts from a single pin. An in-service bit will continue to be set, however, to inhibit interrupts from other lower-priority 80188 interrupt sources. Special procedures should be followed when resetting |S bits at the end of interrupt service routines. Software polling of the external masters {S register is required to determine if there is more than one bit set. If so, the IS bit in the 80188 remains active and the next interrupt service routine is entered. Operation in a Polled Environment The controller may be used in a polled mode if interrupts are undesirable. When polling, the processor disables interrupts and then polls the interrupt controller whenever it is conve- nient. Polling the interrupt controller is accomplished by reading the Poll Word (Figure 9). bit 16 in the poll word indicates to the processor that an interrupt of hign enough priority is requesting service. Reading the Poll Word causes the In-Service bit of the highest-priority source to be set. It is desirable to be able to read the Poll Word information without guaranteeing service of any pending interrupt, i.e., not set the indicated in-service bit. The 80188 provides a Poll Status Word in addition to the conventional Poll Word to allow this to be done. Poll Word information is duplicated in the Poll Status Word, but reading the Poll Status Word does not set the associated in-service bit. These words are located in two adjacent memory locations in the register file. Master (NON-iIRMX) Mode Features Programmable Priority The user can program the interrupt sources into any of eight different priority levels. The programming is done by placing a 3-bit priority level (0-7) in the control register of each interrupt source. (A source with a priority level of 4 has higher priority over all priority levels from 5 to 7. Priority registers containing values lower than 4 have greater priority.) All interrupt sources have preprogrammed default priority levels (see Table 4). If two requests with the same programmed priority level are pending at once, the priority ordering scheme shown in Table 4 is used. If the serviced interrupt routine reenables interrupts, it allows other requests to be serviced. End-of-Interrupt Command The end-of-interrupt (EC!) command is used by the program- mer to reset the In-Service (IS) bit when an interrupt service routine is completed. The EOI command is issued by writing the proper pattern to the EOI register. There are two types of EOI commands, specific and nonspecific. The nonspecific command does not specify which IS bit is reset. When issued, the interrupt controller automatically resets the IS bit of the highest priority source with an active service routine. A specific EOI command requires that the programmer send the interrupt vector type to the interrupt controller indicating which source's IS bit is to be reset. This command is used when the fully nested structure has been disturbed or the highest priority IS bit that was set does not belong to the service routine in progress. 25Trigger Mode The four external interrupt pins can be programmed in either edge- or level-trigger mode. The control register for each external source has a level-trigger mode (LTM) bit. All interrupt inputs are active HIGH. In the edge sense mode or the level- trigger mode the interrupt request must remain active (HIGH) until the interrupt request is acknowledged by the 80188 CPU. In the edge-sense mode, if the level remains high after the interrupt is acknowledged, the input is disabled and no further requests will be generated. The input level must go LOW for at least one clock cycle to reenable the input. In the level-trigger mode, no such provision is made: holding the interrupt input HIGH will cause continuous interrupt requests. Interrupt Vectoring The 80188 Interrupt Controller will generate interrupt vectors for the integrated DMA channels and the integrated Timers. In addition, the Interrupt Controller will generate interrupt vectors for the external interrupt lines if they are not configured in Cascade or Special Fully Nested Mode. The interrupt vectors generated are fixed and cannot be changed (see Table 4). Interrupt Controller Registers The Interrupt Controller register model is shown in Figure 23. It contains 15 registers. All registers can both be read or written unless specified otherwise. In-Service Register This register can be read from or written into. The format is shown in Figure 24. It contains the In-Service bit for each of the interrupt sources. The In-Service bit for each of the interrupt sources. The In-Service bit is set to indicate that a source's service routine is in progress. When an In-Service bit is set, the interrupt controller will not generate interrupts to the CPU when it receives interrupt requests from devices with a lower programmed priority level. The TMR bit is the In-Service bit for all three timers; the DO and D1 bits are the In-Service bits for the two DMA channels; the 10-13 are the In-Service bits for the external interrupt pins. The IS bit is set when the processor acknowledges an interrupt request either by an interrupt acknowledge or by reading the poll register. The iS bit is reset at the end of the interrupt service routine by an end- of-interrupt command issued by the CPU. Interrupt Request Register The internal interrupt sources have interrupt request bits inside the interrupt controller. The format of this register is shown in Figure 24. A read from this register yields the status of these bits. The TMR bit is the logical OR of all timer interrupt requests. DO and D1 are the interrupt request bits for the DMA channels. The state of the external interrupt input pins is aiso indicated. The state of the external interrupt pins is not a stored condition inside the interrupt controller, therefore the external interrupt bits cannot be written. The external interrupt request bits show exactly when an interrupt request is given to the interrupt controller, so if edge-triggered mode is selected, the bit in the register will be HIGH only after an inactive-to-active transition. For internal interrupt sources, the register bits are set when a request arrives and are reset when the processor acknowl- edges the requests. Mask Register This is a 16-bit register that contains a mask bit for each interrupt source. The format for this register is shown in Figure 24. Aone in a bit position corresponding to a particular source serves to mask the source from generating interrupts. These mask bits are the exact same bits which are used in the individual control registers; programming a mask bit using the mask register will also change this bit in the individual contro! registers, and vice versa. 80188 INTAO INT 8259A PIC AFO02801 Figure 22. Cascade Mode Interrupt Connection 26Priority Mask Register OFFSET INT3 CONTROL REGISTER 3EH This register is used to mask all interrupts below Particular interrupt priority levels. The format of this register is shown in INT2 CONTROL REGISTER 3CH Figure 25. The code in the lower three bits of this register inhibits interrupts of priority lower (a higher priority number) INT? CONTROL REGISTER 3AH than the code specified. For exampie, 100 written into this register masks interrupts of level five (101), six (110), and INTO CONTROL REGISTER 38H seven (111). The register is reset to seven (111) upon RESET so all interrupts are unmasked. DMA 1 CONTROL REGISTER 36H . Interrupt Status Register DMA 0 CONTROL REGISTER 34H This register contains general interrupt controller status infor- mation. The format of this register is shown in Figure 26. The TIMER CONTROL REGISTER 32H bits in the status register have the following functions: INTERRUPT CONTROLLER STATUS REGIS- 30H DHLT: DMA Halt Transfer; setting this bit halts all DMA TER 0 transfers. it is automatically set whenever a non- maskable interrupt occurs, and it is reset when an IRET INTERRUPT REQUEST REGISTER 2EH instruction is executed. The purpose of this bit is to allow prompt service of all non-maskable interrupts. IN-SERVICE REGISTER 2CH This bit may also be set by the CPU. PRIORITY MASK REGISTER 2AH IRTx: These three bits represent the individual timer interrupt request bits. These bits are used to differentiate the MASK REGISTER 28H timer interrupts, since the timer IR bit in the interrupt request register is the "OR" function of all timer POLL STATUS REGISTER 26H interrupt requests. Note that setting any one of these three bits initiates an interrupt request to the interrupt POLL REGISTER 24H controller. EO! REGISTER 22H Figure 23. Interrupt Controller Registers (Non-iRMX 86 Mode) 15 14 10 9 8 7 6 5 4 3 2 1 0 o]o]|. - fo fo |e fs { to | 0 | oo [| o | tr] 1514 3 2 1 0 | PRM2| PRM1 | PRMO | ao oO QO Figure 25. Priority Mask Register Format 15 (14 7 6 5 4 3 2 1 0 [oHLT] 0 | . . . . [o | of oj o | [ iat2 | iT | 1RTO | Q Figure 26. Interrupt Status Register Format 27Timer, DMA 0, 1; Control Registers These registers are the control words for all the internal interrupt sources. The format for these registers is shown in Figure 27. The three bit positions PRO, PR1, and PR2 represent the programmable priority level of the interrupt source. The MSK bit inhibits interrupt requests from the interrupt source. The MSK bits in the individual control registers are the exact same bits as are in the Mask Register; modifying them in the individual control registers will also modify them in the Mask Register, and vice versa. INTO-INT3 Control Registers These registers are the control words for the four external input pins. Figure 28 shows the format of the INTO and INT1 Control registers; Figure 29 shows the format of the INT2 and INT3 Control registers. In cascade mode or special fully nested mode, the control words for INT2 and INT3 are not used. The bits in the various control registers are encoded as follows: PRO-2: Priority programming information. Highest priori- ty = 000, lowest priority = 111. LTM: Level-trigger mode bit. 1 = level-triggered; 0 = edge-triggered. Interrupt Input levels are ac- tive high. In level-triggered mode, an interrupt is generated whenever the external line is high. In edge-triggered mode, an interrupt will be generated only when this level is preceded by an inactive-to-active transition on the line. In both cases, the level must remain active until the interrupt is acknowledged. MSK: Mask bit, 1 = mask; 0 = nonmask. Cc: Cascade mode bit, 1 = cascade; 0 = direct SFNM: Special fully nested mode bit, 1 = SFNM; 0 =normal nested mode. EOI Register The end of the interrupt register is a command register which can only be written into. The format of this register is shown in Figure 30. It initiates an EO! command when written to by the 80188 CPU. The bits in the EOI register are encoded as follows: Sx Encoded information that specifies an interrupt source vector type as shown in Table 4. For ex- ample, to reset the In-Service bit for DMA channei 0, these bits should be set to 01010, since the vector type for DMA channel 0 is 10. Note that to reset the single In-Service bit for any of the three timers, the vector type for timer 0(8) should be written in this register. 1514 4 3 2 1 0 [ o | o | | o | Msk | pR2 | Pri | Pro | Figure 27. Timer/DMA Control Register Formats 1514 7 6 5 4 3 2 1 0 [ o | o | | o |sFNM| c | LTM | Msk{ pR2 | PR1 | PRO | Figure 28. INTO/INT1 Control Register Formats 15 14 5 4 3 2 1 0 fo fo]. | o | .uTM | Msk | PR2 | PR1 | PRO | Figure 29. INT2/INT3 Control Register Formats NSPEC/: A bit that determines the type of EOI command. SPEC Nonspecific = 1, Specific = 0. Poll and Poll Status Registers These registers contain polling information. The format of these registers is shown in Figure 31. They can only be read. Reading the Poll register constitutes a software poll. This will set the IS bit of the highest priority pending interrupt. Reading the poll status register will not set the IS bit of the highest priority pending interrupt; only the status of pending interrupts will be provided. Encoding of the Poll and Poll Status register bits are as follows: Sx Encoded information that indicates the vector type of the highest priority interrupting source. Valid only when INTREQ = 1. INTREQ: This bit determines if an interrupt request is pres- ent. Interrupt Request = 1; no Interrupt Request = 0. 28iRMX 86 COMPATIBILITY MODE This mode allows iRMX 86-80188 compatibility. The interrupt model of IRMX 86 requires one master and multiple slave 8259As in cascaded fashion. When iRMX mode is used, the internal 80188 interrupt controller will be used as a slave controller to an external master interrupt controller. The internal 80188 resources will be monitored through the inter- nal interrupt controller, while the external controller functions as the system master interrupt controller. Upon reset, the 80188 interrupt controller will be in the non- iRMX 86 mode of operation. To set the controller in the iRMX 86 mode, bit 14 of the Relocation Register should be set. Because of pin limitations caused by the need to interface to an external 8259A master, the internal interrupt controller will no longer accept external inputs. There are however, enough 80188 interrupt controller inputs (internally) to dedicate one to each timer. In this mode, each timer interrupt source has its own mask bit, IS bit, and control word. The iRMX 86 operating system requires peripherals to be assigned fixed priority levels. This is incompatible with the normal operation of the 80188 interrupt controller. Therefore, the initialization software must program the proper priority levels for each source. The required priority levels for the internal interrupt sources in iRMX mode are shown in Table 16. Table 16. Internal Source Priority Level Priority Level Interrupt Source 0 Timer 0 (reserved) DMA 0 DMA 1 Timer 1 Timer 2 aOhon These level assignments must remain fixed in the iRMX 86 mode of operation. iRMX 86 Mode External Interface The configuration of the 80188 with respect to an external 8259A master is shown in Figure 32. The INTO input is used as the 80188 CPU interrupt input. INT3 functions as an output to send the 80188 siave-interrupt-request to one of the 8 master- PIC-inputs. 15 14 13 SPEC/ nspec| 0 o | S4 | S3 | S2 |} S1 | SO Figure 30. EOI Register Format 15 14 13 5 4 3 2 1 0 iNT REQ 0 0 0 S4 } $3 | S2 |] S1 so Figure 31. Poll Register Format 8259A MASTER inTA REQUESTS FROM INTA wo <_einen SLAVES 80126 INT. IN INT | IR? soiee CA60-2 SUAVE SELECT CASCADE wn ADDRESS DECODER int2 NTS 80188 SI. AVE INTERRUPT OUTPUT AFO02811 Figure 32. iRMX 86 Interrupt Controller Interconnection 29Correct master-slave interface requires decoding of the slave addresses (CASO-2). Slave 8259As do this internally. Be- cause of pin limitations, the 80188 salve address will have to be decoded externally. INT1 is used as a slave-select input. Note that the slave vector address is transferred internally, but the READY input must be supplied externally. INT2 is used as an acknowledge output, suitable to drive the INTA input of an 8259A. Interrupt Nesting iRMX 86 mode operation allows nesting of interrupt requests. When an interrupt is acknowledged, the priority logic masks off all priority levels except those with equal or higher priority. Vector Generation in the iRMX 86 MODE Vector generation in IRMX mode is exactly like that of an 8259A slave. The interrupt controller generates an 8-bit vector which the CPU multiplies by four and uses as an address into a vector table. The significant five bits of the vector are user- programmable while the lower three bits are generated by the priority logic. These bits represent the encoding of the priority level requesting service. The significant five bits of the vector are programmed by writing to the Interrupt Vector register at offset 20H. Specific End-of-Interrupt In iRMX mode the specific EOl command operates to reset an in-service bit of a specific priority. The user supplies a 93-bit priority-level value that points to an in-service bit to be reset. The command is executed by writing the correct value in the Specific EOI register at offset 22H. Interrupt Controller Registers in the iRMX 86 Mode Ail control and command registers are located inside the internal peripheral control block. Figure 33 shows the offsets of these registers. End-of-Interrupt Register The end-ot-interrupt register is a command register which can only be written. The format of this register is shown in Figure 34. It initiates an EO] command when written by the 80188 CPU. The bits in the EOI register are encoded as follows: Ly: Encoded value indicating the priority of the IS bit to be reset. In-Service Register This register can be read from or written into. It contains the in- service bit for each of the internal sources. The format for this register is shown in Figure 35. Bit positions 2 and 3 corre- spond to the DMA channels; positions 0, 4, and 5 correspond to the integral timers. The source's IS bit is set when the processor acknowledges its interrupt request. Interrupt Request Register This register indicates which internal peripherals have interrupt requests pending. The format of this register is shown in Figure 35. The interrupt request bits are set when a request arrives from an internal source, and are rest when the processor acknowledges the request. Mask Register This register contains a mask bit for each interrupt source. The format for this register is shown in Figure 35. If the bit in this register corresponding to a particular interrupt source is set, any interrupts from that source will be masked. These mask bits are exactly the same bits which are used in the individual control registers, i.e., changing the state of a mask bit in this register will also change the state of the mask bit in the individual interrupt control register corresponding to the bit. Control Registers These registers are the control words for all the internat interrupt sources. The format of these registers is shown in Figure 36. Each of the timers and both of the DMA channels have their own Control Register. The bits of the Control Registers are encoded as follows: Pry: 3-bit encoded field indicating a priority level for the source; note that each source must be programmed at specified levels. msk: mask bit for the priority level indicated by pr, bits. OFFSET LEVEL 5 CONTROL REGISTER 3AH (TIMER 2) LEVEL 4 CONTROL REGISTER 38H (TIMER 14) LEVEL 3 CONTROL REGISTER 36H (DMA 4) LEVEL 2 CONTROL REGISTER 34H (DMA 0) LEVEL 0 CONTROL REGISTER 30H (TIMER 0} INTERRUPT-REQUEST REGISTER | 2EH IN-SERVICE REGISTER 2CH PRIORITY-LEVEL MASK REGISTER | 2AH MASK REGISTER 28H SPECIFIC EOI REGISTER 22H INTERRUPT VECTOR REGISTER | 20H Figure 33. Interrupt Controller Registers {IRMX 86 Mode) 3015 14 13 8 foflojfo|. . | 0 7 6 5 4 3 2 14 90 Tolofo]fo]ofwl{iu]r| Figure 34. Specific EQI Register Format 15 14 13 8 [ofofo]|-. 7 6 5 4 3 2 1 0 [o[o]|o [TmR2]TMA1 | D1 | vo | 0 | TMRO | Figure 35. In-Service, Interrupt Request, and Mask Register Format Interrupt Vector Register This register provides the upper five bits of the interrupt vector address. The format of this register is shown in Figure 37. The interrupt controller itself provides the lower three bits of the interrupt vector as determined by the priority level of the interrupt request. The format of the bits in this register is: 5-bit field indicating the upper five bits of the vector address. Priority-Level Mask Register be This register indicates the lowest priority-level interrupt which will be serviced. The encoding of the bits in this register is: my: 3-bit encoded field indication priority-level value. Ail levels of lower priority will be masked. Interrupt Controller and Reset Upon RESET, the interrupt controller will perform the following actions: @ All SENM bits reset to 0, implying Fully Nested Mode. Alt PR bits in the various control registers set to 1. Tis places all sources at lowest priority (level 111). All LTM bits reset to 0, resulting in edge-sense mode. All Interrupt Service bits reset to 0. All Interrupt Request bits reset to 0. All MSK (Interrupt Mask) bits set to t (mask). All C (Cascade) bits reset to 0 (non-cascade). All PRM (Priority Mask) bits set to 1, implying no levels masked. Initialized to NON-iRMX 86 mode. 15 14 13 8 fofofo]. . | 0 Pojlofo| 5 4 3 2 1 0 [sk] PR | PR: | PRO | o Figure 36. Control Word Format 15 14 13 8 7 6 & 4 3 2 4 0 [oflofo]. ~Tolul3[2f]w[ol]olo |} Figure 37. Interrupt Vector Register Format 15 14 43 8 7 6 & 4 3 2 1 0 [ofofol. ~Tole[o] ojo] o [me] m | mo | Figure 38. Priority Level Mask Register 31RESET vee 4H] 20 MHz xi x2 ucs 29843 ORI AD RESET AES _ 29845 ORESS Rom RES a00-A07 poss Ag-Ai5 ALE sts OE ste O 0188-10 RO wr I PROGRAM RAM &CSO-3 SADY +5 aROY TT] NM rc HoLoL | a SJ) LOW RAM tes TMRIN Ot +5 s} TMR OUT 0 1 CLOCK 2946/2947 | A kK > __ LITRANSCEIVER | 00-D7 = DEN (oD 1 OE SERIAL TERMINAL va oT +t | $ PCsa Al a2 INTO J oIsk intenFace KO > (e) DISK INTI HARDWARE CSA Rao Figure 39. Typical 80188 Computer AF002826 32xt x2 ucs| cs RESET ROM RES Low RAM ALE ics WR ADO-AD7 29843 OR ADORESS AB-ANS > 29645 [> bus ste OE | ts BOE oe po188-10 1 NMI Ty 2946/2947 LL. HOLD? >| TRANSCEIVER DATA BUS u MULTI. D MASTER SYSTEM BUS cLKOUT ove ae OEM S0-S2 BU BUS CONTROL - S $0-82 CONTROLLER > COMMANDS CEN 108___ AEN [Ly 80-62 AEN Bus CH ARBITER | RBITRATION pose _ SYSBIRESE TOeK (OCK ResBide sv SRDY | GNO ARDY AEN AEN XACK / AF002835 Figure 40. Typical 80188 Multi-Master Bus Interface 33ABSOLUTE MAXIMUM RATINGS Storage Temperature ..........0.. ee -65C to + 150C Voltage on Any Pin with Respect to Ground...................0.000008 -10 Vto +7 V Power Dissipation (steady state 70C)................... 2.0 W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial {C) Devices Temperature (Tp) ...........ccccccecccceeeaveenene 0 to +70C (TC) oo cece cece eee ece terre een ee 0 to +110C Supply Voltage (VGC) .....-.:eceeeeeeeeeeeeeeees 5V + 10% Industrial (1) Devices Temperature (Ta).........c ccc cceceeaeeseevees ~40 to +85C Supply Voltage (Vcc) Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS (over operating range unless otherwise specified) Parameters Description Test Conditions Min. Max. Units Vit Input LOW Voltage -0.5 +0.8 Volts Vi (al orespt eee RES) 2.0 Voc + 0.5 Volts Vind Input HIGH Voltage (RES) 3.0 Voc + 0.5 Volts VoL Output LOW Voltage (a = e m for 2 other outputs 0.45 Volts Vou Output HIGH Voltage lon =-400 nA 24 Volts Ta = -40C 600** loc Power Supply Current Ta =0C 500 mA Ta = 70C 375 lu Input Leakage Current OV| TCHSY i | TCLOV TCLAV-w| - [TCLAX TCHDx >| T S, Arg/Sy- A/S An Aw S,-S, TLHLL | TLLAX _. ALE a od f. TCHLH > TAVAL TCHLL TLLAX b TeLox TCLAV- Ke TCLAZ TOVCL - FLOAT / AD,-AD, Ay~Ay Float A DATA IN - Ais Ag AworAs iH TRHAV READ CYCLE TAVCH < TAZRL>| TCLRH a A TCHCTV = TCLRL t | TRURH TCHCTV ov/R / WAR, INTA = Von TevcTv>} TCVDEX > DEN ~ TCHCSX Pcs, ics, | TCLCSV | MCS Notes: 1. Following a Write cycle, the Local Bus is floated by the 80188 only when the 80188 enters a ''Hold Acknowledge" state. 2. INTA occurs one clock later in RMX-mode. 3. Status inactive just prior to Ty. WF006226 38TCLLV SWITCHING WAVEFORMS (Cont'd.) aa aae TCL! a WF006232 CLKOUT \N_ DRGO, oral TINVCL >| TINVCH NMI, TEST INTO-3 TIMERIN WF006240 CLKOUT \ TCHOSV QS0, QS1 x WFO06250 39SWITCHING WAVEFORMS (Cont'd.) Tr | Ty | | T, CLKOUT TARYHCH >| - TCHARYX i 45 ARDY | | TARYCHL TARYLCL ARDY WFO0G6262 ~t TSRYCL >| }~ TCLSAY SRDY WF006270 HOLD-HLDA TIMING Ts Tt CLKOUT PV S VS VS PLS ow | THYCL | e THYCL HOLD pj (+ TCLHAV TCLHAV | [a HLDA | et TCLAV __ TCLAZ A015-ADO oe ae --3 to 80188 \ -- + > 80188 DEN oe oe L --Y WS TCHCV > ~ j~e TCHCZ b- A19/S8-A16/S3, _____ -- ae --7y pO $7, __-- - ee + be oTih, $2-S0 WF006282 40SWITCHING WAVEFORMS (Cont'd.) CLKIN TCKHL TCKLH TCHICH2>| <_ TCL2CL1 H cLKouT Tc1coe TCLCt TCHCL TCLCL | WF006293 TIMER ON 80188 \ TIMERIN _ TCLIMV |~<- TIMEROUT 2-6 CLOCKS f WF006300 80188 INSTRUCTION TIMINGS @ All word-data is located on even-address boundaries. The following instruction timings represent the minimum All jumps and calls include the time required to fetch the execution time in clock cycles for each instruction. The timings opcode of the next instruction at the destination address. given are based on the following assumptions: All instructions which involve memory reference can require one (and in some cases, two) additional clocks above the minimum timings shown. This is due to the asynchronous nature of the handshake between the BIU and the Execution @ No wait states or bus HOLDS occur. unit. @ The opcode, along with any data or displacement required for execution of a particular instruction, has been pre- fetched and resides in the queue at the time it is needed. 4iINSTRUCTION SET SUMMARY Segment register Memory Register Segment register Register/memory with register Register with accumulator IN = input from: Fixed port Variable port OUT = Output to: Fixed port Variable port XLAT = Translate byte to AL LEA = Load EA to register LDS = Load pointer to DS LES = Load pointer to ES LAHF = Load AH with flags SAHF = Store AH into flags PUSHF = Push flags POPF = Pop flags mod 0 0 0 r/m 01011 reg O000regii11 (reg # 01) | 10010 reg 1110010w 1110110w 1110011w zy 2 a 111014111W 11010111 11000101] modegiim ] (moder | 11000100] modregt/m | (mod#11) | 10011111 10011110 10011100 10011101 20 10 W 18 18 on Ww Clock FUNCTION FORMAT Cycles Comments DATA TRANSFER MOV = Move: Register to Register/Memory 1000100w 2/2 Register/memory to register tO00101W 2/9 Immediate to register/memory [1100011w]| modo00 rm | data [ dataitw=1 | 12-13 8/16-bit Immediate to register [ 1011w reg | data [data itw=1 | 3-4 8/16-bit Memory to accumulator [ 1010000w | addr-low | addr-high | 9 Accumulator ta. memory [1010001w| addriow | addr-high | 8 Register/memory to segment register 10001110 mod 0 reg r/m 2/9 Segment register to register/memory 10001100 mod 0 reg r/m 2/11 PUSH = Push: Memory mod 1140 f/m 16 Register 01010 reg 10 000reg 110 9 Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp. 1982 42INSTRUCTION SET SUMMARY (Cont'd.) Clock FUNCTION FORMAT Cycles Comments ARITHMETIC ADD = Add: Reg/memory with register to either aqoao000dw 3/10 Immediate to register / memory | 100000sw i mod 0 0 0 r/m | data | data if s w= 01 4/16 Immediate to accumulator [ovoo0010W| data [ dataitw=1 | 3/4 8/16-bil ADC = Add with carry: Reg/memory with register ta either gq00100dw 3/10 immediate to register/memory [1 ococgosw | mod 0 1 0 r/m l data I data if s w=01 | 4/16 Immediate to accumulator ao01010w] data [ dataitw=1 | av4 8/16-bit INC = increment: Register/memary 111114111w mod 0 0 0 r/m 3/15 Register 01000 reg 3 SUB = Subtract: Rleg/memory and register to either 001010dw 3/10 Immediate from register/memory [ 100000sw | mod 101 F/m | data | data if s w=01 4/16 Immediate from accumulator o010110w| data [ gataitw=1 | a/4 8/16-bit SB = Subtract with borrow: Fleg/memory and register to either 000110dw 3/10 Immediate from register/memory { 1900000sw | mod 01 1 f/m | data | data if s w=01 4/16 Immediate from accumulator [ooo1110Ww]| data [ dataitw=1 | a4 a/16-bit DEC = Decrement: Register memory mod 0 0 1 r/m 3/15 Register 01001 reg 3 CMP = Compare: Register/memory with register o0011101Ww 3/10 Register with register/memory 0011100w 3/10 Immediate with register/memory [ 100000sw l mod 11 1 r/m | data l data ifs w=01 3/10 immediate with accumulator po11110w| data [ dataitw=1 | 3/4 8/16-bit NEG = Change sign 11117011w mod 0 11 r/m a AAA= ASCII adjust for add 00110111 8 OAA = Decimal adjust for add 00100111 4 AAS = ASCII adjust for subtract 00111111 7 DAS = Decimal adjust for subtract 00101111 4 MUL = Mulitiply (unsigned) 1111011w mod 1 0 0 F/m Register-Byte 26-28 Register-Word 35-37 Memory-Byte 32-34 Memory-Word 41-43 IMUL = Integer multiply (signed): 1111011Ww mod 10 1 r/m Register-Byte 25-28 Register-Word 34-37 Memory-Byte 31-34 Memory-Word (signed) DIV = Divide (unsigned): Register-Byte Register-Word Memory-Byte Memory-Word 11171011wW mod 110 r/m Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp. 1982INSTRUCTION SET SUMMARY (Cont'd.) Clock FUNCTION FORMAT Cycles Comments ARITHMETIC (Continued): IDIV = Integer divide (signed): 1141011wW mod t 11 r/m 44-52 Register-Byte Register-Word 53-61 Memory-Byte 50-58 Memory-Word 59-67 AAM = ASCII adjust for multiply 11010100/]/00001010 19 AAD = ASCII adjust for divide 11010101 00001010 15 CBW = Convert byte to word 1001411000 2 CWD = Convert word to double word 10011001 4 LoGic Shift/Rotate Instructions: Register/Memory by 1 110T000w 2/15 Register/Memory by CL t+t1O01001tw = 3 = e = . 7 | Instruction 000 ROL 001 ROR 010 RCL ott RCR 100 SHL/SAL 101 SHR 111 SAR AND = And: Reg/memory and register to either 001000dw Immediate to register/memory tooo9000w| mod10drm | data | data if w=4 immediate to accumulator [ 0010010w [ data | data if w=1 TEST = And function to flags, no result: Register/memory and register 1000010Ww immediate data and register/memory 111101T1WwW [ mod 000 1r/m data | data if w=1 Immediate data and accumulator [10 +10100w [ data | data if w=1 | OR = Or: Reg/memory and register ta either o00010dw Immediate to register/memory [ 1000000Ww l mod 00 1 r/m | data [ data if w=1 | data if wet | Immediate to accumulator Z 0000110w] data XOR = Exclusive or: Reg/memory and register to either 001100dw Immediate to register/memory [ 1000006Ww | mod 1 1 0 r/m data | dataitw=1 | Immediate to accumulator [ 001101Gw [ data NOT = Invert register/memory 117471G0114w STRING MANIPULATION: MOVS = Move byte/word [roico70w | CMPS = Compare byte/word [rovoottw | SCAS = Scan byte/word [ro1o1tiw | LODS = Load byte/wd to AL/AX [tovo1i0oW] STOS = Stor byte/wd from AL/A [rototo1w] data ifw=1 | Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp. 1982 3/10 4/16 3/4 3/10 4/10 v4 3/10 4/16 3/4 3/10 4/16 3/4 8+ 8n 5+ 22n 5+ 15n 6+11n 8/16-bit 8/16-bit 8/16-bit 8/16-bit 44INSTRUCTION SET SUMMARY (Cont'd.) Clock FUNCTION FORMAT Cycles Comments STRING MANIPULATION (Continued): Repeated by count in CX MOVS = Move string 141110010 14 CONTROL TRANSFER CALL = Call: Direct within segment [4 1101000 l disp-low | disp-high | Register memory 41111111 mod 0 10 r/m indirect within segment Direct intersegment [ 10011010 | segment offset ] segment selector indirect intersegment V14dt1411 mod 0 1 1 r/m (mod # 11) JMP = Unconditional jump: Short/long 41101011 disp-low disp-high | Direct within segment [ 11101001 Register/memory indirect within segment 1t11171111 mod 10 0 r/m Direct intersegment [ 44t101010 | segment offset segment selector Indirect intersegment 411711911 mod 101 r/m (mod # 11} RET = Return from CALL: Within segment 11000011 Within seg adding immed to SP [ 11000010 | data-low | data-high | Intersegment 11001011 data-high | Intersegment adding immediate ta SP { 441001010 | data-low 13/19 23 3B 26 22 25 Not Repeated Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of intel Corp. 1982 45INSTRUCTION SET SUMMARY (Cont'd.) Clock FUNCTION FORMAT Cycles Comments CONTROL TRANSFER (Continued): JE/JZ = Jump on equal zero [or110+100] disp 4/13 13 if JMP taken JLAJNGE = Jump on tess not greater or equal [01111100] disp | 4/13 4 if UMP not taken JLE/JNG = Jump on jess or equal not greater [orisi1t0] dso | 4/13 JB/JNAE = Jump on below not above or equal 4/13 JBE/JNA = Jump on below or equal not above [o1i101t10] disp 4/13 JP/JPE = Jump on parity parity even 4/13 JO = Jump on overflow [ori1o0000| dsp | 4/13 JS = Jump on sign 4/13 JNE/JNZ = Jump on not equal not zero 4/13 JNL/JGE = Jump on not less greater or equal 4/13 JNLE/JG = Jump on not less or equal greater forttiait] disp 4/13 JNB/JAE = Jump on not below above or equal 4/13 JNBE/JA = Jump on not below or equal above [orstorii] dsp | 4/13 JNP/JPO = Jump on not par / par odd 4/13 JNO = Jump on not overflow [ori110001] dsp | 4/13 JNS = Jump on not sign 4/13 LOOP = Loop CX times [1+100010[ dsp 5/18 LOOPZ/LOOPE = Loop while zero equal 6/16 LOOPNZ/LOOPNE = Loop while not zero equal [71100000] dso 6/16 JCXZ = Jump on CX zero [11100011] disp 16 JMP taken/ JMP not taken toe Type specified 11001101 Type 3 11001100 if INT. taken? if INT. not INTO = Interrupt on overflow 11001110 taken IRET = Interrupt retuen 110014311 Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp. 1982 46INSTRUCTION SET SUMMARY (Cont'd.) Clock FUNCTION FORMAT Cycles Comments PROCESSOR CONTROL CLC = Clear carry 2 CMC = Complement carry 2 STC = Set carry 2 CLO = Clear direction 2 STD = Set direction 2 CLI = Clear interrupt 2 STI = Set interrupt 2 HLT = Halt 2 WAIT = Wait 6 if Test =0 LOCK = Bus iock prefix 11110000 ESC = Processor Extension Escape 100117TTT mod LLL r/m - 5 = % a 3 3 a a 3 Uv 3 o oO g g Qo g Oo g Oo a3 @ Q 3 FOOTNOTES The effective Address (EA) of the memory operand is computed according to the mod and 1/m fields: if mod = 11 then r/m is treated as a REG field if mod = 00 then DISP =0 , disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended to 16-bits, disp-high is absent if mod = 10 then DISP = disp-high: disp-low if rm=000 then EA if r/m= 001 then EA if r/m=010 then EA if r/m=011 then EA if rm= 100 then EA if r/m= 101 then EA if r/m=110 then EA if r/m=111 then EA = (BX) + (SI) + DISP = (BX) + (Dl) + DISP = (BP) + (SI) + DISP = (BP) + (DI) + DISP = (SI) + DISP = (Dl) + DISP | = (BP) + DISP = (BX) + DISP DISP follows 2nd byte of instruction (before data if required) except if mod = 00 and r/m= 110 then EA = disp-high: disp-low. SEGMENT OVERRIDE PREFIX 0011reg i110 reg is assigned according to the following: Segment Register ES cs ss DS REG is assigned according to the following table: 16-Bit (w= 1) 8-Bit (w = 0) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 Sl 111 Di 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register. The physical addresses of the destination operands of the string primitive operations (those addressed bythe DI register) are computed using the ES segment, which may not be overrid- den.PHYSICAL DIMENSIONS* CA2086 ek ay th, ---k4__ | Lt N tT PUNE 2 , LANE moe o72a7% *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering. 48PHYSICAL DIMENSIONS (Cont'd.) .075 x 45 REF. Pin 1 (Reference Corner) BOTTOM VIEW (Pins facing up) 4 1.140 2 1.180 1,000 BSC. BCcCOEFGHIJI KL CGX068 1 2 a] oe 4 1.140 5 re 1000 Bsc 7 a 9 0 14 2ccetooce) 08H OHOCODO I oo .030 x 45 REF. {3 PLACES) he 925 055 PID # 07547C *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering. 49PHYSICAL DIMENSIONS (Cont'd.) PL 068 080 REF. Fm ooo ospsnpnnoon Ve woe + r ft 8 4 a 28 # = % DoT AIo ooo IT ooo ooo => ae ab Pio e Dera *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering. 50Sales Offices North American ALABAMA. . (205) 882-9122 ARIZONA . (602) 242-4400 CALIFORN Culver Ci -(213) 645-1524 Newport (714) 752-6262 Roseville . .(916) 786-6700 San Diego . (619) 560-7030 San Jose. . (408) 452-0500 Woodland . (818) 992-4155 CANADA, Ontario, Kanata .... (613) 592-0060 Willowdale .. -(416) 224-5193 COLORADO .... . (303) 741-2900 CONNECTICUT 203) 264-7800 FLORIDA, Clearwater ......... (813) 530-9971 Ft. Lauderdale . (305) 776-2001 Orlando ... . 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