TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC4051BP, TC4051BF, TC4051BFN, TC4051BFT
TC4052BP, TC4052BF, TC4052BFN, TC4052BFT
TC4053BP, TC4053BF, TC4053BFN, TC4053BFT
TC4051B
Single 8-Channel Multiplexer/Demultiplexer
TC4052B
Differential 4-Channel
Multiplexer/Demultiplexer
TC4053B
Triple 2-Channel Multiplexer/Demultiplexer
TC4051B, TC4052B and TC4053B are multiplexers with
capabilities of selection and mixture of analog signal and digital
signal. TC4051B has 8 channels configuration. TC4052B has 4
channel × 2 configuration and TC4053B has 2 channel × 3
configuration. The digital signal to the control terminal turns
“ON” the corresponding switch of each channel, with large
amplitude (VDD VEE) can be switched by the control signal
with small logical amplitude (VDD VSS). For example, in the
case of VDD = 5 V VSS = 0 V and VEE = 5 V, signals between 5
V and +5 V can be switched from the logical circuit with single
power supply of 5 volts. As the ON-resistance of each switch is
low, these can be connected to the circuits with low input
impedance.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC4051BP, TC4052BP, TC4053BP
TC4051BF, TC4052BF, TC4053BF
TC4051BFN, TC4052BFN, TC4053BFN
TC4051BFT, TC4052BFT, TC4053BFT
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
SOL16-P-150-1.27 : 0.13 g (typ.)
TSSOP16-P-0044-0.65A : 0.06 g (typ.)
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
2
Pin Assignment
Truth Table
Control Inputs “ON” Channel
Inhibit CΔ B A TC4051B TC4052B TC4053B
L L L L 0 0X, 0Y 0X, 0Y, 0Z
L L L H 1 1X, 1Y 1X, 0Y, 0Z
L L H L 2 2X, 2Y 0X, 1Y, 0Z
L L H H 3 3X, 3Y 1X, 1Y, 0Z
L H L L 4 0X, 0Y, 1Z
L H L H 5 1X, 0Y, 1Z
L H H L 6 0X, 1Y, 1Z
L H H H 7 1X, 1Y, 1Z
H X X X None None None
X: Don’t care
Δ: Except TC4052B
VDD 16
2
1
0
15
14
13
12
11
10
1
2
3
4
5
6
7
7
5
INH
VEE
VSS
3
89
A
B
(top view)
6
COM
TC4051B
4
C
VDD
16
2X
1X
X-COM
15
14
13
12
11
10
1
2
3
4
5
6
7
3Y
1Y
INH
VEE
VSS
0X
89
3X
A
(top view)
2Y
Y-COM
0Y
TC4052B
B
VDD 16
Y-COM
X-COM
1X
15
14
13
12
11
10
1
2
3
4
5
6
7
Z-COM
0Z
INH
VEE
VSS
0X
8 9
A
B
(top view)
0Y
1Z
TC4053B
1Y
C
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
3
Logic Diagram
TC4051B
TC4052B
13
12
A
5
B
INH
C
14
15
1
2
4
Logic Level Converter
OUT IN c
COMMON
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
0
3
5
1
2
4
6
7
3
11
10
9
6
7
VEE
8
VSS
16
VDD
12
11
A
5
B
INH
14
15
1
2
4
Logic Level Converter
OUT IN c
Y-COMMON
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
0X
3X
1Y
1X
2X
0Y
2Y
3Y
3
10
9
6
7
VEE
8
VSS
16
VDD
X-COMMON
13
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
4
TC4053B
Truth Table
Control
C
Impedance between
IN-OUT (Note)
H
L
0.5 to 5 × 102 Ω
>109 Ω
Note: See electrical characteristics
Absolute Maximum Ratings (Note)
Characteristics Symbol Rating Unit
DC supply voltage VDD-VSS 0.5 to 20 V
DC supply voltage VDD-VEE 0.5 to 20 V
Control input voltage VCIN V
SS 0.5 to VDD + 0.5 V
Switch I/O voltage VI/VO V
EE 0.5 to VDD + 0.5 V
Control input current ICIN ±10 mA
Potential difference across I/O during
ON VI-VO 0.5 to 0.5 V
Power dissipation PD 300 (DIP)/180 (SOIC) mW
Operating temperature range Topr 40 to 85 °C
Storage temperature range Tstg 65 to 150 °C
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
OUT IN c
14
2
A
5
B
INH
C
12
13
1
3
Logic Level Converter
Z-COMMON
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
OUT IN c
X-COMMON
0Y
0Z
0X
1X
1Y
1Z
4
11
10
9
6
7
VEE
8
VSS
16
VDD
Y-COMMON
15
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
5
Operating Ranges (Note)
Characteristics Symbol Test Condition Min Typ. Max Unit
VDD-VSS 3 18
DC supply voltage
VDD-VEE 3 18
V
Control input voltage VIN V
SS V
DD V
Input/output voltage VIN/VOUT V
EE V
DD V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused Control inputs must be tied to either VDD or VSS.
Static Electrical Characteristics
Test Condition 40°C 25°C 85°C
Characteristics Symbol
VSS
(V)
VEE
(V)
VDD
(V) Min Max Min Typ. Max Min Max
Unit
Control input high
voltage VIH
5
10
15
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
Control input low
voltage VIL
VIS = VDD
thru 1 kΩ
VEE = VSS
RL = 1 kΩ
to VSS
IIS < 2 μA
on all OFF
channels
5
10
15
1.5
3.0
4.0
2.25
4.5
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
On-state
resistance RON
0 VIS VDD
RL = 10 kΩ
0
0
0
0
0
0
5
10
15
850
210
140
240
110
80
950
250
160
1200
300
200
Ω
ΔOn-state
resistance
between any 2
switches
RONΔ
0
0
0
0
0
0
5
10
15
10
6
4
Ω
Input/output
leakage current IOFF
VIN = 18 V, VOUT = 0 V
VIN = 0 V, VOUT = 18 V
18
18
±100
±100
±0.01
±0.01
±100
±100
±1000
±1000
nA
Quiescent supply
current IDD V
IN = VSS, VDD (Note)
5
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
μA
Input current IIN
VIH = 18 V
VIL = 0 V
18
18
0.1
0.1
105
105
0.1
0.1
1.0
1.0 μA
Input capacitance CIN 5 7.5 pF
Switch input
capacitance CIN 10 pF
Output
capacitance COUT
TC4051B
TC4052B
TC4053B
10
10
10
58
30
17
pF
Feedthrough
capacitance
CIN-
C-OUT
TC4051B
TC4052B
TC4053B
10
10
10
0.2
0.2
0.2
pF
Note: All valid input combinations.
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
6
Dynamic Electrical Characteristics (Ta = 25°C, CL = 50 pF)
Test Condition
Characteristics Symbol
VSS
(V)
VEE
(V)
VDD
(V)
Min Typ. Max Unit
Phase difference between
input to output φI-O
0
0
0
0
0
0
5
10
15
15
8
6
45
20
15
ns
Propagation delay time
(A, B, C, -OUT)
tpZL
tpZH
tpLZ
tpHZ
RL = 1 kΩ
0
0
0
0
0
0
0
0
5
7.5
5
10
15
5
7.5
170
90
70
100
80
550
240
160
240
160
ns
Propagation delay time
(INH-OUT)
tpZL
tpZH
RL = 1 kΩ
0
0
0
0
0
0
0
0
5
7.5
5
10
15
5
7.5
120
60
50
80
60
380
200
160
200
160
ns
Propagation delay time
(INH-OUT)
tpLZ
tpHZ
RL = 1 kΩ
0
0
0
0
0
0
0
0
5
7.5
5
10
15
5
7.5
170
90
70
100
80
450
210
160
210
160
ns
3dB cutoff frequency
TC4051B
TC4052B
TC4053B
fmax (I-O) RL = 1 kΩ (Note 1)
5
5
5
5
5
5
5
5
5
20
30
40
MHz
Total harmonic distortion
RL = 10 kΩ
f = 1 kHz (Note 2)
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
0.15
0.03
0.02
%
50dB feedthrough
(switch off) R
L = 1 kΩ (Note 3) 555 500 kHz
Crosstalk R
L = 1 kΩ (Note 4) 555 1.5 MHz
Crosstalk
(control-OUT)
RIN = 1 kΩ
ROUT = 10 kΩ
CL = 15 pF
0
0
0
0
0
0
5
10
15
200
400
600
mV
Note 1: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10
is
OS
V
V = 3dB shall be fmax.
Note 2: Vis shall be sine wave of
±4
VV EEDD p-p.
Note 3: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10
is
OS
V
V = 50dB shall be
feed-through.
Note 4: Sine wave of ±2.5 Vp-p shall be used for Vis and the frequency of 20 log 10
is
OS
V
V = 50dB shall be
crosstalk.
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
7
Package Dimensions
Weight: 1.00 g (typ.)
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
8
Package Dimensions
Weight: 0.18 g (typ.)
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
9
Package Dimensions (Note)
Note: This package is not available in Japan.
Weight: 0.13 g (typ.)
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
10
Package Dimensions
Weight: 0.06 g (typ.)
TC4051,4052,4053BP/BF/BFN/BFT
2007-10-01
11
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