Data Sheet AD7172-2
Rev. A | Page 45 of 60
The device is taken out of reset on the master clock falling edge
following the SYNC input low to high transition. Therefore,
when multiple devices are being synchronized, take the SYNC
Ainput high on the master clock rising edge to ensure that all
devices are released on the master clock falling edge. If the
SYNC input is not taken high in sufficient time, a difference of
one master clock cycle between the devices is possible, that is,
the instant at which conversions are available differs from
device to device by a maximum of one master clock cycle.
The SYNC input can also be used as a start conversion
command for a single channel when in normal synchronization
mode. In this mode, the rising edge of SYNC input starts a
conversion, and the falling edge of the RDY output indicates when
the conversion is complete. The settling time of the filter is
required for each data register update. After the conversion is
complete, bring the SYNC input low in preparation for the next
conversion start signal.
Alternate Synchronization
In alternate synchronization mode, the SYNC input operates as
a start conversion command when several channels of the
AD7172-2 are enabled. Setting the ALT_SYNC bit in the interface
mode register to 1 enables an alternate synchronization scheme.
When the SYNC input is taken low, the ADC completes the
conversion on the current channel, selects the next channel in
the sequence, and then waits until the SYNC input is taken high
to start the conversion. The RDY output goes low when the
conversion is complete on the current channel, and the data
register is updated with the corresponding conversion.
Therefore, the SYNC input does not interfere with the sampling
on the currently selected channel but allows the user to control
the instant at which the conversion begins on the next channel
in the sequence.
Alternate synchronization mode can be used only when several
channels are enabled. It is not recommended to use this mode
when a single channel is enabled.
ERROR FLAGS
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors with the
ADC conversion, errors with the CRC check, and errors caused
by changes in the registers, respectively. In addition, the ERROR
output can indicate that an error has occurred.
ADC_ERROR
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an over-
range or underrange result is output from the ADC. The ADC
also outputs all 0s or all 1s when an undervoltage or overvoltage
occurs. This flag is reset only when the overvoltage or undervoltage
condition is removed. This flag is not reset by a read of the data
register.
CRC_ERROR
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag is reset when the status register is explicitly read.
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD7172-2 monitors the values in
the on-chip registers. If a bit changes, the REG_ERROR bit is set
to 1. Therefore, for writes to the on-chip registers, set the
REG_CHECK bit to 0. When the registers have been updated, the
REG_CHECK bit can be set to 1. The AD7172-2 calculates a
checksum of the on-chip registers. If one of the register values
has changed, the REG_ERROR bit is set to 1. If an error is flagged,
the REG_CHECK bit must be set to 0 to clear the REG_ERROR
bit in the status register. The register check function does not
monitor the data register, status register, or interface mode register.
ERROR Input/Output
When the SYNC_EN bit in the GPIOCON register is set to 0,
the SYNC/ERROR pin functions as an error input/output pin or
a general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
When the ERR_EN bits are set to 10, the SYNC/ERROR pin
functions as an open-drain error output, ERROR. The three
error bits in the status register (ADC_ERROR, CRC_ERROR, and
REG_ERROR) are OR’ed, inverted, and mapped to the ERROR
output. Therefore, the ERROR output indicates that an error has
occurred. The status register must be read to identify the error
source.
When the ERR_EN bits are set to 01, the SYNC/ERROR pin
functions as an error input, ERROR. The error output of another
component can be connected to the AD7172-2 ERROR input so
that the AD7172-2 indicates when an error occurs on either itself
or the external component. The value on the ERROR input is
inverted and OR’ed with the errors from the ADC conversion,
and the result is indicated via the ADC_ERROR bit in the status
register. The value of the ERROR input is reflected in the
ERR_DAT bit in the GPIO configuration register.
The ERROR input/output is disabled when the ERR_EN bits are set
to 00. When the ERR_EN bits are set to 11, the SYNC/ERROR pin
operates as a general-purpose output.
DATA_STAT
The contents of the status register can be appended to each con-
version on the AD7172-2 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The two LSBs of the status register
indicate to which channel the conversion corresponds. In
addition, the user can determine if any errors are being flagged
by the error bits.