TLV70433
OUT
IN
GND
MSP430
1 Fm
VIN
DBV PACKAGE
SOT23
(TOP VIEW)
NC
NC
GND
IN
OUT
1
2
3
5
4
TLV704xx
www.ti.com
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
24-V Input Voltage, 150-mA, Ultralow I
Q
Low-Dropout Regulators
1FEATURES DESCRIPTION
The TLV704xx series of low dropout (LDO) regulators
23•Wide Input Voltage Range: 2.5 V to 24 V are ultralow quiescent current devices designed for
•Low 3.2-μA Quiescent Current extremely power-sensitive applications. Quiescent
•Ground Pin Current: 3.4 μA at 100-mA IOUT current is virtually constant over the complete load
current and ambient temperature range. These
•Stable with Any Capacitor (>0.47 μF) devices are an ideal power management attachment
•Operating Junction Temperature: to low-power microcontrollers, such as the MSP430.
–40°C to +125°CThe TLV704xx operate over a wide operating input
•Available in SOT23-5 Package voltage of 2.5 V to 24 V. Thus, it is an excellent
–See Package Option Addendum at end of choice for both battery-powered systems as well as
this document for complete list of available industrial applications that see large line transients.
voltage options The TLV704xx is available in a 3-mm ×3-mm
SOT23-5 package, which is ideal for cost-effective
APPLICATIONS board manufacturing.
•Ultralow Power Microcontrollers
•E-Meters
•Fire Alarms/Smoke Detector Systems
•Handset Peripherals
•Industrial/Automotive Applications
•Remote Controllers
•Zigbee™Networks
•PDAs
•Portable, Battery-Powered Equipment
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Zigbee is a trademark of ZigBee Alliance.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV704xx
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PRODUCT VOUT
XX is nominal output voltage (for example 33 = 3.3 V)
TLV704xxyyyz YYY is Package Designator
Zis Package Quantity
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. VALUE UNIT
MIN MAX
Voltage(2) IN –0.3 24 V
Current source OUT Internally limited
Operating junction, TJ–40 +150 °C
Temperature Storage, Tstg –65 +150 °C
Human body model (HBM) 2 kV
QSS 009-105 (JESD22-A114A)
Electrostatic Discharge Rating(3) Charge device model (CDM) 500 V
QSS 009-147 (JESD22-C101B.01)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION TLV70433DBV
THERMAL METRIC(1) DBV UNITS
5 PINS
θJA Junction-to-ambient thermal resistance 213.1
θJCtop Junction-to-case (top) thermal resistance 110.9
θJB Junction-to-board thermal resistance 97.4 °C/W
ψJT Junction-to-top characterization parameter 22.0
ψJB Junction-to-board characterization parameter 78.4
θJCbot Junction-to-case (bottom) thermal resistance n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
POWER DISSIPATION RATING TABLE TA≤25°C POWER TA= +70°C POWER TA= +85°C POWER
BOARD PACKAGE RθJA RATING RATING RATING
High-K(1) DBV 213.1 °C/W 470 mW 258 mW 188 mW
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch ×3-inch, multilayer board with 1-ounce internal power
and ground planes and 2-ounce copper traces on top and bottom of the board.
2Copyright ©2010–2011, Texas Instruments Incorporated
_+
Current
Sense
R1
R2
VIN
GND
VOUT
ILIM
Bandgap
Reference
VREF =1.205V
R =840kW
2
TLV704xx
www.ti.com
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS
All values are at TA= +25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 µF, unless otherwise noted.
TLV704xx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 24 V
VOOutput voltage range 1.2 5 V
VOUT DC output accuracy –2 2 %
ΔVOfor ΔVIN Line regulation VOUT(NOM) + 1 V <VIN <24 V 20 50 mV
0 mA <IOUT <10 mA 10 mV
VOUT ≤3.3 V 0 mA <IOUT <50 mA 25 mV
0 mA <IOUT <100 mA 33 50 mV
ΔVOfor ΔIOUT Load regulation 0 mA <IOUT <10 mA 7 mV
VOUT ≥3.3 V 0 mA <IOUT <50 mA 35 mV
0 mA <IOUT <100 mA 50 75 mV
IOUT = 10 mA 75 mV
VDO Dropout voltage(1) IOUT = 50 mA 400 mV
IOUT = 100 mA 850 1100 mV
ICL Output current limit VOUT = 0 V 160 1000 mA
IOUT = 0 mA 3.2 4.5 µA
IGND Ground pin current IOUT = 100 mA 3.4 5.5 µA
Power-supply rejection
PSRR f = 100 kHz, COUT = 10 µF 60 dB
ratio
Operating junction
TJ–40 +125 °C
temperature
(1) VIN = VOUT(NOM) –0.1 V.
FUNCTIONAL BLOCK DIAGRAM
Table 1. Pin Descriptions
TLV704xx
NAME DBV DESCRIPTION
GND 1 Ground
IN 2 Unregulated input voltage.
OUT 3 Regulated output voltage. Any capacitor greater than 1 µF between this pin and ground is needed for stability.
NC 4, 5 No connection. This pin can be left open or tied to ground for improved thermal performance.
Copyright ©2010–2011, Texas Instruments Incorporated 3
3.4
3.38
3.36
3.34
3.32
3.3
3.28
3.26
3.24
3.22
3.2
Output Voltage (V)
48 12 16 20 24
Input Voltage (V)
-40 C
+85 C
°
°
°+25 C
V = 3.3 V
I = 5 mA
OUT
OUT
Output Current (mA)
0 30 60 90 120 150
3.6
3.5
3.4
3.3
3.2
3.1
3
Output Voltage (V)
- °40 C
+25 C°
+85 C°
Junction Temperature (°C)
-40 -25 -10 520 35 50 65 80 95 110 125
3.465
3.432
3.399
3.366
3.333
3.3
3.267
3.234
3.201
3.168
3.135
Output Voltage (V)
I = 80 mA
OUT
I = 10 mA
OUT
V = 4.3 V
IN
120
100
80
60
40
20
0
Dropout Voltage (mV)
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3
Input Voltage (V)
-40 C
+85 C
+25 C
°
°
°
I = 10 mA
OUT
2100
1800
1500
1200
900
600
300
0
Dropout Voltage (mV)
0 30 60 90 120 150
Output Current (mA)
-40 C
+85 C
+25 C
°
°
°
Junction Temperature (°C)
-40 -25 -10 520 35 50 65 80 95 110 125
4.5
4
3.5
3
2.5
2
Ground Current ( A)m
V = 4.3 V
V = 3.3 V
I = 1 Fm
IN
OUT
OUT
TLV704xx
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS LOAD REGULATION
LINE REGULATION (VOUT = 3.3 V)
Figure 1. Figure 2.
OUTPUT VOLTAGE vs DROPOUT VOLTAGE vs INPUT VOLTAGE
JUNCTION TEMPERATURE TLV70433
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT GROUND CURRENT vs JUNCTION TEMPERATURE
Figure 5. Figure 6.
4Copyright ©2010–2011, Texas Instruments Incorporated
0 30 60 90 120 150
Output Current (mA)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Ground Pin Current ( A)m
-40 C
+85 C
+25 C
°
°
°
V = 3.3 V
OUT
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Ground Pin Current ( A)m
3 6 9 12 15 18 21 24
Input Voltage (V)
-40 C
+85 C
+25 C
°
°
°
V = 3.3 V
OUT
8
7
6
5
4
3
2
1
0
Output Spectral Noise Density ( V/ )m ?Hz
100 1 k 10 k 100 k
Frequency (Hz)
V = 4.3 V
V = 3.3 V
C = 1 F
IN
OUT
OUT m
I = 50 mA
OUT
I = 1 mA
OUT
V = 3.3 V
C = 10 F
OUT
OUT m
R = 66
LW
VIN VOUT
8
7
6
5
4
3
2
1
0
Input Voltage (V)
Output Voltage (V)
Time (2 ms/div)
V = 4.3 V
V = 3.3 V
C = 10 F
T = +25 C
IN
OUT
OUT m
J°
I = 50 mA
OUT
I = 1 mA
OUT
100
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
10 100 1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
TLV704xx
www.ti.com
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS (continued)
GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs LOAD CURRENT
Figure 7. Figure 8.
CURRENT LIMIT vs OUTPUT SPECTRAL NOISE DENSITY vs
JUNCTION TEMPERATURE FREQUENCY
Figure 9. Figure 10.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY POWER-UP/POWER-DOWN
Figure 11. Figure 12.
Copyright ©2010–2011, Texas Instruments Incorporated 5
Time (50 ms/div)
5.3
4.3
100
50
0
50-
Input Voltage (V) Output Voltage (mV)
V = 3.3 V
I = 50 mA
C = 10 F
IN
OUT
OUT m
Time (0.5 ms/div)
100
50
0
200
0
200-
Output Current (mA) Output Voltage (mV)
V = 4.3 V
V = 3.3 V
C = 10 Fm
IN
OUT
OUT
TLV704xx
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 13. Figure 14.
6Copyright ©2010–2011, Texas Instruments Incorporated
PD+ǒVIN *VOUTǓ IOUT
PD(max) +TJmax*TA
RqJA
TLV704xx
www.ti.com
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
APPLICATION INFORMATION
The TLV704xx series belong to a family of ultralow IQTAis the ambient temperature.
LDO regulators. IQremains fairly constant over the The regulator dissipation is calculated using
complete output load current and temperature range. Equation 2:
The devices are ensured to operate over a
temperature range of –40°C to +125°C. (2)
Power dissipation resulting from quiescent current is
INPUT AND OUTPUT CAPACITOR negligible.
REQUIREMENTS
The TLV704 requires a 1-µF or larger capacitor REGULATOR PROTECTION
connected between OUT and GND for stability.
Ceramic or tantalum capacitors can be used. Larger The TLV704xx series of LDO regulators use a
value capacitors result in better transient and noise PMOS-pass transistor that has a built-in back diode
performance. that conducts reverse current when the input voltage
drops below the output voltage (for example, during
Although an input capacitor is not required for power-down). Current is conducted from the output to
stability, when a 0.1-µF or larger capacitor is placed the input and is not internally limited. If extended
between IN and GND, it counteracts reactive input reverse voltage operation is anticipated, external
sources and improves transient and noise limiting might be appropriate.
performance. Higher value capacitors are necessary
if large, fast rise time load transients are anticipated. The TLV704xx features internal current limiting.
During normal operation, the TLV704xx limits output
current to approximately 250 mA. When current
BOARD LAYOUT RECOMMENDATIONS limiting engages, the output voltage scales back
Input and output capacitors should be placed as linearly until the overcurrent condition ends. Take
close to the device pins as possible. To avoid care not to exceed the rated maximum operating
interference of noise and ripple on the board, it is junction temperature of +125°C. Continuously running
recommended that the board be designed with the device under conditions where the junction
separate ground planes for VIN and VOUT, with the temperature exceeds +125°C degrades device
ground plane connected only at the device GND pin. reliability.
In addition, the ground connection for the output The ability to remove heat from the die is different for
capacitor should be connected directly to the device each package type, presenting different
GND pin. considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
POWER DISSIPATION AND JUNCTION of other components moves the heat from the device
TEMPERATURE to the ambient air. Performance data for JEDEC
To ensure reliable operation, worst-case junction high-K boards are given in the Power Dissipation
temperature should not exceed +125°C. This Rating table. Using heavier copper increases the
restriction limits the power dissipation the regulator effectiveness in removing heat from the device. The
can handle in any given application. To ensure the addition of plated through-holes to heat-dissipating
junction temperature is within acceptable limits, layers also improves heatsink effectiveness. Power
calculate the maximum allowable dissipation, PD(max),dissipation depends on input voltage and load
and the actual dissipation, PD, which must be less conditions. Power dissipation (PD) is equal to the
than or equal to PD(max).product of the output current and the voltage drop
across the output pass element, as shown in
The maximum power dissipation limit is determined Equation 2.
using Equation 1:
PACKAGE MOUNTING
(1) Solder pad footprint recommendations for the
TLV704xx are available from the Texas Instruments
where: web site at www.ti.com through the TLV704 series
TJmax is the maximum allowable junction product folders. The recommended land pattern for
temperature. the DBV package is appended to this data sheet.
RθJA is the thermal resistance junction-to-ambient
for the package (see the Power Dissipation
Rating table).
Copyright ©2010–2011, Texas Instruments Incorporated 7
TLV704xx
SBVS148C –OCTOBER 2010–REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November, 2010) to Revision C Page
•Revised document to reflect PK package option removal .................................................................................................... 1
•Removed SOT89 (PK) package from front-page figure ....................................................................................................... 1
•Revised Thermal Information table and Power Dissipation Rating table ............................................................................. 2
•Added load regulation specifications for VOUT ≥3.3 V .......................................................................................................... 3
•Deleted PK package information from Pin Descriptions table .............................................................................................. 3
•Removed Figure 15 and Figure 16 ....................................................................................................................................... 7
Changes from Revision A (October, 2010) to Revision B Page
•Updated document to reflect availability of PK package option ........................................................................................... 1
•Corrected typo in front-page figure ....................................................................................................................................... 1
•Changed Pin Descriptions table to correct pin numbering for PK package option ............................................................... 3
•Revised Typical Characteristics section; added and removed graphs ................................................................................. 4
•Updated format of Application Information section ............................................................................................................... 7
•Added Package Mounting section and ................................................................................................................................. 7
8Copyright ©2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV70430DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70430DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70433DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70433DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70436DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70436DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70450DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV70450DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV70430DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70433DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70436DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV70450DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV70430DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70433DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70436DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV70450DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2012
Pack Materials-Page 2
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