TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com 24-V Input Voltage, 150-mA, Ultralow IQ Low-Dropout Regulators FEATURES DESCRIPTION * * * * * The TLV704xx series of low dropout (LDO) regulators are ultralow quiescent current devices designed for extremely power-sensitive applications. Quiescent current is virtually constant over the complete load current and ambient temperature range. These devices are an ideal power management attachment to low-power microcontrollers, such as the MSP430. 1 23 * Wide Input Voltage Range: 2.5 V to 24 V Low 3.2-A Quiescent Current Ground Pin Current: 3.4 A at 100-mA IOUT Stable with Any Capacitor (> 0.47 F) Operating Junction Temperature: -40C to +125C Available in SOT23-5 Package - See Package Option Addendum at end of this document for complete list of available voltage options The TLV704xx operate over a wide operating input voltage of 2.5 V to 24 V. Thus, it is an excellent choice for both battery-powered systems as well as industrial applications that see large line transients. The TLV704xx is available in a 3-mm x 3-mm SOT23-5 package, which is ideal for cost-effective board manufacturing. APPLICATIONS * * * * * * * * * Ultralow Power Microcontrollers E-Meters Fire Alarms/Smoke Detector Systems Handset Peripherals Industrial/Automotive Applications Remote Controllers ZigbeeTM Networks PDAs Portable, Battery-Powered Equipment DBV PACKAGE SOT23 (TOP VIEW) TLV70433 VIN GND 1 IN 2 OUT 3 5 NC 4 NC OUT IN MSP430 GND 1 mF 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Zigbee is a trademark of ZigBee Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2011, Texas Instruments Incorporated TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PRODUCT VOUT XX is nominal output voltage (for example 33 = 3.3 V) YYY is Package Designator Z is Package Quantity TLV704xxyyyz (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE Voltage (2) IN Current source OUT Temperature Electrostatic Discharge Rating (3) (1) UNIT MIN MAX -0.3 24 V Internally limited Operating junction, TJ -40 +150 C Storage, Tstg -65 +150 C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Charge device model (CDM) QSS 009-147 (JESD22-C101B.01) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. (2) (3) THERMAL INFORMATION TLV70433DBV THERMAL METRIC (1) DBV UNITS 5 PINS JA Junction-to-ambient thermal resistance 213.1 JCtop Junction-to-case (top) thermal resistance 110.9 JB Junction-to-board thermal resistance 97.4 JT Junction-to-top characterization parameter 22.0 JB Junction-to-board characterization parameter 78.4 JCbot Junction-to-case (bottom) thermal resistance n/a (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. POWER DISSIPATION RATING TABLE (1) 2 BOARD PACKAGE RJA TA 25C POWER RATING TA = +70C POWER RATING TA = +85C POWER RATING High-K (1) DBV 213.1 C/W 470 mW 258 mW 188 mW The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Copyright (c) 2010-2011, Texas Instruments Incorporated TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS All values are at TA = +25C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 F, unless otherwise noted. TLV704xx PARAMETER TEST CONDITIONS MIN TYP Input voltage range VO MAX UNIT 24 V Output voltage range 1.2 5 V VOUT DC output accuracy -2 2 % VO for VIN Line regulation 50 mV VOUT(NOM) + 1 V < VIN < 24 V VOUT 3.3 V VO for IOUT Load regulation VOUT 3.3 V Dropout voltage (1) VDO ICL Output current limit IGND Ground pin current PSRR Power-supply rejection ratio TJ Operating junction temperature (1) 20 0 mA < IOUT < 10 mA 10 mV 0 mA < IOUT < 50 mA 25 mV 0 mA < IOUT < 100 mA 33 0 mA < IOUT < 10 mA 7 mV 0 mA < IOUT < 50 mA 35 mV 0 mA < IOUT < 100 mA 50 IOUT = 10 mA 75 IOUT = 50 mA 400 IOUT = 100 mA 850 VOUT = 0 V 160 50 75 mV mV mV mV 1100 mV 1000 mA IOUT = 0 mA 3.2 4.5 A IOUT = 100 mA 3.4 5.5 A f = 100 kHz, COUT = 10 F 60 -40 dB +125 C VIN = VOUT(NOM) - 0.1 V. FUNCTIONAL BLOCK DIAGRAM VOUT VIN Current Sense ILIM _ GND + VREF = 1.205 V Bandgap Reference R1 R2 R2 = 840 kW Table 1. Pin Descriptions TLV704xx NAME DBV GND 1 DESCRIPTION Ground IN 2 Unregulated input voltage. OUT 3 Regulated output voltage. Any capacitor greater than 1 F between this pin and ground is needed for stability. NC 4, 5 No connection. This pin can be left open or tied to ground for improved thermal performance. Copyright (c) 2010-2011, Texas Instruments Incorporated 3 TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS LOAD REGULATION (VOUT = 3.3 V) LINE REGULATION 3.6 3.4 VOUT = 3.3 V IOUT = 5 mA 3.38 3.5 Output Voltage (V) Output Voltage (V) 3.36 3.34 3.32 3.3 3.28 3.26 -40C +25C +85C 3.24 3.22 3.4 3.3 3.2 -40C +25C +85C 3.1 3 3.2 4 8 12 16 20 0 24 30 60 Input Voltage (V) 3.465 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE DROPOUT VOLTAGE vs INPUT VOLTAGE TLV70433 120 IOUT = 10 mA 100 Dropout Voltage (mV) 3.366 3.333 IOUT = 10 mA 3.3 3.267 3.234 IOUT = 80 mA 3.201 80 60 40 -40C +25C +85C 20 3.168 3.135 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.5 2.6 2.7 2.8 Figure 3. 3 3.1 3.2 3.3 Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT GROUND CURRENT vs JUNCTION TEMPERATURE 4.5 2100 1800 Ground Current (mA) 4 Dropout Voltage (mV) 2.9 Input Voltage (V) Junction Temperature (C) 1500 1200 900 600 -40C +25C +85C 300 0 0 30 60 90 Output Current (mA) Figure 5. 4 150 Figure 2. 3.399 Output Voltage (V) 120 Figure 1. VIN = 4.3 V 3.432 90 Output Current (mA) 120 150 VIN = 4.3 V VOUT = 3.3 V IOUT = 1 mF 3.5 3 2.5 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (C) Figure 6. Copyright (c) 2010-2011, Texas Instruments Incorporated TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GROUND PIN CURRENT vs INPUT VOLTAGE VOUT = 3.3 V 3.5 3 2.5 2 1.5 1 -40C +25C +85C 0.5 3.5 3 2.5 2 1.5 1 -40C +25C +85C 0.5 0 0 250 6 9 12 15 18 21 30 60 90 120 Input Voltage (V) Output Current (mA) Figure 7. Figure 8. CURRENT LIMIT vs JUNCTION TEMPERATURE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY VOUT = 3.3 V, VIN = 4.8 V -40C 200 0 24 Output Spectral Noise Density (mV/?Hz) 3 Current Limit (mA) VOUT = 3.3 V 4 Ground Pin Current (mA) 4 Ground Pin Current (mA) GROUND PIN CURRENT vs LOAD CURRENT 4.5 4.5 +25C +85C 150 100 50 0 150 8 7 VIN = 4.3 V VOUT = 3.3 V COUT = 1 mF IOUT = 1 mA 6 IOUT = 50 mA 5 4 3 2 1 0 100 Temperature (C) 1k 10 k 100 k Frequency (Hz) Figure 9. Figure 10. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-UP/POWER-DOWN 8 VIN = 4.3 V VOUT = 3.3 V COUT = 10 mF TJ = +25C 90 80 70 7 IOUT = 1 mA Input Voltage (V) Output Voltage (V) Power-Supply Rejection Ratio (dB) 100 60 50 40 30 IOUT = 50 mA 20 6 VOUT = 3.3 V RL = 66 W COUT = 10 mF 5 4 3 VIN VOUT 2 1 10 0 0 10 100 1k 10 k 100 k 1M 10 M Time (2 ms/div) Frequency (Hz) Figure 11. Copyright (c) 2010-2011, Texas Instruments Incorporated Figure 12. 5 TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 3.3 V IOUT = 50 mA COUT = 10 mF 100 50 0 -50 5.3 4.3 Time (50 ms/div) Figure 13. 6 LOAD TRANSIENT RESPONSE Output Current (mA) Output Voltage (mV) Input Voltage (V) Output Voltage (mV) LINE TRANSIENT RESPONSE 200 VIN = 4.3 V VOUT = 3.3 V COUT = 10 mF 0 -200 100 50 0 Time (0.5 ms/div) Figure 14. Copyright (c) 2010-2011, Texas Instruments Incorporated TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION The TLV704xx series belong to a family of ultralow IQ LDO regulators. IQ remains fairly constant over the complete output load current and temperature range. The devices are ensured to operate over a temperature range of -40C to +125C. P D + VIN * VOUT INPUT AND OUTPUT CAPACITOR REQUIREMENTS Power dissipation resulting from quiescent current is negligible. The TLV704 requires a 1-F or larger capacitor connected between OUT and GND for stability. Ceramic or tantalum capacitors can be used. Larger value capacitors result in better transient and noise performance. REGULATOR PROTECTION Although an input capacitor is not required for stability, when a 0.1-F or larger capacitor is placed between IN and GND, it counteracts reactive input sources and improves transient and noise performance. Higher value capacitors are necessary if large, fast rise time load transients are anticipated. BOARD LAYOUT RECOMMENDATIONS Input and output capacitors should be placed as close to the device pins as possible. To avoid interference of noise and ripple on the board, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the ground connection for the output capacitor should be connected directly to the device GND pin. POWER DISSIPATION AND JUNCTION TEMPERATURE To ensure reliable operation, worst-case junction temperature should not exceed +125C. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined using Equation 1: T max * T A P D(max) + J R qJA (1) where: TJmax is the maximum allowable junction temperature. RJA is the thermal resistance junction-to-ambient for the package (see the Power Dissipation Rating table). Copyright (c) 2010-2011, Texas Instruments Incorporated TA is the ambient temperature. The regulator Equation 2: dissipation is I OUT calculated using (2) The TLV704xx series of LDO regulators use a PMOS-pass transistor that has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. The TLV704xx features internal current limiting. During normal operation, the TLV704xx limits output current to approximately 250 mA. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. Take care not to exceed the rated maximum operating junction temperature of +125C. Continuously running the device under conditions where the junction temperature exceeds +125C degrades device reliability. The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC high-K boards are given in the Power Dissipation Rating table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2. PACKAGE MOUNTING Solder pad footprint recommendations for the TLV704xx are available from the Texas Instruments web site at www.ti.com through the TLV704 series product folders. The recommended land pattern for the DBV package is appended to this data sheet. 7 TLV704xx SBVS148C - OCTOBER 2010 - REVISED AUGUST 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November, 2010) to Revision C Page * Revised document to reflect PK package option removal .................................................................................................... 1 * Removed SOT89 (PK) package from front-page figure ....................................................................................................... 1 * Revised Thermal Information table and Power Dissipation Rating table ............................................................................. 2 * Added load regulation specifications for VOUT 3.3 V .......................................................................................................... 3 * Deleted PK package information from Pin Descriptions table .............................................................................................. 3 * Removed Figure 15 and Figure 16 ....................................................................................................................................... 7 Changes from Revision A (October, 2010) to Revision B Page * Updated document to reflect availability of PK package option ........................................................................................... 1 * Corrected typo in front-page figure ....................................................................................................................................... 1 * Changed Pin Descriptions table to correct pin numbering for PK package option ............................................................... 3 * Revised Typical Characteristics section; added and removed graphs ................................................................................. 4 * Updated format of Application Information section ............................................................................................................... 7 * Added Package Mounting section and ................................................................................................................................. 7 8 Copyright (c) 2010-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV70430DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70430DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70433DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70433DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70436DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70436DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70450DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70450DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 26-Jun-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TLV70430DBVR SOT-23 DBV 5 3000 178.0 9.0 TLV70433DBVR SOT-23 DBV 5 3000 178.0 TLV70436DBVR SOT-23 DBV 5 3000 178.0 TLV70450DBVR SOT-23 DBV 5 3000 178.0 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70430DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV70433DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV70436DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV70450DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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