SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
High-Impedance State During Power Up
and Power Down
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (J) DIPs
description
These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH540 are ideal for driving bus lines or buffer memory address registers. These devices feature inputs
and outputs on opposite sides of the package that facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LVTH540 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH540 is characterized for operation from –40°C to 85°C.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LVTH540 ...J OR W PACKAGE
SN74LVTH540 . . . DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
SN54LVTH540 . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
Y7
Y6 OE2
A8
GND
Y8 VCC
SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUT
OE1 OE2 A
OUTPUT
Y
L L L H
LLH L
HXX Z
XHX Z
logic symbol†
2
A1 3
A2 4
A3
1
Y1
18
Y2
17
Y3
16
&EN
5
A4 6
A5 7
A6
Y4
15
Y5
14
Y6
13
19
OE1
OE2
8
A7 9
A8
Y7
12
Y8
11
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
218
SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVTH540 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH540 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVTH540 48 mA. . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH540 64 mA. . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH540 SN74LVTH540
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH540 SN74LVTH540
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
V
VOH
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
V
V
OH
VCC =3V
IOH = –24 mA 2
V
V
CC =
3
V
IOH = –32 mA 2
V
VCC =27V
IOL = 100 µA 0.2 0.2
V
V
V
CC =
2
.
7
V
IOL = 24 mA 0.5 0.5
V
VOL
V3V
IOL = 16 mA 0.4 0.4
V
V
OL
VCC =3V
IOL = 32 mA 0.5 0.5
V
V
CC =
3
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
I
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
A
II
Control inputs VCC = 3.6 V, VI = VCC or GND ±1±1
µA
I
I
Data inputs‡
VCC =36V
VI = VCC 1 1 µ
A
Data inputs
‡
V
CC =
3
.
6
V
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
II(hold)
Data inputs
VCC =3V
VI = 0.8 V 75 75
µA
I
I(hold)
D
a
t
a
i
npu
t
s
V
CC =
3
V
VI = 2 V –75 –75 µ
A
IOZH VCC = 3.6 V, VO = 3 V 5 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V –5 –5 µA
IOZPU§VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = Don’t care ±100 ±100 µA
IOZPD§VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = Don’t care ±100 ±100 µA
I
V36VI0
Outputs high 0.19 0.19
A
ICC VCC = 3.6 V, IO = 0,
VI
=
VCC or GND
Outputs low 5 5 mA
CC
VI
=
VCC
or
GND
Outputs disabled 0.19 0.19
∆ICCVCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND 0.2 0.2 mA
CiVI = 3 V or 0 3 3 pF
CoVO = 3 V or 0 7 7 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡Unused pins at VCC or GND
§This parameter is warranted but not production tested.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH540 SN74LVTH540
UNIT
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
13.9 4.7 1.1 2.4 3.8 4.6
ns
tPHL
1 3.9 4.7 1.1 2.7 3.8 4.6 ns
tPZH
1.4 5.3 6.3 1.5 3.4 5.2 6.2
ns
tPZL OE
1.4 5.5 6.1 1.5 3.7 5.3 5.9 ns
tPHZ
1.4 5.9 6.2 1.5 3.9 5.6 5.9
ns
tPLZ OE
1.4 5.5 5.8 1.5 3.5 5 5.3 ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVTH540, SN74LVTH540
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS681 – MARCH 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Data Input
Timing Input 2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈ 0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPZL and tPZH are the same as ten.
F. tPLZ and tPHZ are the same as tdis.
G. tPLH and tPHL are the same as tpd.
6 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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product or service without notice, and advises its customers to obtain the latest version of relevant information
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the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
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Copyright 1996, Texas Instruments Incorporated